Universal logic memory cell

Abstract

SOLUTION: In a universal logic memory cell 300, a first network element 310 and a second network element 311 are composed of a first parallel connection part to which a common drain region is connected and a second parallel connection part to which a common source region is connected between a first serial connection part in which drain regions and source regions of two triple-gate silicon elements of four triple-gate silicon elements 301 are connected in series and a second serial connection part in which drain regions and source regions of the remaining two triple-gate silicon elements are connected in series. The triple-gate silicon elements aligned in respective positions are selectively driven in either one of a first channel mode and a second channel mode.EFFECT: A universal logic memory cell can be embodied that provides a ternary logic operation function and a memory function using triple-gate silicon elements driven by a positive feedback loop.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] [Cross - reference to Related Applications] This application claims the benefit of priority based on Korean Patent Application No. 10 - 2023 - 0191705 filed on December 26, 2023, and all the contents disclosed in the literature of the Korean patent application are incorporated herein by reference.

[0002] The present invention relates to a general - purpose logic memory cell composed of triple - gate silicon devices, and more particularly, to a technology for implementing a general - purpose logic memory cell that provides a ternary logic operation function and a memory function using a triple - gate silicon device driven by a positive feedback loop.

Background Art

[0003] In a conventional von Neumann - based computer system, a processor and a memory are separated, and data is transmitted via a bus.

[0004] However, with the increase in computing performance, a bottleneck phenomenon occurs due to the difference in data - processing speeds between the processor and the memory, and it has begun to show limitations in processing large - volume data.

[0005] In other words, the von Neumann - based system, which is a revolutionary development in the semiconductor industry, has improved the integration density and performance of modern computers, but due to the physical separation between the processor and the memory hierarchy, a lot of energy is consumed, and there are drawbacks such as long data transmission and waiting times.

[0006] Considering the increase in data - intensive applications such as 5G communication standards, the Internet of Things (IoT), and artificial intelligence (AI) after the Fourth Industrial Revolution, a new computing paradigm is essential for large - scale data - processing requirements.

[0007] In order to solve the above problems, research on logic memory technology that integrates computing and memory functions has been concentrated and accelerated.

[0008] Since logic memory technology performs the computing function of a processor and the memory function of a memory in the same space, it can reduce the delay time and power consumption that occur during data transmission, and can significantly improve the integration degree of the system.

[0009] Conventional logic memory technologies have been actively studied based on SRAM (static random access memory) corresponding to volatile memory elements, DRAM (dynamic RAM), and ReRAM (resistive RAM), MRAM (magnetoresistive RAM), PCRAM (phase-change RAM), etc. corresponding to non-volatile memory elements.

[0010] In the case of logic memory technology based on volatile memory elements, a large number of transistors are required for stable operation, so there are limitations in terms of large overall area and high power consumption.

[0011] Also, in the case of logic memory technology based on non-volatile memory elements, a complex process is required because non-silicon materials are used, and it is difficult to be put into practical use due to low device uniformity and stability.

[0012] In addition, the logic memory technologies that have already been studied cannot implement all basic CMOS logic operations in one cell, and individual circuits and wiring are required for logic operations, resulting in low integration.

[0013] Therefore, there is a need to develop a general-purpose logic memory cell technology that can be fabricated by utilizing silicon-based CMOS processes, perform all basic logic operations in one cell, and store the values.

[0014] Conventional logic memory technologies have been studied in various memories such as DRAM (dynamic random access memory), SRAM (static RAM), which are volatile memory elements, and PRAM (phase-change RAM), ReRAM (resistive RAM), MRAM (magnetoresistive RAM), etc., which are non-volatile memory elements.

[0015] However, since these cannot define n-channel and p-channel, there are difficulties in applying them to existing CMOS logic operations.

[0016] In particular, logic-memory technologies based on non-volatile memory elements generally require new process steps that are not the silicon-based CMOS process, and it is difficult to put them into practical use due to low device uniformity and reliability.

[0017] Also, in order to overcome the limitations of the information density of existing CMOS binary logic systems, multi-valued logic systems having more than two logic states have been studied in various elements. However, since they commonly use leakage current flowing through the elements, there is a problem of consuming high power.

[0018] In particular, elements using tunneling principle-based negative differential resistance (NDR), negative differential transconductance (NDT), quantum dots (QD), etc. have limitations in reliability and operating temperature, so there are difficulties in applying them to multi-valued logic systems.

[0019] As a result, conventional binary logic operation methods have limitations in relatively improving integration density and information density.

Summary of the Invention

Problems to be Solved by the Invention

[0020] The present invention aims to embody a general-purpose logic memory cell that provides a ternary logic operation function and a memory function using a triple-gate silicon device driven by a positive feedback loop.

[0021] The present invention aims to embody a general-purpose logic memory cell that performs all basic ternary logic operations in a single structure using a triple-gate silicon device and stores the operation results.

[0022] The present invention aims to embody a general-purpose logic memory cell by utilizing a triple-gate silicon device, which is a silicon-based feedback memory device applying an existing CMOS process.

[0023] The present invention aims to improve the limits of processing speed and integration due to the data bottleneck phenomenon through the integration of logic operations and storage functions.

[0024] The present invention aims to improve standby power efficiency with excellent memory characteristics that maintain logic operation values without structural changes and external biases by using channel mode reconfiguration characteristics.

Means for Solving the Problems

[0025] A general-purpose logic memory cell according to an embodiment of the present invention includes a first network element and a second network element using a plurality of triple-gate silicon devices. Each of the plurality of triple-gate silicon devices includes a drain region, a channel region, and a source region. A supply voltage is applied to the drain region and the source region, and a gate region is formed on the channel region with first and second programming gate electrodes and a control gate electrode formed thereon. A program voltage V applied through the first and second programming gate electrodes PGAccording to the level of, in the channel region, the channel region under the first and second programming gate electrodes operates in either the first channel mode or the second channel mode, and the control voltage V applied through the control gate electrode CG Based on the level of, it is determined to be in either the on state or the off state, and the first network element and the second network element output the voltage V at either the positive level, zero level, or negative level according to either one of the states in either one of the channel modes described above OUT By determining the level of, a ternary logic operation function and a memory function can be performed.

[0026] The first network element and the second network element include a first series connection portion in which the drain regions and source regions of two of the four triple-gate silicon elements among the plurality of triple-gate silicon elements are connected in series, and a second series connection portion in which the drain regions and source regions of the remaining two triple-gate silicon elements are connected in series. The first parallel connection portion to which the common drain region between them is connected, and the second parallel connection portion to which the common source region is connected. The drain voltage V among the common voltages is applied through the first parallel connection portion of the first network element DD is applied, the source voltage V among the common voltages is applied through the second parallel connection portion of the second network element SS is applied, and the output voltage V can be measured at the portion where the second parallel connection portion of the first network element and the first parallel connection portion of the second network element are connected as either one of them OUT can be measured.

[0027] When the first network element operates in the second channel mode and the second network element operates in the first channel mode, when the level of the control voltage V CG is at a negative level, the level of the output voltage V OUT is determined to be at a positive level, and the control voltage V CGWhen the level of is the positive level, the output voltage V OUT Determine the level of as the negative level, and the control voltage V CG When the level of is the zero level, the output voltage V OUT The ternary logic operation function of determining the level of as the zero level can be performed.

[0028] When the first network element operates in the first channel mode and the second network element operates in the second channel mode, the control voltage V CG When the level of is the negative level, the output voltage V OUT Determine the level of as the negative level, and the control voltage V CG When the level of is the positive level, the output voltage V OUT Determine the level of as the positive level, and the control voltage V CG When the level of is the zero level, the output voltage V OUT The ternary logic operation function of determining the level of as the zero level can be performed.

[0029] When the first network element operates in the second channel mode and the second network element operates in the first channel mode, and the control voltage V CG Among them, the first control voltage V IN1 Is applied to the left side of the first network element and the upper side of the second network element, and the control voltage V CG Among them, the second control voltage V IN2 Is applied to the right side of the first network element and the lower side of the second network element, and the first control voltage V IN1 And the second control voltage V IN2 When any one of the levels is the negative level, the output voltage V OUT Determine the level of as the positive level, and the first control voltage V IN1 And the second control voltage V IN2 When both levels are the positive level, the output voltage V OUT Determine the level of as the negative level, and the first control voltage VIN1 and both the level of the second control voltage V IN2 are at the zero level, or when one of the levels is at the zero level and the other level is at the positive level, the output voltage V OUT can perform the ternary logic operation function of determining the level of to be the zero level.

[0030] The first network element operates in the second channel mode, the second network element operates in the first channel mode, and the control voltage V CG Among them, the first control voltage V IN1 is applied to the upper side of the first network element and the left side of the second network element, and the control voltage V CG Among them, the second control voltage V IN2 is applied to the lower side of the first network element and the right side of the second network element, and when one of the levels of the first control voltage V IN1 and the second control voltage V IN2 is at the positive level, the level of the output voltage V OUT is determined to be at the negative level, and when both of the levels of the first control voltage V IN1 and the second control voltage V IN2 are at the negative level, the level of the output voltage V OUT is determined to be at the positive level, and when both of the first control voltage V IN1 and the second control voltage V IN2 are at the zero level, or when one of the levels is at the zero level and the other level is at the negative level, the output voltage V OUT can perform the ternary logic operation function of determining the level of to be the zero level.

[0031] The first network element operates in the first channel mode, the second network element operates in the second channel mode, and the control voltage V CG Among them, the first control voltage V IN1is applied to the upper side of the first network element and the left side of the second network element, and the control voltage V CG Among them, the second control voltage V IN2 is applied to the lower side of the first network element and the right side of the second network element, and the first control voltage V IN1 and the second control voltage V IN2 When any one of the levels is a negative level, the level of the output voltage V OUT is determined to be a negative level, and the first control voltage V IN1 and the second control voltage V IN2 When both levels are positive levels, the level of the output voltage V OUT is determined to be a positive level, and the first control voltage V IN1 and the second control voltage V IN2 When both levels are zero levels, or when one level is a zero level and the other level is a positive level, the level of the output voltage V OUT can perform the ternary logic operation function of determining the level to be a zero level.

[0032] The first network element operates in the second channel mode, the second network element operates in the first channel mode, and the control voltage V CG Among them, the first control voltage V IN1 is applied to the left side of the first network element and the upper side of the second network element, and the control voltage V CG Among them, the second control voltage V IN2 is applied to the right side of the first network element and the lower side of the second network element, and the first control voltage V IN1 and the second control voltage V IN2 When any one of the levels is a positive level, the level of the output voltage V OUT is determined to be a positive level, and the first control voltage V IN1 and the second control voltage V IN2 When both levels are negative levels, the output voltage VOUT Determine the level as a negative level, and for the first control voltage V IN1 and the second control voltage V IN2 when both levels are at the zero level, or when one of the levels is at the zero level and the other level is at the negative level, the ternary logic operation function of determining the level of the output voltage V OUT can be performed to be at the zero level.

[0033] The left side of the first network element operates in the first channel mode, the right side of the first network element operates in the second channel mode, the upper left side of the second network element operates in the second channel mode, the upper right side of the second network element operates in the first channel mode, the lower left side of the second network element operates in the first channel mode, the lower right side of the second network element operates in the second channel mode, and for the control voltage V CG among them, the first control voltage V IN1 is applied to the upper sides of the first network element and the second network element, and for the control voltage V CG among them, the second control voltage V IN2 is applied to the lower sides of the first network element and the second network element. When the levels of the first control voltage V IN1 and the second control voltage V IN2 are the same, either at the negative level or the positive level, the level of the output voltage V OUT is determined to be at the positive level. When the levels of the first control voltage V IN1 and the second control voltage V IN2 are opposite, either at the negative level or the positive level, the level of the output voltage V OUT is determined to be at the negative level. When either one of the levels of the first control voltage V IN1 and the second control voltage V IN2 is at the zero level, the ternary logic operation function of determining the level of the output voltage V OUT can be performed to be at the zero level.

[0034] The upper left side of the first network element operates in the second channel mode, the upper right side of the first network element operates in the first channel mode, the lower left side of the first network element operates in the first channel mode, the lower right side of the first network element operates in the second channel mode, the left side of the second network element operates in the first channel mode, the right side of the second network element operates in the second channel mode, and the control voltage V CG Among them, the first control voltage V IN1 is applied to the upper sides of the first network element and the second network element, and the control voltage V CG Among them, the second control voltage V IN2 is applied to the lower sides of the first network element and the second network element. When both the levels of the first control voltage V IN1 and the second control voltage V IN2 are positive levels, the level of the output voltage V OUT is determined to be a negative level. When both the levels of the first control voltage V IN1 and the second control voltage V IN2 are negative levels, the level of the output voltage V OUT is determined to be a negative level. When the levels of the first control voltage V IN1 and the second control voltage V IN2 are negative or positive levels such that they are opposite to each other, the level of the output voltage V OUT is output as a positive level. When either one of the levels of the first control voltage V IN1 and the second control voltage V IN2 is at zero level, the ternary logic operation function that determines the level of the output voltage V OUT to be zero level can be performed.

[0035] The drain region is in a p-doped state, the source region is in an n-doped state, the channel region is in an intrinsic state, and in the channel region, the channel region under the first and second programming gate electrodes is at the program voltage V PG When the level of is a positive level, it operates as an n-channel corresponding to the first channel mode, and when the level of the program voltage V PG is a negative level, it can operate as a p-channel corresponding to the second channel mode.

[0036] When the drain voltage V DD applied to the drain region, the source voltage V SS applied to the source region, the program voltage V PG and the control voltage V CG are applied at zero level, the memory function can be performed while maintaining the level of the output voltage V OUT .

[0037] For each of the plurality of triple-gate silicon elements, when the channel region under the first and second programming gate electrodes in the channel region operates in the first channel mode, the level of the applied control gate voltage V CG is determined to be in an on state when it is higher than the latch-up voltage which is the voltage when the current rapidly increases, and can be determined to be in an off state when the level of the applied control gate voltage V CG is lower than the latch-up voltage.

[0038] For each of the plurality of triple-gate silicon elements, when the channel region under the first and second programming gate electrodes in the channel region operates in the first channel mode, the applied control voltage V CGWhen the level of increases to a level higher than the latch-up voltage, the height of the potential barrier between the channel region under the control gate electrode and the channel region under the second programming gate electrode adjacent to the source region in the channel region decreases, and a first positive feedback loop is generated in which electrons are injected from the source region due to the decreased potential barrier, and it can enter the on state in which current flows.

[0039] Each of the plurality of triple-gate silicon elements has a channel region under the first and second programming gate electrodes in the channel region. When operating in the second channel mode, the applied control gate voltage V CG is determined to be in the off state when the level is higher than the latch-up voltage, which is the voltage when the current rapidly increases. The applied control gate voltage V CG can be determined to be in the on state when the level is lower than the latch-up voltage.

[0040] Each of the plurality of triple-gate silicon elements has a channel region under the first and second programming gate electrodes in the channel region. When operating in the second channel mode, the applied control voltage V CG When the level decreases to a level lower than the latch-up voltage, the height of the potential barrier between the channel region under the control gate electrode and the channel region under the first programming gate electrode adjacent to the drain region in the channel region decreases, and a second positive feedback loop is generated in which holes are injected from the drain region due to the decreased potential barrier, and it can enter the on state in which current flows.

Advantages of the Invention

[0041] The present invention can implement a general-purpose logic memory cell that provides a ternary logic operation function and a memory function using a triple-gate silicon device driven by a positive feedback loop.

[0042] The present invention can implement a general-purpose logic memory cell that performs all basic ternary logic operations in a single structure using a triple-gate silicon device and stores the operation results.

[0043] The present invention can implement a general-purpose logic memory cell by utilizing a triple-gate silicon device, which is a silicon-based feedback memory device applying an existing CMOS process.

[0044] The present invention can improve the limits of processing speed and integration due to the data bottleneck phenomenon through the fusion of a logic operation and a storage function.

[0045] The present invention can improve standby power efficiency with excellent memory characteristics that maintain logic operation values without structural changes and external biases by using channel mode reconfiguration characteristics.

Brief Description of the Drawings

[0046]

Figure 1A

Figure 1B

Figure 2A

Figure 2B

Figure 2C

Figure 3

Figure 4A

Figure 4B

Figure 5A

Figure 5B

Figure 6A

Figure 6B

Figure 7A

Figure 7B

Mode for Carrying Out the Invention

[0047] Hereinafter, various embodiments of this document will be described with reference to the accompanying drawings.

[0048] The embodiments and the terms used therein are not intended to limit the technology described in this specification to specific embodiments, but should be understood to include various modifications, equivalents, and / or alternatives of the embodiments.

[0049] In the following description of various embodiments, if it is determined that a detailed description of a related known function or configuration may obscure the gist of the invention, the detailed description thereof will be omitted.

[0050] Furthermore, the terms described below are terms defined in consideration of the functions in various embodiments, and these may vary depending on the intention or convention of the user or operator, etc. Therefore, the definition should be made based on the content throughout this specification.

[0051] In connection with the description of the drawings, similar reference numerals may be used for similar components.

[0052] The singular form can include the plural form unless the context clearly indicates otherwise.

[0053] In this document, expressions such as "A or B" or "at least one of A and / or B" can include all possible combinations of the items listed together.

[0054] Expressions such as "first", "second", "primary", or "secondary" can modify the component without regard to order or importance, and are only used to distinguish one component from another, without limiting the component.

[0055] When it is mentioned that a certain (e.g., first) component is "(functionally or communicatively) connected to" or "connected to" another (e.g., second) component, the certain component can be directly connected to the other component or connected via another component (e.g., a third component).

[0056] In this specification, "(configured to)" can be used interchangeably with, depending on the situation, for example, "suitable for", "having the ability to", "modified to", "made to", "capable of", or "designed to" in terms of hardware or software.

[0057] In certain situations, the expression "an apparatus configured to" may mean that the apparatus, together with other apparatuses or components, "is capable of".

[0058] For example, the phrase "a processor configured (or set) to perform A, B, and C" can mean a dedicated processor (e.g., an embedded processor) for performing the operations, or a general - purpose processor (e.g., a CPU or an application processor) that can perform the operations by executing one or more software programs stored in a memory device.

[0059] Also, the term "or" means an inclusive or rather than an exclusive or.

[0060] That is, unless otherwise stated or apparent from the context, the expression "x uses a or b" means any one of the natural inclusive permutations.

[0061] Terms such as "... unit" and "[... device]" used hereinafter mean a unit that processes at least one function or operation, which can be embodied in hardware, software, or a combination of hardware and software.

[0062] FIG. 1A and FIG. 1B are diagrams for explaining a triple - gate silicon element that constitutes a general - purpose logic memory cell according to an embodiment of the present invention.

[0063] FIG. 1A illustrates the structure of a triple - gate silicon element that constitutes a general - purpose logic memory cell according to an embodiment of the present invention.

[0064] Referring to FIG. 1A, a triple-gate silicon device 100 according to an embodiment of the present invention includes a drain region 101, a channel region 102, a source region 103, and a gate region. The gate region includes a first and a second programming gate electrode 106 and a control gate electrode 105 formed on a gate insulating film 104.

[0065] As an example, a drain electrode may be connected to the drain region 101 to apply a drain voltage, and a source electrode for applying a source voltage may be connected and formed on the source region 103.

[0066] According to an embodiment of the present invention, the triple-gate silicon device 100 includes a drain region 101, a channel region 102, and a source region 103 that are p-i-n nanostructures.

[0067] As an example, the drain region 101 may be in a p-doped state, the source region 103 may be in an n-doped state, and the channel region 102 may be in an intrinsic state.

[0068] In the channel region 102, the channel region under the first and second programming gate electrodes 106 operates as an n-channel corresponding to the first channel mode when the level of the program voltage V PG is at a positive level, and can operate as a p-channel corresponding to the second channel mode when the level of the program voltage V PG is at a negative level.

[0069] The triple-gate silicon devices 100 can be configured in a plurality to form a general-purpose logic memory cell.

[0070] That is, the triple-gate silicon devices 100 are configured in a plurality to form a general-purpose logic memory cell, but some of the plurality may be composed of first network elements and some may be composed of second network elements.

[0071] The triple-gate silicon device 100 operates in either the first channel mode or the second channel mode in the channel region according to the level of the program voltage V applied via the first and second programming gate electrodes 106. PG Specifically, according to the level of the program voltage V, the channel region under the first and second programming gate electrodes 106 in the channel region can operate in either the first channel mode or the second channel mode.

[0072] In addition, the triple-gate silicon device 100 can be determined to be in either an on state or an off state based on the level of the control voltage V applied via the control gate electrode. CG Specifically, based on the level of the control voltage V, it can be determined to be in either an on state or an off state.

[0073] Therefore, the general-purpose logic memory cell can perform a logic operation function and a memory function based on the level of the output voltage V that changes according to either one of the states in any one of the channel modes that have already been performed. OUT Specifically, based on the level of the output voltage V, it can perform a logic operation function and a memory function.

[0074] That is, the first network element and the second network element can perform a ternary logic operation function and a memory function by determining the level of the output voltage V to be either a positive level, a zero level, or a negative level according to either one of the states in any one of the channel modes that have already been performed. OUT Specifically, by determining the level of the output voltage V, it can perform a ternary logic operation function and a memory function.

[0075] For example, since the first and second programming gate electrodes 106 are electrically connected, the same program voltage V can be applied at once. PG Specifically, the same program voltage V can be applied.

[0076] FIG. 1B illustrates a circuit symbol related to the operating state of the general-purpose logic memory cell according to an embodiment of the present invention.

[0077] Referring to FIG. 1B, the circuit symbol 111 according to an embodiment of the present invention illustrates a circuit symbol when the channel region of the triple-gate silicon device operates in the first channel mode and operates as an n-channel.

[0078] As an example, circuit symbol 110 illustrates the circuit symbol when the channel region of the triple-gate silicon element operates in the second channel mode and operates as a p-channel.

[0079] In circuit symbols 110 and 111, in a nanostructure including a drain region, a channel region, a source region, and a gate region, first and second programming gate electrodes and a control gate electrode are formed in the gate region, a programming gate terminal PG and a control gate terminal CG are connected, a drain electrode is formed in the drain region, a drain terminal D is connected, a source electrode is formed in the source region, and a source terminal S is connected.

[0080] Circuit symbol 111 indicates that the triple-gate silicon element is in the first channel mode state through the channel mode state region.

[0081] In other words, by showing the channel mode state region in a solid form, circuit symbol 111 can indicate that the triple-gate silicon element is operating as an n-channel.

[0082] Circuit symbol 110 indicates that the triple-gate silicon element is in the second channel mode state through the channel mode state region.

[0083] Circuit symbol 110 can indicate that the triple-gate silicon element is operating as a p-channel by showing the channel mode state region in an empty form.

[0084] For example, the triple-gate silicon element can be referred to as a triple-gate feedback field effect element.

[0085] Figures 2A to 2C are diagrams for explaining the operating principle of the triple-gate silicon element according to an embodiment of the present invention.

[0086] FIG. 2A illustrates the operating principle when the triple-gate silicon device according to an embodiment of the present invention operates as a p-channel.

[0087] Referring to FIG. 2A, when a positive voltage is applied through the drain terminal and a negative voltage corresponding to a negative level of the program voltage is applied from the programming gate terminal to the triple-gate silicon device 200 according to an embodiment of the present invention, the channel region under the programming gate electrode PG in the channel region is programmed as a p-channel and operates as a p-channel.

[0088] When the triple-gate silicon device 200 according to an embodiment of the present invention operates as a p-channel, the operating state is determined to be an off state when the level of the control voltage applied through the control gate terminal is higher than the latch-up voltage, which is the voltage at which the current rapidly increases, and is determined to be an on state when the level of the applied control voltage is lower than the latch-up voltage.

[0089] As an example, the triple-gate silicon device is determined to be in an on state or an off state based on the level of the control voltage applied through the control gate terminal.

[0090] The on and off operating states of the triple-gate silicon device can be additionally explained through the energy band 201 corresponding to the off state and the energy band 202 corresponding to the on state.

[0091] When the triple-gate silicon device according to an embodiment of the present invention operates as a p-channel, the energy band 202 when it is in the on state and the energy band 201 when it is in the off state can be confirmed based on the level of the control voltage.

[0092] According to the energy band 201 and the energy band 202, when the channel region operates in the second channel mode corresponding to the p-channel mode in the channel region under the first and second programming gate electrodes, if the level of the control voltage V CG decreases to a level lower than the latch-up voltage, the height of the potential barrier between the channel region under the control gate electrode and the channel region under the first programming gate electrode adjacent to the drain region in the channel region decreases, and a second positive feedback loop is generated in which holes are injected from the drain region due to the decreased potential barrier, resulting in an on state in which current flows.

[0093] That is, the triple-gate silicon device can switch from the energy band 201 to the energy band 202 when the second positive feedback loop occurs.

[0094] It can be confirmed that the injection and accumulation of charges are repeated, a positive feedback loop is generated, and the device switches to the on state in which current flows.

[0095] For example, the second positive feedback loop can be a positive feedback loop in which holes become the majority carriers in the channel region.

[0096] FIG. 2B illustrates the operating principle when the triple-gate silicon device according to an embodiment of the present invention operates as an n-channel.

[0097] Referring to FIG. 2B, when a negative voltage is applied to the triple-gate silicon device 210 according to an embodiment of the present invention via the source terminal and a positive voltage corresponding to a positive level of the program voltage is applied from the programming gate terminal, the channel region under the programming gate electrode PG in the channel region is programmed to an n-channel and operates as an n-channel.

[0098] As an example, the triple-gate silicon device is determined to be in an on state or an off state based on the level of the control voltage applied through the control gate terminal.

[0099] When the triple-gate silicon device 210 according to an embodiment of the present invention operates as an n-channel, the operating state is determined to be on when the level of the control voltage applied through the control gate terminal is higher than the latch-up voltage, which is the voltage at which the current rapidly increases, and may be determined to be off when the level of the applied control gate voltage V CG is lower than the latch-up voltage.

[0100] When the triple-gate silicon device according to an embodiment of the present invention operates as an n-channel, the energy band 211 when it is in the off state is illustrated based on the level of the control voltage, and the energy band 212 when it is in the on state is illustrated.

[0101] Referring to the energy band 211 and the energy band 212, when the channel regions under the first and second programming gate electrodes in the channel region operate in the first channel mode corresponding to the n-channel mode, as the level of the control voltage V CG increases to a level higher than the latch-up voltage, the height of the potential barrier between the channel region under the control gate electrode and the channel region under the second programming gate electrode adjacent to the source region in the channel region decreases, and a first positive feedback loop in which electrons are injected from the source region due to the decreased potential barrier is generated, resulting in an on state in which current flows.

[0102] That is, in the triple-gate silicon device, a first positive feedback loop is generated, and the energy band switches from the energy band 211 to the energy band 212.

[0103] It can be confirmed that the injection and accumulation of charges are repeated to generate a positive feedback loop, and the device switches to the on state in which current flows.

[0104] For example, the first positive feedback loop can be a positive feedback loop in which electrons are majority carriers in the channel region.

[0105] FIG. 2C illustrates the operations associated with the first and second positive feedback loops when the triple-gate silicon device according to an embodiment of the present invention operates as an n-channel and a p-channel.

[0106] Referring to FIG. 2C, graph 220 shows the operating characteristics of the n-channel mode of the triple-gate silicon device, and graph 221 shows the operating characteristics of the p-channel mode of the triple-gate silicon device.

[0107] Graph 220 shows that when the triple-gate silicon device operating in the n-channel mode has an on state and an off state according to the voltage applied to the control gate electrode, if the control gate voltage is lower than the latch-up voltage, which is the voltage at which the current rapidly increases, the flow of electrons and holes is blocked by the potential barrier and the device has an off state, and when the control gate voltage increases and becomes greater than the latch-up voltage, electrons in the source region are injected into the channel over the potential barrier and accumulated in the potential well adjacent to the drain region, indicating that the height of the potential barrier decreases.

[0108] As a result, holes in the drain region are injected into the channel and accumulated in the potential well adjacent to the source region, and the height of the potential barrier decreases.

[0109] The injection and accumulation of charges are repeated to generate a positive feedback loop, and the device enters the on state in which current flows.

[0110] Graph 221 shows that in the case of a triple-gate silicon device operating in p-channel mode, when the control gate voltage is greater than the latch-up voltage, the flow of electrons and holes is blocked by the potential barrier and the device turns off. When the control gate voltage decreases and becomes less than the latch-up voltage, holes in the drain region are injected into the channel over the potential barrier and accumulated in the potential well adjacent to the source region, showing the characteristic that the height of the potential barrier decreases.

[0111] According to an embodiment of the present invention, the triple-gate silicon device can form a first positive feedback loop or a second positive feedback loop according to the level of the control voltage applied to the gate region, and at the same time, can be an element in which the on or off state is variably controlled in the first channel mode and the second channel mode. Here, the first channel mode is an n-channel mode, and the second channel mode is a p-channel mode.

[0112] Also, the triple-gate silicon device is turned on while charge carriers are accumulated in the potential well of the channel region to form a positive feedback loop, which can be utilized as a memory function for storing data in the channel region.

[0113] Therefore, the present invention can implement a general-purpose logic memory cell by utilizing a triple-gate silicon device, which is a silicon-based feedback memory device applying an existing CMOS process.

[0114] FIG. 3 is a diagram for explaining a general-purpose logic memory cell according to an embodiment of the present invention.

[0115] FIG. 3 illustrates a circuit diagram of a general-purpose logic memory cell including a first network element and a second network element using a plurality of triple-gate silicon devices according to an embodiment of the present invention.

[0116] Referring to FIG. 3, a general-purpose logic memory cell 300 according to an embodiment of the present invention is composed of a first network element 310 and a second network element 311, and the first network element 310 and the second network element 311 are composed of a plurality of triple-gate silicon elements 301.

[0117] More specifically, the first network element 310 and the second network element 311 include a first series connection portion in which the drain regions and source regions of two of the four triple-gate silicon elements are connected in series, and a second series connection portion in which the drain regions and source regions of the remaining two triple-gate silicon elements are connected in series. A first parallel connection portion to which a common drain region therebetween is connected, and a second parallel connection portion to which a common source region is connected.

[0118] The first network element 310 can be referred to as a pull-up network element, and the second network element 311 can be referred to as a pull-down network element.

[0119] According to an embodiment of the present invention, the general-purpose logic memory cell 300 can perform ternary logic operation functions and memory functions.

[0120] As an example, the general-purpose logic memory cell 300 performs a ternary logic operation with positive-level, zero-level, and negative-level outputs based on positive-level, zero-level, and negative-level inputs, and supplies a power supply, a voltage corresponding to the voltage applied through the program gate electrode, and the input voltage applied through the control gate electrode to "0" to control the memory function of maintaining the already set voltage state.

[0121] According to an embodiment of the present invention, each of the first network element 310 and the second network element 311 is composed of four triple-gate silicon elements, which can be divided and referred to as two triple-gate silicon elements as the upper side, lower side, left side, and right side, or can be divided and referred to as one triple-gate silicon element as the upper left side, upper right side, lower left side, and lower right side.

[0122] The triple-gate silicon elements arranged at each position can be selectively driven in either the first channel mode or the second channel mode.

[0123] The above-described configuration can be changed according to the arrangement of the network elements and may be differently referred to according to the changed connection configuration.

[0124] The first network element 310 has a drain voltage V among the common voltages applied through the first parallel connection portion of the first network element 310. DD is applied.

[0125] The second network element 311 has a source voltage V among the common voltages applied through the second parallel connection portion of the second network element 311. SS is applied.

[0126] The general-purpose logic memory cell 300 according to an embodiment of the present invention can measure an output voltage V at a portion where the second parallel connection portion of the first network element 310 and the first parallel connection portion of the second network element 311 are connected. OUT is measured.

[0127] The general-purpose logic memory cell 300 is composed of the first network element 310 and the second network element 311, and based on the content measured by the output voltage V of the drain voltage V and the source voltage V according to the operating state of the triple-gate silicon element 301. DD and the source voltage V SS is measured by the output voltage V OUT embodies a logical operation.

[0128] A generic logic memory cell 300 according to one embodiment of the present invention uses a plurality of triple-gate silicon devices.

[0129] Each of the plurality of triple-gate silicon elements includes a drain region, a channel region, and a source region, with a supply voltage applied to the drain region and the source region, and a gate region with first and second programming gate electrodes and a control gate electrode formed over the channel region.

[0130] Also, each of the plurality of triple-gate silicon elements is coupled to a programming voltage V ... PG In response to the level of the control voltage V applied via the control gate electrode, the channel region under the first and second programming gate electrodes operates in one of the first channel mode and the second channel mode. CG Based on the level of the signal, the state can be determined to be either an on state or an off state.

[0131] The first network element 310 and the second network element 311 set the output voltage V to one of a positive level, a zero level, and a negative level according to one state already determined in one channel mode already performed. OUT By determining the level of, ternary logic functions and memory functions can be performed.

[0132] Ternary logic functions are logic functions associated with TNOT, TYES, TNAND, TNOR, TAND, TOR, TXNOR and TXOR gates.

[0133] Therefore, the present invention can realize a universal logic memory cell that provides ternary logic operation functions and memory functions using triple-gate silicon devices driven by a positive feedback loop.

[0134] In addition, the present invention can embody a general-purpose logic memory cell that performs all ternary basic logical operations in a single structure using a triple-gate silicon element and stores the operation results.

[0135] FIG. 4A is a diagram for explaining the operation of the TNOT gate of the general-purpose logic memory cell according to an embodiment of the present invention.

[0136] FIG. 4A illustrates a circuit diagram and a timing diagram in relation to the operation of the TNOT gate of the general-purpose logic memory cell according to an embodiment of the present invention.

[0137] Referring to FIG. 4A, in the general-purpose logic memory cell 400 according to an embodiment of the present invention, based on the programming voltage applied through the programming gate terminal PG, the triple-gate silicon element constituting the first network element operates in the second channel mode, and the triple-gate silicon element constituting the second network element operates in the first channel mode.

[0138] At this time, when the level of the control voltage V, which is the input voltage IN applied through the control gate terminal CG, is a negative level, the level of the output voltage V measured through the output terminal is a positive level, and when the level of the control voltage V is a positive level, the level of the output voltage V is a negative level, and it can perform a logical operation function corresponding to the operation of the TNOT gate. CG OUT CG OUT

[0139] In addition, when the level of the control voltage V is a zero level, the general-purpose logic memory cell 400 can perform a logical operation function corresponding to the operation of the TNOT gate, which determines the level of the output voltage V to be a zero level. CG OUT

[0140] The timing diagram 401 shows the negative-level input voltage V corresponding to "-1"​​​​​​IN When IN is applied, it exemplifies that the output voltage V at the positive level corresponding to "1" OUT is logically operated and output.

[0141] Also, the timing diagram 401 exemplifies that when the input voltage V at the positive level corresponding to "1" IN is applied, the output voltage V at the negative level corresponding to "-1" OUT is logically operated and output.

[0142] Also, the timing diagram 401 exemplifies that when the input voltage V at the zero level corresponding to "0" IN is applied, the output voltage V at the zero level corresponding to "0" OUT is logically operated and output.

[0143] Also, it shows that it performs a memory function of maintaining (holding) the calculated logical value even when the supply voltage V SUP , the program voltage V PG , and the input voltage V IN are removed.

[0144] For example, the supply voltage V SUP is composed of the drain voltage V DD and the source voltage V SS , and the program voltage V PG is composed of the program voltage V PG N corresponding to the n-channel, and the program voltage V PG P corresponding to the p-channel.

[0145] Figure 4B is a diagram for explaining the operation of the TYES gate of the general-purpose logic memory cell according to an embodiment of the present invention.

[0146] Figure 4B exemplifies a circuit diagram and a timing diagram in relation to the operation of the TYES gate of the general-purpose logic memory cell according to an embodiment of the present invention.

[0147] Referring to FIG. 4B, in the general-purpose logic memory cell 410 according to an embodiment of the present invention, based on the programming voltage applied through the programming gate terminal PG, the triple-gate silicon element constituting the first network element operates in the first channel mode, and the triple-gate silicon element constituting the second network element operates in the second channel mode.

[0148] At this time, when the level of the control voltage V, which is the input voltage IN applied through the control gate terminal CG, is at a positive level, the output voltage V measured through the output terminal CG has a positive level, and when the level of the control voltage V OUT is at a negative level, the output voltage V CG has a negative level, and it can perform a logic operation function corresponding to the operation of the TYES gate. OUT

[0149] Also, when the level of the control voltage V CG is at a zero level, the general-purpose logic memory cell 410 can perform a logic operation function corresponding to the operation of the TYES gate, which determines the level of the output voltage V OUT to be at a zero level.

[0150] The timing diagram 411 illustrates that when a negative input voltage V IN corresponding to "-1" is applied, a negative output voltage V OUT corresponding to "-1" is logically operated and output.

[0151] Also, the timing diagram 411 illustrates that when a positive input voltage V IN corresponding to "1" is applied, a positive output voltage V OUT corresponding to "1" is logically operated and output.

[0152] Also, the timing diagram 411 illustrates that when a zero input voltage V IN corresponding to "0" is applied, a zero output voltage V corresponding to "0"OUT illustrates that it is logically operated and output.

[0153] Also, it shows that it performs a memory function of maintaining (holding) the calculated logical value even when the supply voltage V SUP , the program voltage V PG , and the input voltage V IN are removed.

[0154] For example, the supply voltage V SUP is composed of the drain voltage V DD and the source voltage V SS , and the program voltage V PG is composed of the program voltage V PG N corresponding to the n-channel, and the program voltage V PG P corresponding to the p-channel.

[0155] FIG. 5A is a diagram for explaining the operation of the TNAND gate of the general-purpose logic memory cell according to an embodiment of the present invention.

[0156] FIG. 5A illustrates a circuit diagram and a timing diagram in relation to the operation of the TNAND gate of the general-purpose logic memory cell according to an embodiment of the present invention.

[0157] Referring to FIG. 5A, in the general-purpose logic memory cell 500 according to an embodiment of the present invention, based on the programming voltage applied through the programming gate terminal PG, the triple-gate silicon element constituting the first network element operates in the second channel mode, and the triple-gate silicon element constituting the second network element operates in the first channel mode.

[0158] Also, in the general-purpose logic memory cell 500, the first control voltage IN1 among the control voltages V CG is applied to the left side of the first network element and the upper side of the second network element, and the second control voltage IN2 among the control voltages V CG is applied to the right side of the first network element and the lower side of the second network element.

[0159] Accordingly, when either one of the levels of the first control voltage IN1 and the second control voltage IN2 is at a negative level, the general-purpose logic memory cell 500 determines the level of the output voltage V OUT to be at a positive level.

[0160] Also, when both of the levels of the first control voltage IN1 and the second control voltage IN2 are at positive levels, the general-purpose logic memory cell 500 can perform the logic operation function of a TNAND gate that determines the level of the output voltage V OUT to be at a negative level.

[0161] Also, when both of the levels of the first control voltage IN1 and the second control voltage IN2 are at zero levels, or when one of the levels is at a zero level and the other level is at a positive level, the general-purpose logic memory cell 500 can perform a ternary logic operation function by performing the logic operation function of a TNAND gate that determines the level of the output voltage V OUT to be at a zero level.

[0162] Timing diagram 501 shows that when inputs corresponding to combinations of “-1”, “0”, and “1” are applied to two input voltages V IN1 , V IN2 , values corresponding to “-1”, “0”, and “1” are calculated at the output voltage V OUT , thereby performing a ternary logic operation function.

[0163] Also, it shows that a memory function of maintaining (holding) the calculated logic value is performed even when the supply voltage V SUP , the program voltage V PG , and the input voltages V IN1 , V IN2 are removed.

[0164] For example, the supply voltage V SUP is the drain voltage V DD and the source voltage V SSis composed of a program voltage V PG is the program voltage V corresponding to the n-channel PG N , and the program voltage V corresponding to the p-channel PG P .

[0165] FIG. 5B is a diagram for explaining the operation of the TNOR gate of the general-purpose logic memory cell according to an embodiment of the present invention.

[0166] FIG. 5B illustrates a circuit diagram and a timing diagram in relation to the operation of the TNOR gate of the general-purpose logic memory cell according to an embodiment of the present invention.

[0167] Referring to FIG. 5B, in the general-purpose logic memory cell 510 according to an embodiment of the present invention, based on the programming voltage applied through the programming gate terminal PG, the triple-gate silicon element constituting the first network element operates in the second channel mode, and the triple-gate silicon element constituting the second network element operates in the first channel mode.

[0168] Also, in the general-purpose logic memory cell 510, among the control voltages V CG , the first control voltage IN1 is applied to the upper side of the first network element and the left side of the second network element, and among the control voltages V CG , the second control voltage IN2 is applied to the lower side of the first network element and the right side of the second network element.

[0169] Thereby, when either one of the levels of the first control voltage V IN1 and the second control voltage V IN2 is at a positive level, the level of the output voltage V OUT is determined to be at a negative level.

[0170] Also, in the general-purpose logic memory cell 510, the first control voltage V IN1 and the second control voltage V IN2When both levels are negative levels, the output voltage V OUT is determined to be a positive level.

[0171] Also, the general-purpose logic memory cell 510 performs a TNOR operation among ternary logic operation functions that determine the level of the output voltage V IN1 and the second control voltage V IN2 to be a zero level when both levels are zero levels, or when one of the levels is a zero level and the other level is a negative level. OUT The timing diagram 511 shows that a ternary logic operation function is performed by calculating values corresponding to "-1", "0", and "1" for the output voltage V

[0172] when inputs corresponding to combinations of " -1", "0", and "1" are applied to two input voltages V IN1 , V IN2 . OUT It also shows that a memory function of maintaining (holding) the calculated logical value is performed even when the supply voltage V

[0173] , the program voltage V SUP , and the input voltages V PG , V IN1 , V IN2 are removed.

[0174] For example, the supply voltage V SUP is composed of the drain voltage V DD and the source voltage V SS , and the program voltage V PG is composed of the program voltage V PG N corresponding to the n-channel and the program voltage V PG P corresponding to the p-channel.

[0175] FIG. 6A is a diagram for explaining the operation of the TAND gate of the general-purpose logic memory cell according to an embodiment of the present invention.

[0176] FIG. 6A illustrates a circuit diagram and a timing diagram in relation to the operation of the TAND gate of a general-purpose logic memory cell according to an embodiment of the present invention.

[0177] Referring to FIG. 6A, in a general-purpose logic memory cell 600 according to an embodiment of the present invention, based on a programming voltage applied through a programming gate terminal PG, a triple-gate silicon element constituting a first network element operates in a first channel mode, and a triple-gate silicon element constituting a second network element operates in a second channel mode.

[0178] Also, in the general-purpose logic memory cell 600, a first control voltage IN1 among the control voltages V CG is applied to the upper side of the first network element and the left side of the second network element, and a second control voltage IN2 among the control voltages V CG is applied to the lower side of the first network element and the right side of the second network element.

[0179] Thus, when either one of the levels of the first control voltage V IN1 and the second control voltage V IN2 is a negative level, the general-purpose logic memory cell 600 performs a logical operation to determine the level of the output voltage V OUT as a negative level.

[0180] Also, when both of the levels of the first control voltage V IN1 and the second control voltage V IN2 are positive levels, the general-purpose logic memory cell 600 determines the level of the output voltage V OUT as a positive level.

[0181] Also, when both of the levels of the first control voltage V IN1 and the second control voltage V IN2 are zero levels, or when one of the levels is a zero level and the other level is a positive level, the output voltage V OUTPerforms a ternary logic operation function that determines the level of [[ID=]] as the zero level.

[0182] That is, the general-purpose logic memory cell 600 performs the operation of a TAND gate.

[0183] Timing diagram 601 shows that when inputs corresponding to combinations of "-1", "0", and "1" are applied to two input voltages V IN1 , V IN2 , a ternary logic operation function is performed by calculating values corresponding to "-1", "0", and "1" at the output voltage V OUT .

[0184] Also, it shows that a memory function of maintaining (holding) the calculated logical value is performed even when the supply voltage V SUP , the program voltage V PG , and the input voltages V IN1 , V IN2 are removed.

[0185] For example, the supply voltage V SUP is composed of the drain voltage V DD and the source voltage V SS , and the program voltage V PG is composed of the program voltage V PG N corresponding to the n-channel, and the program voltage V PG P corresponding to the p-channel.

[0186] FIG. 6B is a diagram for explaining the operation of the TOR gate of the general-purpose logic memory cell according to an embodiment of the present invention.

[0187] FIG. 6B illustrates a circuit diagram and a timing diagram in relation to the operation of the TOR gate of the general-purpose logic memory cell according to an embodiment of the present invention.

[0188] Referring to FIG. 6B, in a general-purpose logic memory cell 610 according to an embodiment of the present invention, based on a programming voltage applied through a programming gate terminal PG, a triple-gate silicon element constituting a first network element operates in a first channel mode, and a triple-gate silicon element constituting a second network element operates in a second channel mode.

[0189] Also, in the general-purpose logic memory cell 610, a first control voltage IN1 among the control voltages V CG is applied to the left side of the first network element and the upper side of the second network element, and a second control voltage IN2 among the control voltages V CG is applied to the right side of the first network element and the lower side of the second network element.

[0190] Thereby, when either one of the levels of the first control voltage V IN1 and the second control voltage V IN2 is at a positive level, the level of the output voltage V OUT is determined to be at a positive level.

[0191] Also, in the general-purpose logic memory cell 610, when both levels of the first control voltage V IN1 and the second control voltage V IN2 are at negative levels, the level of the output voltage V OUT is determined to be at a negative level.

[0192] Also, in the general-purpose logic memory cell 610, when both levels of the first control voltage V IN1 and the second control voltage V IN2 are at zero levels, or when one level is at zero level and the other level is at a negative level, the general-purpose logic memory cell 610 performs a ternary logic operation function of determining the level of the output voltage V OUT to be at zero level.

[0193] Timing diagram 611 shows two input voltages V IN1 ,V IN2When an input corresponding to a combination of “-1”, “0”, and “1” is applied, the output voltage V OUT shows that a TOR logic operation is performed in relation to a ternary logic operation function by calculating values corresponding to “-1”, “0”, and “1” with

[0194] Also, it shows that a memory function is performed to maintain (Hold) the calculated logical value even when the supply voltage V SUP , the program voltage V PG , the input voltage V IN1 , V IN2 are removed.

[0195] For example, the supply voltage V SUP is composed of the drain voltage V DD and the source voltage V SS , and the program voltage V PG is composed of the program voltage V PG N corresponding to the n-channel, and the program voltage V PG P corresponding to the p-channel.

[0196] FIG. 7A is a diagram for explaining the operation of the TXNOR gate of the general-purpose logic memory cell according to an embodiment of the present invention.

[0197] FIG. 7A illustrates a circuit diagram and a timing diagram in relation to the operation of the TXNOR gate of the general-purpose logic memory cell according to an embodiment of the present invention.

[0198] Referring to FIG. 7A, in the general-purpose logic memory cell 700 according to an embodiment of the present invention, the left side of the triple-gate silicon element constituting the first network element operates in the first channel mode, the right side operates in the second channel mode, the upper left side of the triple-gate silicon element constituting the second network element operates in the second channel mode, the upper right side operates in the first channel mode, the lower left side operates in the first channel mode, and the lower right side operates in the second channel mode.

[0199] A general-purpose logic memory cell 700 according to an embodiment of the present invention has a control voltage V CG Among them, the first control voltage V IN1 is applied above the first network element and the second network element, and the control voltage V CG Among them, the second control voltage V IN2 is applied below the first network element and the second network element.

[0200] According to an embodiment of the present invention, when both the levels of the first control voltage V IN1 and the second control voltage V IN2 are negative levels, the level of the output voltage V OUT is output as a positive level.

[0201] The general-purpose logic memory cell 700 has a first control voltage V IN1 and a second control voltage V IN2 When both levels are positive levels, the level of the output voltage V OUT is output as a positive level.

[0202] Also, when either one of the levels of the first control voltage V IN1 and the second control voltage V IN2 is at the zero level, the level of the output voltage V OUT is output as a negative level.

[0203] Also, when any one of the levels of the first control voltage V IN1 and the second control voltage V IN2 is at the zero level, the general-purpose logic memory cell 700 can perform a ternary logic operation function of determining the level of the output voltage V OUT as the zero level.

[0204] The timing diagram 701 shows two input voltages V IN1 , V IN2When an input corresponding to a combination of “-1”, “0”, and “1” is applied, the output voltage V OUT performs a TXNOR logic operation in relation to a ternary logic operation function by calculating values corresponding to “-1”, “0”, and “1”.

[0205] Also, when the supply voltage V SUP , the program voltage V PG , and the input voltage V IN1 , V IN2 are removed, it indicates that it performs a memory function of maintaining (holding) the calculated logical value.

[0206] For example, the supply voltage V SUP is composed of the drain voltage V DD and the source voltage V SS , and the program voltage V PG is composed of the program voltage V PG N corresponding to the n-channel, and the program voltage V PG P corresponding to the p-channel.

[0207] FIG. 7B is a diagram for explaining the operation of the TXOR gate of the general-purpose logic memory cell according to an embodiment of the present invention.

[0208] FIG. 7B exemplifies a circuit diagram and a timing diagram in relation to the operation of the TXOR gate of the general-purpose logic memory cell according to an embodiment of the present invention.

[0209] Referring to FIG. 7B, in the general-purpose logic memory cell 710 according to an embodiment of the present invention, the upper left side of the triple-gate silicon element constituting the first network element operates in the second channel mode, the upper right side operates in the first channel mode, the lower left side operates in the first channel mode, the lower right side operates in the second channel mode, the left side of the triple-gate silicon element constituting the second network element operates in the first channel mode, and the right side operates in the second channel mode.

[0210] A general-purpose logic memory cell 710 according to an embodiment of the present invention has a control voltage V CG Of which, the first control voltage V IN1 Is applied above the first network element and the second network element, and the control voltage V CG Of which, the second control voltage V IN2 Is applied below the first network element and the second network element.

[0211] Also, when both the levels of the first control voltage V IN1 And the second control voltage V IN2 Are negative levels or positive levels, the level of the output voltage V OUT Is determined to be a negative level.

[0212] Also, when the levels of the first control voltage V IN1 And the second control voltage V IN2 Are negative levels or positive levels such that they are opposite, the level of the output voltage V OUT Is output as a positive level.

[0213] Also, when any one of the levels of the first control voltage V IN1 And the second control voltage V IN2 Is a zero level, it can perform a ternary logic operation function of determining the level of the output voltage V OUT To be a zero level.

[0214] Timing diagram 711 shows that when inputs corresponding to combinations of "-1", "0", and "1" are applied to two input voltages V IN1 , V IN2 , the values corresponding to "-1", "0", and "1" are calculated at the output voltage V OUT To perform a TXOR logic operation in relation to the ternary logic operation function.

[0215] Also, the supply voltage V SUP , the program voltage VPG , the input voltage V IN1 , V IN2 indicates that it performs a memory function of maintaining (holding) the calculated logical value even when is removed.

[0216] For example, the supply voltage V SUP is composed of the drain voltage V DD and the source voltage V SS , and the program voltage V PG corresponds to the program voltage V PG N for the n-channel, and the program voltage V PG P for the p-channel.

[0217] Therefore, the present invention can improve the processing speed and the limits of integration due to the data bottleneck phenomenon through the integration of logical operations and storage functions.

[0218] In addition, the present invention can improve the standby power efficiency with excellent memory characteristics of maintaining the logical operation value without changing the structure and external bias by using the channel mode reconfiguration characteristics.

[0219] In the above-described specific embodiments, the components included in the invention are represented as singular or plural by the presented specific embodiments.

[0220] However, the singular or plural expressions are selected to suit the situations presented for the convenience of explanation, and the above-described embodiments are not limited to singular or plural components. A component expressed in plural may be composed of a single one, and a component expressed in singular may be composed of plural ones.

[0221] On the other hand, although specific embodiments have been described in the description of the invention, various modifications are possible as long as they do not deviate from the scope of the technical idea included in the various embodiments.

[0222] Therefore, the scope of the present invention should not be defined as being limited to the described embodiments, but should be defined not only by the claims described below but also by equivalents to these claims.

Claims

1. including a first network element and a second network element using a plurality of triple-gate silicon elements, Each of the plurality of triple-gate silicon devices includes a drain region, a channel region, and a source region, a supply voltage is applied to the drain region and the source region, and includes a gate region in which first and second programming gate electrodes and a control gate electrode are formed on the channel region. Depending on the level of the program voltage (V ＰＧ ), in the channel region, the channel region under the first and second programming gate electrodes operates in either the first channel mode or the second channel mode, and based on the level of the control voltage (V ＣＧ ), it is determined to be in either an on state or an off state. The first network element and the second network element output a voltage (V ＯＵＴ ), by determining the level of which to be one of a positive level, a zero level, and a negative level according to any one of the states in any one of the performed channel modes, perform a ternary logic operation function and a memory function, and are characterized by a general-purpose logic memory cell.

2. The first network element and the second network element are composed of a first parallel connection part to which a common drain region is connected between a first series connection part in which drain regions and source regions of two of the four triple-gate silicon elements among the plurality of triple-gate silicon elements are connected in series, and a second series connection part in which drain regions and source regions of the remaining two triple-gate silicon elements are connected in series, and a second parallel connection part to which a common source region is connected. A drain voltage (V ＤＤ ) among the common voltages is applied through the first parallel connection part of the first network element, and a source voltage (V ＳＳ ) among the common voltages is applied through the second parallel connection part of the second network element. An output voltage (V ＯＵＴ ) is measured as any one of the parts where the second parallel connection part of the first network element and the first parallel connection part of the second network element are connected. The general-purpose logic memory cell according to claim 1, characterized in that.

3. When the first network element operates in the second channel mode and the second network element operates in the first channel mode, when the level of the control voltage (V ＣＧ ), the level of the output voltage (V ＯＵＴ ) is determined to be a positive level, and when the level of the control voltage (V ＣＧ ) is a positive level, the level of the output voltage (V ＯＵＴ ) is determined to be a negative level, and when the level of the control voltage (V ＣＧ ) is a zero level, the level of the output voltage (V ＯＵＴ ) is determined to be a zero level, and the ternary logic operation function is performed. The general-purpose logic memory cell according to claim 2, characterized in that.

4. When the first network element operates in the first channel mode and the second network element operates in the second channel mode, when the level of the control voltage (V ＣＧ ), determine that the level of the output voltage (V ＯＵＴ ) is a negative level, and when the level of the control voltage (V ＣＧ ) is a positive level, determine that the level of the output voltage (V ＯＵＴ ) is a positive level, and when the level of the control voltage (V ＣＧ ) is a zero level, perform the ternary logic operation function of determining that the level of the output voltage (V ＯＵＴ ) is a zero level. The general-purpose logic memory cell according to claim 2, characterized by this.

5. The first network element operates in the second channel mode, the second network element operates in the first channel mode, and the control voltage (V ＣＧ ), among which the first control voltage (V ＩＮ１ ), is applied to the left side of the first network element and the upper side of the second network element, and the control voltage (V ＣＧ ), among which the second control voltage (V ＩＮ２ ), is applied to the right side of the first network element and the lower side of the second network element. When either one of the levels of the first control voltage (V ＩＮ１ ) and the second control voltage (V ＩＮ２ ) is a negative level, the level of the output voltage (V ＯＵＴ ) is determined to be a positive level. When both of the levels of the first control voltage (V ＩＮ１ ) and the second control voltage (V ＩＮ２ ) are positive levels, the level of the output voltage (V ＯＵＴ ) is determined to be a negative level. When both of the levels of the first control voltage (V ＩＮ１ ) and the second control voltage (V ＩＮ２ ) are zero levels, or when one of the levels is a zero level and the other one is a positive level, the level of the output voltage (V ＯＵＴ ) is determined to be a zero level, performing the ternary logic operation function as described above. The general-purpose logic memory cell according to claim 2, characterized in that.

6. The first network element operates in the second channel mode, the second network element operates in the first channel mode, and the control voltage (V ＣＧ ), among which the first control voltage (V ＩＮ１ ), is applied to the upper side of the first network element and the left side of the second network element, and the control voltage (V ＣＧ ), among which the second control voltage (V ＩＮ２ ), is applied to the lower side of the first network element and the right side of the second network element. When either one of the levels of the first control voltage (V ＩＮ１ ) and the second control voltage (V ＩＮ２ ) is at a positive level, the level of the output voltage (V ＯＵＴ ) is determined to be at a negative level. When both levels of the first control voltage (V ＩＮ１ ) and the second control voltage (V ＩＮ２ ) are at negative levels, the level of the output voltage (V ＯＵＴ ) is determined to be at a positive level. When both the first control voltage (V ＩＮ１ ) and the second control voltage (V ＩＮ２ ) are at zero levels, or when one of the levels is at a zero level and the other level is at a negative level, the level of the output voltage (V ＯＵＴ ) is determined to be at a zero level, and the ternary logic operation function is performed. The general-purpose logic memory cell according to claim 2, characterized in that it performs the above.

7. The first network element operates in the first channel mode, the second network element operates in the second channel mode, and the control voltage (V ＣＧ ), among which the first control voltage (V ＩＮ１ ), is applied to the upper side of the first network element and the left side of the second network element, and the control voltage (V ＣＧ ), among which the second control voltage (V ＩＮ２ ), is applied to the lower side of the first network element and the right side of the second network element. When either one of the levels of the first control voltage (V ＩＮ１ ) and the second control voltage (V ＩＮ２ ) is a negative level, the level of the output voltage (V ＯＵＴ ) is determined to be a negative level. When both levels of the first control voltage (V ＩＮ１ ) and the second control voltage (V ＩＮ２ ) are positive levels, the level of the output voltage (V ＯＵＴ ) is determined to be a positive level. When both levels of the first control voltage (V ＩＮ１ ) and the second control voltage (V ＩＮ２ ) are zero levels, or when one of the levels is a zero level and the other level is a positive level, the general-purpose logic memory cell according to claim 2, which is characterized by performing the ternary logic operation function of determining the level of the output voltage (V ＯＵＴ ) to be a zero level.

8. The first network element operates in the second channel mode, the second network element operates in the first channel mode, and the control voltage (V ＣＧ ), among which the first control voltage (V ＩＮ１ ), is applied to the left side of the first network element and the upper side of the second network element, and the control voltage (V ＣＧ ), among which the second control voltage (V ＩＮ２ ), is applied to the right side of the first network element and the lower side of the second network element. When either one of the levels of the first control voltage (V ＩＮ１ ) and the second control voltage (V ＩＮ２ ) is at a positive level, the level of the output voltage (V ＯＵＴ ) is determined to be at a positive level. When both levels of the first control voltage (V ＩＮ１ ) and the second control voltage (V ＩＮ２ ) are at negative levels, the level of the output voltage (V ＯＵＴ ) is determined to be at a negative level. When both levels of the first control voltage (V ＩＮ１ ) and the second control voltage (V ＩＮ２ ) are at zero levels, or when one of the levels is at a zero level and the other level is at a negative level, the level of the output voltage (V ＯＵＴ ) is determined to be at a zero level, and the ternary logic operation function is performed. The general-purpose logic memory cell according to claim 2, characterized in that it performs the above.

9. The left side of the first network element operates in the first channel mode, the right side of the first network element operates in the second channel mode, the upper left side of the second network element operates in the second channel mode, the upper right side of the second network element operates in the first channel mode, the lower left side of the second network element operates in the first channel mode, the lower right side of the second network element operates in the second channel mode, and the control voltage (V ＣＧ ), among which the first control voltage (V ＩＮ１ ), is applied to the upper sides of the first network element and the second network element, and the control voltage (V ＣＧ ), among which the second control voltage (V ＩＮ２ ), is applied to the lower sides of the first network element and the second network element. When the levels of the first control voltage (V ＩＮ１ ) and the second control voltage (V ＩＮ２ ) are the same, either negative level or positive level, the level of the output voltage (V ＯＵＴ ) is determined to be a positive level. When the levels of the first control voltage (V ＩＮ１ ) and the second control voltage (V ＩＮ２ ) are opposite, either negative level or positive level, the level of the output voltage (V ＯＵＴ ) is determined to be a negative level. When either one of the levels of the first control voltage (V ＩＮ１ ) and the second control voltage (V ＩＮ２ ) is a zero level, the level of the output voltage (V ＯＵＴ ) is determined to be a zero level, and the ternary logic operation function is performed. The general-purpose logic memory cell according to claim 2, characterized by performing the above.

10. The upper left side of the first network element operates in the second channel mode, the upper right side of the first network element operates in the first channel mode, the lower left side of the first network element operates in the first channel mode, the lower right side of the first network element operates in the second channel mode, the left side of the second network element operates in the first channel mode, the right side of the second network element operates in the second channel mode, and the control voltage (V ＣＧ ), among which the first control voltage (V ＩＮ１ ), is applied to the upper sides of the first network element and the second network element, and the control voltage (V ＣＧ ), among which the second control voltage (V ＩＮ２ ), is applied to the lower sides of the first network element and the second network element. When both the levels of the first control voltage (V ＩＮ１ ), and the second control voltage (V ＩＮ２ ) are positive levels, the level of the output voltage (V ＯＵＴ ) is determined to be a negative level. When both the levels of the first control voltage (V ＩＮ１ ) and the second control voltage (V ＩＮ２ ) are negative levels, the level of the output voltage (V ＯＵＴ ) is determined to be a negative level. When the levels of the first control voltage (V ＩＮ１ ) and the second control voltage (V ＩＮ２ ) are negative or positive levels such that they are opposite, the level of the output voltage (V ＯＵＴ ) is determined to be a positive level. When either one of the levels of the first control voltage (V ＩＮ１ ) and the second control voltage (V ＩＮ２ ) is a zero level, the level of the output voltage (V ＯＵＴ ) is determined to be a zero level. The general-purpose logic memory cell according to claim 2, which performs the ternary logic operation function as described above.

11. the drain region is in a p-doped state, the source region is in an n-doped state, the channel region is in an intrinsic state, In the channel region, the channel region under the first and second programming gate electrodes operates as an n-channel corresponding to the first channel mode when the level of the program voltage (V ＰＧ ) is a positive level, and operates as a p-channel corresponding to the second channel mode when the level of the program voltage (V ＰＧ ) is a negative level. The general-purpose logic memory cell according to claim 2, characterized in that.

12. The drain voltage (V ＤＤ ) applied to the drain region, the source voltage (V ＳＳ ) applied to the source region, the program voltage (V ＰＧ ), and the control voltage (V ＣＧ ) are applied at zero level, and the general-purpose logic memory cell according to claim 11, characterized in that the memory function is performed while maintaining the level of the output voltage (V ＯＵＴ ).

13. Each of the plurality of triple-gate silicon devices has a channel region under the first and second programming gate electrodes in the channel region. When operating in the first channel mode, the applied control gate voltage (V ＣＧ ), if the level is higher than the latch-up voltage which is the voltage at which the current rapidly increases, is determined to be in the on state, and the applied control gate voltage (V ＣＧ ), if the level is lower than the latch-up voltage, is determined to be in the off state. The general-purpose logic memory cell according to claim 1, characterized in that.

14. Each of the plurality of triple-gate silicon devices has a channel region under the first and second programming gate electrodes in the channel region. When operating in the first channel mode, when the level of the applied control voltage (V ＣＧ ), increases to a level higher than the latch-up voltage, the height of the potential barrier between the channel region under the control gate electrode and the channel region under the second programming gate electrode adjacent to the source region in the channel region decreases, and a first positive feedback loop in which electrons are injected from the source region due to the lowered potential barrier occurs, and the general-purpose logic memory cell according to claim 13, characterized in that it enters the on state in which current flows.

15. Each of the plurality of triple-gate silicon elements is such that when the channel region under the first and second programming gate electrodes in the channel region operates in the second channel mode, the level of the applied control gate voltage (V ＣＧ ), which is the voltage at which the current rapidly increases, is higher than the latch-up voltage, and is determined to be in the off state, and when the level of the applied control gate voltage (V ＣＧ ) is lower than the latch-up voltage, it is determined to be in the on state. The general-purpose logic memory cell according to claim 1, characterized in that.

16. Each of the plurality of triple-gate silicon elements has a channel region under the first and second programming gate electrodes in the channel region. When operating in the second channel mode, when the level of the applied control voltage (V ＣＧ ) decreases to a level lower than the latch-up voltage, the height of the potential barrier between the channel region under the control gate electrode and the channel region under the first programming gate electrode adjacent to the drain region in the channel region decreases, and a second positive feedback loop through which holes are injected from the drain region due to the lowered potential barrier is generated, and the general-purpose logic memory cell according to claim 15, characterized in that it enters the on state in which current flows.

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