Substrate structure designed for power and RF application

Abstract

To provide a method and system suitable for use in an epitaxial growth process for substrate structures applicable to various semiconductor processing operations.SOLUTION: A substrate 100 includes a support structure having a core 110 made of a polycrystalline ceramic material, a first adhesive layer 112 bonded to the core, a conductive layer 114 bonded to the first adhesive layer, a second adhesive layer 116 bonded to the conductive layer, and a barrier layer 118 bonded to the second adhesive layer. The substrate further includes a bonding layer 120 bonded to the support structure, a substantially single-crystal layer 122 bonded to the bonding layer and including at least one of silicon carbide, sapphire, or gallium nitride, and an epitaxial material 130 bonded to the substantially single-crystal layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Cross - Reference to Related Applications

[0001] This application claims priority based on U.S. Provisional Patent Application No. 62 / 350,084, entitled "ENGINEERED SUBSTRATE STRUCTURE FOR POWER AND RF APPLICATIONS", filed on June 14, 2016, and U.S. Provisional Patent Application No. 62 / 350,077, entitled "ENGINEERED SUBSTRATE STRUCTURE AND METHOD OF MANUFACTURE", filed on June 14, 2016, the disclosures of which are hereby incorporated by reference in their entireties for all purposes.

[0002]

[0002] The following two U.S. patent applications were filed simultaneously with this application, and the disclosures of these two applications are hereby incorporated by reference in their entireties for all purposes.

[0003]

[0003] Application No. 15 / 621,335, entitled "ENGINEERED SUBSTRATE STRUCTURE FOR POWER AND RF APPLICATIONS", filed on June 13, 2017 (Attorney Docket No. 098825 - 1049529 - 001110US).

[0004]

[0004] Application No. 15 / 621,338, entitled "ENGINEERED SUBSTRATE STRUCTURE AND METHOD OF MANUFACTURE", filed on June 13, 2017 (Attorney Docket No. 098825 - 1049532 - 001610US).

Background Art

[0005]

[0005] A light-emitting diode (LED) structure is typically grown epitaxially on a sapphire substrate. Currently, many products use LED devices including lighting, computer monitors, and other display devices.

[0006]

[0006] The growth of a gallium nitride-based LED structure on a sapphire substrate is a heteroepitaxial growth process because the substrate and the epitaxial layer are composed of different materials. Due to the heteroepitaxial growth process, the epitaxially grown material may exhibit various adverse effects including a decrease in uniformity and metrics related to the electronic / optical properties of the epitaxial layer. Therefore, improved methods and systems related to the epitaxial growth process and substrate structure are needed in the art.

Summary of the Invention

[0007]

[0007] The present invention generally relates to a designed substrate structure. More specifically, the present invention relates to methods and systems suitable for use in an epitaxial growth process. As a mere example, the present invention is applied to methods and systems for providing a substrate structure suitable for epitaxial growth, the structure of which is characterized by a coefficient of thermal expansion (CTE) that substantially matches that of the epitaxial layer growing thereon. The method and technology can be applied to various semiconductor processing operations.

[0008]

[0008] According to one embodiment of the present invention, a substrate is provided. The substrate includes a support structure comprising a polycrystalline ceramic core, a first adhesive layer bonded to the polycrystalline ceramic core, a conductive layer bonded to the first adhesive layer, a second adhesive layer bonded to the conductive layer, and a barrier layer bonded to the second adhesive layer. The substrate also includes a silicon oxide layer bonded to the support structure, a substantially single-crystalline silicon layer bonded to the silicon oxide layer, and an epitaxial III-V layer bonded to the substantially single-crystalline silicon layer. The substrate also includes a silicon oxide layer bonded to the support structure, a substantially single-crystalline silicon layer bonded to the silicon oxide layer, and an epitaxial III-V layer bonded to the substantially single-crystalline silicon layer.

[0009] According to another embodiment of the present invention, a method for manufacturing a substrate is provided. The method includes preparing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core in a first adhesive shell, encapsulating the first adhesive shell in a conductive shell, encapsulating the conductive shell in a second adhesive shell, and encapsulating the second adhesive shell in a barrier shell to form a support structure. The method also includes bonding a bonding layer to the support structure, bonding a substantially single-crystalline silicon layer to the bonding layer, forming an epitaxial silicon layer by epitaxial growth on the substantially single-crystalline silicon layer, and forming an epitaxial III-V layer by epitaxial growth on the epitaxial silicon layer.

[0010] According to a particular embodiment of the present invention, a designed substrate structure is provided. The designed substrate structure includes a support structure, a bonding layer coupled to the support structure, a substantially single-crystalline silicon layer coupled to the bonding layer, and an epitaxial single-crystalline silicon layer coupled to the substantially single-crystalline silicon layer. The support structure includes a polycrystalline ceramic core, a first adhesive layer coupled to the polycrystalline ceramic core, a conductive layer coupled to the first adhesive layer, a second adhesive layer coupled to the conductive layer, and a barrier shell coupled to the second adhesive layer.

[0011]

[0011] Many advantages are achieved by the present invention over the prior art. For example, embodiments of the present invention provide a substrate structure designed with CTE matching for a gallium nitride-based epitaxial layer suitable for use in optical, electronic, and optoelectronic applications. The encapsulation layer utilized as a component of the designed substrate structure prevents the diffusion of impurities present in the central portion of the substrate from reaching the semiconductor processing environment in which the designed substrate is utilized. Important properties related to the substrate material, including coefficient of thermal expansion, lattice mismatch, thermal stability, and shape control, are uniquely designed for improved (e.g., optimized) matching with the gallium nitride-based epitaxial layer and device layers, as well as various device architectures and performance goals. Since the substrate material layers are integrated together in a conventional semiconductor manufacturing process, process integration is simplified. These and other embodiments of the present invention will be described in more detail in connection with the following text and the accompanying drawings, along with many of its advantages and features.

Brief Description of the Drawings

[0012]

Figure 1

Figure 2A

Figure 2B

Figure 2C

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Mode for Carrying Out the Invention

[0013]

[0022] Embodiments of the present invention relate to a designed substrate structure. More specifically, the present invention relates to methods and systems suitable for use in an epitaxial growth process. By way of example only, the present invention is applicable to methods and systems for providing a substrate structure suitable for epitaxial growth, the structure being characterized by a coefficient of thermal expansion (CTE) that substantially matches that of the epitaxial layer growing thereon. The methods and techniques can be applied to various semiconductor processing operations.

[0014]

[0023] FIG. 1 is a simplified schematic diagram showing a designed substrate structure according to an embodiment of the present invention. The designed substrate 100 shown in FIG. 1 is suitable for various electronic and optical applications. The designed substrate includes a core 110 that can have a coefficient of thermal expansion (CTE) that substantially matches that of the epitaxial material to be grown on the designed substrate 100. The epitaxial material 130 is shown as an optional feature as it is not required as an element of the designed substrate but is typically grown on the designed substrate.

[0015]

[0024] In applications involving the growth of gallium nitride (GaN)-based materials (epitaxial layers including GaN-based layers), the core 110 can be made of polycrystalline ceramic material, such as polycrystalline aluminum nitride (AlN) that can include a bonding material such as yttrium oxide. Other materials can be used for the core 110, including polycrystalline gallium nitride (GaN), polycrystalline aluminum gallium nitride (AlGaN), polycrystalline silicon carbide (SiC), polycrystalline zinc oxide (ZnO), polycrystalline gallium trioxide (Ga2O3), etc.

[0016]

[0025] The thickness of the core can be on the order of 100 to 1500 μm, for example 725 μm. The core 110 is encapsulated in a first adhesive layer 112, which can be referred to as a shell or encapsulating shell. In one embodiment, the first adhesive layer 112 includes a tetraethyl orthosilicate (TEOS) layer having a thickness of about 1,000 Å. In other embodiments, the thickness of the first adhesive layer varies, for example, from 100 Å to 2,000 Å. Although TEOS is used in the adhesive layer in some embodiments, other materials (e.g., ceramics, particularly polycrystalline ceramics) that provide adhesion between a subsequently deposited layer and the underlying layer or material can also be used in accordance with embodiments of the present invention. For example, SiO2 or other silicon oxides (Si x O y ) adhere well to ceramic materials and provide a surface suitable, for example, for the subsequent deposition of conductive materials. In some embodiments, the first adhesive layer 112 completely surrounds the core 110 to form a completely encapsulated core and can be formed using an LPCVD process. The first adhesive layer 112 provides a surface on which subsequent layers are adhered to form an element of the substrate structure designed.

[0017]

[0026] In addition to the use of LPCVD processes, furnace processes, etc. to form the first encapsulation adhesive layer, other semiconductor processes including CVD processes or similar deposition processes can be utilized according to embodiments of the present invention. As an example, a deposition process that coats a part of the core can be utilized, the core can be turned over, and the deposition process can be repeated to coat additional parts of the core. Thus, in some embodiments, LPCVD technology is utilized to provide a completely encapsulated structure, but other film-forming technologies can be utilized depending on the specific application.

[0018]

[0027] A conductive layer 114 is formed so as to surround the adhesive layer 112. In one embodiment, since polysilicon has poor adhesion to ceramic materials, the conductive layer 114 is a shell of polysilicon (i.e., polycrystalline silicon) formed so as to surround the first adhesive layer 112. That is. In embodiments where the conductive layer is polysilicon, the thickness of the polysilicon layer can be on the order of 500 - 5,000 Å, for example 2,500 Å. In some embodiments, the polysilicon layer can be formed as a shell so as to completely surround the first adhesive layer 112 (e.g., a TEOS layer), thereby forming a completely encapsulated first adhesive layer and can be formed using an LPCVD process. In other embodiments, as will be described later, the conductive material can be formed on a part of the adhesive layer, for example, the lower half of the substrate structure. In some embodiments, the conductive material can be formed as a completely encapsulating layer and then removed on one side of the substrate structure.

[0019]

[0028] In one embodiment, the conductive layer 114 can be a polysilicon layer doped to provide a highly conductive material, for example, a polysilicon layer doped with boron to provide a p-type polysilicon layer. In some embodiments, for providing high conductivity, the doping with boron is at a level of 1×10 19 cm -3 to 1×10 20 cm -3 . Other dopants at different dopant concentrations (e.g., 1×1016 cm -3 to 5×10 18 cm -3 Using a dopant concentration (such as phosphorus, arsenic, bismuth, etc.) in the range of, it is possible to provide either an n-type or p-type semiconductor material suitable for use in a conductive layer. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0020]

[0029] The presence of the conductive layer 114 is useful when electrostatically chucking a designed substrate to a semiconductor processing tool, such as a tool having an electrostatic chuck (ESC). The conductive layer 114 enables rapid de-chucking after processing in a semiconductor processing tool. Thus, embodiments of the present invention provide a substrate structure that can be processed in a manner utilized with conventional silicon wafers. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0021]

[0030] A second adhesive layer 116 (for example, a TEOS layer having a thickness of about 1,000 Å) is formed to surround the conductive layer 114. In some embodiments, the second adhesive layer 116 completely surrounds the conductive layer 114 to form a complete encapsulation structure and can be formed using an LPCVD process, a CVD process, or any other suitable deposition process including the deposition of spin-on dielectrics.

[0022]

[0031] A barrier layer 118, such as a silicon nitride layer, is formed to surround the second adhesive layer 116. In one embodiment, the barrier layer 118 is a silicon nitride layer 118 having a thickness of about 2,000 Å to 5,000 Å. The barrier layer 118 can, in some embodiments, completely surround the second adhesive layer 116 to form a complete encapsulation structure and can be formed using a LPCVD process. In addition to silicon nitride layers, amorphous materials including SiCN, SiON, AlN, SiC, etc. can be used as the barrier layer. In some embodiments, the barrier layer 118 includes several sub-layers constructed to form the barrier layer. Thus, the term barrier layer is not intended to mean a single layer or a single material, but rather is intended to encompass one or more materials laminated in a composite manner. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0023]

[0032] In some embodiments, the barrier layer 118, such as a silicon nitride layer, prevents elements present within the core 110, such as yttrium oxide (i.e., yttria), oxygen, metal impurities, other trace elements, etc., from diffusing and / or outgassing into the environment of the semiconductor processing chamber where the designed substrate can be present, for example, during a high temperature (e.g., 1,000 °C) epitaxial growth process. Using the encapsulation layer described herein, ceramic materials containing polycrystalline AlN designed for non-cleanroom environments can be utilized in semiconductor process flows and cleanroom environments.

[0024]

[0033] FIG. 2A is a secondary ion mass spectrometry (SIMS) profile showing the species concentration as a function of depth for a designed structure according to an embodiment of the present invention. The designed structure did not include the barrier layer 118. Referring to FIG. 2A, several species present in the ceramic core (e.g., yttrium, calcium, and aluminum) are reduced to negligible concentrations in the designed layers 120 / 122. The concentrations of calcium, yttrium, and aluminum drop by 3, 4, and 6 orders of magnitude, respectively.

[0025]

[0034] Figure 2B is a SIMS profile showing the species concentration as a function of depth for a designed structure without a barrier layer after annealing according to an embodiment of the present invention. As described above, during semiconductor processing operations, the designed substrate structure provided by embodiments of the present invention may be exposed to high temperatures (about 1100 ° C) for several hours, for example, during the epitaxial growth of GaN-based layers.

[0026]

[0035] In the case of the profile shown in Figure 2B, the designed substrate structure was annealed at 1100 ° C for 4 hours. As shown in Figure 2B, calcium, yttrium, and aluminum, which were originally present at low concentrations in the sample during deposition, diffused into the designed layer and reached concentrations similar to those of other elements.

[0027]

[0036] Figure 2C is a SIMS profile showing the species concentration as a function of depth for a designed structure with a barrier layer after annealing according to an embodiment of the present invention. The integration of the diffusion barrier layer 118 (for example, a silicon nitride layer) into the designed substrate structure prevents the diffusion of calcium, yttrium, and aluminum into the designed layer during the annealing process that occurred in the absence of the diffusion barrier layer. As shown in Figure 2C, calcium, yttrium, and aluminum present in the ceramic core remain at low concentrations in the designed layer after annealing. Thus, the use of the barrier layer 118 (for example, a silicon nitride layer) prevents these elements from diffusing through the diffusion barrier and thereby being released into the environment surrounding the designed substrate. Similarly, any other impurities contained within the bulk ceramic material are also contained by the barrier layer.

[0028]

[0037] Typically, the ceramic material utilized to form the core 110 is fired at a temperature in the range of 1,800 °C. This process is expected to remove a significant amount of impurities present in the ceramic material. These impurities can include yttrium, calcium, as well as other elements and compounds resulting from the use of yttria as a sintering agent. Subsequently, during the epitaxial growth process, which is carried out at a much lower temperature in the range of 800 °C to 1,100 °C, the subsequent diffusion of these impurities is expected to be slight. However, contrary to conventional expectations, the inventors have found that significant diffusion of elements can occur through the designed substrate layers even during the epitaxial growth process at a temperature much lower than the firing temperature of the ceramic material. Accordingly, embodiments of the present invention incorporate a barrier layer 118 (e.g., a silicon nitride layer) to prevent the out-diffusion of background elements to epitaxial layers such as layers 120 / 122 designed from a polycrystalline ceramic material (e.g., AlN) and any GaN layer 130. The silicon nitride layer 118, which encapsulates the underlying layers and materials, provides the desired barrier layer function.

[0029]

[0038] As shown in Figure 2B, elements originally present within the core 110 that contain yttrium diffuse into and through the first TEOS layer 112, the polysilicon layer 114, and the second TEOS layer 116. However, the presence of the silicon nitride layer 118 prevents these elements from diffusing through the silicon nitride layer, thereby preventing their release into the environment surrounding the designed substrate, as shown in Figure 2C.

[0030]

[0039] Referring back to Figure 1, a bonding layer 120 (e.g., a silicon oxide layer) is deposited on a portion of the barrier layer 118, e.g., on the upper surface of the barrier layer, and is then used during the bonding of the substantially single-crystalline silicon layer 122. The bonding layer 120 can be approximately 1.5 μm thick in some embodiments.

[0031]

[0040] The substantially single-crystalline layer 122 is suitable for use as a growth layer during an epitaxial growth process for forming the epitaxial material 130. In some embodiments, the epitaxial material 130 includes a GaN layer having a thickness of 2 μm to 10 μm, which can be utilized as one of a plurality of layers used in optoelectronic devices, RF devices, power devices, etc. In one embodiment, the substantially single-crystalline layer 122 includes a substantially single-crystalline silicon layer attached to the silicon oxide layer 118 using a layer transfer process.

[0032]

[0041] FIG. 3 is a simplified schematic view showing a designed substrate structure according to an embodiment of the present invention. The designed substrate 300 shown in FIG. 3 is suitable for various electronic and optical applications. The designed substrate includes a core 110 that can have a coefficient of thermal expansion (CTE) that substantially matches the CTE of the epitaxial material 130 grown on the designed substrate 300. The epitaxial material 130 is shown as an optional feature as it is not required as an element of the designed substrate structure but is typically grown on the designed substrate structure.

[0033]

[0042] In applications involving the growth of gallium nitride (GaN)-based materials (epitaxial layers including GaN-based layers), the core 110 can be a polycrystalline ceramic material, such as polycrystalline aluminum nitride (AlN). The thickness of the core can be on the order of 100 to 1500 μm, for example, 725 μm. The core 110 is encapsulated in a first adhesive layer 112 that can be referred to as a shell or encapsulating shell. In this embodiment, the first adhesive layer 112 completely encapsulates the core, which is not required by the present invention as will be discussed in more detail with respect to FIG. 4.

[0034]

[0043] In one embodiment, the first adhesive layer 112 includes a tetraethyl orthosilicate (TEOS) layer having a thickness of about 1,000 Å. In other embodiments, the thickness of the first adhesive layer varies, for example, from 100 Å to 2,000 Å. Although TEOS is used in the adhesive layer in some embodiments, other materials that provide adhesion between the subsequently deposited layer and the underlying layer or material can also be used according to embodiments of the present invention. For example, SiO2, SiON, etc. adhere well to ceramic materials and provide a surface suitable for subsequent deposition of, for example, conductive materials. In some embodiments, the first adhesive layer 112 completely surrounds the core 110 to form a completely encapsulated core and can be formed using a low-pressure chemical vapor deposition (LPCVD) process. The adhesive layer provides a surface onto which subsequent layers are adhered to form an element of the designed substrate structure.

[0035]

[0044] In addition to the use of LPCVD processes, furnace processes, etc. to form the encapsulating adhesive layer, other semiconductor processes can be used according to embodiments of the present invention. As an example, deposition processes such as CVD, PECVD, etc. can be utilized to coat a portion of the core, the core can be flipped, and the deposition process can be repeated to coat additional portions of the core.

[0036]

[0045] A conductive layer 314 is formed on at least a portion of the first adhesive layer 112. In one embodiment, the conductive layer 314 includes polysilicon (i.e., polycrystalline silicon) formed by a deposition process on the lower part (e.g., the lower half or the back surface) of the core / adhesive layer structure. In embodiments where the conductive layer is polysilicon, the thickness of the polysilicon layer can be on the order of thousands of angstroms, for example, 3,000 Å. In some embodiments, the polysilicon layer can be formed using an LPCVD process.

[0037]

[0046] In one embodiment, the conductive layer 314 can be a polysilicon layer doped to provide a highly conductive material. For example, the conductive layer 314 can be doped with boron to provide a p-type polysilicon layer. In some embodiments, to provide high conductivity, Doping with boron is at a level in the range of about 1×10 19 cm -3 to 1×10 20 cm -3 The presence of the conductive layer is useful when electrostatically chucking the designed substrate to a semiconductor processing tool, such as a tool having an electrostatic chuck (ESC). The conductive layer 314 enables rapid de-chucking after processing. Accordingly, embodiments of the present invention provide a substrate structure that can be processed in a manner utilized with conventional silicon wafers. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0038]

[0047] A second adhesive layer 316 (e.g., a second TEOS layer) is formed to surround the conductive layer 314 (e.g., a polysilicon layer). The thickness of the second adhesive layer 316 is about 1,000 Å. In some embodiments, the second adhesive layer 316 can completely surround the conductive layer 314 and the first adhesive layer 112 to form a complete encapsulation structure and can be formed using an LPCVD process. In other embodiments, the second adhesive layer 316 only partially surrounds the conductive layer 314 ending at a position indicated by a plane 317 that can be aligned with the upper surface of the conductive layer 314. In this example, the upper surface of the conductive layer 314 will contact a portion of the barrier layer 118. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0039]

[0048] A barrier layer 118 (e.g., a silicon nitride layer) is formed to surround the second adhesive layer 316. In some embodiments, the thickness of the barrier layer 118 is about 4,000 Å to 5,000 Å. In some embodiments, the barrier layer 118 can completely surround the second adhesive layer 316 to form a complete encapsulation structure and can be formed using an LPCVD process.

[0040]

[0049] In some embodiments, the use of a silicon nitride barrier layer prevents elements present within the core 110, such as yttrium oxide (i.e., yttria), oxygen, metallic impurities, other trace elements, etc., from diffusing and / or outgassing into the environment of a semiconductor processing chamber in which the designed substrate may be present, for example, during a high temperature (e.g., 1,000 °C) epitaxial growth process. The encapsulation layer described herein can be utilized to enable the use of a ceramic material containing polycrystalline AlN designed for a non-cleanroom environment within a semiconductor process flow and a cleanroom environment.

[0041]

[0050] FIG. 4 is a simplified schematic diagram showing a designed substrate structure according to another embodiment of the present invention. In the embodiment shown in FIG. 4, a first adhesive layer 412 is formed on at least a portion of the core 110 but does not encapsulate the core 110. In this embodiment, the first adhesive layer 412 is formed on the lower surface (the back side of the core 110) of the core 110 to enhance the adhesion of a subsequently formed conductive layer 414, as will be more fully described below. Although the adhesive layer 412 is shown only on the lower surface of the core 110 in FIG. 4, it will be understood that the deposition of adhesive layer material on other portions of the core does not adversely affect the performance of the designed substrate structure and such material can be present in various embodiments. One of ordinary skill in the art will recognize many variations, modifications, and alternatives.

[0042]

[0051] The conductive layer 414 does not encapsulate the first adhesive layer 412 and the core 110, but is substantially aligned with the first adhesive layer 412. The conductive layer 414 is shown as extending along the bottom or back surface of the first adhesive layer 412 and then extending upward along a portion of the side surface, although the extension along the vertical plane is not required by the present invention. Thus, embodiments can utilize deposition on one side of the substrate structure, masking of one side of the substrate structure, etc. The conductive layer 414 can be formed on one side, for example, a part of the bottom surface / back surface of the first adhesive layer 412. The conductive layer 414 provides electrical conduction on one side of the designed substrate structure, which can be advantageous in RF and high-power applications. The conductive layer can include doped polysilicon as described with respect to the conductive layer 114 in FIG. 1.

[0043]

[0052] A portion of the core 110, a portion of the first adhesive layer 412, and the conductive layer 414 are covered by a second adhesive layer 416 to enhance the adhesion of the barrier layer 418 to the underlying material. The barrier layer 418 forms an encapsulation structure to prevent diffusion from the underlying layer as described above.

[0044]

[0053] In addition to the semiconductor-based conductive layer, in other embodiments, the conductive layer 414 is a metal layer, such as 500 Å of titanium.

[0045]

[0054] Referring back to FIG. 4, depending on the embodiment, one or more layers can be removed. For example, layers 412 and 414 can be removed, leaving only the single adhesive shell 416 and the barrier layer 418. In another embodiment, only layer 414 can be removed. In this embodiment, layer 412 can also balance the stress caused by layer 120 deposited on layer 418 and the wafer bend. A configuration of the substrate structure having an insulating layer on the upper surface of the core 110 (e.g., having only an insulating layer between the core 110 and layer 120) provides benefits in power / RF applications where a high-insulation substrate is desired.

[0046]

[0055] In another embodiment, the barrier layer 418 may directly encapsulate the core 110, followed by the conductive layer 414 and then the adhesive layer 416. In this embodiment, the layer 120 can be deposited directly onto the adhesive layer 416 from above. In yet another embodiment, the adhesive layer 416 can be deposited onto the core 110, followed by the barrier layer 418, and then the conductive layer 414, and another adhesive layer 412 can follow.

[0047]

[0056] Although several embodiments have been discussed with respect to layers, the term layer should be understood such that a layer can include several sub - layers that are constructed to form the layer of interest. Thus, the term layer is not intended to mean a single layer of a single material, but rather is intended to encompass one or more materials that are compositely laminated to form the desired structure. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0048]

[0057] FIG. 5 is a simplified flowchart showing a method of manufacturing a substrate designed according to an embodiment of the present invention. Using this method, a substrate with a CTE match to one or more epitaxial layers grown on the substrate can be manufactured. The method 500 includes providing a polycrystalline ceramic core (510), encapsulating the polycrystalline ceramic core in a first adhesive layer (e.g., a tetraethyl orthosilicate (TEOS) shell) to form a shell (512), and forming a support structure by encapsulating the first adhesive layer in a conductive shell (514) (e.g., a polysilicon shell). The first adhesive layer can be formed as a single layer of TEOS. The conductive shell can be formed as a single layer of polysilicon.

[0049]

[0058] The method also includes encapsulating the conductive shell in a second adhesive layer (516) (e.g., a second TEOS shell) and encapsulating the second adhesive layer in a barrier layer shell (518). The second adhesive layer can be formed as a single layer of TEOS. The barrier layer shell can be formed as a single layer of silicon nitride.

[0050]

[0059] When the support structure is formed by processes 510 - 518, the method further includes bonding a bonding layer (e.g., a silicon oxide layer) to the support structure (520) and bonding a substantially single crystal layer, e.g., a substantially single crystal silicon layer, to the silicon oxide layer (522). According to embodiments of the present invention, other substantially single crystal layers including SiC, sapphire, GaN, AlN, SiGe, Ge, diamond, Ga2O3, ZnO, etc. can be used. The bonding of the bonding layer can include the deposition of a bonding material followed by the planarization process described herein. In the embodiments described below, bonding a substantially single crystal layer (e.g., a substantially single crystal silicon layer) to the bonding layer utilizes a layer transfer process where the layer is a single crystal silicon layer transferred from a silicon wafer.

[0051]

[0060] Referring to FIG. 1, the bonding layer 120 can be formed by the deposition of a thick (e.g., 4 μm thick) oxide layer, followed by a chemical mechanical polishing (CMP) process that thins the oxide to a thickness of about 1.5 μm. The thick initial oxide may be present after the fabrication of the polycrystalline core and serves to fill voids and surface features that may be present on the support structure and may continue to be present when the encapsulation layer shown in FIG. 1 is formed. The CMP process provides a substantially flat surface that is free of voids, particles, or other features and can then be used during a wafer transfer process to bond a substantially single crystal layer 122 (e.g., a substantially single crystal silicon layer) to the bonding layer 120. The bonding layer 120 need not be characterized by an atomically flat surface, but should provide a substantially flat surface that aids in the bonding of the substantially single crystal layer (e.g., a substantially single crystal silicon layer) with the desired reliability.

[0052]

[0061] Using a layer transfer process, a substantially single-crystalline silicon layer 122 can be bonded to a bonding layer 120. In some embodiments, a silicon wafer (e.g., a silicon (111) wafer) is implanted to form a cleavage plane. After wafer bonding, the silicon substrate can be removed along with a portion of the single-crystalline silicon layer beneath the cleavage plane, resulting in the detached single-crystalline silicon layer 122 shown in FIG. 1. The thickness of the substantially single-crystalline layer 122 can be varied to suit the specifications of various applications. Further, the crystal orientation of the substantially single-crystalline layer 122 can be varied to suit the application specifications. Additionally, the doping level and profile in the substantially single-crystalline layer 122 can be varied to suit the specifications of a particular application.

[0053]

[0062] The method shown in FIG. 5 may also include smoothing a substantially single-crystalline layer (524). In some embodiments, the thickness and surface roughness of the substantially single-crystalline layer 122 can be modified for high-quality epitaxial growth. Slightly different specifications may exist regarding the thickness and surface smoothness of the substantially single-crystalline layer 122 depending on the different device applications. The cleavage process peels the substantially single-crystalline layer 122 from the bulk single-crystalline silicon wafer at the peak of the implanted ion profile. After cleavage, the substantially single-crystalline layer 122 can be adjusted or modified in several ways before being utilized as a growth surface for epitaxial growth of other materials such as gallium nitride.

[0054]

[0063] First, the transferred substantially single-crystalline layer 122 may contain a small residual hydrogen concentration and may have some crystal damage due to implantation. Therefore, it may be beneficial to remove the thin portion of the transferred substantially single-crystalline layer 122 where the crystal lattice is damaged. In some embodiments, the implantation depth can be adjusted to be greater than the desired final thickness of the substantially single-crystalline layer 122. The additional thickness allows for the removal of the thin damaged portion of the transferred substantially single-crystalline layer, leaving behind the undamaged portion of the desired final thickness.

[0055]

[0064] Second, it may be desirable to adjust the overall thickness of the substantially single-crystalline layer 122. Generally, the substantially single-crystalline layer 122 is desirably thick enough to provide a high-quality lattice template for the growth after one or more epitaxial layers, but also desirably thin enough to be highly compliant. The substantially single-crystalline layer 122 can be said to be "compliant" when the substantially single-crystalline layer 122 is relatively thin so that its physical properties are not overly constrained and it can mimic the physical properties of the surrounding material, which tends not to generate crystal defects. The compliance of the substantially single-crystalline layer 122 can be inversely proportional to the thickness of the substantially single-crystalline layer 122. The higher the compliance, the lower the defect density of the epitaxial layer grown on the template, enabling the growth of a thicker epitaxial layer. In some embodiments, the thickness of the substantially single-crystalline layer 122 can be increased by epitaxially growing silicon on the exfoliated silicon layer. can be.

[0056]

[0065] Third, it may be beneficial to improve the smoothness of the substantially single-crystalline layer 122. The smoothness of the layer can be related to the total hydrogen dose amount, the presence of any co-implanted species, and the annealing conditions used to form the hydrogen-based cleavage plane. As will be described later, the initial roughness resulting from layer transfer (i.e., the cleavage process) can be reduced by thermal oxidation and oxide layer stripping.

[0057]

[0066] In some embodiments, the removal of the damaged layer and the adjustment of the final thickness of the substantially single-crystalline layer 122 can be achieved by thermal oxidation of the upper part of the exfoliated silicon layer, followed by oxide layer stripping with hydrofluoric acid (HF). For example, a 0.5-μm-thick exfoliated silicon layer can be thermally oxidized to form a silicon dioxide layer with a thickness of about 420 nm. After removing the grown thermal oxide, the remaining silicon thickness in the transfer layer can be about 53 nm. During thermal oxidation, the implanted hydrogen can move towards the surface. Therefore, subsequent oxide layer stripping can remove some damage. Also, thermal oxidation is typically performed at a temperature of 1000 °C or higher. The high temperature can also repair lattice damage.

[0058]

[0067] The silicon oxide layer formed on top of the substantially single crystal layer during thermal oxidation can be removed using HF acid etching. The etching selectivity between silicon oxide and silicon (SiO2:Si) by HF acid can be adjusted by adjusting the temperature and concentration of the HF solution as well as the stoichiometry and density of the silicon oxide. Etching selectivity refers to the etching rate of one material with respect to another material. The selectivity of the HF solution can be in the range of about 10:1 to about 100:1 with respect to (SiO2:Si). High etching selectivity can reduce the surface roughness from the initial surface roughness by similar factors. However, the surface roughness of the resulting substantially single crystal layer 122 may still be larger than desired. For example, the bulk Si(111) surface can have a root mean square (RMS) surface roughness of less than 0.1 nm as determined by a 2 μm × 2 μm atomic force microscope (AFM) scan before additional processing. In some embodiments, the desired surface roughness for epitaxial growth of a gallium nitride material on Si(111) can be less than 1 nm, less than 0.5 nm, or less than 0.2 nm over a 30 μm × 30 μm AFM scan area.

[0059]

[0068] If the surface roughness of the substantially single crystal layer 122 after thermal oxidation and oxide layer removal exceeds the desired surface roughness, additional surface smoothing can be performed. There are several ways to smooth the silicon surface. These methods can include hydrogen annealing, laser trimming, plasma smoothing, and touch polishing (e.g., chemical mechanical polishing or CMP). These methods can include preferential attack of high aspect ratio surface peaks. Thus, high aspect ratio features on the surface can be removed more quickly than low aspect ratio features, thus resulting in a smoother surface.

[0060]

[0069] It should be understood that the specific process shown in FIG. 5 provides a specific method for manufacturing a substrate designed according to an embodiment of the present invention. According to another embodiment, another series of steps can also be performed. For example, an alternative embodiment of the present invention can perform the steps outlined above in a different order. Further, the individual steps shown in FIG. 5 may include a plurality of sub-steps that can be performed in various orders as appropriate for the individual steps. Further, additional steps can be added or removed depending on the specific application. One skilled in the art will recognize many variations, modifications, and alternatives.

[0061]

[0070] FIG. 6 is a simplified schematic diagram showing an epitaxial / designed substrate structure for RF and power applications according to an embodiment of the present invention. In some LED applications, the designed substrate structure provides a growth substrate that enables the growth of high-quality GaN layers, and the designed substrate structure is then removed. However, in the case of RF and power device applications, the designed substrate structure forms part of the completed device, and as a result, the electrical, thermal, and other properties of the designed substrate structure or elements of the designed substrate structure are important for a specific application.

[0062]

[0071] Referring to FIG. 1, the single-crystalline silicon layer 122 is typically a detached layer separated from a silicon donor wafer using implantation and lift-off techniques. Typical implants are hydrogen and boron. For power and RF device applications, the electrical properties of the layers and materials in the designed substrate structure are important. For example, some device architectures require 3Using a highly insulating silicon layer having a resistance exceeding Ωcm, leakage through the substrate and the interface layer is reduced or eliminated. Other applications utilized a design including a conductive silicon layer of a predetermined thickness (e.g., 1 μm) for connecting the source of the device to other elements. Therefore, in these applications, it is desirable to control the dimensions and characteristics of the single crystal silicon layer. In designs where implantation and lift-off techniques are used during layer transfer, residual implanted atoms, such as hydrogen or boron, are present in the silicon layer, thereby changing the electrical properties. Furthermore, for example, using adjustments of the implantation dose, surface roughness and cleavage plane position accuracy, which can affect the conductivity and the full width at half maximum (FWHM) of the implantation profile, and the implantation depth which can affect the layer thickness, it can be difficult to control the thickness, conductivity, and other characteristics of the thin silicon layer.

[0063]

[0072] According to an embodiment of the present invention, silicon epitaxy on a designed substrate structure is utilized to achieve the desired characteristics of a single crystal silicon layer suitable for a specific device design.

[0064]

[0073] Referring to FIG. 6, the epitaxial / designed substrate structure 600 includes a designed substrate structure 610 and a silicon epitaxial layer 620 formed thereon. The designed substrate structure 610 can be similar to the designed substrate structures shown in FIGS. 1, 3, and 4. Typically, the substantially single crystal silicon layer 122 is about 0.5 μm after layer transfer. Using a surface conditioning process, in some processes, the thickness of the single crystal silicon layer 122 can be reduced to about 0.3 μm. To increase the thickness of the single crystal silicon layer to about 1 μm for use in forming a reliable ohmic contact, for example, using an epitaxial process, an epitaxial single crystal silicon layer 620 is grown on the substantially single crystal silicon layer 122 formed by the layer transfer process. The epitaxial single crystal silicon layer 620 can be grown using various epitaxial growth processes including CVD, ALD, MBE, etc. The thickness of the epitaxial single crystal silicon layer 620 can be in the range of about 0.1 μm to about 20 μm, for example, between 0.1 μm and 10 μm.

[0065]

[0074] FIG. 7 is a simplified schematic diagram showing a group-III nitride epitaxial layer on a designed substrate structure according to an embodiment of the present invention. The structure shown in FIG. 7 can be referred to as a double epitaxial structure, as will be described below. As shown in FIG. 7, a designed substrate structure 710 including an epitaxial single-crystalline silicon layer 620 has a group-III nitride epitaxial layer 720 formed thereon. In one embodiment, the group-III nitride epitaxial layer includes gallium nitride (GaN).

[0066]

[0075] The desired thickness of the group-III nitride epitaxial layer 720 can vary substantially depending on the desired function. In some embodiments, the thickness of the group-III nitride epitaxial layer 720 can vary between 0.5 μm and 100 μm, for example, a thickness greater than 5 μm. The resulting breakdown voltage of a device fabricated on the group-III nitride epitaxial layer 720 can vary depending on the thickness of the group-III nitride epitaxial layer 720. Some embodiments provide a breakdown voltage of at least 100 V, 300 V, 600 V, 1.2 kV, 1.7 kV, 3.3 kV, 5.5 kV, 13 kV, or 20 kV.

[0067]

[0076] To provide conductivity between portions of the group-III nitride epitaxial layer 720 that can include multiple sub-layers, a set of vias 724 are formed, passing in this example from the top surface of the group-III nitride epitaxial layer 720 to the epitaxial single-crystalline silicon layer 620. The vias 724 can be aligned with an insulating layer (not shown) such that they are insulated from the group-III nitride epitaxial layer 720. As an example, these vias can be used to provide an ohmic contact through the vias, thereby connecting the electrodes of a diode or transistor to the underlying silicon layer by relaxing the charge accumulated within the device.

[0068]

[0077] When a III-V epitaxial layer is grown on a single-crystalline silicon layer 122, it is difficult to terminate via etching within the single-crystalline silicon layer 122. For example, it is difficult to etch up to 5 μm of GaN and reliably terminate the etching with a 0.3 μm silicon layer across the entire wafer. Therefore, it is difficult to form such an ohmic contact through the via. Utilizing embodiments of the present invention makes it possible to provide a single-crystalline silicon layer with a thickness of several microns, which is difficult to use injection and lift-off processes because high injection energy is required to achieve a large injection depth. Instead, the thick silicon layer enables applications such as the illustrated vias that allow for various device designs.

[0069]

[0078] In addition to increasing the thickness of the silicon "layer" by epitaxially growing a single-crystalline silicon layer 620 on the single-crystalline silicon layer 122, other adjustments including modifications such as conductivity and crystallinity can be made to the original characteristics of the single-crystalline silicon layer 122. For example, if a silicon layer of about 10 μm is desired before additional epitaxial growth of a III-V layer or other materials, such a thick layer can be grown according to embodiments of the present invention.

[0070]

[0079] The injection process may affect the characteristics of the single-crystalline silicon layer 122. For example, residual boron / hydrogen atoms may affect the electrical characteristics of silicon. Therefore, embodiments of the present invention remove a portion of the single-crystalline silicon layer 122 before epitaxial growth of the single-crystalline silicon layer 620. For example, the single-crystalline silicon layer 122 can be thinned to form a layer with a thickness of 0.1 μm or less, removing most or all of the residual boron / hydrogen atoms. Subsequent growth of the single-crystalline silicon layer 620 is used to provide a single-crystalline material having electrical and / or other characteristics substantially independent of the corresponding characteristics of the layer formed using the layer transfer process.

[0071]

[0080] In addition to increasing the thickness of the single-crystalline silicon material coupled to the designed substrate structure, electrical characteristics including the conductivity of the epitaxial single-crystalline silicon layer 620 can be different from those of the single-crystalline silicon layer 122. The doping of the growing epitaxial single-crystalline silicon layer 620 can generate p-type silicon by doping boron and generate n-type silicon by doping phosphorus. Undoped silicon can be grown to provide high-resistance silicon used in devices having insulating regions. The insulating layer can be particularly useful in RF devices.

[0072]

[0081] The lattice constant of the epitaxial single-crystalline silicon layer 620 can be adjusted to be different from the lattice constant of the single-crystalline silicon layer 122 during growth to produce a strained epitaxial material. In addition to silicon, other elements can be epitaxially grown to provide layers including strained layers, layers including silicon germanium, and the like. For example, a buffer layer can be grown on the single-crystalline silicon layer 122, on the epitaxial single-crystalline silicon layer 620, or between the layers to enhance subsequent epitaxial growth. These buffer layers can include strained III-V layers, silicon germanium strained layers, and the like. Further, the buffer layer and other epitaxial layers can be varied in molar fraction, dopant, polarity, and the like. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0073]

[0082] In some embodiments, the strain present in the single-crystalline silicon layer 122 or the epitaxial single-crystalline silicon layer 620 can be relaxed during the growth of subsequent epitaxial layers including III-V epitaxial layers.

[0074]

[0083] FIG. 8 is a simplified flowchart showing a method of manufacturing a designed substrate according to another embodiment of the present invention. This method includes forming a support structure by providing a polycrystalline ceramic core (810), and forming a first adhesive layer bonded to at least a part of the polycrystalline ceramic core (812). The first adhesive layer can include a tetraethyl orthosilicate (TEOS) layer. The method also includes forming a conductive layer bonded to the first adhesive layer (814). The conductive layer can be a polysilicon layer. The first adhesive layer can be formed as a single layer of TEOS. The conductive layer can be formed as a single layer of polysilicon.

[0075]

[0084] The method also includes forming a second adhesive layer bonded to at least a part of the conductive layer (816), and forming a barrier shell (818). The second adhesive layer can be formed as a single layer of TEOS. The barrier shell can be formed as a single layer of silicon nitride or as a series of sub-layers forming the barrier shell.

[0076]

[0085] Once the support structure is formed by processes 810-818, the method further includes bonding a bonding layer (e.g., a silicon oxide layer) to the support structure (820), and bonding a substantially single crystal silicon layer or a substantially single crystal layer to the silicon oxide layer (822). The bonding of the bonding layer can include the deposition of a bonding material followed by the planarization process described herein.

[0077]

[0086] Using a layer transfer process, a substantially single crystal silicon layer 122 can be bonded to a bonding layer 120. In some embodiments, a silicon wafer (e.g., a silicon (111) wafer) is implanted to form a cleavage plane. After wafer bonding, the silicon substrate can be removed along with a portion of the single crystal silicon layer under the cleavage plane, resulting in the detached single crystal silicon layer 122 shown in FIG. 1. The thickness of the substantially single crystal silicon layer 122 can be varied to suit the specifications of various applications. Further, the crystal orientation of the substantially single crystal layer 122 can be varied to suit the specifications of the application. Additionally, the doping level and profile in the substantially single crystal layer 122 can be varied to suit the specifications of a particular application. In some embodiments, as described above, the substantially single crystal silicon layer 122 can be smoothed.

[0078]

[0087] The method shown in FIG. 8 also includes forming an epitaxial silicon layer by epitaxial growth on a substantially single crystal silicon layer (824), and forming an epitaxial III-V layer by epitaxial growth on the epitaxial silicon layer (826). In some embodiments, the epitaxial III-V layer can include gallium nitride (GaN).

[0079]

[0088] It should be understood that the specific process shown in FIG. 8 provides a particular method for manufacturing a substrate designed according to another embodiment of the present invention. According to another embodiment, another series of steps can also be performed. For example, an alternative embodiment of the present invention can perform the steps outlined above in a different order. Further, the individual steps shown in FIG. 8 can include multiple sub-steps that can be performed in various orders as appropriate for the individual steps. Additionally, depending on the particular application, additional steps can be added or removed. One skilled in the art will recognize many variations, modifications, and alternatives.

[0080]

[0089] Also, the examples and embodiments described in this specification are for illustrative purposes only, and various modifications or changes will be suggested to those skilled in the art, and it is understood that they are within the spirit and scope of this application and the appended claims.

Claims

1. A support structure comprising: a polycrystalline ceramic core; a first adhesive layer bonded to the polycrystalline ceramic core; a conductive layer bonded to the first adhesive layer; a second adhesive layer bonded to the conductive layer; a barrier layer bonded to the second adhesive layer; a bonding layer bonded to the support structure; a substantially single crystal layer including at least one of silicon carbide, sapphire, or gallium nitride, bonded to the bonding layer; and an epitaxial semiconductor layer bonded to the substantially single crystal layer. A substrate comprising:

2. The substrate according to claim 1, wherein the polycrystalline ceramic core comprises aluminum nitride.

3. The substrate according to claim 1, wherein the bonding layer comprises silicon oxide.

4. The substrate according to claim 1, wherein the epitaxial semiconductor layer comprises an epitaxial III-V layer.

5. The substrate according to claim 4, wherein the epitaxial III-V layer comprises an epitaxial gallium nitride layer having a thickness of about 5 μm or more.

6. The substrate according to claim 4, further comprising a plurality of vias penetrating from the epitaxial III-V layer to the epitaxial semiconductor layer.

7. The substrate according to claim 1, wherein the epitaxial semiconductor layer comprises an epitaxial single crystal silicon layer, and the substrate further comprises an epitaxial III-V layer bonded to the epitaxial single crystal silicon layer.

8. The substrate according to claim 1, wherein the first adhesive layer encapsulates the polycrystalline ceramic core, the conductive layer encapsulates the first adhesive layer, and the second adhesive layer encapsulates the conductive layer.

9. The substrate according to claim 1, wherein an epitaxial silicon layer is formed on the substantially single crystal layer.

10. The substrate according to claim 1, wherein the first adhesive layer comprises a first tetraethyl orthosilicate (TEOS) layer encapsulating the polycrystalline ceramic core, the conductive layer comprises a polysilicon layer encapsulating the first TEOS layer, the second adhesive layer comprises a second TEOS layer encapsulating the polysilicon layer, and the barrier layer comprises a silicon nitride layer encapsulating the second TEOS layer.

11. A method of manufacturing a substrate, the method comprising: providing a polycrystalline ceramic core; forming a first adhesive layer bonded to the polycrystalline ceramic core; forming a conductive layer bonded to the first adhesive layer; forming a second adhesive layer bonded to the conductive layer; forming a barrier layer bonded to the second adhesive layer; forming a bonding layer bonded to the support structure; forming a substantially single crystal layer including at least one of silicon carbide, sapphire, or gallium nitride, bonded to the bonding layer; and forming an epitaxial semiconductor layer bonded to the substantially single crystal layer. Forming a support structure by forming a barrier layer bonded to the second adhesive layer; Forming a bonding layer bonded to the support structure; Bonding a substantially single-crystalline layer to the bonding layer, wherein the substantially single-crystalline layer comprises at least one of silicon carbide, sapphire, or gallium nitride; Forming one or more epitaxial III-V layers bonded to the substantially single-crystalline layer; A method comprising.

12. The first adhesive layer encapsulates the polycrystalline ceramic core; The conductive layer encapsulates the first adhesive layer; The second adhesive layer encapsulates the conductive layer; The method according to claim 11, wherein the barrier layer encapsulates the second adhesive layer.

13. The method according to claim 11, further comprising forming an epitaxial silicon layer on the substantially single-crystalline layer.

14. The method according to claim 11, wherein the polycrystalline ceramic core comprises aluminum nitride, and the one or more epitaxial III-V layers comprise an epitaxial gallium nitride layer having a thickness of about 5 μm or more.

15. The method according to claim 14, wherein the one or more epitaxial III-V layers further comprise an epitaxial aluminum nitride layer, an epitaxial aluminum gallium nitride layer, or a combination thereof.

16. The method according to claim 11, further comprising forming a strained epitaxial silicon layer bonded to the substantially single-crystalline layer before forming the one or more epitaxial III-V layers, and the one or more epitaxial III-V layers are bonded to the strained epitaxial silicon layer.

17. The method according to claim 11, further comprising forming a plurality of vias penetrating from the one or more epitaxial III-V layers to the substantially single-crystalline layer.

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