Drive circuit, semiconductor device, and power supply device

Abstract

To provide a drive circuit capable of suppressing an output ripple.SOLUTION: A drive circuit (10X) has a switch output stage (HB), a first signal generation circuit (19) configured so as to generate a first signal (SET), a second signal generation circuit (16), a drive control circuit (1B), a frequency diffusion control circuit (22x) configured so as to perform frequency diffusion control to an oscillation frequency of the first signal (SET), and an output ripple suppression circuit (24) configured so as to control the second signal generation circuit (16) by correcting at least either an error signal (Vc) or ramp voltage (Vrmp) according to the oscillation frequency after the frequency diffusion control.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The invention disclosed in this specification relates to a drive circuit, a semiconductor device, and a power supply device.

Background Art

[0002] Conventionally, a switching power supply circuit for forming a switching power supply device has been proposed.

[0003] As an example of the prior art related to the above, Patent Document 1 can be cited.

Prior Art Document

Patent Document

[0004]

Patent Document 1

[0005] [Summary] The switching power supply circuit disclosed in Patent Document 1 had room for further consideration regarding suppression of output ripple.

[0006] The drive circuit disclosed in this specification includes a switch output stage, a first signal generation circuit, a second signal generation circuit, a drive control circuit, a frequency spread control circuit, and an output ripple suppression circuit. The switch output stage is configured to generate a switch voltage that is pulse-driven between a first logic value and a second logic value. The first signal generation circuit is configured to generate a first signal that defines the switching timing of the switch voltage to the first logic value. The second signal generation circuit is configured to generate a second signal that defines the switching timing of the switch voltage to the second logic value in response to a comparison between an error signal and a ramp voltage. The drive control circuit is configured to control the switch output stage to pulse-drive the switch voltage according to the first signal and the second signal. The frequency spread control circuit is configured to perform frequency spread control on the oscillation frequency of the first signal. The output ripple suppression circuit is configured to correct at least one of the error signal and the ramp voltage according to the oscillation frequency after frequency spread control, and to control the second signal generation circuit.

[0007] The semiconductor device disclosed in this specification is configured by integrating the drive circuit having the above configuration.

[0008] The power supply device disclosed in this specification includes the semiconductor device having the above configuration, and a rectifying and smoothing circuit configured to rectify and smooth the switch voltage to generate an output voltage. The semiconductor device includes an error signal generation circuit configured to generate an error signal according to the difference between the output voltage and the target voltage of the output voltage.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

[0010] [Detailed Description] [Regarding the power supply device Y of the comparative example] First, the power supply device Y will be described as a comparative example of the power supply device X of the present disclosure. Next, the problems of the comparative example will be described, and then the power supply device X of the present disclosure will be described.

[0011] FIG. 1 is a block diagram showing the configuration of the power supply device Y according to the comparative example. As shown in FIG. 1, the power supply device Y is a step-down DC / DC converter that generates an output voltage Vout from an input voltage Vin and supplies it to a load (not shown). The power supply device Y includes a power supply control device 10y and various discrete components (for example, an inductor L1, capacitors C1 to C3, and resistors R1 and R2).

[0012] [Regarding the power supply control device 10y] The power supply control device 10y is a semiconductor integrated circuit device (so-called power supply control IC [Integrated Circuit]). The power supply control device 10y includes external terminals T1 to T4 as means for establishing electrical connection with the outside of the device.

[0013] The external terminal T1 is connected to the input terminal of the input voltage Vin. The external terminal T2 is connected to the first terminal of the inductor L1. The second terminal of the inductor L1 is connected to the output terminal of the output voltage Vout together with the first terminals of the capacitors C1 to C3 and the resistor R1. The external terminal T3 is connected to the ground terminal PGND. Note that hereinafter, the potential applied to the ground terminal PGND may be referred to as the ground potential PGND (= 0V). The second terminal of the resistor R1 is connected to the external terminal T4 together with the first terminal of the resistor R2. The second terminals of the capacitors C1 and C2 and the resistor R2 are all connected to the ground terminal PGND.

[0014] The power control device 10y includes a switch output stage HB, an error amplifier 13, a phase compensation circuit 14, a lamp voltage generation circuit 15, a reset comparator 16, a skip signal generation circuit 23, an SSCG [Spread Spectrum Clock Generator] circuit 21y, and a driver 1B.

[0015] The switch output stage HB is a half-bridge output stage including an output element 11 and a rectifying element 12. Each of the output element 11 and the rectifying element 12 is an N-channel type MOS [metal oxide semiconductor] field effect transistor. The output element 11 and the rectifying element 12 are complementarily switched and driven according to the gate signals G1 and G2. Here, the term "complementary" should be interpreted in a broad sense to include not only the case where the on / off states of the output element 11 and the rectifying element 12 are completely reversed, but also the case where a dead time (so-called) is provided between the two simultaneous off periods.

[0016] The drain of the output element 11 is connected to the external terminal T1. The source of the output element 11 and the drain of the rectifying element 12 are both connected to the external terminal T2. The source of the rectifying element 12 is connected to the external terminal T3. The gates of the output element 11 and the rectifying element 12 are respectively connected to the applied terminals of the gate signals G1 and G2.

[0017] When the gate signal G1 is at a high level and the gate signal G2 is at a low level, the output element 11 turns on and the rectifying element 12 turns off. Then, a current flows through the path from the external terminal T1 through the output element 11 to the external terminal T2, and electrical energy is stored in the inductor L1.

[0018] On the other hand, when the gate signal G1 is at a low level and the gate signal G2 is at a high level, the output element 11 turns off and the rectifying element 12 turns on. Then, a current flows through the path from the external terminal T3 through the rectifying element 12 to the external terminal T2 until the electrical energy stored in the inductor L1 is dissipated.

[0019] By repeating such switching driving, a rectangular-wave switching voltage Vsw appears at the external terminal T2. By smoothing the switching voltage Vsw using the smoothing rectifying circuit 25 composed of the capacitors C1, C2 and the inductor L1, a DC output voltage Vout can be obtained.

[0020] The error amplifier 13 outputs an error current I0 corresponding to the difference between the feedback voltage Vfb (= divided voltage of the output voltage Vout) input from the external terminal T4 to the inverting input terminal (-) and a predetermined reference voltage Vref input to the non-inverting input terminal (+), thereby generating an error voltage Vc at the output terminal. Specifically, when Vfb < Vref, the error current I0 flows from the error amplifier 13 into the phase compensation circuit 14 and the error voltage Vc is pulled up. Conversely, when Vfb > Vref, the error current I0 is drawn from the phase compensation circuit 14 into the error amplifier 13 and the error voltage Vc is pulled down. Note that the absolute value of the error current I0 increases as the difference value between the feedback voltage Vfb and the reference voltage Vref increases.

[0021] The phase compensation circuit 14 is an RC circuit connected between the output terminal of the error amplifier 13 and the ground terminal. The phase compensation capacitance value and the phase compensation resistance value may be appropriately set in consideration of the output feedback loop gain, respectively.

[0022] The lamp voltage generation circuit 15 includes a current detection circuit 15A, a slope voltage generation circuit 15B, and an addition circuit 15C. The current detection circuit 15A generates a current sense signal Vsns proportional to the current flowing through the output element 11 during the on interval of the output element 11 (i.e., the inductor current IL during the on interval of the output element 11) by converting the current into a voltage.

[0023] The slope voltage generation circuit 15B generates a sawtooth-shaped slope voltage Vsl (charge / discharge voltage) synchronized with the set signal SET. The slope voltage generation circuit 15B gradually increases the slope voltage Vsl starting from 0V during the on interval of the output element 11. The addition circuit 15C generates a lamp voltage Vrmp as the sum voltage of the current sense signal Vsns and the slope voltage Vsl. Therefore, the lamp voltage Vrmp has a slope or offset corresponding to the inductor current IL. The lamp voltage Vrmp is 0V in the intervals other than the on interval of the output element 11.

[0024] The reset comparator 16 compares the error voltage Vc input to the non-inverting input terminal (+) with the lamp voltage Vrmp input to the inverting input terminal (-) to generate a reset signal RST. Therefore, the reset signal RST becomes high level when Vc > Vsl and becomes low level when Vc < Vsl.

[0025] The skip signal generation circuit 23 generates a skip signal SKIP according to the output voltage Vout and inputs it to the driver 1B. When the voltage value of the output voltage Vout becomes smaller than a predetermined voltage value, the skip signal generation circuit 23 raises the skip signal SKIP from low level to high level. Conversely, when the voltage value of the output voltage Vout becomes equal to or higher than the predetermined voltage value, the skip signal generation circuit 23 lowers the skip signal SKIP from high level to low level.

[0026] The SSCG circuit 21y generates a set signal SET and inputs it to the driver 1B. The set signal SET is a pulse signal that rises from a low level to a high level at a predetermined frequency. The SSCG circuit 21y generates the set signal SET in such a way as to modulate (spread) the frequency. The detailed configuration of the SSCG circuit 21y will be described later. Note that the oscillation frequency of the set signal SET is also simply referred to as the "pulse frequency" hereinafter.

[0027] Based on the input of the set signal SET and the reset signal RST, the driver 1B generates gate signals G1 and G2 and performs switching driving of the switch output stage HB. Specifically, it is as follows.

[0028] When the driver 1B detects the rising edge of the set signal SET, it sets the gate signal G1 to a high level and the gate signal G2 to a low level so that the output element 11 turns on and the rectifying element 12 turns off. Also, when the driver 1B detects the rising edge of the reset signal RST, it sets the gate signal G1 to a low level and the gate signal G2 to a high level so that the output element 11 turns off and the rectifying element 12 turns on.

[0029] <Regarding the switching operation of the switch output stage HB> As described above, the oscillator 19 inputs the set signal SET to the driver 1B. When the driver 1B detects the rising edge of the set signal SET, it turns on the output element 11 and turns off the rectifying element 12. Then, the switch voltage Vsw rises from a low level (= PGND) to a high level (≈ Vin). As a result, the inductor current IL changes from decreasing to increasing and the lamp voltage Vrmp begins to rise.

[0030] After that, when the lamp voltage Vrmp exceeds the error voltage Vc, the reset signal RST rises to the high level. At this time, the driver 1B turns off the output element 11 and turns on the rectifying element 12. As a result, the inductor current IL changes from increasing to decreasing. Also at this time, the lamp voltage Vrmp rapidly drops to 0V. Therefore, the reset signal RST falls to the low level without hysteresis. Also, the switch voltage Vsw falls from the high level (≈Vin) to the low level (≈PGND). Thereafter, the same operation as above is repeated.

[0031] <Pulse Skip Control> When the skip signal SKIP is at the low level, the driver 1B controls the switching drive of the switch output stage HB in the above-described operation according to the set signal SET and the reset signal RST.

[0032] On the other hand, when the inductor current IL decreases and the output voltage Vout falls below a predetermined voltage value, the skip signal SKIP falls to the high level. When the driver 1B detects the fall of the skip signal SKIP, it performs pulse skip control. Specifically, the driver 1B masks the set signal SET and temporarily stops the switching drive of the switch output stage HB (the above-described switching drive). When the inductor current IL increases and the output voltage Vout exceeds the above-mentioned predetermined voltage value, the skip signal SKIP falls to the low level. Then, the driver 1B releases the masking of the set signal SET and resumes the above-described basic switching control thereafter. By the above series of operations, the error voltage Vc is stabilized (clamped) in the vicinity of a predetermined voltage value.

[0033] <Regarding the SSCG Circuit 21y> The SSCG circuit 21y includes a frequency spread control circuit 22y and an oscillator 19.

[0034] The frequency spread control circuit 22y generates a triangular wave signal S1 and inputs it to the oscillator 19. The triangular wave signal S1 is a digital triangular wave signal.

[0035] The frequency spread control circuit 22y linearly and monotonically increases the voltage value of the triangular wave signal S1 from a predetermined minimum value to a predetermined maximum value at a predetermined increase rate. When the voltage value of the triangular wave signal S1 reaches the maximum value, the frequency spread control circuit 22y linearly and monotonically decreases the voltage value of the triangular wave signal S1 to the minimum value at a predetermined decrease rate (the same rate as the above-described increase rate). Thereafter, similarly, the frequency spread control circuit 22y repeatedly and monotonically increases and decreases the voltage value of the triangular wave signal S1 between the minimum value and the maximum value.

[0036] The oscillator 19 is provided with a DAC [Digital to Analog Converter] that receives the triangular wave signal S1 (not shown). The oscillator 19 modulates (spreads) the pulse frequency of the set signal SET according to the voltage value of the triangular wave signal S1. Specifically, as the voltage value of the triangular wave signal S1 increases, the pulse frequency of the set signal SET is increased, and as the voltage value of the triangular wave signal S1 decreases, the pulse frequency of the set signal SET is decreased.

[0037] As described above, the switch output stage HB switches the input voltage Vin using the pulse frequency of the set signal SET as the switching frequency, thereby generating the output voltage Vout. Further, the SSCG circuit 21y modulates the switching frequency of the switch output stage HB by modulating the pulse frequency of the set signal SET using the triangular wave signal S1. By modulating the switching frequency of the switch output stage HB, an increase in switching noise is suppressed. As a result, deterioration of EMI (Electro Magnetic Interference) characteristics is suppressed.

[0038] <Regarding modulation of pulse frequency and output ripple> Subsequently, regarding the modulation of the pulse frequency and the output ripple, a detailed explanation will be given using the timing chart shown in FIG. 2. FIG. 2 is a timing chart showing the output voltage Vout of the power supply device Y according to the comparative example, the triangular wave signal S1, the error voltage Vc, and the lamp voltage Vrmp.

[0039] As shown in FIG. 2, during the period from time t1 to t2, the voltage value of the triangular wave signal S1 is decreasing. At this time, as described above, as the voltage value of the triangular wave signal S1 decreases, the pulse frequency decreases (not shown). When the pulse frequency decreases (that is, when the rising interval of the set signal SET becomes longer), the on-duty of the switch output stage HB decreases, and the average current of the inductor current IL decreases (not shown). Therefore, as shown in FIG. 2, during the period from time t1 to t2, the output voltage Vout decreases. As the output voltage Vout decreases, the feedback voltage Vfb also decreases (not shown). As a result, during the period from time t1 to t2, the error voltage Vc increases. Also, the coincidence point of the error voltage Vc and the ramp voltage vrmp increases.

[0040] On the other hand, during the period from time t2 to t3, the voltage value of the triangular wave signal S1 is increasing. At this time, as described above, as the voltage value of the triangular wave signal S1 increases, the pulse frequency increases (not shown). When the pulse frequency increases (that is, when the rising interval of the set signal SET becomes shorter), the on-duty of the switch output stage HB increases, and the average current of the inductor current IL increases (not shown). Therefore, as shown in FIG. 2, during the period from time t2 to t3, the output voltage Vout increases. As the output voltage Vout increases, the feedback voltage Vfb also increases (not shown). As a result, during the period from time t2 to t3, the error voltage Vc decreases. Also, the coincidence point of the error voltage Vc and the ramp voltage vrmp decreases.

[0041] As described above, a power supply device such as the power supply device Y described above (a power supply device including a power control device that diffusely controls the switching frequency) may cause the ripple voltage of the output voltage Vout to increase (that is, the output voltage Vout fluctuates up and down) as the average current value of the inductor current IL fluctuates up and down.

[0042] In response to such problems, the power supply device X of the present disclosure is capable of suppressing an increase in the ripple voltage generated in the output voltage Vout. Hereinafter, the power supply device X according to the embodiment of the present disclosure will be described in detail. Note that the power supply device X according to the embodiment of the present disclosure includes a configuration common to the above-described power supply device Y. Therefore, the same reference numerals are given to the common configurations and the description thereof is omitted.

[0043] <Regarding the power supply device X of the embodiment according to the present disclosure> FIG. 3 is a block diagram showing the configuration of the power supply device X according to the embodiment of the present disclosure. As shown in FIG. 3, the power supply device X is a step-down DC / DC converter that generates an output voltage Vout (<Vin) from an input voltage Vin and supplies it to a load. The power supply device X includes a power control device 10x (drive circuit) and various discrete components (for example, an inductor L1 (output current generation circuit), capacitors C1 to C3, and resistors R1, R2).

[0044] <Regarding the power control device 10x> The power control device 10x is a semiconductor integrated circuit device (so-called power control IC [Integrated Circuit]). The power control device 10x includes external terminals T1 to T4 as means for establishing an electrical connection with the outside of the device.

[0045] The power control device 10x includes a switch output stage HB, an error amplifier 13, a phase compensation circuit 14, a ramp voltage generation circuit 15 (voltage control circuit), a reset comparator 16, a skip signal generation circuit 23, an SSCG circuit 21x, an output ripple suppression circuit 24, and a driver 1B.

[0046] <Regarding the SSCG circuit 21x> The SSCG circuit 21x generates a set signal SET and inputs it to the driver 1B. The set signal SET is a pulse signal that rises from a low level to a high level at a predetermined pulse frequency. The SSCG circuit 21x generates the set signal SET by modulating (spreading) the pulse frequency.

[0047] The SSCG circuit 21x includes a frequency spread control circuit 22x and an oscillator 19.

[0048] The frequency spread control circuit 22x generates a triangular wave signal S1 and inputs it to the oscillator 19 and the output ripple suppression circuit 24. The triangular wave signal S1 is a digital triangular wave signal. The frequency spread control circuit 22x generates the triangular wave signal S1 in the same manner as the aforementioned frequency spread control circuit 22y.

[0049] The output ripple suppression circuit 24 controls the output of the ramp voltage generation circuit 15 so as to correct the ramp voltage Vrmp according to the pulse frequency of the set signal SET. Specifically, the output ripple suppression circuit 24 increases the ramp voltage Vrmp as the pulse frequency of the set signal SET decreases. Conversely, the output ripple suppression circuit 24 decreases the ramp voltage Vrmp as the pulse frequency of the set signal SET increases. The detailed configuration of the output ripple suppression circuit 24 will be described later. lower decreases. Conversely, the output ripple suppression circuit 24 decreases the ramp voltage Vrmp as the pulse frequency of the set signal SET increases. upper decreases. The detailed configuration of the output ripple suppression circuit 24 will be described later.

[0050] FIG. 4 is a diagram showing the configuration of the main part of the power supply control device 10x (the slope voltage generation circuit 15B, the output ripple suppression circuit 24, the reference voltage generation circuit 17, and its peripheral circuits). Hereinafter, the main part of the power supply control device 10x will be described.

[0051] <Regarding the reference voltage generation circuit 17> As shown in FIG. 4, the reference voltage generation circuit 17 generates a reference voltage V2 that depends on the output voltage Vout. Specifically, the reference voltage generation circuit 17 includes a voltage divider and a multi-stage low-pass filter, and divides and smoothes the rectangular wave-shaped switch voltage Vsw to generate the reference voltage V2. The detailed configuration of the reference voltage generation circuit 17 is as follows.

[0052] The reference voltage generation circuit 17 includes resistors R14 to R19 and capacitors C12 to C14.

[0053] The first end of resistor R14 is connected to the applied end of the switch voltage Vsw. The second end of resistor R14 is connected to the first ends of resistors R15 and R16 respectively. The second end of resistor R16 is connected to the first ends of resistor R17 and capacitor C12 respectively. The second end of resistor R17 is connected to the first ends of resistor R18 and capacitor C13 respectively. The second end of resistor R18, the first ends of resistor R19 and capacitor C14 are all connected to the output end of the reference voltage V2. The second ends of resistors R15, R19 and capacitors C12 to C14 are all connected to the ground end.

[0054] <Regarding the slope voltage generation circuit 15B> The slope voltage generation circuit 15B includes N-channel MOS field effect transistors N11 and N12, P-channel MOS field effect transistors P11 and P12, resistors R11 to R13, capacitor C11, and operational amplifier AMP1.

[0055] Resistors R11 and R12 are connected in series between the applied end of the input voltage Vin and the ground end. The connection node between resistor R11 and resistor R12 corresponds to the output end of the divided voltage Vdiv1 (= {R12 / (R11 + R12)} × Vin) according to the input voltage Vin. The non-inverting input terminal (+) of the operational amplifier AMP1 is connected to the connection node between the above-mentioned resistor R11 and resistor R12. The inverting input terminal (-) of the operational amplifier AMP1 is connected to the source of transistor N1 and the first end of resistor R13. The output terminal of the operational amplifier AMP1 is connected to the gate of transistor N11. The second end of resistor R13 is connected to the ground end.

[0056] The sources of transistors P11 and P12 are both connected to the applied end of the power supply voltage AVCC. The gates of transistors P11 and P12 are both connected to the drain of transistor P11. The drain of transistor P11 is connected to the drain of transistor N11.

[0057] The drains of transistors P12 and N12 and the first terminal of capacitor C11 are all connected to the output terminal of the slope voltage Vsl. The second terminal of capacitor C11 and the source of transistor N12 are both connected to the ground terminal. The gate of transistor N12 is connected to the application terminal of the internal control signal S2.

[0058] The internal control signal S2 is a control signal generated by a signal generation circuit (not shown) so as to switch between a high level and a low level based on the set signal SET output from the oscillator 19. Specifically, the internal control signal S2 becomes low level during the on period of the output element 11 (the period from the detection timing of the rising edge of the set signal SET to the detection timing of the falling edge of the next set signal SET), and becomes high level during the off period of the output element 11 (the period from the detection timing of the falling edge of the set signal SET to the detection timing of the rising edge of the next set signal SET).

[0059] In the slope voltage generation circuit 15B having the above configuration, the operational amplifier AMP1 controls the gate of the transistor N11 so that the non-inverting input terminal (+) and the inverting input terminal (-) are in an imaginary short circuit. As a result, a drain current Id1 (= Vdiv / R13) corresponding to the divided voltage Vdiv1 (and thus the input voltage Vin) flows through the drain of the transistor N11. Also, transistors P11 and P12 form a so-called current mirror, and replicate the above drain current Id1 to generate a charging current Ichg1 (= α × Id1, where α is the mirror ratio).

[0060] Transistor N12 functions as a charge and discharge switch that switches the charge and discharge of capacitor C11 in synchronization with the internal control signal S2. Specifically, during the low level period of the internal control signal S2 (= the on period of the output element 11), the transistor N12 turns off, so the capacitor C11 is charged by the charging current Ichg (the combined current of the charging current Ichg1 and the correction current Ichg2 described later). On the other hand, during the high level period of the internal control signal S2 (= the off period of the output element 11), the transistor N12 turns on, so the capacitor C11 is quickly discharged.

[0061] Note that the slope voltage generation circuit 15B outputs the charging voltage of the capacitor C11 as the slope voltage Vsl. Therefore, the slope voltage Vsl rises with a slope corresponding to the charging current Ichg when the output element 11 is on, and becomes a ramp waveform that quickly falls to zero when the output element 11 is off.

[0062] <Regarding the output ripple suppression circuit 24> As described above, the output ripple suppression circuit 24 corrects the ramp voltage Vrmp according to the voltage value of the triangular wave signal S1. Specifically, the output ripple suppression circuit 24 generates a correction current Ichg2 that varies according to the voltage value of the triangular wave signal S1, and variably controls the charging speed of the capacitor C11 by adding the correction current Ichg2 to the charging current Ichg1. More specifically, it is as follows.

[0063] The output ripple suppression circuit 24 includes an N-channel MOS field effect transistor N30, P-channel MOS field effect transistors P30 and P31, a correction voltage generation circuit 30, a resistor R31, and an operational amplifier AMP2.

[0064] The correction voltage generation circuit 30 is connected between the applied terminal and the ground terminal of the reference voltage Vref, and receives the triangular wave signal S1 from the frequency spread control circuit 22x. The correction voltage generation circuit 30 divides the reference voltage Vref at a ratio corresponding to the input of the triangular wave signal S1 and outputs a divided voltage Vdiv2. In other words, the correction voltage generation circuit 30 increases or decreases the voltage value of the divided voltage Vdiv2 according to the voltage value of the triangular wave signal S1. The specific configuration of the correction voltage generation circuit 30 is as follows.

[0065] The correction voltage generation circuit 30 includes resistors R30a and R30b. The resistors R30a and R30b are connected in series between the applied terminal and the ground terminal of the reference voltage Vref. The connection node between the resistor R30a and the resistor R30b corresponds to the output terminal of the divided voltage Vdiv2 (={R30b / (R30a + R30b)}×Vref) corresponding to the reference voltage Vref.

[0066] Each of the resistors R30a and R30b is a variable resistor configured such that its resistance value varies according to the voltage value of the triangular wave signal S1. The correction voltage generation circuit 30 varies the resistance values of the resistors R30a and R30b according to the voltage value of the triangular wave signal S1, and increases or decreases the voltage value of the divided voltage Vdiv2. Specifically, the correction voltage generation circuit 30 varies the resistance values of the resistors R30a and R30b such that Vdiv2 decreases as the voltage value of the triangular wave signal S1 increases.

[0067] The non-inverting input terminal (+) of the operational amplifier AMP2 is connected to the connection node between the above-described resistors R30a and R30b. The inverting input terminal (-) of the operational amplifier AMP2 is connected to the source of the transistor N30 and the first terminal of the resistor R31. The output terminal of the operational amplifier AMP2 is connected to the gate of the transistor N30. The second terminal of the resistor R31 is connected to the ground terminal.

[0068] The sources of the transistors P30 and P31 are both connected to the terminal to which the power supply voltage AVCC is applied. The gates of the transistors P30 and P31 are both connected to the drain of the transistor P30. The drain of the transistor P30 is connected to the drain of the transistor N30.

[0069] The drain of the transistor P31 is connected to the output terminal of the slope voltage Vsl together with the first terminal of the capacitor C11.

[0070] In the output ripple suppression circuit 24 having the above-described configuration, the operational amplifier AMP2 controls the gate of the transistor N30 such that the non-inverting input terminal (+) and the inverting input terminal (-) are in an imaginary short circuit. As a result, a drain current Id2 (= Vdiv2 / R31) corresponding to the divided voltage Vdiv2 flows through the drain of the transistor N30. Further, the transistors P30 and P31 form a so-called current mirror, and replicate the above-described drain current Id2 to generate a correction current Ichg2 (= β × Id2, where β is the mirror ratio).

[0071] As a result, as described above, a charging current Ichg obtained by synthesizing the charging current Ichg1 and the correction current Ichg2 flows into the capacitor C11. The capacitor C11 is charged by the charging current Ichg. Among the charging current Ichg, the charging current Ichg1 occupies approximately 90%, and the correction current Ichg2 occupies approximately 10%.

[0072] Note that the output ripple suppression circuit 24 varies the correction current Ichg2 according to the triangular wave signal S1. Specifically, the output ripple suppression circuit 24 decreases the current value of the correction current Ichg2 as the voltage value of the triangular wave signal S1 decreases. small That is, the output ripple suppression circuit 24 corrects so as to increase the slope voltage Vsl as the pulse frequency of the set signal SET decrease decreases. As the slope voltage Vsl decreases, lower the ramp voltage Vrmp decreases. lower lower

[0073] Also, the output ripple suppression circuit 24 increases the current value of the correction current Ichg2 as the voltage value of the triangular wave signal S1 increases. large That is, the output ripple suppression circuit 24 corrects so as to increase the slope voltage Vsl as the pulse frequency of the set signal SET increase decreases. As the slope voltage Vsl decreases, upper the ramp voltage Vrmp decreases. The increase and decrease of the current value of the correction current Ichg2 are achieved by variably controlling the resistance values of the resistors R30a and R30b. upper upper

[0074] <Regarding the input stage 20> The input stage 20 includes P-channel type MOS field effect transistors P13 to P19 and resistor circuits R20 and R21.

[0075] ​​​​The sources of transistors P16 to P19 are all connected to the applied terminal of the power supply voltage AVCC. The gates of transistors P16 to P19 are all connected to the drain of transistor P16.

[0076] Transistors P16 to P19 function as a current mirror. Specifically, transistors P16 to P19 replicate the reference current Iref input to the drain of transistor P16 and output it from the drains of transistors P17 to P19.

[0077] The drain of transistor P18, together with the source of transistor P14, is connected to the non-inverting input terminal (+) of the reset comparator 16 and the inverting input terminal (-) of the skip comparator 18. The drain of transistor P14 is connected to the ground terminal. The gate of transistor P14 is connected to the applied terminal of the error voltage Vc.

[0078] The resistance circuit R20 includes an N-channel MOS field effect transistor N20, resistors R20a, and R20b. The applied terminal of the internal control signal S3 is connected to the gate of transistor N20. The drain of transistor N20 is connected to the first terminal of resistor R20a. The source of transistor N20 is connected to the first terminal of resistor R20b. The second terminal of resistor R20a is connected to the inverting input terminal (-) of the reset comparator 16 together with the drain of transistor P17. The second terminal of resistor R20b is connected to the source of transistor P13. The drain of transistor P13 is connected to the ground terminal. The gate of transistor P13 is connected to the applied terminal of the slope voltage Vsl.

[0079] A current sense signal Vsns is applied to a connection node n1 between a second terminal of a resistor R20a and a drain of a transistor P17. At the connection node n1, a voltage signal is generated by adding a voltage value of the current sense signal Vsns and a voltage value obtained by multiplying a drain current of the transistor P13 (= a current value corresponding to an on-threshold voltage and a reference current Iref of the transistor P13) by a combined resistance value of the resistor R20a and the resistor R20b. The voltage signal generated at this connection node n1 is input as a lamp voltage Vrmp to an inverting input terminal (-) of a reset comparator 16. The reset comparator 16 compares an on-threshold voltage Vca of the transistor P14 with the lamp voltage Vrmp and generates a reset signal RST.

[0080] As described above, the slope voltage Vsl has a ramp waveform that changes according to an internal control signal S2 (more specifically, an on / off state of the output element 11). The drain current of the transistor P13 fluctuates according to this slope voltage Vsl. The voltage across both ends of the resistors R20a and 20b fluctuates according to this drain current, thereby causing the lamp voltage Vrmp to fluctuate.

[0081] By increasing the current value of the correction current Ichg2 in the output ripple suppression circuit 24 to increase the charging speed of the capacitor C11, the increase rate of the current value of the drain current of the transistor P13 becomes higher. As a result, the increase rate of the voltage value of the lamp voltage Vrmp becomes higher (= the lamp voltage Vrmp rises). Conversely, by decreasing the current value of the correction current Ichg2 in the output ripple suppression circuit 24 to decrease the charging speed of the capacitor C11, the increase rate of the current value of the drain current of the transistor P13 becomes lower. As a result, the increase rate of the voltage value of the lamp voltage Vrmp becomes lower (= the lamp voltage Vrmp falls).

[0082] Note that the resistance circuit R20 is configured to be able to vary a combined resistance of the resistor R20a and the resistor 20b. Specifically, by varying a voltage value of an internal control signal S3 input to a gate of the transistor N20 to control a voltage across both ends of the resistor R20b, the combined resistance of the resistor R20a and the resistor R20b is varied.

[0083] The resistance circuit R21 includes an N-channel MOS field-effect transistor N21, resistors R21a and R21b. The applied end of the internal control signal S4 is connected to the gate of the transistor N21. The drain of the transistor N21 is connected to the first end of the resistor R21a. The source of the transistor N21 is connected to the first end of the resistor R21b. The second end of the resistor R21a is connected to the non-inverting input terminal (+) of the skip comparator 18 together with the drain of the transistor P19. The second end of the resistor R21b is connected to the source of the transistor P15. The drain of the transistor P15 is connected to the ground terminal. The gate of the transistor P15 is connected to the applied end of the reference voltage V2.

[0084] At the connection node n2 between the second end of the resistor R21a and the drain of the transistor P19, a node voltage V2a is generated by adding the reference voltage V2, the on-threshold voltage of the transistor P15, the voltage across both ends of the resistor R21a, and the voltage across both ends of the resistor R21b. The node voltage V2a is input to the non-inverting input terminal (+) of the skip comparator 18.

[0085] The resistance circuit R21 is configured to be able to switch the resistance value of the resistor R21b. Specifically, by varying the voltage value of the internal control signal S4 input to the gate of the transistor N21, it is possible to control the switching of the resistance value of the resistor R21b.

[0086] The skip comparator 18 compares the on-threshold voltage Vca of the transistor P14 with the node voltage V2a to generate a skip signal SKIP. The skip signal SKIP becomes low level when Vc > V2 (when Vca > V2a), and becomes high level when Vc < V2 (Vca > V2a) (when Vca < V2a).

[0087] <Regarding the modulation of the pulse frequency and the up and down fluctuations of the output voltage Vout in the present disclosure> FIG. 5 is a timing chart showing the output voltage Vout of the power supply device X according to the embodiment of the present disclosure, the triangular wave signal S1, the error voltage Vc, and the ramp voltage Vrmp.

[0088] As shown in FIG. 5, in the period from time t11 to t12, the voltage value of the triangular wave signal S1 is decreasing. At this time, as described above, as the voltage value of the triangular wave signal S1 decreases, the pulse frequency of the set signal SET decreases (not shown).

[0089] Here, as described above, the output ripple suppression circuit 24 corrects so as to increase the ramp voltage Vrmp as the pulse frequency of the set signal SET decreases. Then, the rate of increase of the voltage value of the ramp voltage Vrmp lower increases. That is, the interval from the rising timing of the ramp voltage Vrmp to the timing when the ramp voltage Vrmp and the error voltage Vc coincide decrease becomes shorter. For this reason, as the pulse frequency of the set signal SET decreases, the pulse frequency of the reset signal RST also decreases. As a result, even if the voltage value of the triangular wave signal S1 decreases in the period from time t11 to t12, the decrease in the on-duty of the switch output stage HB is suppressed. That is, when the voltage value of the triangular wave signal S1 increases, it is possible to suppress the increase in the average current of the inductor current IL (output current) and thus the output voltage Vout. long

[0090] Also, in the period from time t12 to t13, the voltage value of the triangular wave signal S1 is increasing. At this time, as described above, as the voltage value of the triangular wave signal S1 increases, the pulse frequency of the set signal SET increases (not shown).

[0091] Here, as described above, the output ripple suppression circuit 24 corrects so as to increase the ramp voltage Vrmp as the pulse frequency of the set signal SET increases. Then, the rate of increase of the voltage value of the ramp voltage Vrmp upper increases. rise ​That is, the interval from the rising timing of the lamp voltage Vrmp to the timing when the lamp voltage Vrmp and the error voltage Vc coincide is short reduced. Therefore, as the pulse frequency of the set signal SET increases, the pulse frequency of the reset signal RST also increases. As a result, even if the voltage value of the triangular wave signal S1 increases during the period from time t12 to t13, the increase in the on-duty of the switch output stage HB is suppressed. That is, when the voltage value of the triangular wave signal S1 decreases, it is possible to suppress the decrease in the average current of the inductor current IL and thus the output voltage Vout.

[0092] Therefore, it is possible to suppress the up and down fluctuations of the output voltage Vout (that is, suppress the increase in the ripple voltage of the output voltage Vout) while modulating the switching frequency of the switch output stage HB to suppress EMI noise.

[0093] <Modification Example> In addition, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. For example, as the output element 11, a P-channel type MOS field effect transistor may be used. Also, as the rectifying element 12, a diode may be used. That is, the rectification method of the power supply device X is not limited to the synchronous rectification method, and a diode rectification method may be adopted. Further, at least one of the output element 11 and the rectifying element 12 may be externally attached to the power supply control device 10x.

[0094] Also, part or all of the phase compensation circuit 14 may be externally attached to the power supply control device 10x.

[0095] Also, while the output ripple suppression circuit 24 controls the output of the ramp voltage generation circuit 15 to correct the ramp voltage Vrmp according to the pulse frequency of the set signal SET, alternatively, the error signal Vc can be corrected to control the output of the ramp voltage generation circuit 15. Specifically, as the pulse frequency of the set signal SET decreases, the output ripple suppression circuit 24 corrects the error signal Vc to increase or decrease it. Conversely, as the pulse frequency of the set signal SET increases, the output ripple suppression circuit 24 corrects the error signal Vc to increase it.

[0096] Also, the output ripple suppression circuit 24 can correct the current sense signal Vsns to correct the ramp voltage Vrmp. Specifically, as shown in FIG. 6, the output ripple suppression circuit 24 is connected to the current detection circuit 15A. Then, the output ripple suppression circuit 24 corrects the current sense signal Vsns by synthesizing the detected value of the inductor current IL with the current value of the correction current Ichg2, thereby increasing or decreasing the ramp voltage Vrmp.

[0097] Also, as shown in FIG. 7, the output terminal of the output ripple suppression circuit 24 may be configured to be connected to the connection node n1. The output ripple suppression circuit 24 injects the correction current Ichg2 into the connection node n1. As a result, during the on period of the transistor P13 (i.e., the off period of the transistor N12 and the on period of the output element 11), the connection node n1 has a voltage value calculated by multiplying the combined current of the drain current of the transistor P13 (the current corresponding to the on threshold voltage and the reference current Iref of the transistor P13) and the correction current Ichg2 by the combined resistance value of the resistor R20a and the resistor R20b, which serves as the ramp voltage Vrmp.

[0098] Also, as shown in FIG. 8, the output terminal of the output ripple suppression circuit 24 may be connected to the connection node n1 and the drain of the transistor N12 (= the output terminal of the slope voltage Vsl). In this case, at the connection node n1, a voltage value calculated by multiplying the combined resistance value of the resistor R20a and the resistor R20b by the combined current obtained by adding the drain current of the transistor P13 (a current corresponding to the on-threshold voltage of the transistor P13 and the reference current Iref) and a part of the correction current Ichg2 occurs as the ramp voltage Vrmp. Also, the remaining part of the correction current Ichg2 charges the capacitor C11 together with the charging current Ichg1. The output ripple suppression circuit 24 corrects the ramp voltage Vrmp by directly varying the voltage value of the connection node n1 with the correction current Ichg2 and increasing the charging speed of the capacitor C11 to correct the slope voltage Vsl.

[0099] Note that, in these cases as well, the output ripple suppression circuit 24, similar to the description in the above embodiment, lowers the ramp voltage Vrmp by decreasing the current value of the correction current Ichg2 as the voltage value of the triangular wave signal S1 decreases, and raises the ramp voltage Vrmp by increasing the current value of the correction current Ichg2 as the voltage value of the triangular wave signal S1 increases.

[0100] <Appendix> The drive circuit (10X) disclosed in the specification includes a switch output stage (HB) configured to generate a switch voltage (Vsw) that is pulse-driven between a first logic value and a second logic value, a first signal generation circuit (19) configured to generate a first signal (SET) that defines the switching timing of the switch voltage (Vsw) to the first logic value, a second signal generation circuit (16) configured to generate a second signal (RST) that defines the switching timing of the switch voltage (Vsw) to the second logic value according to the comparison between the error signal (Vc) and the ramp voltage (Vrmp), a drive control circuit (1B) configured to control the switch output stage (HB) to pulse-drive the switch voltage (Vsw) according to the first signal (SET) and the second signal (RST), a frequency spread control circuit (22x) configured to perform frequency spread control on the oscillation frequency of the first signal (SET), and an output ripple suppression circuit (24) configured to correct at least one of the error signal (Vc) and the ramp voltage (Vrmp) according to the oscillation frequency after the frequency spread control and control the second signal generation circuit (16) (the first configuration).

[0101] The drive circuit (10X) according to the first configuration may include a first current generation circuit (P12) configured to generate a predetermined first current (Ichg1), and a current-voltage conversion circuit (15) configured to convert a current signal (Ichg) including the first current (Ichg1) into a ramp voltage (Vrmp). The output ripple suppression circuit (24) may be configured to generate a second current (Ichg2) whose current value varies based on the oscillation frequency, and correct the ramp voltage (Vrmp) by flowing the second current (Ichg2) into the current-voltage conversion circuit (15) so that the second current (Ichg2) is included in the current signal (Ichg) (the second configuration).

[0102] The drive circuit (10X) according to the second configuration may be configured to include a variable voltage generation circuit (30) configured to generate a variable voltage (Vdiv2) whose voltage value varies at the oscillation frequency, and a second current generation circuit (P31) configured to generate a second current (Ichg2) according to the variable voltage (Vdiv2) (third configuration).

[0103] The drive circuit (10X) according to the third configuration may be configured such that the variable voltage generation circuit (30) includes a variable resistance circuit (R30a, R30b) configured such that the resistance value varies based on the oscillation frequency, and is configured to generate a variable voltage (Vdiv2) according to the resistance value (fourth configuration).

[0104] The drive circuit (10X) according to any one of the second to fourth configurations may be configured such that the current-voltage conversion circuit (15) includes a capacitor (C11) charged by a current signal and outputting a charge-discharge voltage (Vsl) corresponding to the charged charge amount, and a voltage control circuit (P13, R20, 15C, 20, n1) configured to generate a lamp voltage (Vrmp) based on the charge-discharge voltage (Vsl). The output ripple suppression circuit (24) may be configured to correct the lamp voltage (Vrmp) by flowing the second current (Ichg2) into the capacitor (C11) so that the current signal includes a combined current of the first current (Ichg1) and the second current (Ichg2) and correcting the charge-discharge voltage (Vsl) (fifth configuration).

[0105] The drive circuit (10X) according to any one of the second to fourth configurations includes an output current generation circuit (L1) that generates an output current (IL) according to a switch voltage (Vsw). The current-voltage conversion circuit (15) includes a detection voltage generation circuit (15A) that detects the output current (IL) and generates a detection voltage (Vsns) according to the output current (IL), a capacitor (C11) that is charged by a current signal and outputs a charge-discharge voltage (Vsl) according to the charged charge amount, a third current generation circuit (20) that generates a predetermined third current (Iref), and a voltage control circuit (P13, R20, 15C, 20, n1) configured to generate a lamp voltage (Vrmp) based on the charge-discharge voltage (Vsl), the third current (Iref), and the detection voltage (Vsns). The output ripple suppression circuit (24) may be configured to correct the lamp voltage (Vrmp) by flowing a second current (Ichg2) into the third current generation circuit (20), combining the second current (Ichg2) with the third current (Iref), and correcting the third current (Iref) (the sixth configuration).

[0106] The drive circuit (10X) according to the first configuration includes an output current generation circuit (L1) configured to generate an output current (IL) according to a switch voltage (Vsw), a first current generation circuit (P12) configured to generate a predetermined first current (Ichg1), and a current-voltage conversion circuit configured to convert a current signal including the first current (Ichg1) into a lamp voltage (Vrmp). The current-voltage conversion circuit includes a detection voltage generation circuit (15A) configured to detect the output current (IL) and generate a detection voltage (Vsns) according to the output current (IL), a capacitor (C11) configured to be charged by a current signal and output a charge-discharge voltage (Vsl) according to the charged charge amount, and a voltage control circuit (15) configured to generate a lamp voltage (Vrmp) based on the charge-discharge voltage (Vsl) and the detection voltage (Vsns). The output ripple suppression circuit (24) may be configured to correct the lamp voltage (Vrmp) by flowing a second current (Ichg2) into the detection voltage generation circuit (15A), combining the second current (Ichg2) with the output current (IL), and correcting the detection voltage (Vsns) (the seventh configuration).

[0107] The semiconductor device disclosed in the specification may be configured to integrate a drive circuit (10X) according to any one of the first to seventh configurations (eighth configuration).

[0108] The power supply device (X) disclosed in the specification includes a semiconductor device according to the eighth configuration and a rectifying and smoothing circuit (25) configured to rectify and smooth a switch voltage (Vsw) to generate an output voltage (Vout). The semiconductor device may be configured to include an error signal generation circuit (13) configured to generate an error signal (Vc) according to a difference between the output voltage (Vout) and a target voltage (Vref) of the output voltage (Vout) (ninth configuration).

Explanation of Signs

[0109] 1B Driver 10x Power control device 10y Power control device 11 Output element 12 Rectifying element 13 Error amplifier 14 Phase compensation circuit 15 Ramp voltage generation circuit 15A Current detection circuit 15B Slope voltage generation circuit 15C Addition circuit 16 Reset comparator 17 Reference voltage generation circuit 18 Skip comparator 19 Oscillator 20 Input stage 21x SSCG circuit 21y SSCG circuit 22x Frequency spread control circuit 22y Frequency spread control circuit 23 Skip signal generation circuit 24 Output ripple suppression circuit 25 Smoothing rectifying circuit 30 Voltage dividing circuit AMP1 Operational amplifier AMP2 Operational amplifier AVCC power supply voltage Capacitors C1 and C2 Capacitors C11 to C14 Gate signals G1 and G2 HB switch output stage Error current I0 Inductor current IL Charge current Ichg Charge current Ichg1 Correction current Ichg2 Drain currents Id1 and Id2 Reference current Iref Inductor L1 Transistors N11 and N12 Transistors N20 and N21 Transistor N30 Transistors P11 to P19 Transistors P30 and P31 PGND ground terminal Resistors R1 and R2 Resistors R11 to R19 Resistance circuits R20 and R21 Resistors R20a and R20b Resistors R21a and R21b Resistors R30a and R30b Resistor R31 Reset signal RST Triangle wave signal S1 Internal control signals S2 to S4 Set signal SET Skip signal SKIP External terminals T1 to T4 Reference voltage V2 Node voltage V2a Error voltage Vc On threshold voltage Vca Divided voltage Vdiv1 Divided voltage Vdiv2 Feedback voltage Vfb Input voltage Vin Output voltage Vout Reference voltage Vref Ramp voltage Vrmp Vsl Slope Voltage Vsns Current Sense Signal Vsw Switch Voltage X Power Supply Y Power Supply n1 Connection Node n2 Connection Node

Claims

1. A switch output stage configured to generate a switched voltage that is pulse-driven between a first logic value and a second logic value; A first signal generation circuit configured to generate a first signal that defines the switching timing of the switched voltage to the first logic value; A second signal generation circuit configured to generate a second signal that defines the switching timing of the switched voltage to the second logic value in response to a comparison between an error signal and a ramp voltage; A drive control circuit configured to control the switch output stage to pulse-drive the switched voltage in response to the first signal and the second signal; A frequency spread control circuit configured to frequency spread control the oscillation frequency of the first signal; An output ripple suppression circuit configured to correct at least one of the error signal and the ramp voltage in accordance with the oscillation frequency after frequency spread control, and to control the second signal generation circuit; A drive circuit comprising the above.

2. A first current generation circuit configured to generate a predetermined first current; A current-voltage conversion circuit configured to convert a current signal including the first current into the ramp voltage; Comprising, The output ripple suppression circuit generates a second current whose current value varies based on the oscillation frequency, and corrects the ramp voltage by flowing the second current into the current-voltage conversion circuit so that the second current is included in the current signal. The drive circuit according to claim 1.

3. The output ripple suppression circuit, A variable voltage generation circuit configured to generate a variable voltage whose voltage value varies at the oscillation frequency; A second current generation circuit configured to generate the second current in response to the variable voltage; The drive circuit according to claim 2, including the above.

4. The variable voltage generation circuit includes a variable resistance circuit configured such that the resistance value varies based on the oscillation frequency, and generates the variable voltage according to the resistance value. The drive circuit according to claim 3.

5. The current-voltage conversion circuit, A capacitor that is charged by the current signal and outputs a charge-discharge voltage corresponding to the charged charge amount; A voltage control circuit configured to generate the ramp voltage based on the charge-discharge voltage; Including, The drive circuit according to claim 2, wherein the output ripple suppression circuit corrects the lamp voltage by flowing the second current into the capacitor so that the current signal includes a combined current of the first current and the second current, thereby correcting the charge and discharge voltage.

6. An output current generation circuit configured to generate an output current corresponding to the switch voltage, The current-voltage conversion circuit, A detection voltage generation circuit configured to detect the output current and generate a detection voltage corresponding to the output current; A capacitor configured to be charged by the current signal and output a charge and discharge voltage corresponding to the charged charge amount; A third current generation circuit configured to generate a predetermined third current; A voltage control circuit configured to generate the lamp voltage based on the charge and discharge voltage, the third current, and the detection voltage; including The drive circuit according to claim 2, wherein the output ripple suppression circuit corrects the lamp voltage by flowing the second current into the third current generation circuit, combining the second current with the third current, and correcting the third current.

7. An output current generation circuit configured to generate an output current corresponding to the switch voltage; A first current generation circuit configured to generate a predetermined first current; A current-voltage conversion circuit configured to convert a current signal including the first current into the lamp voltage; comprising The current-voltage conversion circuit, A detection voltage generation circuit configured to detect the output current and generate a detection voltage corresponding to the output current; A capacitor configured to be charged by the current signal and output a charge and discharge voltage corresponding to the charged charge amount; A voltage control circuit configured to generate the lamp voltage based on the charge and discharge voltage and the detection voltage; including The drive circuit according to claim 1, wherein the output ripple suppression circuit corrects the lamp voltage by flowing the second current into the detection voltage generation circuit, combining the second current with the output current, and correcting the detection voltage.

8. A semiconductor device in which the drive circuit according to any one of claims 1 to 7 is integrated.

9. The semiconductor device according to claim 8, A rectifying and smoothing circuit configured to rectify and smooth the switch voltage to generate an output voltage; comprising The semiconductor device is a power supply device including an error signal generation circuit configured to generate the error signal according to a difference between the output voltage and a target voltage of the output voltage.

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