Semiconductor device, frequency trimming register, ultrasonic sonar sensor and vehicle

Abstract

To improve robustness of a value of a flip-flop included in a semiconductor device.SOLUTION: A semiconductor device (1, 1A, 1B) comprises: a holder circuit (2, 2A) including flip-flops (71-77, 811, 812, 813); an ECC encoder (3) capable of outputting an ECC value (Ne) and output data (Dout) or correction data (Dcor); an ECC storage section (4) which stores the ECC value (Ne) as a storage value (Nf); a comparator circuit (5) which determines from the ECC value (Ne) and the storage value (Nf) whether or not an error of the output data (Dout) is correctable; and a self-refresh circuit (6) configured to execute self-refresh for overwriting the holder circuit (2, 2A) with the correction data (Dcor) when there is a correctable error in the output data (Dout).SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device, a frequency trimming register using the semiconductor device, an ultrasonic sonar sensor using the frequency trimming register, and a vehicle.

Background Art

[0002] A semiconductor device stores and updates values in a volatile element called a flip-flop. In a semiconductor device, it is known that the value of a flip-flop is destroyed by soft errors caused by power supply and ground noise, noise (EMS: Electro Magnetic Susceptibility) emitted from other devices, and external disturbance noise such as cosmic rays (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] There is an increasing demand for improving the robustness of the values of flip-flops included in semiconductor devices.

[0005] A semiconductor device according to an aspect of the present disclosure includes a holding circuit configured to have at least one flip-flop for each bit data of input data and hold the bit data, an ECC encoder configured to output an ECC value decoded according to the bit data held by the holding circuit and output data according to the plurality of bit data or corrected data obtained by correcting the output data when an error exists in the output data and correction is possible, an ECC storage unit configured to store the ECC value as a stored value, A comparison circuit configured to compare the ECC value output from the ECC encoder with the stored value stored in the ECC storage unit and determine whether the ECC encoder can correct it; A self-refresh circuit configured to execute self-refresh to overwrite the holding circuit with the corrected data when the comparison circuit determines that there is an error in the output data and the error can be corrected by the ECC encoder.

Brief Description of the Drawings

[0006]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

[0007] [Detailed Description] Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the drawings referred to, the same parts are denoted by the same reference numerals, and redundant descriptions regarding the same parts are omitted in principle. In this specification, for the sake of simplification of description, the names of information, signals, physical quantities, functional parts, circuits, elements, or components, etc. corresponding to the symbols or reference numerals may be omitted or abbreviated by indicating the symbols or reference numerals of information, signals, physical quantities, functional parts, circuits, elements, or components, etc.

[0008] In this specification, "connection" between any circuit elements, wirings, and a plurality of parts forming a circuit includes the case of being mechanically connected and also includes the case of being electrically connected, in other words, the case where electricity flows. That is, "connect" includes the case of "electrically connecting".

[0009] Also, "ground" refers to a reference conductive part having a reference potential of 0V (zero volts) or the 0V potential itself. The reference conductive part is formed of a conductor such as metal. The 0V potential may also be referred to as the ground voltage GND. In the embodiments of the present disclosure, a voltage shown without particularly providing a reference represents a voltage seen from the ground voltage GND.

[0010] There may be a case where it is said that the value of the output is inverted, and inversion means that the value switches from "0" to "1" or from "1" to "0".

[0011] In this specification, a MOS (Metal Oxide Semiconductor) field effect transistor refers to a transistor whose gate structure is composed of at least three layers of "a layer made of a conductor or a semiconductor such as polysilicon having a small resistance value", "an insulating layer", and "a P-channel type, N-channel type, or intrinsic semiconductor layer". That is, the gate structure of a MOS field effect transistor is not limited to a three-layer structure of metal, oxide, and semiconductor.

[0012] <First Embodiment> A first embodiment of the present disclosure will be described. FIG. 1 is a configuration diagram of an example of a semiconductor device 1 according to the first embodiment. In the semiconductor device 1, input data Din is held and output to an external device as output data Dout. The input data Din input to the semiconductor device 1 is digital data, which is 8 bits here, but the input data Din is not limited to 8-bit data.

[0013] FIG. 2 is a schematic diagram showing the structure of the input data Din. As shown in FIG. 2, in the semiconductor device 1, the input data Din is 8-bit digital data. And the input data Din has a configuration in which bit data Bt1 to Bt8 taking values of "0" or "1" are arranged in order. The semiconductor device 1 has an input terminal 11 configured to be able to input each of the 8-bit data Bt1 to Bt8. Further, the semiconductor device 1 has an output terminal 12 that outputs output data Dout or correction data Dcor, which is digital data of the same number of bits as the input data Din, to a processing device COM provided outside.

[0014] The semiconductor device 1 shown in FIG. 1 includes a holding circuit 2, an ECC (Error Correction Cord) encoder 3, an ECC storage unit 4, a comparison circuit 5, and a self-refresh circuit 6. Note that the semiconductor device 1 is an integrated circuit IC (Integrated Circuit) in which the holding circuit 2, the ECC encoder 3, the ECC storage unit 4, the comparison circuit 5, and the self-refresh circuit 6 are integrated on a single semiconductor substrate Bd (see FIG. 5), but is not limited thereto.

[0015] <Holding Circuit 2> The holding circuit 2 has a configuration for holding the input data Din and is, for example, a register. The holding circuit 2 has terminals to which the bit data Bt1 to Bt8 of the input terminal 11 are input. The holding circuit 2 includes seven flip-flops 71 to 77 and a bit error correction circuit 8.

[0016] The seven flip-flops 71 to 77 are D-type flip-flops. Bit data Bt1 to Bt7 are input to the input terminals of the seven flip-flops 71 to 77 respectively. Each of the flip-flops 71 to 77 holds the value of the bit data Bt1 to Bt7. A synchronized clock signal is input to the reset terminals of each of the flip-flops 71 to 77. The flip-flops 71 to 77 output the held data as output Df1 to Df7.

[0017] In the semiconductor device 1, soft errors may occur in which the built-in flip-flops malfunction due to external disturbance noises such as power supply and ground noises, EMS, and cosmic rays. Therefore, the semiconductor device 1 has a configuration in which the ECC encoder 3 corrects errors caused by flip-flops, and includes a bit error correction circuit 8 as a circuit for holding bit data Bt8 that requires higher reliability than the other bit data Bt1 to Bt7.

[0018] <Bit error correction circuit 8> FIG. 3 is a configuration diagram of the bit error correction circuit 8. As shown in FIG. 1, bit data Bt8 is input to the bit error correction circuit 8. The bit data Bt8 is data that requires higher reliability than the bit data Bt1 to Bt7. As shown in FIG. 3, the bit error correction circuit 8 includes a multiplexing circuit 81, a majority decision circuit 82, an error detection circuit 83, and a multiplexing refresh circuit 84.

[0019] As shown in FIG. 3, the multiplexing circuit 81 has a plurality of, here, three flip-flops 811, 812, and 813. In the multiplexing circuit 81, the flip-flops 811, 812, and 813 are connected in parallel. Bit data Bt8 is input to the multiplexing circuit 81, and the bit data Bt8 is input to each of the flip-flops 811, 812, and 813 via a wiring formed by branching.

[0020] Also, the outputs of flip - flops 811, 812, and 813 are input to the majority - voting circuit 82. The majority - voting circuit 82 has a plurality of, here, three AND circuits 821, 822, 823 and an OR circuit 824. The outputs of flip - flop 811 and flip - flop 812 are input to AND circuit 821. Also, the outputs of flip - flop 812 and flip - flop 813 are input to AND circuit 822. Further, the outputs of flip - flop 813 and flip - flop 811 are input to AND circuit 823. Then, the outputs of each of AND circuits 821, 822, 823 are input to OR circuit 824. The output of OR circuit 824 is the output Df8 of the bit - error correction circuit 8.

[0021] The error - detection circuit 83 detects the outputs of flip - flops 811, 812, and 813. The error - detection circuit 83 detects the presence or absence of an error based on the outputs of flip - flops 811, 812, and 813.

[0022] And the error - detection circuit 83 outputs an error - detection output Sgm to the multiplexed refresh circuit 84. The error - detection output Sgm is "0" when there is no error and becomes "1" when an error is detected.

[0023] The multiplexed refresh circuit 84 receives the error - detection output Sgm from the error - detection circuit 83 and detects the output Df8 of the OR circuit 824. Then, when the error - detection output Sgm is "1", the multiplexed refresh circuit 84 adjusts (refreshes) the flip - flops 811, 812, and 813 so that the outputs of flip - flops 811, 812, and 813 become the output Df8, and outputs a multiplexed refresh signal Rfm.

[0024] By including the multiplexing circuit 81 and the majority voting circuit 82, even if a malfunction occurs in any of the flip-flops 811, 812, and 813 due to external disturbance noise such as EMS or cosmic rays and one of the outputs is inverted, the output Df8 of the OR circuit 824 becomes a value corresponding to the bit data Bt8 which is the input signal. In the present embodiment, the output Df8 of the OR circuit 824 is the same value as the bit data Bt8. That is, the bit error correction circuit 8 holds the bit data Bt8 and can correct the outputs of the flip-flops 811, 812, and 813 to the correct outputs even if an error occurs in the multiplexing circuit 81.

[0025] Since the bit error correction circuit 8 has a configuration including the multiplexing circuit 81 and the majority voting circuit 82, even if an error occurs in any of the flip-flops 811, 812, and 813, the inversion of the output is suppressed. Furthermore, in the bit error correction circuit 8, by refreshing the flip-flops 811, 812, and 813 promptly after an error occurs, the flip-flops 811, 812, and 813 can be set to a state where no error has occurred.

[0026] There may be a case where external disturbance noise acts continuously on the bit error correction circuit 8. Even in such a case, it is possible to suppress the occurrence of a soft error in another flip-flop while a soft error has occurred in one of the flip-flops 811, 812, and 813. That is, it is possible to suppress the occurrence of errors in two of the flip-flops 811, 812, and 813 simultaneously. As a result, the output Df8 of the bit error correction circuit 8 has higher reliability compared to the outputs Df1 to Df7 based on the bit data Bt1 to Bt7.

[0027] Also, the error detection output Sgm is output to an external processing device COM. The external processing device COM can recognize that an error has occurred in the bit error correction circuit 8 but the error has been corrected. For example, when the output of the error detection output Sgm from the bit error correction circuit 8 occurs frequently, it is also possible to determine that there is a problem in one of the flip-flops 811, 812, and 813.

[0028] <ECC Encoder 3> The output Df1 to Df7 of flip-flops 71 to 77 and the output Df8 of the bit error correction circuit 8 are input to the ECC encoder 3. That is, the outputs Df1 to Df8 output according to the bit data Bt1 to Bt8 held by the holding circuit 2 are input.

[0029] The ECC encoder 3 generates an ECC value Ne which is a value for identifying an error based on the outputs Df1 to Df8. Then, the ECC encoder 3 outputs the ECC value Ne to the ECC storage unit 4 and the comparison circuit 5. The ECC encoder 3 can identify the bit data in which an error has occurred based on the ECC value Ne and correct the bit data. Then, the ECC encoder 3 generates at least one of output data Dout, correction data Dcor, and processed data Dcrr according to the outputs Df1 to Df8 and outputs it to the processing device COM.

[0030] The ECC encoder 3 sends the ECC value Ne when no error has occurred to the ECC storage unit 4. The ECC storage unit 4 stores the ECC value Ne when no error has occurred. Note that the ECC encoder 3 may send the new ECC value Ne to the ECC storage unit 4 when, for example, the input data Din is switched and a new ECC value Ne is generated. By doing so, the processing can be reduced compared to the case of constantly transmitting the ECC value Ne. The ECC storage unit 4 has a configuration capable of outputting a stored value Nf which is the ECC value stored for the comparison circuit 5. Also, the ECC storage unit 4 has a configuration capable of outputting the stored value Nf to the ECC encoder 3.

[0031] The ECC encoder 3 can identify and correct the output in which an error has occurred only when an error has occurred in one of the outputs Df1 to Df8. That is, when an error has occurred in one of the outputs Df1 to Df8, the ECC encoder 3 generates correction data Dcor obtained by correcting the error by arithmetic processing and outputs it to the processing device COM.

[0032] Also, when there is no error, the ECC encoder 3 outputs output data Dout corresponding to the outputs Df1 to Df8 to the processing device COM. Also, when an error occurs in two or more outputs, the same process as the generation of the correction data Dcor is performed to generate the processed data Dcrr and output it to the processing device COM. Note that when an error occurs in two or more outputs, the ECC encoder 3 may output, as the processed data Dcrr, data corresponding to the outputs Df1 to Df8 including an error by the same process as the generation of the output data Dout.

[0033] <Comparison circuit 5> The comparison circuit 5 compares the ECC value Ne generated by the ECC encoder 3 with the stored value Nf which is the ECC value stored in the ECC storage unit 4 to determine whether there is an error in the outputs Df1 to Df8.

[0034] When there is an error in one of the outputs Df1 to Df8, the comparison circuit 5 outputs a correction error output Err1 to the processing device COM. The value of the correction error output Err1 is "0" when there is no error, and "1" when there is an error in one or more outputs.

[0035] Also, when there are errors in two or more of the outputs Df1 to Df8, the comparison circuit 5 outputs a non-correctable error output Err2 to the processing device COM. The value of the non-correctable error output Err2 is "0" when there is no error or when there is an error in one output, and "1" when there are errors in two or more outputs.

[0036] The values of the correction error output Err1 and the non-correctable error output Err2 output to the processing device COM are either both "0", both "1", or the correction error output Err1 is "0" and the non-correctable error output Err2 is "1".

[0037] <Self-refresh circuit 6> The self-refresh circuit 6 acquires any one of the output data Dout, correction data Dcor, and processed data Dcrr output from the ECC encoder 3, and the correction error output Err1 or the uncorrectable error output Err2. Then, based on the values of the correction data Dcor and the correction error output Err1 or the uncorrectable error output Err2, the self-refresh circuit 6 outputs a self-refresh signal Rfs to the holding circuit 2. The holding circuit 2 adjusts (refreshes) the flip-flops 71 to 77 and the flip-flops 811, 812, 813 of the bit error correction circuit 8 as necessary based on the self-refresh signal Rfs.

[0038] The self-refresh circuit 6 outputs the self-refresh signal Rfs when the correction error output Err1 is "1" and the uncorrectable error output Err2 is "0". Note that the ECC encoder 3 may be configured to send a value that is uncorrectable instead of outputting the uncorrectable error output Err2 to the self-refresh circuit 6.

[0039] The semiconductor device 1 has the configuration as described above.

[0040] <Configuration of Semiconductor Device 1> Next, the operation of the semiconductor device 1 will be described with reference to the drawings. FIG. 4 is a flowchart showing the operation of the semiconductor device 1.

[0041] As shown in FIG. 4, when the ECC encoder 3 receives the outputs Df1 to Df8, it generates an ECC value Ne (step S101). The ECC encoder 3 determines the presence or absence of an error based on the ECC value Ne and the stored value Nf (step S102). If there is no error (Yes in step S102), the ECC encoder 3 outputs the output data Dout obtained by arranging the outputs Df1 to Df8 in order (step S103).

[0042] Also, when there is an error (if the answer is "No" in step S102), the ECC encoder 3 determines whether it can identify the output in which the error has occurred among the outputs Df1 to Df8 (step S104). Note that being able to identify the output in which the error has occurred can include the case where it is determined that there is an error in one of the outputs Df1 to Df8. In other words, not being able to identify the output in which the error has occurred can include the case where it is determined that there are errors in two or more of the outputs Df1 to Df8.

[0043] When the output in which the error has occurred can be identified (if the answer is "Yes" in step S104), the ECC encoder 3 performs an operation to correct the error and outputs corrected data Dcor, which is the output including the corrected output arranged in order, to the processing device COM (step S105).

[0044] Also, when the output in which the error has occurred cannot be identified (if the answer is "No" in step S104), the ECC encoder 3 outputs processed data Dcrr obtained by performing the same operation as when generating the corrected data Dcor on the outputs Df1 to Df8 including the error (step S106). Note that when the output in which the error has occurred cannot be identified, the ECC encoder 3 may be configured to output, without correction, the data obtained by arranging the outputs Df1 to Df8 in order as the processed data Dcrr. In this case, when the answer is "No" in step S104, the configuration may be such that the process transitions to step S103.

[0045] The ECC encoder 3 outputs the ECC value Ne to the comparison circuit 5 (step S107). Note that step S107 is configured to be executed after steps S103 to S106, but is not limited thereto. For example, step S107 may be executed before steps S103 to S106. Also, step S107 may be executed simultaneously with any one of steps S103 to S106.

[0046] When the comparison circuit 5 receives the ECC value Ne, the comparison circuit 5 calls the stored value Nf from the ECC storage unit 4 (step S108). Then, the comparison circuit 5 compares the ECC value Ne with the stored value Nf and determines whether there is an error in the output Df1 to output Df8 (step S109). Note that when the ECC value Ne and the stored value Nf match, the comparison circuit 5 determines that there is no error, and when they do not match, the comparison circuit 5 determines that there is an error. When the comparison circuit 5 determines that there is no error (Yes in step S109), the comparison circuit 5 outputs the values of the correction error output Err1 and the uncorrectable error output Err2 as "0" (step S110).

[0047] When the comparison circuit 5 determines that there is an error (No in step S109), the comparison circuit 5 determines whether the error is a correctable error based on the comparison result (step S111). When the comparison circuit 5 determines that the error is a correctable error (Yes in step S111), the comparison circuit 5 outputs the correction error output Err1 with the value "1" and the uncorrectable error output Err2 with the value "0" to the processing device COM (step S112). When the comparison circuit 5 determines that the error is an uncorrectable error (No in step S111), the comparison circuit 5 outputs the correction error output Err1 with the value "1" and the uncorrectable error output Err2 with the value "1" to the processing device COM (step S113).

[0048] In step S110, when the correction error output Err1 and the uncorrectable error output Err2 with the value "0" are output, the output data Dout is output in step S103. In step S111, when the comparison circuit 5 outputs the correction error output Err1 with the value "1", the corrected data Dcor is output in step S105. Also, in step S113, when the comparison circuit 5 outputs the uncorrectable error output Err2 with the value "1", the processed data Dcrr is output in step S105.

[0049] Then, in step S112, after the comparison circuit 5 outputs a correction error output Err1 with a value of "1" and a non-correctable error output Err2 with a value of "0", the self-refresh circuit 6 outputs a self-refresh signal Rfs to the holding circuit 2 (step S114).

[0050] The holding circuit 2 refreshes the flip-flops 71 to 77 and the flip-flops 811, 812, 813 of the bit error correction circuit 8 so that the output Df1 to Df8 can become values that can generate the corrected data Dcor even if the ECC encoder 3 does not execute correction (step S115). That is, the self-refresh circuit 6 overwrites the holding circuit 2 with the corrected data Dcor.

[0051] After steps S110, S113, and S115 are executed, the process returns to step S101 to resume the generation of the ECC value Ne.

[0052] By having the ECC encoder 3, the semiconductor device 1 can output the corrected data Dcor obtained by correcting the error when correction is possible to the processing device COM. Also, by outputting the non-correctable error output Err2 indicating that a non-correctable error has occurred from the comparison circuit 5 to the processing device COM, the processing device COM can recognize that the received processed data Dcrr contains a non-correctable error.

[0053] As a result, in the processing device COM, the use of the processed data Dcrr containing a non-correctable error is suppressed. For example, it can be suppressed that the processing device COM malfunctions due to the processed data Dcrr containing a non-correctable error. Also, the processing device COM can take measures against non-correctable errors such as temporarily stopping, stopping, or resetting the system.

[0054] Also, in the semiconductor device 1, when error correction is performed by the ECC encoder 3, the self-refresh circuit 6 outputs a self-refresh signal Rfs so as to perform self-refresh of the holding circuit 2. That is, in the semiconductor device 1, after a correctable error occurs, self-refresh is promptly performed so that the output of the flip-flop becomes the correct output. As a result, it is difficult for errors to occur simultaneously in a plurality of flip-flops, and the occurrence of uncorrectable errors in the outputs Df1 to Df8 is suppressed.

[0055] Furthermore, even when an error occurs in two of the flip-flops 811, 812, and 813 of the bit error correction circuit 8 and an error occurs in the output Df8 of the bit error correction circuit 8, the error in the output Df8 can be corrected using the ECC encoder 3. Then, the flip-flops 811, 812, and 813 are refreshed so as to operate normally. Thereby, the reliability of the output Df8 can be ensured.

[0056] <Layout of the semiconductor substrate Bd> FIG. 5 is a plan view showing a logic layout L in the semiconductor substrate Bd. As shown in FIG. 5, a logic layout L in which elements are arranged is formed on the semiconductor substrate Bd. The logic layout L has a power supply strap wiring Vst and a ground strap wiring Gst. The ground strap wiring Gst surrounds the logic layout L and divides the logic layout into a plurality of sections in the first direction X by a plurality of wirings extending in the second direction Y.

[0057] Also, the power supply strap wiring Vst surrounds the logic layout L and divides the logic layout into a plurality of sections in the second direction Y by a plurality of wirings extending in the first direction X. The power supply strap wiring Vst is connected to a power supply terminal that supplies the power supply voltage Vcc. Also, the ground strap wiring Gst is connected to the ground voltage GND. The logic layout L is divided into a plurality, here 12 regions Ar1 to Ar12, surrounded by the power supply strap wiring Vst and the ground strap wiring Gst. Note that in the logic layout L shown in FIG. 5, it is divided into 4 parts in the first direction X and 3 parts in the second direction Y.

[0058] In the semiconductor device 1, elements are arranged in the regions Ar1 to Ar12. In the semiconductor device 1, the flip-flop 811 of the bit error correction circuit 8 is arranged in the region Ar8, the flip-flop 812 is arranged in the region Ar1, and the flip-flop 813 is arranged in the region Ar10.

[0059] In the logic layout L, when disturbance noise as described above acts on any of the regions Ar1 to Ar12, a soft error may occur in any of the flip-flops 811, 812, 813 due to the disturbance noise. In the logic layout L of the semiconductor device 1, each of the flip-flops 811, 812, 813 is arranged in different regions Ar8, Ar1, Ar10, and the respective regions are not arranged adjacent to each other.

[0060] Therefore, even if a soft error due to disturbance noise occurs in any of the flip-flops 811, 812, 813, the influence of the disturbance noise on the other flip-flops can be suppressed. Thereby, it is possible to suppress the occurrence of soft errors in two of the flip-flops 811, 812, 813.

[0061] In addition, in the logic layout L, a capacitor C1 is arranged in a region Ar7 where no elements are arranged. One end of the capacitor C1 is connected to the power supply strap wiring Vst and the other end is connected to the ground strap wiring Gst. The capacitor C1 is a so-called bypass capacitor and can reduce the influence of the above-described disturbance noise. As a result, the occurrence of soft errors due to the disturbance noise in the flip-flops 811, 812, and 813 is suppressed. As a result, it is possible to stably operate the system including the semiconductor device 1.

[0062] <Second Embodiment> The semiconductor device 1A of the second embodiment will be described with reference to the drawings. FIG. 6 is a configuration diagram of an example of the semiconductor device 1A according to the second embodiment. The semiconductor device 1A shown in FIG. 6 is different from the semiconductor device 1 shown in FIG. 1 in that the holding circuit 2A has two bit error correction circuits 8, but has substantially the same configuration as the semiconductor device 1 in other respects. Therefore, the same reference numerals are given to substantially the same parts as those of the semiconductor device 1 of the semiconductor device 1A, and detailed description thereof is omitted.

[0063] For example, there may be two outputs that require high reliability among the respective outputs Df1 to Df8 constituting the input data Din. In such a case, the bit error correction circuit 8 is provided in a portion where the bit data serving as the output that requires high reliability of the holding circuit 2A is input. That is, the holding circuit 2A has a configuration having two bit error correction circuits 8.

[0064] Then, the error detection circuit 83 outputs an error detection output Sgm to the multiplexed refresh circuit 84 of each bit error correction circuit 8. The holding circuit 2A has an OR circuit 85 to which the error detection output Sgm from each error detection circuit 83 is input. The OR circuit 85 outputs to the processing device COM. The value of the output of the OR circuit 85 is "0" or "1", and becomes "1" when an error has occurred in at least one of the flip-flops 811, 812, and 813 of the two bit error correction circuits 8.

[0065] With such a configuration, the processing device COM can recognize in the bit error correction circuit 8 that an error has occurred but has been corrected. For example, when the output of the error detection output Sgm from the bit error correction circuit 8 occurs frequently, it is also possible to determine that there is a defect in any of the flip - flops 811, 812, 813.

[0066] In the semiconductor device 1A, the outputs Df7 and Df8 of the bit error correction circuit 8 have higher reliability than the outputs Df1 to Df6 based on the bit data Bt1 to Bt6. Other features are the same as those of the first embodiment.

[0067] <Third Embodiment> The semiconductor device 1B of the third embodiment will be described with reference to the drawings. FIG. 7 is a configuration diagram of an example of the semiconductor device 1B according to the third embodiment. The semiconductor device 1B shown in FIG. 7 is different from the semiconductor device 1 shown in FIG. 1 in that it has a combination circuit 9, but in other respects, it has substantially the same configuration as the semiconductor device 1. Therefore, the same reference numerals are given to the substantially same parts as those of the semiconductor device 1B, and detailed descriptions are omitted.

[0068] In the semiconductor device 1B, the combination circuit 9 has a configuration in which interrupt data Dint can be input to the holding circuit 2. The interrupt data Dint is pre - determined data. As shown in FIG. 7, the interrupt data Dint has interrupt bit data Dt1 to Dt8 corresponding to the bit data Bt1 to Bt8 of the input data Din. The interrupt data Dint is, for example, information for controlling the entire or a part of the system including the semiconductor device 1B to a pre - determined state, such as stopping, pausing, or resetting the system.

[0069] In addition, the combination circuit 9 is configured to be able to output interrupt data Dint. The semiconductor device 1B is provided with a switch group S1 to S8, each of which is configured to switch to either bit data Bt1 to Bt8 or interrupt bit data Dt1 to Dt8. The switch group S1 to S8 is controlled by the uncorrectable error output Err2. During normal operation, it is connected so that the bit data Bt1 to Bt8 of the input data Din can be input.

[0070] The uncorrectable error output Err2 from the comparison circuit 5 is output to the processing device COM and is also output to the switch group S1 to S8. The combination circuit 9 outputs the interrupt data Dint to the holding circuit 2.

[0071] The switch group S1 to S8 switches to input either the input data Din or the interrupt data Dint to the semiconductor device 1B. The uncorrectable error output Err2 is input to the switch group S1 to S8. When the uncorrectable error output Err2 is "0", the switch group S1 to S8 switches to input the input data Din to the semiconductor device 1B. When the uncorrectable error output Err2 is "1", the switch group S1 to S8 switches to input the input data Din from the combination circuit 9 to the semiconductor device 1B.

[0072] Thereby, when the ECC value Ne contains an uncorrectable error, the input data Din is switched to the interrupt data Dint. The semiconductor device 1B and the system including the semiconductor device 1B are controlled to a predetermined state by the input of the interrupt data Dint.

[0073] By configuring the semiconductor device 1B in this way, when an error occurs in two or more of the outputs Df1 to Df8 and the error cannot be corrected, the state of the system including the semiconductor device 1B can be quickly transitioned to a predetermined state. Thereby, it is possible to suppress the behavior of the system including the semiconductor device 1B from being disturbed and quickly stabilize it.

[0074] In the present embodiment, the combinational circuit 9 is configured to output the interrupt data Dint when the uncorrectable error output Err2 is "1", but the present invention is not limited to this. For example, when the input data Din is input to the combinational circuit 9 and the uncorrectable error output Err2 becomes "1", it may operate to newly output the input data Din to the holding circuit 2.

[0075] For example, even when an error occurs in the output due to a temporary soft error of the flip - flops 71 to 77, 811, 812, 813 caused by external disturbance noise as described above, it is possible to quickly return to the operation based on the input data Din. Thereby, even when a temporary soft error occurs, malfunction of the system including the semiconductor device 1B can be suppressed.

[0076] Note that the switch groups S1 to S8 may all operate to switch simultaneously, or only some of the switches may be switched so that the interrupt bit data is input by a value that can stop or limit the operation of the semiconductor device 1B.

[0077] Also, as the switch for switching between the input data Din and the interrupt data Dint, a switching circuit using MOS transistors may be used. In this case, the switching circuit may be incorporated inside the combinational circuit 9. That is, the uncorrectable error output Err2 is input to the combinational circuit 9, and the combinational circuit 9 may be configured to also serve as a driver circuit that controls the switching circuit based on the uncorrectable error output Err2.

[0078] Also, although an example of switching between the input data Din and the interrupt data Dint using the switch groups S1 to S8 is given, the present invention is not limited to this. For example, the combinational circuit 9 may be a circuit that can selectively output one of the input data Din and the interrupt data Dint, and may be provided with software.

[0079] In this configuration, even if the operation of the combinational circuit 9 outputting the input data Din to the holding circuit 2 is repeated a predetermined number of times, when the occurrence of an uncorrectable error output Err2 becoming "1" is repeated, the combinational circuit 9 may be made to output interrupt data Dint prepared separately.

[0080] By configuring in this way, in the case of a temporary soft error, the system including the semiconductor device 1B can be stably operated without stopping the system. Also, in the case of a persistent soft error, the system including the semiconductor device 1B can be quickly transitioned to a determined state. Thereby, it is possible to suppress the behavior of the system including the semiconductor device 1B from being disrupted and quickly stabilize it.

[0081] <Usage> The above-described semiconductor device 1 can be used as the frequency trimming register 205 of the ultrasonic sonar sensor 200. FIG. 8 is a configuration diagram of an example of the ultrasonic sonar sensor 200. The ultrasonic sonar sensor 200 is a sensor that irradiates an object with an output wave and detects the distance to the object and the shape of the object based on the time until the reflected wave reflected by the object is detected.

[0082] As shown in FIG. 8, the ultrasonic sonar sensor 200 is connected to the host computer Host, operates based on an instruction from the host computer Host, and outputs measurement results to the host computer Host. That is, the ultrasonic sonar sensor 200 has a configuration capable of communicating with the host computer Host.

[0083] The ultrasonic sonar sensor 200 performs a transmission operation of an output wave signal and a reception operation of a reflected wave using a piezoelectric element Pz. The ultrasonic sonar sensor 200 includes a transmission unit 201, a reception unit 202, a logic unit 203, an oscillation circuit 204, and a frequency trimming register 205.

[0084] The transmitting unit 201 is configured to be able to send a pulse of a predetermined frequency to the piezoelectric element Pz so that the piezoelectric element Pz outputs an output wave in response to an instruction from the logic unit 203. Further, the receiving unit 202 receives an input wave in the ultrasonic range using the externally connected piezoelectric element Pz. Then, the receiving unit 202 converts the input wave into an input signal of an electrical signal and outputs it to the logic unit 203. The logic unit 203 operates the transmitting unit 201 and the receiving unit 202, and transmits reception data corresponding to the input signal sent from the receiving unit 202 to the host computer Host.

[0085] The logic unit 203, the transmitting unit 201, and the receiving unit 202 operate based on the clock signal Clk output from the oscillation circuit 204. If the frequency of the clock signal Clk deviates from a determined value, the operation of the ultrasonic sonar sensor 200 becomes unstable, and communication with the host computer Host may become impossible. Therefore, the oscillation circuit 204 is generated based on the output data output from the frequency trimming register 205. The semiconductor device 1 is used for the frequency trimming register 205. As described above, in the semiconductor device 1, errors are corrected for the output data using the bit error correction circuit 8 and the ECC encoder 3, so that the oscillation circuit 204 can output a clock signal Clk with a stable frequency. Thereby, communication between the ultrasonic sonar sensor 200 and the host computer Host can be stabilized.

[0086] Also, by using the semiconductor device 1B of the third embodiment described above as the frequency trimming register 205, the operation of the ultrasonic sonar sensor 200 can be stabilized, and when affected by external noise, it quickly transitions to a predetermined state, for example, interrupting measurement, stopping operation, pausing temporarily, resetting, etc. Therefore, the occurrence of malfunctions in the ultrasonic sonar sensor 200, the host computer Host, and the device to which the ultrasonic sonar sensor 200 is attached can be suppressed.

[0087] FIG. 9 is a schematic view of a vehicle Vc equipped with an ultrasonic sonar sensor 200. As shown in FIG. 9, the ultrasonic sonar sensor 200 can be suitably used as a sensor of a contact prevention device of the vehicle Vc. The vehicle Cr includes, in addition to an engine vehicle, an electric vehicle (xEV such as a battery electric vehicle (BEV), a hybrid electric vehicle (HEV), a plug-in hybrid electric vehicle / plug-in hybrid vehicle (PHEV / PHV), or a fuel cell electric vehicle / fuel cell vehicle (FCEV / FCV)).

[0088] When the ultrasonic sonar sensor 200 is attached to the vehicle Vc and used as part of a vehicle collision prevention device, the driver is quickly notified of a malfunction of the ultrasonic sonar sensor 200, and the ultrasonic sonar sensor 200 is reset. Thereby, the driver recognizes that the collision prevention device is not operating and concentrates on driving, and for example, by adopting a configuration in which the ultrasonic sonar sensor 200 is reset, it is possible to quickly bring the collision prevention device back into a reusable state.

[0089] <Others> The above-described embodiments should be considered to be illustrative in all respects and not restrictive, and the technical scope of the present invention is indicated by the claims rather than the description of the above embodiments, and it should be understood that all modifications belonging to the meaning and scope equivalent to the claims are included.

[0090] <Supplementary Note> Hereinafter, the various embodiments described above will be summarized.

[0091] The semiconductor devices (1, 1A, 1B) described above have at least one flip-flop (71 to 77, 811, 812, 813) for each bit data (Bt1 to Bt8) of the input data and can hold the bit data (Bt1 to Bt8). A holding circuit (2) having a configuration, An ECC encoder (3) configured to output an ECC value (Ne) decoded according to bit data (Bt1 to Bt8) held by a holding circuit (4), output data (Dout) according to the plurality of bit data (Bt1 to Bt8), or corrected data (Dcor) obtained by correcting the output data (Dout) when an error exists in the output data (Dout) and correction is possible. An ECC storage unit (4) configured to store the ECC value (Ne) as a stored value (Nf). A comparison circuit (5) configured to compare the ECC value (Ne) output from the ECC encoder (3) with the stored value (Nf) stored in the ECC storage unit (4) and determine whether the ECC encoder (3) can perform correction. A self-refresh circuit (6) configured to execute self-refresh to overwrite the holding circuit (2) with the corrected data (Dcor) when the comparison circuit (5) determines that there is an error in the output data (Dout) and the error can be corrected by the ECC encoder (3). The configuration (first configuration) has this.

[0092] In the semiconductor device (1, 1A, 1B) having the first configuration, the holding circuit (2, 2A) includes a multiplexing circuit (81) having a plurality of flip-flops (811, 812, 813) connected in parallel to which one bit data (Bt8) is respectively input. A majority decision circuit (82) configured to output the result of majority decision on the output of the multiplexing circuit (81). An error detection circuit (83) configured to output that an error in the output of the multiplexing circuit (81) has been detected. A multiplexing refresh circuit (84) configured to execute refresh to overwrite the multiplexing circuit (81) with the output (Dt8) of the majority decision circuit (82) when the error detection circuit (83) detects an error. The bit error correction circuit (8) having this configuration. The bit error correction circuit (8) has a configuration (second configuration) in which at least one bit data (Bt8) is input.

[0093] In the semiconductor device (1, 1A, 1B) having the second configuration, the bit error correction circuit (8) has a configuration (third configuration) in which bit data (Bt8) that requires higher reliability than other bit data (Bt1 to Bt7) among a plurality of bit data (Bt1 to Bt8) is input.

[0094] In the semiconductor device (1A) having the second or third configuration, the holding circuit (2A) has a plurality of bit error correction circuits (8). When an error detection circuit (84) of at least one bit error correction circuit (8) detects an error, it has a configuration (fourth configuration) that outputs that an error has been detected.

[0095] In the semiconductor device (1, 1A, 1B) having any one of the second to fourth configurations, a logic layout (L) formed on a substrate (Bd), a power supply strap wiring (Vst) configured to divide the logic layout (L) into a plurality of sections in a first direction (X) and to which a power supply voltage (Vcc) is connected, a ground strap wiring (Gst) configured to divide the logic layout (L) into a plurality of sections in a second direction (Y) intersecting the first direction (X) and to which a ground voltage is connected, and has Flip-flops (811, 812, 813) of the bit error correction circuit (8) are arranged in regions (Ar1 to Ar12) surrounded by the power supply strap wiring (Vst) and the ground strap wiring (Gst) and in regions (Ar8, Ar1, Ar10) that are not adjacent to each other (fifth configuration).

[0096] In the semiconductor device (1, 1A, 1B) having the fifth configuration, a capacitor (C1) having a configuration arranged in a region (Ar7) where no electronic component is arranged among the plurality of regions (Ar1 to Ar12) and connected to the power supply strap wiring (Vst) and the ground strap wiring (Gst) is provided (sixth configuration).

[0097] In the semiconductor device (1B) having any one of the first to seventh configurations, a combination circuit (9) configured to output predetermined interrupt data (Dint) is further provided. The combination circuit (9) has a configuration (seventh configuration) that operates according to the ECC error output (Err1) of the comparison circuit (5).

[0098] A frequency trimming register (205) having a configuration using the semiconductor device (1, 1A, 1B) having any one of the first to seventh configurations is configured (eighth configuration).

[0099] The frequency trimming register (205) having the eighth configuration, An oscillation circuit (204) that outputs a clock signal (Clk) according to the output from the frequency trimming register (205), A transmission unit (201) and a reception unit (202) that operate according to the clock signal (Clk), A piezoelectric element (Pz) that is connected to the transmission unit (201) and the reception unit (202) and detects a transmitted output wave and a reflected wave that is the output wave reflected by an object, A logic unit (203) that controls the transmission unit (201) and the reception unit (202) according to the clock signal (Clk) and outputs received data to an external device, are configured to form an ultrasonic sonar sensor (200) having a configuration (ninth configuration).

[0100] A vehicle (Vc) having a configuration using the ultrasonic sonar sensor (200) having the ninth configuration is configured (tenth configuration).

Explanation of Signs

[0101] 1, 1A, 1B Semiconductor device 11 Input terminal 12 Output terminal 2, 2A Holding circuit 3 ECC encoder 4 ECC storage unit 5 Comparison circuit 6 Self-refresh circuit 71 - 77 Flip-flop 8-bit error correction circuit 81 multiplexing circuit 811~813 flip-flops 82 majority decision circuit 821~823 AND circuits 824 OR circuit 83 error detection circuit 84 multiplexing refresh circuit 85 OR circuit 9 combinational circuit 200 ultrasonic sonar sensor 201 transmitter 202 receiver 203 logic unit 204 oscillation circuit 205 frequency trimming register Bd semiconductor substrate Bt1~Bt8 bit data C1 capacitor COM processing device Clk clock signal Vc vehicle

Claims

1. A holding circuit having at least one flip-flop for each bit data of input data and capable of holding the bit data, An ECC encoder configured to output an ECC value decoded according to the bit data held by the holding circuit, and output data according to the plurality of bit data or corrected data obtained by correcting the output data when an error exists in the output data and correction is possible, An ECC storage unit configured to store the ECC value as a stored value, A comparison circuit configured to compare the ECC value output from the ECC encoder with the stored value stored in the ECC storage unit and determine whether the error can be corrected by the ECC encoder, A semiconductor device having a self-refresh circuit configured to execute self-refresh to overwrite the holding circuit with the corrected data when the comparison circuit determines that there is an error in the output data and the error can be corrected by the ECC encoder.

2. The holding circuit includes A multiplexing circuit having a plurality of flip-flops connected in parallel to which each of the one bit data is input, A majority decision circuit configured to output the result of majority decision of the output of the multiplexing circuit, An error detection circuit configured to output that an error in the output of the multiplexing circuit has been detected, A bit error correction circuit having a multiplexing refresh circuit configured to execute refresh to overwrite the multiplexing circuit with the output of the majority decision circuit when the error detection circuit detects an error, The bit error correction circuit is configured such that at least one of the bit data is input. The semiconductor device according to claim 1.

3. The bit error correction circuit is configured such that bit data requiring higher reliability than other bit data among the plurality of bit data is input. The semiconductor device according to claim 2.

4. The holding circuit has a plurality of the bit error correction circuits, The semiconductor device according to claim 2, configured to output that an error has been detected when the error detection circuit of at least one of the bit error correction circuits detects an error.

5. Further having a combination circuit configured to output predetermined interrupt data, The semiconductor device according to claim 1, wherein the combination circuit is configured to operate in accordance with a correction error output output from the comparison circuit.

6. A logic layout formed on a substrate, A power supply strap wiring configured to divide the logic layout into a plurality of sections in a first direction and to which a power supply voltage is connected, A ground strap wiring configured to divide the logic layout into a plurality of sections in a second direction intersecting the first direction and to which a ground voltage is connected, and The semiconductor device according to claim 2, wherein the flip-flops of the bit error correction circuit are arranged in regions surrounded by the power supply strap wiring and the ground strap wiring and not adjacent to each other.

7. The semiconductor device according to claim 6, further comprising a capacitor configured to be arranged in a region where no electronic component is arranged among the plurality of regions and to be connected to the power supply strap wiring and the ground strap wiring.

8. A frequency trimming register having a configuration including the semiconductor device according to any one of claims 1 to 7.

9. The frequency trimming register according to claim 8, An oscillation circuit that outputs a clock signal in accordance with an output from the frequency trimming register, A transmission unit and a reception unit that operate in accordance with the clock signal, A piezoelectric element connected to the transmission unit and the reception unit and configured to detect a transmitted output wave and a reflected wave that is the output wave reflected by an object, and An ultrasonic sonar sensor configured to control the transmission unit and the reception unit in accordance with the clock signal and to output received data to an external device.

10. A vehicle configured to include the ultrasonic sonar sensor according to claim 9.

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