Three-level power conversion device, railway vehicle, control method for three-level power conversion device and production method for three-level power conversion device

Abstract

To provide a three-level power conversion device, etc., capable of operating even without newly creating a control signal with respect to a MOSFET for clamp.SOLUTION: A three-level power conversion device comprises positive-side, neutral-point and negative-side power supply lines 101-103 and MOSFETs 111-116. The MOSFETs 111-114 are connected in series of four. A high potential terminal of the MOSFET 115 is connected to a connection point of the MOSFETs 112 and 113, and a low potential side terminal is connected to the neutral-point power supply line 102. A high-potential side terminal of the MOSFET 116 is connected to the neutral-point power supply line 102, and a low potential side terminal is connected to a connection point of the MOSFETs 113 and 114. An AC terminal 104 is connected to the connection point of the MOSFET 112 and 113. The same control signal as a control terminal of the MOSFET 116 is given to a control terminal of the MOSFET 112. The same control signal as a control terminal of the MOSFET 115 is given to a control terminal of the MOSFET 113.SELECTED DRAWING: Figure 1A

Description

Technical Field

[0001] The present invention relates to a three-level power conversion device, a railway vehicle, a control method for a three-level power conversion device, and a production method for a three-level power conversion device. In particular, the present invention relates to a three-level power conversion device using a semiconductor element capable of conducting current bidirectionally.

Background Art

[0002] As a circuit for converting between direct current and alternating current, there are a two-level circuit in which the potential levels of the direct current side circuit consist of two levels, positive and negative, a three-level circuit consisting of three potential levels, a multi-level circuit composed of five or more potentials, and the like. The two-level circuit has a simple configuration and can form a system in a small size and at low cost. Therefore, it is widely used in various fields, including automobiles, household appliances, and industrial equipment. On the other hand, the three-level circuit has features such as reducing noise by reducing distortion of the AC output waveform, and being able to use semiconductor switching elements with a low rated voltage. Since semiconductor switching elements with a lower rated voltage have less loss and lower cost, it is beneficial for miniaturization and cost reduction of power conversion devices. A three-level power conversion device that converts between direct current and alternating current using a three-level circuit is widely used in high-voltage systems exceeding several thousand volts, such as power transmission applications and railway vehicle drive applications, due to the above two features.

[0003] Fig. 7 shows a conventional three-level circuit using clamp diodes. In Fig. 7, 101 is the positive power line, 102 is the neutral point power line, 103 is the negative power line, 104 is the AC terminal, 111 to 114 are MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), 117 to 120 are diodes, 131 to 134 are gate drivers, 141 is the upper controller, 142 is the positive power capacitor, 143 is the negative power capacitor, and 501 and 502 are clamp diodes.

[0004] In the three-level circuit shown in Fig. 7, when the two switching elements MOSFET111 and MOSFET112 on the positive side from the AC terminal 104 are turned on, the potential of the positive power line 101 is output to the AC terminal 104. Similarly, when the MOSFETs 113 and 114 on the negative side are turned on, the potential of the negative power line 103 is output to the AC terminal 104. Also, when the two central MOSFETs 112 and 113 directly connected to the AC terminal 104 are turned on, the potential of the neutral power line 102 is output to the AC terminal 104. At this time, a clamp diode 501 and a clamp diode 502 are connected between the neutral point and the MOSFETs 112 and 113, and the path through which the current flows automatically switches according to the direction of the current. For example, when current flows from the neutral power line 102 to the AC terminal 104, the current flows through the clamp diode 501 and the MOSFET 112. Conversely, when current flows from the AC terminal 104 to the neutral power line 102, the current flows through the MOSFET 113 to the clamp diode 502. In recent years, in response to the global trend of decarbonization, the reduction of losses and improvement of efficiency in power conversion circuits have been promoted. Even in the aforementioned three-level circuit, various technologies for reducing the losses of switching elements and diodes have been proposed.

[0005] Patent Document 1 discloses a method for reducing the losses of clamp diodes used in a three-level circuit. The three-level circuit of Patent Document 1 includes first, second, third, and fourth switching elements connected in series, first, second, third, and fourth diodes each connected in anti-parallel to these switching elements, a fifth diode, a sixth diode, and a neutral-point clamped power converter that derives an output terminal from the connection point of the second and third switching elements, and includes a fifth switching element connected in parallel with the fifth diode and a sixth switching element connected in parallel with the sixth diode.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] By providing a MOSFET in parallel with a clamp diode and flowing current through the MOSFET in addition to the diode, the conduction loss during current conduction is reduced. Also, for example, in FIG. 7, when outputting the potential of the neutral point power line 102, conventionally, there was only one current path, such as from the clamp diode 501 to the MOSFET 112 or from the MOSFET 113 to the clamp diode 502. However, by adding a MOSFET in parallel with the clamp diode, it becomes possible to flow current bidirectionally through the above two paths simultaneously. There is also an advantage that the conduction loss can be reduced by reducing the current flowing through each switching element due to the current dispersion. However, in the prior art, there was a problem that a gate control signal for a MOSFET provided at the position of the clamp diode (hereinafter referred to as a clamp MOSFET) had to be newly generated. An object of the present invention is to provide a three-level power conversion device or the like that can operate without newly creating a control signal for a clamp MOSFET even when a clamp MOSFET is provided.

Means for Solving the Problems

[0008] To solve the above problems, the present invention is a three-level power conversion device that mutually converts direct current and alternating current using three potential levels, comprising: first to third power supply lines respectively having first to third potentials; first to sixth semiconductor elements having a high potential terminal, a low potential terminal, and a control terminal, and capable of bidirectional conduction between the high potential terminal and the low potential terminal; wherein the first to fourth semiconductor elements are connected in series, the high potential terminal of the first semiconductor element is connected to the first power supply line, the low potential terminal of the first semiconductor element is connected to the high potential terminal of the second semiconductor element, the low potential terminal of the second semiconductor element is connected to the high potential terminal of the third semiconductor element, the low potential terminal of the third semiconductor element is connected to the high potential terminal of the fourth semiconductor element, the low potential terminal of the fourth semiconductor element is connected to the third power supply line, the high potential side terminal of the fifth semiconductor element is connected to the connection point between the second semiconductor element and the third semiconductor element, the low potential side terminal of the fifth semiconductor element is connected to the second power supply line, the high potential side terminal of the sixth semiconductor element is connected to the second power supply line, the low potential side terminal of the sixth semiconductor element is connected to the connection point between the third semiconductor element and the fourth semiconductor element, the alternating current terminal is connected to the connection point between the second semiconductor element and the third semiconductor element, the same control signal as that of the control terminal of the sixth semiconductor element is applied to the control terminal of the second semiconductor element, and the same control signal as that of the control terminal of the fifth semiconductor element is applied to the control terminal of the third semiconductor element. In this case, even when a clamp MOSFET is provided, a three-level power conversion device that can operate without newly creating a control signal for the clamp MOSFET can be provided.

[0009] Here, for example, the three-level power conversion device further comprises first to sixth drive circuits respectively connected to the control terminals of the first to sixth semiconductor elements to apply control signals, and the control signals are generated by an upper controller connected to the first to sixth drive circuits, and the control signal applied to the second drive circuit is branched and applied to the sixth drive circuit, and the control signal applied to the third drive circuit is branched and applied to the fifth drive circuit. In this case, the same control signal can be obtained more easily. Further, for example, the power conversion device further includes first to sixth drive circuits respectively connected to the control terminals of the first to sixth semiconductor elements to provide control signals. The control signals are generated by a host controller connected to the first to sixth drive circuits. The control signal provided to the second drive circuit and the control signal provided to the sixth drive circuit are respectively generated by the host controller with the same control signal. The control signal provided to the third drive circuit and the control signal provided to the fifth drive circuit are respectively generated by the host controller with the same control signal. In this case, only four types of gate control signals need to be generated by the host controller. Furthermore, for example, the power conversion device further includes first to sixth diodes respectively connected to the first to sixth semiconductor elements, with the cathode terminal connected to the high potential terminal and the anode terminal connected to the low potential terminal. In this case, destruction of the semiconductor elements due to short - circuit of the arm can be prevented. Still further, for example, the power conversion device further includes first to fourth drive circuits respectively connected to the control terminals of the first to fourth semiconductor elements to provide control signals. The control signal branched from the output of the third drive circuit and transmitted through the first insulation circuit is input to the control terminal of the fifth semiconductor element, and the control signal branched from the output of the second drive circuit and transmitted through the second insulation circuit is input to the control terminal of the sixth semiconductor element. In this case, miniaturization and cost reduction of the three - level power conversion device can be achieved. And, for example, the propagation delays of the first insulation circuit and the second insulation circuit are within 1 μs. In this case, normal operation of the three - level power conversion device can be ensured. Also, for example, the first to sixth semiconductor elements are packaged in pairs of two in one package each. In this case, enlargement of the three - level power conversion device can be prevented. Furthermore, for example, the series circuit of the first semiconductor element and the fifth semiconductor element, the series circuit of the second semiconductor element and the third semiconductor element, and the series circuit of the fourth semiconductor element and the sixth semiconductor element are each packaged in one package. In this case, it is suitable as a combination for packaging in one package each. Furthermore, for example, the difference in the operations between the second drive circuit and the sixth drive circuit and the difference in the operations between the third drive circuit and the fifth drive circuit are each within 1 μs. In this case, the normal operation of the three-level power conversion device can be ensured.

[0010] Moreover, the present invention is a railway vehicle equipped with the above three-level power conversion device. In this case, it is possible to provide a railway vehicle using a DC-AC conversion device that has achieved miniaturization and cost reduction.

[0011] Furthermore, the present invention is a control method for a three-level power conversion device that converts direct current and alternating current using three potential levels, comprising: first to third power supply lines each having a first to third potential; first to sixth semiconductor elements each having a high potential terminal, a low potential terminal, and a control terminal, and capable of bidirectional conduction between the high potential terminal and the low potential terminal. The first to fourth semiconductor elements are connected in series. The high potential terminal of the first semiconductor element is connected to the first power supply line, the low potential terminal of the first semiconductor element is connected to the high potential terminal of the second semiconductor element, the low potential terminal of the second semiconductor element is connected to the high potential terminal of the third semiconductor element, the low potential terminal of the third semiconductor element is connected to the high potential terminal of the fourth semiconductor element, and the low potential terminal of the fourth semiconductor element is connected to the third power supply line. The high potential side terminal of the fifth semiconductor element is connected to the connection point between the second semiconductor element and the third semiconductor element, the low potential side terminal of the fifth semiconductor element is connected to the second power supply line, the high potential side terminal of the sixth semiconductor element is connected to the second power supply line, the low potential side terminal of the sixth semiconductor element is connected to the connection point between the third semiconductor element and the fourth semiconductor element, the alternating current terminal is connected to the connection point between the second semiconductor element and the third semiconductor element, the same control signal as that of the control terminal of the sixth semiconductor element is applied to the control terminal of the second semiconductor element, and the same control signal as that of the control terminal of the fifth semiconductor element is applied to the control terminal of the third semiconductor element. By turning on the first semiconductor element and the second semiconductor element and turning off the third semiconductor element and the fourth semiconductor element, a first mode in which current flows between the first power supply line and the alternating current terminal is achieved. By turning on the second semiconductor element and the third semiconductor element and turning off the first semiconductor element and the fourth semiconductor element, a second mode in which current flows between the second power supply line and the alternating current terminal is achieved. By turning on the third semiconductor element and the fourth semiconductor element and turning off the first semiconductor element and the second semiconductor element, a third mode in which current flows between the third power supply line and the alternating current terminal is achieved. Thus, it is a control method for a three-level power conversion device that controls by including these modes. In this case, even when a clamp MOSFET is provided, it is possible to provide a control method for a three-level power conversion device that can operate without newly creating a control signal for the clamp MOSFET.

[0012] Here, for example, between the first mode and the second mode, it includes a fifth mode in which the first semiconductor element is turned off from the first mode, and between the second mode and the third mode, it further includes a sixth mode in which the second semiconductor element is turned off from the second mode. In this case, destruction of the semiconductor element due to a short circuit of the arm can be prevented. Also, for example, the periods of the fifth mode and the sixth mode are within 10 μs. In this case, conduction loss and deterioration of the semiconductor element can be suppressed. Furthermore, for example, when stopping the three-level power conversion device in the first mode, the second semiconductor element is turned off after the first semiconductor element is turned off, and when stopping the three-level power conversion device in the third mode, the third semiconductor element is turned off after the fourth semiconductor element is turned off. In this case, destruction of the semiconductor element when stopping the three-level power conversion device can be prevented. And, for example, the time difference when turning off the second semiconductor element after turning off the first semiconductor element, and the time difference when turning off the third semiconductor element after turning off the fourth semiconductor element are 1 μs or more. In this case, the time required to prevent destruction of the semiconductor element when stopping the three-level power conversion device can be ensured. Also, for example, when stopping the three-level power conversion device in the second mode, both the second semiconductor element and the third semiconductor element are turned off. In this case, the control when stopping the three-level power conversion device becomes easier.

[0013] The present invention is a method for manufacturing a three-level power conversion device that mutually converts direct current and alternating current using three potential levels, comprising: first to third power supply lines respectively having first to third potentials; first to fourth semiconductor elements each having a high potential terminal, a low potential terminal, and a control terminal and enabling bidirectional current conduction between the high potential terminal and the low potential terminal; and first and second diodes. The first to fourth semiconductor elements are connected in series, with the high potential terminal of the first semiconductor element connected to the first power supply line, the low potential terminal of the first semiconductor element connected to the high potential terminal of the second semiconductor element, the low potential terminal of the second semiconductor element connected to the high potential terminal of the third semiconductor element, the low potential terminal of the third semiconductor element connected to the high potential terminal of the fourth semiconductor element, and the low potential terminal of the fourth semiconductor element connected to the third power supply line. The cathode terminal of the first diode is connected to the connection point between the second and third semiconductor elements, the anode terminal of the first diode is connected to the second power supply line, the cathode terminal of the second diode is connected to the second power supply line, and the anode terminal of the second diode is connected to the connection point between the third and fourth semiconductor elements. The alternating current terminal is connected to the connection point between the second and third semiconductor elements. For the three-level power conversion device, fifth and sixth semiconductor elements each having a high potential terminal, a low potential terminal, and a control terminal and enabling bidirectional current conduction between the high potential terminal and the low potential terminal are added. The high potential side terminal of the fifth semiconductor element is connected to the cathode terminal of the first diode and also to the connection point between the second and third semiconductor elements, the low potential side terminal of the fifth semiconductor element is connected to the second power supply line, the high potential side terminal of the sixth semiconductor element is connected to the second power supply line, and the low potential side terminal of the sixth semiconductor element is connected to the anode terminal of the second diode and also to the connection point between the third and fourth semiconductor elements. The control terminal of the second semiconductor element is supplied with the same control signal as the control terminal of the sixth semiconductor element, and the control terminal of the third semiconductor element is supplied with the same control signal as the control terminal of the fifth semiconductor element. In this case, an existing three-level power conversion device can be updated to the three-level power conversion device of the present embodiment with low loss and high efficiency. [Effect of the Invention]

[0014] According to the present invention, even when a clamp MOSFET is provided, a three-level power conversion device or the like that can operate without newly creating a control signal for the clamp MOSFET can be provided. [Brief Description of the Drawings]

[0015]

Figure 1A

Figure 1B

Figure 1C

Figure 1D

Figure 1E

Figure 1F

Figure 1G

Figure 1H

Figure 1I

Figure 2

Figure 3

Figure 4A

Figure 4B

Figure 5

Figure 6

Figure 7

Embodiments for Carrying Out the Invention

Examples

[0016] Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1A is a circuit diagram of a three-level circuit according to Example 1 of the present embodiment. In FIG. 1A, the same components as those in FIG. 7 are denoted by the same reference numerals. The differences between FIG. 1A and FIG. 7 are that MOSFETs 115 and 116 are added as clamping MOSFETs, and gate drivers 135 and 136 are added for driving the clamping MOSFETs. The feature of this example is that the gate control signal of MOSFET 115, which is a clamping MOSFET, is shared with MOSFET 113, and the gate control signal of MOSFET 116 is shared with the gate control signal of MOSFET 112. With this configuration, it becomes possible to control the gates of MOSFETs 115 and 116 without outputting a new gate control signal from the upper controller 141.

[0017] The three-level circuit shown in FIG. 1A is a three-level circuit that mutually converts direct current and alternating current using three potential levels, and can be said to have the following configuration. First to third power supply lines having first to third potentials (in this case, positive-side power supply line 101, neutral-point power supply line 102, and negative-side power supply line 103), and first to sixth semiconductor elements having a high-potential terminal, a low-potential terminal, and a control terminal, and capable of bidirectional conduction between the high-potential terminal and the low-potential terminal (in this case, MOSFETs 111 to 116). Then, the first to fourth semiconductor elements are connected in series. The high-potential terminal of the first semiconductor element (in this case, MOSFET 111) is connected to the first power line (in this case, the positive-side power line 101). The low-potential terminal of the first semiconductor element is connected to the high-potential terminal of the second semiconductor element (in this case, MOSFET 112). The low-potential terminal of the second semiconductor element is connected to the high-potential terminal of the third semiconductor element (in this case, MOSFET 113). The low-potential terminal of the third semiconductor element is connected to the high-potential terminal of the fourth semiconductor element (in this case, MOSFET 114). The low-potential terminal of the fourth semiconductor element is connected to the third power line (in this case, the negative-side power line 103). Also, the high-potential-side terminal of the fifth semiconductor element (in this case, MOSFET 115) is connected to the connection point between the second and third semiconductor elements. The low-potential-side terminal of the fifth semiconductor element is connected to the second power line (in this case, the neutral-point power line 102). The high-potential-side terminal of the sixth semiconductor element (in this case, MOSFET 116) is connected to the second power line. The low-potential-side terminal of the sixth semiconductor element is connected to the connection point between the third and fourth semiconductor elements. Furthermore, the AC terminal 104 is connected to the connection point between the second and third semiconductor elements. The same control signal as that of the control terminal of the sixth semiconductor element is applied to the control terminal of the second semiconductor element, and the same control signal as that of the control terminal of the fifth semiconductor element is applied to the control terminal of the third semiconductor element. Note that the three-level circuit shown in FIG. 1A further includes first to sixth diodes (in this case, diodes 117 to 122) that are connected to the first to sixth semiconductor elements respectively, with the cathode terminal connected to the high-potential terminal and the anode terminal connected to the low-potential terminal. In addition, it further includes first to sixth drive circuits (in this case, gate drivers 131 to 136) that are connected to the control terminals of the first to sixth semiconductor elements respectively and apply control signals.

[0018] Hereinafter, the circuit operation of the first embodiment of the present invention will be described with reference to FIGS. 1B to 1I. FIG. 1H is a diagram showing a combination of drive control signals for controlling the three-level circuit of this embodiment. In FIG. 1H, gates 1 to 6 represent gate control signals of MOSFETs 111 to 116. When the output current is positive (modes 1 to 5), it represents a state where current flows from the AC terminal to the external circuit, and when the output current is negative (modes 6 to 10), it indicates the opposite. When the output voltage is positive, it shows a state where the potential of the plus-side power line is output to the AC terminal, and when the output voltage is negative, it shows a state where the potential of the minus-side power line is output. Also, when the output voltage is 0, it shows a state where the potential of the neutral point power line 102 is output. However, in the actual circuit, due to voltage drops caused by MOSFETs, diodes, wiring resistances, etc. on the current path, it does not strictly become 0, but here it is defined as approximately 0.

[0019] Next, the operation of Example 1 will be described in order from mode 1. Mode 1 is an operation mode where the output current is positive and MOSFETs 111 and 112 are on. FIG. 1B shows this state, and the current flows from the plus-side power line 101 through MOSFETs 111 and 112 to the AC terminal 104. The potential of the AC terminal 104 becomes approximately equal to the potential of the plus-side power line 101. In mode 1, an on gate control signal shared with MOSFET 112 is also input to MOSFET 116. Therefore, in addition to MOSFETs 111 and 112, MOSFET 116 is also on. However, since the potential of the AC terminal 104 is a positive potential and higher than the neutral point potential, the diode 119 is in the reverse bias state, and even if MOSFET 116 is on, no current flows through the diode 116 to the AC terminal 104.

[0020] When MOSFET 111 is turned off from this state, it shifts to mode 2. FIG. 1C shows the current paths of modes 2 and 3. In Mode 2, MOSFET112 and MOSFET116 are on, and the current path is divided into two. The first is the path from the neutral point power line 102, through the diode 121 and MOSFET112, to the AC terminal 104. In the conventional diode clamp type three-level circuit shown in FIG. 7, current only flows through this path. On the other hand, in this embodiment, current also flows through the other path. The other path is from the neutral point power line 102, through MOSFET116, and via the diode 119 to the AC terminal 104. In this embodiment, since the gate control signals of MOSFET112 and MOSFET116 are shared, when MOSFET111 is turned off in Mode 1, current naturally commutes to the two paths in Mode 2. Compared with the conventional diode clamp type three-level circuit, the current path increases, and the conduction resistance can be reduced.

[0021] Next, in Mode 3, the gate control signal of MOSFET113 is turned on, and at the same time, MOSFET115, which shares the gate signal, is also turned on. Then, the current that has been flowing through the diode 119 and the diode 121 also flows through MOSFET113 and MOSFET115. As a result, the current is dispersed, the conduction resistance is further reduced, and the loss can be decreased.

[0022] Note that Mode 2 is a mode that occurs temporarily when the state transitions from Mode 1 to Mode 3. It is a period provided to prevent the arm short-circuit phenomenon caused by MOSFET111 - 113 being turned on simultaneously. Generally, it is called by names such as dead time. When an arm short-circuit occurs, the positive and negative terminals of the plus-side power capacitor 142 are short-circuited by MOSFET111 - 113 and the diode 122, which is a so-called power short-circuit, and an excessive current flows, destroying the MOSFET. To prevent this, MOSFET113 must be turned on only after MOSFET111 is turned off, but it is necessary to take a certain margin due to fluctuations in the timing of the control signal. In the case of a high-voltage three-level circuit with a power supply voltage exceeding 600V, at least 3μs, preferably 5 - 10μs or more, should be ensured.

[0023] Figure 1D shows the current paths for Modes 4 and 5. When shifting from Mode 3 to Mode 4, MOSFET 112 turns off. When MOSFET 112 turns off, the current flowing from MOSFET 115 through MOSFET 112 stops. Also, MOSFET 116, which shares the gate signal with MOSFET 112, turns off, and the current flowing through MOSFET 116 also stops. The output current to the AC terminal 104 diverts to the path through the negative-side power line 103, diode 120, MOSFET 113, and diode 119. At this time, although MOSFET 115, which shares the gate control signal with MOSFET 113, is on, no current flows through this path because MOSFET 112 is off.

[0024] Note that the difference in the turn-off timing between MOSFET 112 and MOSFET 116 is preferably within 1 μs. This is because if either turns off late, the current in the path that turned off first will divert to the path that turned off late, and the path that turns off late will have to block twice the current, increasing the stress on the element. Stress refers to degradation due to heat generation during turn-off and degradation of the MOSFET due to surge voltage generated when blocking a large current. If the turn-off timing deviates significantly, the degradation of the MOSFET will accelerate and the system life will be shortened. In the case of elements such as MOSFETs used in high-voltage three-level circuits where the power supply voltage exceeds 600V, the turn-off time is at most about 3 μs. Considering this, it is preferable to limit the turn-off time difference to within 1 μs. This also applies to the case of MOSFET 113 and MOSFET 115. That is, the difference in the turn-off timing between MOSFET 113 and MOSFET 115 is preferably within 1 μs. This can also be said to mean that the difference in the operations between the second drive circuit (in this case, gate driver 132) and the sixth drive circuit (in this case, gate driver 136) and the difference in the operations between the third drive circuit (in this case, gate driver 133) and the fifth drive circuit (in this case, gate driver 135) are each within 1 μs. Note that Mode 4 is also the dead time when transitioning from Mode 3 to Mode 5, and is set to the minimum time that does not cause an arm short circuit, similar to Mode 2.

[0025] Subsequently, in Mode 5, MOSFET 114 turns on and part of the current flowing through diode 120 is shunted to MOSFET 114. After continuing this Mode 5 for a certain period of time to obtain a predetermined output, it transitions back to Mode 4, and thereafter operates while reciprocating between Modes 1 to 5 as in Mode 3 → Mode 2 → Mode 1. During that time, there are also operations that reciprocate between Modes 1 to 3 and operations that reciprocate between Modes 3 to 5, but even in those cases, the basic current path is as described above.

[0026] Next, the operations in Modes 6 to 10 where the current becomes negative will be described. Fig. 1E is a circuit diagram showing the current paths in Modes 6 and 7. In Mode 6, MOSFETs 111 and 112 are on, and the current is shunted to MOSFET 111 and diode 117, and MOSFET 112 and diode 118, and the current flows toward the positive power supply line. In Mode 7, MOSFET 111 turns off, but current continues to flow through diode 117, and the current path remains the same as in Mode 6. Note that this Mode 7 is a dead time period, similar to Mode 2 and Mode 4.

[0027] Fig. 1F shows the current paths in Modes 8 and 9. When MOSFET 113 turns on and transitions from Mode 7 to Mode 8, MOSFET 115, which shares the gate control signal with MOSFET 113, also turns on. Then, a path for current to flow through these to the neutral point power supply line 102 is formed, so the current flows dispersed in two paths as shown in Fig. 1F.

[0028] In Mode 9, MOSFETs 112 and 116 turn off, but since current continues to flow through the parallel diodes 118 and 122, there is no change in the current path. Note that Mode 9 is also the dead time when the mode transitions from Mode 8 to Mode 10.

[0029] Fig. 1G shows the current path of Mode 10. In Mode 10, MOSFET 114 is turned on, and since the potential of the AC terminal 104 drops to the potential of the negative power supply line 103, diodes 118 and 122 are in the reverse bias state and the current in this path stops, and all the current transfers to MOSFETs 113 and 114.

[0030] In the case of Modes 6 to 10 as well, there are operation patterns such as reciprocating between Modes 6 to 10 in the same way as Modes 1 to 5, and patterns of reciprocating between Modes 6 to 8 and Modes 8 to 10.

[0031] Fig. 1I is a sequence diagram showing how pulses are actually input in the operation mode of Fig. 1H. The gate control signals for each of MOSFETs 111 to 116 are shown, where a high level represents an on command and a low level represents an off command. At time t1, MOSFET 111 turns off and the mode transitions to Mode 2, and at time t2, MOSFETs 113 and 115 turn on and the mode transitions to Mode 3. As described above, Mode 2 between times t1 and t2 and Mode 4 between times t3 and t4 are dead time periods, during which MOSFETs 111 and 113, and MOSFETs 112 and 114 are turned off simultaneously to prevent arm short - circuit.

[0032] As described above, according to the present invention, the gate control signals of the MOSFETs 115 and 116 for clamping are made the same as the gate control signals of the MOSFETs 113 and 112, respectively. As a result, without newly generating a gate control signal in the upper controller 141, it is possible to increase the current path when outputting the neutral point potential and reduce the loss. As a result, since it is not necessary to change the software and hardware of the upper controller 141, the cost and period associated with the change are not required, and it is possible to provide a three-level power conversion device with low cost and high efficiency. Further, since it is not necessary to change the upper controller 141, when upgrading the existing main circuit equipment, it is possible to update to a low-loss and high-efficiency three-level power conversion device simply by replacing the clamping diodes of the existing three-level power conversion device with switching elements and adding a gate driver. Therefore, effective reuse due to high efficiency of the existing device is possible, which is also effective in extending the life of the device, reducing the cost of renewal, and preventing environmental destruction due to reduction of waste.

[0033] In FIG. 1A, the signal output from the upper controller 141 is four, and the signals of the gate drivers 135 and 136 are generated by branching the wiring. However, in an environment where there is a concern about signal attenuation or noise mixing at the signal branching portion, a configuration in which commands are output with six signals from the upper controller 141 without branching in the middle is also conceivable.

[0034] In FIG. 1A, the control signal is generated by the upper controller 141 connected to the first to sixth drive circuits (in this case, the gate drivers 131 to 136). At this time, it can also be said that the control signal given to the second drive circuit (in this case, the gate driver 132) is branched and given to the sixth drive circuit (in this case, the gate driver 136). Also, it can be said that the control signal given to the third drive circuit (in this case, the gate driver 133) is branched and given to the fifth drive circuit (in this case, the gate driver 135).

[0035] On the other hand, in a configuration where commands are output from the upper controller 141 with six signals without branching in the middle, it can be said that the control signals given to the second drive circuit (in this case, the gate driver 132) and the control signals given to the sixth drive circuit (in this case, the gate driver 136) are the same control signals respectively generated by the upper controller 141. Also, it can be said that the control signals given to the third drive circuit (in this case, the gate driver 133) and the control signals given to the fifth drive circuit (in this case, the gate driver 135) are the same control signals respectively generated by the upper controller 141.

[0036] Furthermore, in the case of a general three-level circuit, there is a simultaneous turn-on prevention function so that the above-mentioned arm short circuit does not occur accidentally, but in this embodiment, it is possible to protect the newly generated arm short circuit path without addition. The simultaneous turn-on prevention function is a function that suppresses between the control software, the hardware of the upper controller, or the gate drivers so that MOSFET 111 and MOSFET 113, and MOSFET 112 and MOSFET 114 do not turn on simultaneously. With this configuration, even if an on command is accidentally issued to MOSFETs 111 to 114 simultaneously, an arm short circuit can be prevented.

[0037] This anti-simultaneous-turn-on function of the prior art is also effective for the new arm short-circuit mode in the present invention. In the circuit of FIG. 1A, when MOSFET 111 and MOSFET 115 are turned on simultaneously, the positive power supply line 101 and the neutral point power supply line 102 will be short-circuited. Therefore, it is necessary to newly add an anti-simultaneous-turn-on function to the gate drivers of MOSFET 111 and MOSFET 115 and the upper controller 141. However, as shown in this embodiment, if the command signals of MOSFET 113 and MOSFET 115 are made common, there is no need to newly add an anti-simultaneous-turn-on function. Because MOSFET 115 operates with the same signal as MOSFET 113, and MOSFET 113 and MOSFET 111 have an anti-simultaneous-turn-on function, MOSFET 115 will also not prevent simultaneous turn-on with MOSFET 111. Similarly, regarding the simultaneous turn-on of MOSFET 114 and MOSFET 116, according to this embodiment, it can be suppressed without newly adding an anti-simultaneous-turn-on function. Thus, when this embodiment is applied, it is possible to prevent arm short circuits in all operating modes without newly adding an anti-simultaneous-turn-on function even in a three-level main circuit applying a MOSFET to a clamp element.

Embodiment

[0038] FIG. 2 shows a circuit diagram of a second embodiment according to this embodiment. In FIG. 2, the same components as those in FIG. 1A and FIG. 7 are labeled with the same reference numerals. The difference from FIG. 1A is that isolation amplifiers 201 and 202 are provided and gate drivers 135 and 136 are deleted. In Example 1, six gate drivers were prepared, and one gate driver was connected to each MOSFET element. In this example, gate drivers 135 and 136 for MOSFETs 115 and 116 are deleted, and instead, gate drivers 133 and 132 are used to control the gates of MOSFETs 115 and 116, respectively. However, since the source potentials of MOSFET 112 and MOSFET 116, and MOSFET 113 and MOSFET 115 are different, the outputs of the gate drivers that output the driving voltage based on the source potential cannot be shared. Therefore, the gate output voltage for driving MOSFET 116 is output from gate driver 132, branched, and then input to MOSFET 116 via isolation amplifier 202. The input impedance of isolation amplifier 202 is set high so that even if the output of gate driver 132 is branched, it will not affect the gate voltage for driving MOSFET 112. Similarly, MOSFET 115 is also driven by the gate control signal of gate driver 133 transmitted via isolation amplifier 201 in the same manner as MOSFET 116.

[0039] Isolation amplifiers 201 and 202 transmit signals while ensuring insulation through optical transmission components such as photocouplers, magnetic couplers that transmit signals through magnetic coupling, or pulse transformers. The circuits of isolation amplifiers 201 and 202 are composed of the aforementioned insulation components such as photocouplers, an isolation power supply, and several passive components, and can be configured to be smaller and lower in cost than the gate driver.

[0040] According to this example, since the gate voltage after being output from and branched by gate drivers 132 and 133 can be input to the MOSFET via isolation amplifiers 201 and 202, gate drivers 135 and 136 for MOSFETs 115 and 116 can be deleted, which is effective for miniaturizing and reducing the cost of the system.

[0041] In addition, in order to limit the off-time difference between MOSFET112 and MOSFET116 and between MOSFET113 and MOSFET115 within 1 μs, the propagation delays in the isolation amplifiers 201 and 202 need to be within 1 μs.

[0042] The configuration of the three-level circuit in FIG. 2 further includes first to fourth drive circuits (in this case, gate drivers 131 to 134) that are respectively connected to the control terminals of the first to fourth semiconductor elements (in this case, MOSFETs 111 to 114) and supply control signals. A control signal branched from the output of the third drive circuit (in this case, gate driver 133) and transmitted through the first isolation circuit (in this case, isolation amplifier 201) is input to the control terminal of the fifth semiconductor element (in this case, MOSFET 115). A control signal branched from the output of the second drive circuit (in this case, gate driver 132) and transmitted through the second isolation circuit (in this case, isolation amplifier 202) is input to the control terminal of the sixth semiconductor element (in this case, MOSFET 116).

Embodiment

[0043] FIG. 3 shows a circuit diagram of a third embodiment according to the present embodiment. In FIG. 3, the same components as those in FIGS. 1A, 2, and 7 are denoted by the same reference numerals. The feature of this embodiment lies in that a three-level main circuit is configured using three modules each containing two MOSFET elements. In recent years, for high-voltage applications, the number of so-called 2-in-1 elements, which incorporate two series-connected elements in one module, such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFET elements, has been increasing. The 2-in-1 elements are being adopted more frequently because they can reduce the parasitic inductance that causes surge voltage and noise, and can be mounted compactly on devices.

[0044] Even with the three-level circuit according to this embodiment, using these components to configure a three-level power conversion device is effective for miniaturization. In FIG. 3, MOSFET 111, diode 117, MOSFET 115, and diode 121 are connected in series and housed in one MOSFET module 124. Similarly, MOSFET 112, diode 118, MOSFET 113, and diode 119 are housed in MOSFET module 123. Further, MOSFET 114, diode 120, MOSFET 116, and diode 122 are housed in MOSFET module 125. With this configuration, in any of the aforementioned modes 1 to 10, the voltage applied to one module is limited to at most half of the voltage applied between the positive power line 101 and the negative power line 103, and the breakdown voltage of the MOSFET module can be kept low. For example, when the potential difference between the positive power line 101 and the negative power line 103 is 3 kV, with the configuration of this embodiment, the maximum voltage applied to one MOSFET module is limited to 1.5 kV.

[0045] When the applied voltage increases, it is necessary to increase the space distance and creepage distance between the positive and negative terminals of the MOSFET module, which leads to the problem that the MOSFET module becomes larger and the size of the system increases. According to this embodiment, since the applied voltage can be halved as described above, the enlargement of the MOSFET module can be prevented.

[0046] The configuration of the three-level circuit in FIG. 3 can also be described as follows: The first to sixth semiconductor elements (in this case, MOSFETs 111 to 116) are grouped in pairs of two and housed in one package (in this case, MOSFET modules 123 to 125) respectively. Specifically, a series circuit of the first semiconductor element (in this case, MOSFET 111) and the fifth semiconductor element (in this case, MOSFET 115), a series circuit of the second semiconductor element (in this case, MOSFET 112) and the third semiconductor element (in this case, MOSFET 113), and a series circuit of the fourth semiconductor element (in this case, MOSFET 114) and the sixth semiconductor element (in this case, MOSFET 116) are each housed in one package.

Embodiment

[0047] FIGS. 4A and 4B show pulse sequence diagrams for explaining a fourth embodiment according to the present embodiment. FIGS. 4A and 4B show gate signals input to the gates of MOSFETs 111 to 116, where a high level represents on and a low level represents off. The feature of this embodiment lies in defining the order of blocking of MOSFETs in a three-level circuit when an abnormality occurs in the system and the upper controller 141 performs an emergency stop process. In a three-level circuit, when detecting an abnormality and blocking the circuit, depending on the order of blocking of the elements, the elements may be destroyed. For example, the case of performing an emergency stop in mode 1 shown in FIG. 1B will be described. When MOSFETs 111 and 112 are turned off in FIG. 1B, the flowing current turns to the path of the negative side power line 103 → diode 120 → diode 119 → AC terminal 104, and the potential of the AC terminal 104 drops to the potential of the negative side power line 103. At this time, the voltage between the negative side power line 103 and the positive side power line 101 is applied to MOSFETs 111 and 112 in a shared manner. If the turn-off timings of MOSFETs 111 and 112 are completely synchronized, the same voltage is applied to both and they turn off. However, if MOSFET 112 turns off first, the entire voltage between the positive side power line 101 and the negative side power line 103 is applied to MOSFET 112, and the element is destroyed due to overvoltage. As a countermeasure, a sequence is adopted in which MOSFET 111 is turned off first and then MOSFET 112 is turned off.

[0048] This will be described below with reference to FIG. 4A. Figure 4A shows the sequence of pulses leading to an emergency stop in Mode 1 from the normal operating state. Before time t1, it is Mode 3 where MOSFETs 112, 113, 115, and 116 are on. At time t1, MOSFETs 112 and 116 turn off and it enters Mode 4. At time t2, MOSFET 114 turns on and it shifts to Mode 5, and thereafter the modes sequentially switch from time t3 to t6. After it becomes Mode 1 at time t6, an emergency stop process is performed at time t7 and MOSFET 111 turns off. Next, after a predetermined time, at time t8, the remaining MOSFET 112 is cut off and the three-level circuit stops. Since MOSFET 116 operates with the same pulse as MOSFET 112, it turns off together with MOSFET 112 at time t8.

[0049] If MOSFET 111 is cut off first in this way, it shifts to Mode 2 and the current diverts to the path shown in Figure 1C. In this state, the voltage between the positive power supply line 101 and the neutral point power supply line 102 is applied to MOSFET 111, and the voltage between the negative power supply line 103 and the neutral point power supply line 102 is applied to MOSFET 114. Subsequently, after a predetermined time, when MOSFET 112 is cut off, the current diverts to the current path shown in Figure 1D, and the voltage between the negative power supply line 103 and the neutral point power supply line 102, which was applied to MOSFET 114 in the previous Mode 2, is applied to MOSFET 112, and the voltage between the positive power supply line 101 and the neutral point power supply line 102 remains applied to MOSFET 111. In this way, if the outer MOSFET 111 of the three-level circuit is turned off first and then the inner MOSFET 112 is turned off, only half of the voltage between the positive power supply line 101 and the negative power supply line 103 is applied to the element, making it possible to prevent element breakdown.

[0050] Although not shown in the figure, for Mode 5 where MOSFETs 113 and 114 are on, the outer MOSFET 114 can be turned off first and then the inner MOSFET 113 can be turned off in the same way. For Modes 6 and 10, only the direction of the current reverses, and the order of turning off the MOSFETs is the outer MOSFET → the inner MOSFET. In the form of FIG. 4A described above, when stopping the three-level circuit in Modes 1 and 6, the second semiconductor element is turned off after the first semiconductor element is turned off, and when stopping the three-level circuit in Modes 5 and 10, the third semiconductor is turned off after the fourth semiconductor element is turned off. The same applies to the case of stopping the three-level power conversion device using this three-level circuit.

[0051] Note that when turning off the outer MOSFET first, it is desirable to turn off the inner MOSFET at least 1 μs or more earlier. This is because the turn-off operation of the MOSFET takes up to about 1 μs. That is, if the inner MOSFET is turned off 1 μs later than the outer MOSFET, the outer MOSFET can be surely turned off and then the inner MOSFET can be turned off, and the effects of this embodiment can be obtained. In this case, it can also be said that the time difference when turning off the second semiconductor element (in this case, MOSFET112) after turning off the first semiconductor element (in this case, MOSFET111), and the time difference when turning off the third semiconductor element (in this case, MOSFET113) after turning off the fourth semiconductor element (in this case, MOSFET114) are 1 μs or more.

[0052] Next, Modes 3 and 8 in which the inner MOSFETs 112 and 113 are simultaneously on will be described with reference to FIG. 4B. Figure 4B shows a pulse sequence of Mode 3 → Mode 4 → Mode 5 → Mode 4 → Mode 3. After MOSFET 112 and MOSFET 116 are turned on at time t4, if an emergency stop is applied at time t5, MOSFET 112 and MOSFET 113 are turned off simultaneously without a time difference. In Mode 3, as shown in Figure 1C, current flows from the neutral power line 102 to the AC terminal 104, the voltage between the positive power line 101 and the neutral power line 102 is applied to MOSFET 111, and the voltage between the negative power line 103 and the neutral point is applied to MOSFET 114. When MOSFET 112 and MOSFET 113 are turned off from this state, the current commutates and flows through the path in Figure 1D. At this time, the voltage applied to MOSFET 111 remains applied to MOSFET 111 as it is, and the voltage applied to MOSFET 114 is applied to MOSFET 112. Thus, in Mode 3, even if the inner MOSFETs are turned off simultaneously, only half the voltage between the positive power line 101 and the negative power line 103 is applied to the elements, and no breakdown due to overvoltage occurs. Similarly, in Mode 8, only the direction of the current and the position of the element to which the voltage is applied change, but basically the same operation occurs and no element breakdown due to overvoltage occurs.

[0053] The form of Figure 4B described above can also be said to turn off both the second semiconductor element (in this case, MOSFET 112) and the third semiconductor element (in this case, MOSFET 113) when stopping the three-level circuit in Modes 3 and 8. This is the same when stopping the three-level power conversion device using this three-level circuit.

[0054] In Modes 2, 4, 7, and 9, since the outer MOSFETs are already in the off state, only the inner MOSFETs need to be turned off during an emergency stop. That is, in Modes 2 and 7, MOSFET 112 is turned off. Further, in Modes 4 and 9, MOSFET 113 is turned off.

Embodiment

[0055] Figure 5 shows a circuit diagram of a fifth embodiment according to the present embodiment. In FIG. 5, the same components as those in FIGS. 1A, 2, 3, and 7 are denoted by the same reference numerals. The feature of this embodiment is that the dead time is minimized to delete the antiparallel diodes (diodes 117 to 122) of the MOSFETs, and a three-level circuit is configured only with MOSFETs.

[0056] Since the MOSFET is a bidirectional element, it is possible to flow current in the reverse direction by inputting an on control signal to the gate, and the antiparallel diode can be deleted by appropriately performing gate control. However, in mode 2, MOSFETs 112 and 116 are on, but the gate control commands of MOSFETs 113 and 115 through which reverse current flows are off, and the MOSFETs will conduct reverse current in the off state. When a reverse current flows through the MOSFET in the off state, current flows through the built-in parasitic PN diode, resulting in problems such as increased resistance and loss compared to flowing through the on-state MOSFET, and deterioration due to crystal defects inside the MOSFET due to current flowing through the PN junction. Also, in the case of a MOSFET provided with a Schottky barrier diode to prevent current from flowing through the parasitic diode, the loss increases because the current flows through the Schottky barrier diode with a large resistance during conduction. In this embodiment, the above problems are suppressed by limiting the periods of modes 2, 4, 7, and 9 during which the MOSFET conducts reverse current in the off state to the shortest, and a configuration for deleting the reverse diode is realized.

[0057] Regarding the periods of these modes 2, 4, 7, and 9, in the case of MOSFETs used in a three-level circuit with a high breakdown voltage of 600 V or more in view of the conduction loss generated and the degradation of the elements, it is necessary to limit the maximum to 10 μs.

Embodiment

[0058] FIG. 6 shows a circuit diagram of a sixth embodiment according to this embodiment. The sixth embodiment is the case where the configuration of the second embodiment is applied to the three-level circuit of the fifth embodiment. That is, insulation amplifiers 201 and 202 are provided for the three-level circuit of the fifth embodiment, and gate drivers 135 and 136 are deleted. In addition, the configuration of Example 3 can also be applied to the three-level circuit of Example 5. That is, the MOSFETs 111 to 116 of the three-level circuit of Example 5 may be packaged in one package with two MOSFETs in a set.

[0059] As described above, the three-level examples according to this embodiment have been described by taking the MOSFET as an example for the circuit configuration and the gate control method. However, the same effect can be obtained by replacing it with other elements as long as it is an FET-type element that can be energized in the reverse direction. For example, a junction field effect transistor (JFET) or the like. In addition, although the materials of the elements such as MOSFETs and JFETs are not particularly described in the above-described examples, it is not limited to silicon (Si) that is widely and generally used, but also a wide bandgap semiconductor (WBG) that is currently becoming popular. Specifically, it is obvious that the same effect can be obtained with silicon carbide (SiC), gallium nitride (GaN), or the like.

[0060] (Description of effects) In the existing three-level circuit, when the inner MOSFETs (corresponding to MOSFET112 and MOSFET113) are both on, the clamping MOSFETs (MOSFET115 and MOSFET116) are turned on. However, in the actual three-level circuit, MOSFET112 and MOSFET113 operate with different control signals. In order to turn on the clamping MOSFET only at the timing when these two are turned on together, it is necessary to newly generate a control signal pattern different from the control signals of MOSFET112 and MOSFET113. For this reason, it is necessary to change the software of the upper controller 141 that generates the control signal and add a control signal line from the upper controller 141 to the gate driver. Changing the software requires a great deal of time for its production and verification, resulting in a long development period and a large development cost, which is one of the reasons for increasing the product price. In addition, adding a control signal line from the upper controller 141 to the gate driver increases the cost due to an increase in the number of parts and causes the three-level power conversion device to become larger. According to the three-level power conversion device using the three-level circuit of the present embodiment, even when a clamping MOSFET is provided, a three-level power conversion device or the like that can operate without newly creating a control signal for the clamping MOSFET can be provided. In addition, it is not necessary to change the software of the upper controller 141, and it is possible to provide a three-level power conversion device at low cost in a short period of time. Furthermore, according to the three-level power conversion device using the three-level circuit of the present embodiment, for the three-level power conversion device using the conventional three-level circuit shown in FIG. 7, by adding clamping MOSFETs (MOSFET115, MOSFET116), and in Example 1, by adding gate drivers 135 and 136, it is possible to easily update to a three-level power conversion device using a low-loss and high-efficiency three-level circuit. In addition, in Example 2, insulation amplifiers 201 and 202 may be added instead of the gate drivers 135 and 136.

[0061] (Railway vehicle) The three-level power conversion device using the three-level circuit described above can be used, for example, in railway vehicles.

[0062] (Control method of three-level power conversion device) Also, the operation of the three-level power conversion device using the three-level circuit described above can be regarded as a control method of the three-level power conversion device. That is, for the three-level power conversion device using the three-level circuit described in FIGS. 1A, 2 to 6, when the first semiconductor element (in this case, MOSFET 111) and the second semiconductor element (in this case, MOSFET 112) are turned on and the third semiconductor element (in this case, MOSFET 113) and the fourth semiconductor element (in this case, MOSFET 114) are turned off, a first mode (in this case, modes 1, 6) in which energization is performed between the first power supply line (in this case, the positive-side power supply line 101) and the AC terminal 104, and when the second semiconductor element and the third semiconductor element are turned on and the first semiconductor element and the fourth semiconductor element are turned off, a second mode (in this case, modes 3, 8) in which energization is performed between the second power supply line (in this case, the neutral point power supply line 102) and the AC terminal 104, and when the third semiconductor element and the fourth semiconductor element are turned on and the first semiconductor element and the second semiconductor element are turned off, a third mode (in this case, modes 5, 10) in which energization is performed between the third power supply line (in this case, the negative-side power supply line 103) and the AC terminal 104, can be regarded as a control method of a three-level power conversion device including these.

[0063] Furthermore, between the first mode (in this case, modes 1, 6) and the second mode (in this case, modes 3, 8), a fifth mode (in this case, modes 2, 7) in which the first semiconductor element (in this case, MOSFET 111) is turned off from the first mode is included, and between the second mode and the third mode (in this case, modes 5, 10), a sixth mode (in this case, modes 4, 9) in which the second semiconductor element (in this case, MOSFET 112) is turned off from the second mode is further included, and it can be regarded as a control method of a three-level power conversion device. In this case, as described above, the periods (dead times) of the fifth mode (in this case, modes 2, 7) and the sixth mode (in this case, modes 4, 9) are preferably within 10 μs.

[0064] (Production method of three-level power conversion device) Furthermore, as described above, an upcycle can be performed on a three-level power conversion device using an existing three-level circuit to a three-level power conversion device using the three-level circuit of the present embodiment. At this time, the clamp diodes can be replaced with MOSFETs, and in some cases, it is only necessary to add a gate driver, and the update to a low-loss and high-efficiency three-level power conversion device can be easily achieved. Therefore, the present embodiment can be regarded as a production method of a three-level power conversion device that updates a three-level power conversion device using an existing three-level circuit to a three-level power conversion device using the three-level circuit of the present embodiment. In this case, as shown in FIG. 7, an existing three-level circuit can be said to be a three-level circuit that mutually converts direct current and alternating current using three potential levels and has the following configuration. It includes first to third power supply lines (in this case, a positive-side power supply line 101, a neutral-point power supply line 102, and a negative-side power supply line 103) each having a first to third potential, and first to fourth semiconductor elements (in this case, MOSFETs 111 to 114) having a high potential terminal, a low potential terminal, and a control terminal and capable of bidirectional energization between the high potential terminal and the low potential terminal, and first and second diodes (in this case, clamp diodes 501 and 502). The first to fourth semiconductor elements are connected in series. The high potential terminal of the first semiconductor element (in this case, MOSFET 111) is connected to the first power supply line (in this case, the positive-side power supply line 101). The low potential terminal of the first semiconductor element is connected to the high potential terminal of the second semiconductor element (in this case, MOSFET 112). The low potential terminal of the second semiconductor element is connected to the high potential terminal of the third semiconductor element (in this case, MOSFET 113). The low potential terminal of the third semiconductor element is connected to the high potential terminal of the fourth semiconductor element (in this case, MOSFET 114). The low potential terminal of the fourth semiconductor element is connected to the third power supply line (in this case, the negative-side power supply line 103). Also, the cathode terminal of the first diode (in this case, the clamp diode 501) is connected to the connection point between the second semiconductor element and the third semiconductor element. The anode terminal of the first diode is connected to the second power line (in this case, the neutral point power line 102). The cathode terminal of the second diode (in this case, the clamp diode 502) is connected to the second power line. The anode terminal of the second diode is connected to the connection point between the third semiconductor element and the fourth semiconductor element. Furthermore, the AC terminal 104 is connected to the connection point between the second semiconductor element and the third semiconductor element.

[0065] When upscaling a three-level power conversion device using an existing three-level circuit to a three-level power conversion device using the three-level circuit of this embodiment, fifth and sixth semiconductor elements (in this case, MOSFETs 115 and 116) having a high potential terminal, a low potential terminal, and a control terminal and capable of bidirectional conduction between the high potential terminal and the low potential terminal are added. The high potential side terminal of the fifth semiconductor element (in this case, MOSFET 115) is connected to the cathode terminal of the first diode (in this case, diode 121) and also connected to the connection point between the second semiconductor element (in this case, MOSFET 112) and the third semiconductor element (in this case, MOSFET 113). The low potential side terminal of the fifth semiconductor element is connected to the second power line (in this case, the neutral point power line 102). The high potential side terminal of the sixth semiconductor element (in this case, MOSFET 116) is connected to the second power line. The low potential side terminal of the sixth semiconductor element is connected to the anode terminal of the second diode (in this case, diode 122) and also connected to the connection point between the third semiconductor element and the fourth semiconductor element. The same control signal as that of the control terminal of the sixth semiconductor element is applied to the control terminal of the second semiconductor element, and the same control signal as that of the control terminal of the fifth semiconductor element is applied to the control terminal of the third semiconductor element. This can be achieved, for example, by adding gate drivers 135 and 136 as shown in FIG. 1A.

[0066] Also, the forms described above will include at least the following technical matters. <Technical matter 1> A three-level power conversion device that mutually converts direct current and alternating current using three potential levels, comprising: first to third power supply lines respectively having first to third potentials; first to sixth semiconductor elements having a high potential terminal, a low potential terminal, and a control terminal, and capable of bidirectional energization between the high potential terminal and the low potential terminal; the first to fourth semiconductor elements are connected in series, the high potential terminal of the first semiconductor element is connected to the first power supply line, the low potential terminal of the first semiconductor element is connected to the high potential terminal of the second semiconductor element, the low potential terminal of the second semiconductor element is connected to the high potential terminal of the third semiconductor element, the low potential terminal of the third semiconductor element is connected to the high potential terminal of the fourth semiconductor element, the low potential terminal of the fourth semiconductor element is connected to the third power supply line, the high potential side terminal of the fifth semiconductor element is connected to the connection point between the second semiconductor element and the third semiconductor element, the low potential side terminal of the fifth semiconductor element is connected to the second power supply line, the high potential side terminal of the sixth semiconductor element is connected to the second power supply line, the low potential side terminal of the sixth semiconductor element is connected to the connection point between the third semiconductor element and the fourth semiconductor element, the alternating current terminal is connected to the connection point between the second semiconductor element and the third semiconductor element, the same control signal as that of the control terminal of the sixth semiconductor element is applied to the control terminal of the second semiconductor element, and the same control signal as that of the control terminal of the fifth semiconductor element is applied to the control terminal of the third semiconductor element. A three-level power conversion device characterized by this. <Technical matter 2> In the three-level power conversion device described in the above Technical matter 1, it further comprises first to sixth drive circuits respectively connected to the control terminals of the first to sixth semiconductor elements and applying control signals, the control signals are generated by a host controller connected to the first to sixth drive circuits, the control signal applied to the second drive circuit is branched and applied to the sixth drive circuit, and the control signal applied to the third drive circuit is branched and applied to the fifth drive circuit. <Technical matter 3> In the three-level power conversion device described in Technical Matter 1 above, the device further includes first to sixth drive circuits respectively connected to the control terminals of the first to sixth semiconductor elements for providing control signals. The control signals are generated by a host controller connected to the first to sixth drive circuits. The control signal given to the second drive circuit and the control signal given to the sixth drive circuit are respectively generated by the host controller as the same control signal. The control signal given to the third drive circuit and the control signal given to the fifth drive circuit are respectively generated by the host controller as the same control signal. <Technical Matter 4> In the three-level power conversion device described in any one of Technical Matters 1 to 3 above, the device further includes first to sixth diodes respectively connected to the first to sixth semiconductor elements, with the cathode terminal connected to the high potential terminal and the anode terminal connected to the low potential terminal. <Technical Matter 5> In the three-level power conversion device described in Technical Matter 1 above, the device further includes first to fourth drive circuits respectively connected to the control terminals of the first to fourth semiconductor elements for providing control signals. A control signal branched from the output of the third drive circuit and transmitted through the first insulation circuit is input to the control terminal of the fifth semiconductor element, and a control signal branched from the output of the second drive circuit and transmitted through the second insulation circuit is input to the control terminal of the sixth semiconductor element. <Technical Matter 6> In the three-level power conversion device described in Technical Matter 5 above, the propagation delays of the first insulation circuit and the second insulation circuit are within 1 μs. <Technical Matter 7> In the three-level power conversion device described in any one of Technical Matters 1 to 6 above, the first to sixth semiconductor elements are respectively packed in one package with two elements in a set. <Technical Matter 8> In the three-level power conversion device described in Technical Matter 7 above, the series circuit of the first semiconductor element and the fifth semiconductor element, the series circuit of the second semiconductor element and the third semiconductor element, and the series circuit of the fourth semiconductor element and the sixth semiconductor element are respectively packed in one package. <Technical matter 9> In the three-level power conversion device shown in any one of the above Technical matters 1 to 8, the difference in operation between the second drive circuit and the sixth drive circuit and the difference in operation between the third drive circuit and the fifth drive circuit are each within 1 μs. <Technical matter 10> A railway vehicle equipped with the three-level power conversion device shown in any one of the above Technical matters 1 to 9. <Technical matter 11> A control method for a three-level power conversion device that mutually converts direct current and alternating current using three potential levels, comprising: first to third power supply lines each having a first to third potential; first to sixth semiconductor elements having a high potential terminal, a low potential terminal, and a control terminal, and enabling bidirectional conduction between the high potential terminal and the low potential terminal; the first to fourth semiconductor elements are connected in series, the high potential terminal of the first semiconductor element is connected to the first power supply line, the low potential terminal of the first semiconductor element is connected to the high potential terminal of the second semiconductor element, the low potential terminal of the second semiconductor element is connected to the high potential terminal of the third semiconductor element, the low potential terminal of the third semiconductor element is connected to the high potential terminal of the fourth semiconductor element, the low potential terminal of the fourth semiconductor element is connected to the third power supply line, the high potential side terminal of the fifth semiconductor element is connected to the connection point between the second semiconductor element and the third semiconductor element, the low potential side terminal of the fifth semiconductor element is connected to the second power supply line, the high potential side terminal of the sixth semiconductor element is connected to the second power supply line, the low potential side terminal of the sixth semiconductor element is connected to the connection point between the third semiconductor element and the fourth semiconductor element, the alternating current terminal is connected to the connection point between the second semiconductor element and the third semiconductor element, the same control signal as the control terminal of the sixth semiconductor element is applied to the control terminal of the second semiconductor element, and the same control signal as the control terminal of the fifth semiconductor element is applied to the control terminal of the third semiconductor element. By turning on the first semiconductor element and the second semiconductor element and turning off the third semiconductor element and the fourth semiconductor element, a first mode of energizing between the first power supply line and the alternating current terminal is provided; by turning on the second semiconductor element and the third semiconductor element and turning off the first semiconductor element and the fourth semiconductor element, a second mode of energizing between the second power supply line and the alternating current terminal is provided; by turning on the third semiconductor element and the fourth semiconductor element and turning off the first semiconductor element and the second semiconductor element, a third mode of energizing between the third power supply line and the alternating current terminal is provided. The control method of the three-level power conversion device includes these modes to perform control. <Technical Matter 12> In the control method of the three-level power conversion device described in Technical Matter 11 above, between the first mode and the second mode, a fifth mode of turning off the first semiconductor element from the first mode is included, and between the second mode and the third mode, a sixth mode of turning off the second semiconductor element from the second mode is further included. <Technical Matter 13> In the control method of the three-level power conversion device described in Technical Matter 12 above, the periods of the fifth mode and the sixth mode are within 10 μs. <Technical Matter 14> In the control method of the three-level power conversion device described in any one of Technical Matters 11 to 13 above, when stopping the three-level power conversion device in the first mode, turn off the second semiconductor element after turning off the first semiconductor element, and when stopping the three-level power conversion device in the third mode, turn off the third semiconductor element after turning off the fourth semiconductor element. <Technical Matter 15> In the control method of the three-level power conversion device described in Technical Matter 14 above, the time difference when turning off the second semiconductor element after turning off the first semiconductor element, and the time difference when turning off the third semiconductor element after turning off the fourth semiconductor element are 1 μs or more. <Technical Matter 16> In the control method of the three-level power conversion device described in any one of Technical Matters 11 to 15 above, when stopping the three-level power conversion device in the second mode, turn off both the second semiconductor element and the third semiconductor element. <Technical Matter 17> A method for manufacturing a three-level power conversion device that mutually converts direct current and alternating current using three potential levels, comprising: first to third power supply lines respectively having first to third potentials; first to fourth semiconductor elements having a high potential terminal, a low potential terminal, and a control terminal, and enabling bidirectional current conduction between the high potential terminal and the low potential terminal; and first and second diodes. The first to fourth semiconductor elements are connected in four series. The high potential terminal of the first semiconductor element is connected to the first power supply line, the low potential terminal of the first semiconductor element is connected to the high potential terminal of the second semiconductor element, the low potential terminal of the second semiconductor element is connected to the high potential terminal of the third semiconductor element, the low potential terminal of the third semiconductor element is connected to the high potential terminal of the fourth semiconductor element, and the low potential terminal of the fourth semiconductor element is connected to the third power supply line. The cathode terminal of the first diode is connected to the connection point between the second semiconductor element and the third semiconductor element, the anode terminal of the first diode is connected to the second power supply line, the cathode terminal of the second diode is connected to the second power supply line, and the anode terminal of the second diode is connected to the connection point between the third semiconductor element and the fourth semiconductor element. For a three-level power conversion device in which an AC terminal is connected to the connection point between the second semiconductor element and the third semiconductor element, fifth and sixth semiconductor elements having a high potential terminal, a low potential terminal, and a control terminal, and enabling bidirectional current conduction between the high potential terminal and the low potential terminal are added. The high potential side terminal of the fifth semiconductor element is connected to the cathode terminal of the first diode and to the connection point between the second semiconductor element and the third semiconductor element, and the low potential side terminal of the fifth semiconductor element is connected to the second power supply line. The high potential side terminal of the sixth semiconductor element is connected to the second power supply line, and the low potential side terminal of the sixth semiconductor element is connected to the anode terminal of the second diode and to the connection point between the third semiconductor element and the fourth semiconductor element. The same control signal as that of the control terminal of the sixth semiconductor element is applied to the control terminal of the second semiconductor element, and the same control signal as that of the control terminal of the fifth semiconductor element is applied to the control terminal of the third semiconductor element.

[0067] As described above, although the present embodiment has been explained, the technical scope of the present invention is not limited to the scope described in the above embodiment. It is obvious from the description of the claims that the present invention also includes those obtained by making various changes or improvements to the above embodiment within the technical scope of the present invention.

Explanation of Signs

[0068] 101... plus-side power line, 102... neutral-point power line, 103... minus-side power line, 104... AC terminal, 111 to 116... MOSFET, 117 to 122... diode, 131 to 136... gate driver, 141... upper controller, 142... plus-side power capacitor, 143... minus-side power capacitor, 501, 502... clamp diode

Claims

1. A three-level power conversion device that mutually converts direct current and alternating current using three potential levels, comprising: first to third power supply lines each having a first to third potential; first to sixth semiconductor elements having a high potential terminal, a low potential terminal, and a control terminal, and allowing bidirectional current conduction between the high potential terminal and the low potential terminal; and the first to fourth semiconductor elements are connected in series; the high potential terminal of the first semiconductor element is connected to the first power supply line; the low potential terminal of the first semiconductor element is connected to the high potential terminal of the second semiconductor element; the low potential terminal of the second semiconductor element is connected to the high potential terminal of the third semiconductor element; the low potential terminal of the third semiconductor element is connected to the high potential terminal of the fourth semiconductor element; the low potential terminal of the fourth semiconductor element is connected to the third power supply line; the high potential side terminal of the fifth semiconductor element is connected to the connection point between the second and third semiconductor elements; the low potential side terminal of the fifth semiconductor element is connected to the second power supply line; the high potential side terminal of the sixth semiconductor element is connected to the second power supply line; the low potential side terminal of the sixth semiconductor element is connected to the connection point between the third and fourth semiconductor elements; an AC terminal is connected to the connection point between the second and third semiconductor elements; the same control signal as that of the control terminal of the sixth semiconductor element is applied to the control terminal of the second semiconductor element; the same control signal as that of the control terminal of the fifth semiconductor element is applied to the control terminal of the third semiconductor element, characterized in that it is a three-level power conversion device.

2. further comprising first to sixth drive circuits respectively connected to the control terminals of the first to sixth semiconductor elements and applying control signals, the control signals are generated by an upper controller connected to the first to sixth drive circuits, and the three-level power conversion device according to claim 1, wherein the control signal applied to the second drive circuit is branched and applied to the sixth drive circuit, and the control signal applied to the third drive circuit is branched and applied to the fifth drive circuit.

3. further comprising first to sixth drive circuits respectively connected to the control terminals of the first to sixth semiconductor elements and applying control signals, the control signals are generated by an upper controller connected to the first to sixth drive circuits, The control signal supplied to the second drive circuit and the control signal supplied to the sixth drive circuit are such that the same control signal is generated by the upper controller for each, and the control signal supplied to the third drive circuit and the control signal supplied to the fifth drive circuit are such that the same control signal is generated by the upper controller for each. The three-level power conversion device according to claim 1.

4. The three-level power conversion device according to claim 1, further comprising first to sixth diodes each connected to each of the first to sixth semiconductor elements, with the cathode terminal connected to the high potential terminal and the anode terminal connected to the low potential terminal.

5. The three-level power conversion device further comprises first to fourth drive circuits respectively connected to the control terminals of the first to fourth semiconductor elements to supply control signals, a control signal branched from the output of the third drive circuit and transmitted through the first insulation circuit is input to the control terminal of the fifth semiconductor element, a control signal branched from the output of the second drive circuit and transmitted through the second insulation circuit is input to the control terminal of the sixth semiconductor element. The three-level power conversion device according to claim 1.

6. The three-level power conversion device according to claim 5, wherein the propagation delays of the first insulation circuit and the second insulation circuit are within 1 μs.

7. In the three-level power conversion device according to claim 1, the first to sixth semiconductor elements are each packaged in one package with two in a set.

8. The three-level power conversion device according to claim 7, wherein the series circuit of the first semiconductor element and the fifth semiconductor element, the series circuit of the second semiconductor element and the third semiconductor element, and the series circuit of the fourth semiconductor element and the sixth semiconductor element are each packaged in one package.

9. The three-level power conversion device according to claim 1, wherein the difference in operation between the second drive circuit and the sixth drive circuit and the difference in operation between the third drive circuit and the fifth drive circuit are each within 1 μs.

10. A railway vehicle equipped with the three-level power conversion device according to any one of claims 1 to 9.

11. A control method for a three-level power conversion device that mutually converts direct current and alternating current using three potential levels, A first to third power supply lines each having a first to third potential, and first to sixth semiconductor elements each having a high potential terminal, a low potential terminal, and a control terminal, and capable of bidirectional energization between the high potential terminal and the low potential terminal, wherein the first to fourth semiconductor elements are connected in series, the high potential terminal of the first semiconductor element is connected to the first power supply line, the low potential terminal of the first semiconductor element is connected to the high potential terminal of the second semiconductor element, the low potential terminal of the second semiconductor element is connected to the high potential terminal of the third semiconductor element, the low potential terminal of the third semiconductor element is connected to the high potential terminal of the fourth semiconductor element, the low potential terminal of the fourth semiconductor element is connected to the third power supply line, the high potential side terminal of the fifth semiconductor element is connected to the connection point between the second semiconductor element and the third semiconductor element, the low potential side terminal of the fifth semiconductor element is connected to the second power supply line, the high potential side terminal of the sixth semiconductor element is connected to the second power supply line, the low potential side terminal of the sixth semiconductor element is connected to the connection point between the third semiconductor element and the fourth semiconductor element, an AC terminal is connected to the connection point between the second semiconductor element and the third semiconductor element, the same control signal as that of the control terminal of the sixth semiconductor element is applied to the control terminal of the second semiconductor element, and the same control signal as that of the control terminal of the fifth semiconductor element is applied to the control terminal of the third semiconductor element. In a configuration where the first semiconductor element and the second semiconductor element are turned on and the third semiconductor element and the fourth semiconductor element are turned off, a first mode of energization between the first power supply line and the AC terminal, a second mode of energization between the second power supply line and the AC terminal by turning on the second semiconductor element and the third semiconductor element and turning off the first semiconductor element and the fourth semiconductor element, a third mode of energization between the third power supply line and the AC terminal by turning on the third semiconductor element and the fourth semiconductor element and turning off the first semiconductor element and the second semiconductor element, A control method for a three-level power conversion device that controls by including.

12. The control method for a three-level power conversion device according to claim 11, further including a fifth mode of turning off the first semiconductor element from the first mode between the first mode and the second mode, and further including a sixth mode of turning off the second semiconductor element from the second mode between the second mode and the third mode.

13. The control method of the three-level power conversion device according to claim 12, wherein the periods of the fifth mode and the sixth mode are within 10 μs.

14. When stopping the three-level power conversion device in the first mode, turn off the second semiconductor element after turning off the first semiconductor element. The control method of the three-level power conversion device according to claim 11, wherein when stopping the three-level power conversion device in the third mode, turn off the third semiconductor element after turning off the fourth semiconductor element.

15. The control method of the three-level power conversion device according to claim 14, wherein the time difference when turning off the second semiconductor element after turning off the first semiconductor element and the time difference when turning off the third semiconductor element after turning off the fourth semiconductor element are 1 μs or more.

16. The control method of the three-level power conversion device according to claim 11, wherein when stopping the three-level power conversion device in the second mode, turn off both the second semiconductor element and the third semiconductor element.

17. A production method of a three-level power conversion device that mutually converts direct current and alternating current using three potential levels, First to third power supply lines each having first to third potentials, First to fourth semiconductor elements having a high potential terminal, a low potential terminal, and a control terminal, and capable of bidirectional conduction between the high potential terminal and the low potential terminal, First and second diodes, Comprising: The first to fourth semiconductor elements are connected in series, The high potential terminal of the first semiconductor element is connected to the first power supply line, The low potential terminal of the first semiconductor element is connected to the high potential terminal of the second semiconductor element, The low potential terminal of the second semiconductor element is connected to the high potential terminal of the third semiconductor element, The low potential terminal of the third semiconductor element is connected to the high potential terminal of the fourth semiconductor element, The low potential terminal of the fourth semiconductor element is connected to the third power supply line, The cathode terminal of the first diode is connected to the connection point between the second semiconductor element and the third semiconductor element, The anode terminal of the first diode is connected to the second power supply line, The cathode terminal of the second diode is connected to the second power supply line, The anode terminal of the second diode is connected to the connection point between the third semiconductor element and the fourth semiconductor element, For a three-level power conversion device in which the AC terminal is connected to the connection point between the second semiconductor element and the third semiconductor element, Add fifth and sixth semiconductor elements having a high potential terminal, a low potential terminal, and a control terminal, and capable of bidirectional conduction between the high potential terminal and the low potential terminal. The high-potential side terminal of the fifth semiconductor element is connected to the cathode terminal of the first diode and is also connected to the connection point between the second semiconductor element and the third semiconductor element. The low-potential side terminal of the fifth semiconductor element is connected to the second power line. The high-potential side terminal of the sixth semiconductor element is connected to the second power line. The low-potential side terminal of the sixth semiconductor element is connected to the anode terminal of the second diode and is also connected to the connection point between the third semiconductor element and the fourth semiconductor element. Connect such that the same control signal as that of the control terminal of the sixth semiconductor element is applied to the control terminal of the second semiconductor element, and the same control signal as that of the control terminal of the fifth semiconductor element is applied to the control terminal of the third semiconductor element. A method for producing a three-level power conversion device.

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