Game machine

Abstract

To provide a game machine capable of suitably mounting electronic components on a board.SOLUTION: A game machine includes a first decorative board 56 for mounting a bypass capacitor 85. The bypass capacitor 85 includes a pair of first electrode 85a and second electrode 85b. A first pad 171a electrically connected with the first electrode 85a of the bypass capacitor 85, a second pad 171b electrically connected with the second electrode 85b of the bypass capacitor 85, a first wiring pattern 172a, and a third wiring pattern 172c are provided on the first decorative board 56. A direction in which a side of the first pad 171a in which the first wiring pattern 172a is drawn out when seen from the center of the first pad 171a exists is the same direction as a direction in which a side of the second pad 171b in which the third wiring pattern 172c is drawn out when seen from the center of the second pad 171b.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] The present invention relates to a gaming machine.

Background Art

[0002] As a type of gaming machine, pachinko machines, slot machines, etc. are known. In these gaming machines, a lottery is conducted based on the establishment of predetermined lottery conditions, and a privilege is given to the player according to the result of the lottery. In addition, a configuration in which an effect for allowing the player to predict or recognize the result of the lottery is generally performed. These gaming machines include a substrate on which electronic components for advancing the game and electronic components for executing the effect are mounted.

[0003] Specifically for pachinko machines, for example, a lottery is conducted based on the entry of a game ball into the ball entry part provided in the game area, a variable display of a pattern is performed on the display surface of the display device, and when a winning result is obtained in the lottery, a combination of specific patterns or the like is finally stopped and displayed on the display surface, and a configuration for shifting to a special gaming state advantageous to the player is known. When shifting to the special gaming state, for example, the opening and closing of a ball entry device or the like provided in the game area is started, and the payout of game balls is performed based on the entry of the game balls into the ball entry device (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Here, in a gaming machine such as the above example, it is necessary to suitably mount electronic components on the substrate, and there is still room for improvement in this regard.

[0006] The present invention has been made in view of the above-exemplified circumstances and the like, and an object thereof is to provide a gaming machine capable of suitably mounting electronic components on a substrate.

Means for Solving the Problems

[0007] In order to solve the above problems, the invention according to claim 1 is a gaming machine including a predetermined substrate on which a first predetermined electronic component and a second predetermined electronic component smaller than the first predetermined electronic component are mounted. The first predetermined electronic component is mounted on a first predetermined plate surface side which is one plate surface side of the predetermined substrate. The second predetermined electronic component is mounted on a second predetermined plate surface side which is the side opposite to the first predetermined plate surface of the predetermined substrate. In a region on the second predetermined plate surface which is the back side of the region where the first predetermined electronic component is mounted on the first predetermined plate surface, the second predetermined electronic component is not mounted. On the second predetermined plate surface side of the predetermined substrate, a specific electronic component larger than the second predetermined electronic component is mounted. The specific electronic component is mounted in a region on the second predetermined plate surface which is the back side of the region where the first predetermined electronic component is mounted on the first predetermined plate surface. As the second predetermined electronic component, a predetermined second predetermined electronic component and a specific second predetermined electronic component are provided. The predetermined second predetermined electronic component is formed such that a longitudinal direction and a short-side direction are generated along a plane orthogonal to the thickness direction of the predetermined second predetermined electronic component. The specific second predetermined electronic component is formed such that a longitudinal direction and a short-side direction are generated along a plane orthogonal to the thickness direction of the specific second predetermined electronic component. The predetermined second predetermined electronic component and the specific second predetermined electronic component are mounted on the predetermined substrate such that the longitudinal direction of the predetermined second predetermined electronic component and the longitudinal direction of the specific second predetermined electronic component are in the same direction. On the second predetermined plate surface side of the predetermined substrate, a predetermined control component is mounted. Among a plurality of connection parts to which a plurality of electrodes of the specific second predetermined electronic component are electrically connected, there is a predetermined connection part to which a predetermined electrode among the plurality of electrodes of the specific second predetermined electronic component is electrically connected. The predetermined substrate includes a specific connection part to which a predetermined terminal of the predetermined control component is electrically connected. The predetermined connection part and the specific connection part are electrically connected. There is a configuration in which no control component is arranged between the predetermined terminal and the specific second predetermined electronic component. The specific second predetermined electronic component includes a first predetermined electrode and a second predetermined electrode as a pair of electrodes. The predetermined substrate a first predetermined connection part to which the first predetermined electrode is electrically connected; a first predetermined wiring pattern drawn from the first predetermined connection part; a second predetermined connection part to which the second predetermined electrode is electrically connected; a second predetermined wiring pattern drawn from the second predetermined connection part; and includes The direction in which the side of the first predetermined connection part from which the first predetermined wiring pattern is drawn exists when viewed from the center of the first predetermined connection part is the same as the direction in which the side of the second predetermined connection part from which the second predetermined wiring pattern is drawn exists when viewed from the center of the second predetermined connection part. Further, the invention according to claim 2 is a gaming machine including a predetermined substrate on which a first predetermined electronic component and a second predetermined electronic component smaller than the first predetermined electronic component are mounted. The first predetermined electronic component is mounted on a first predetermined plate surface side which is one plate surface side of the predetermined substrate. The second predetermined electronic component is mounted on a second predetermined plate surface side which is the opposite side of the first predetermined plate surface of the predetermined substrate. In the area on the second predetermined plate surface on the back side of the area where the first predetermined electronic component is mounted on the first predetermined plate surface, the second predetermined electronic component is not mounted. The predetermined substrate is provided with a predetermined substrate fixing part for fixing the predetermined substrate. In a region where the distance from the predetermined substrate fixing portion is less than a predetermined distance, the second predetermined electronic component is not mounted. The first predetermined electronic component is mounted in the region where the distance is less than the predetermined distance. As the second predetermined electronic component, a predetermined second predetermined electronic component and a specific second predetermined electronic component are provided. The predetermined second predetermined electronic component is formed such that a longitudinal direction and a lateral direction are generated along a plane orthogonal to the thickness direction of the predetermined second predetermined electronic component. The specific second predetermined electronic component is formed such that a longitudinal direction and a lateral direction are generated along a plane orthogonal to the thickness direction of the specific second predetermined electronic component. The predetermined second predetermined electronic component and the specific second predetermined electronic component are mounted on the predetermined substrate such that the longitudinal direction of the predetermined second predetermined electronic component and the longitudinal direction of the specific second predetermined electronic component are in the same direction. A predetermined control component is mounted on the second predetermined plate surface side of the predetermined substrate. Among the plurality of connection portions to which a plurality of electrodes of the specific second predetermined electronic component are electrically connected, a predetermined connection portion to which a predetermined electrode among the plurality of electrodes of the specific second predetermined electronic component is electrically connected is included. The predetermined substrate includes a specific connection portion to which a predetermined terminal of the predetermined control component is electrically connected. The predetermined connection portion and the specific connection portion are electrically connected. A control component is not arranged between the predetermined terminal and the specific second predetermined electronic component. The predetermined second predetermined electronic component includes a first predetermined electrode and a second predetermined electrode as a pair of electrodes. The predetermined substrate A first predetermined connection portion to which the first predetermined electrode is electrically connected, A first predetermined wiring pattern drawn from the first predetermined connection portion, A second predetermined connection portion to which the second predetermined electrode is electrically connected, A second predetermined wiring pattern drawn from the second predetermined connection portion, comprises, when viewed from the center of the first predetermined connection portion, the direction in which the side of the first predetermined connection portion from which the first predetermined wiring pattern is drawn exists is the same as the direction in which the side of the second predetermined connection portion from which the second predetermined wiring pattern is drawn exists when viewed from the center of the second predetermined connection portion.

Advantages of the Invention

[0008] According to the present invention, it becomes possible to suitably mount an electronic component on a substrate.

Brief Description of the Drawings

[0009]

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Mode for Carrying Out the Invention

[0010] <First Embodiment> Hereinafter, a first embodiment of a pachinko machine 10, which is a type of gaming machine, will be described in detail with reference to the drawings. FIG. 1 is a front view of the pachinko machine 10, and FIGS. 2 and 3 are perspective views showing the main configuration of the pachinko machine 10 developed. Note that in FIG. 2, the configuration within the game area of the pachinko machine 10 is omitted for convenience, and in FIG. 3, the configuration on the rear side of the pachinko machine 10 of the main control device 60 described later is omitted.

[0011] As shown in FIG. 1, the pachinko machine 10 has an outer frame 11 that forms the outer shell of the pachinko machine 10, and a game machine body 12 that is rotatably attached to the front of the outer frame 11. The outer frame 11 is formed by connecting wooden plates on four sides and has a rectangular frame shape. The pachinko machine 10 is installed in a game hall by attaching and fixing the outer frame 11 to the island equipment. Note that in the pachinko machine 10, the outer frame 11 is not an essential configuration, and it may be configured such that the outer frame 11 is provided in the island equipment of the game hall.

[0012] As shown in FIGS. 2 and 3, the game machine body 12 includes an inner frame 13, a front door frame 14 disposed in front of the inner frame 13, and a back pack unit 15 disposed behind the inner frame 13. Among the game machine body 12, the inner frame 13 is rotatably supported by the outer frame 11. Specifically, when viewed from the front, with the left side as the rotation base end side and the right side as the rotation tip end side, the inner frame 13 can rotate forward.

[0013] The front door frame 14 is rotatably supported by the inner frame 13 and can rotate forward with the left side as the rotation base end side and the right side as the rotation tip end side when viewed from the front. Also, the back pack unit 15 is rotatably supported by the inner frame 13 and can rotate backward with the left side as the rotation base end side and the right side as the rotation tip end side when viewed from the front.

[0014] Note that the gaming machine main body 12 is provided with a locking device at its rotating tip, and has a function of putting the gaming machine main body 12 into a locked state where it cannot be opened with respect to the outer frame 11, and also has a function of putting the front door frame 14 into a locked state where it cannot be opened with respect to the inner frame 13. Each of these locked states is released by performing an unlocking operation using an unlocking key on the cylinder lock 17 provided to be exposed on the front surface of the pachinko machine 10.

[0015] <Configuration on the front side> Next, the configuration on the front side of the gaming machine main body 12 will be described.

[0016] The inner frame 13 is mainly composed of a resin base 21 whose outer shape is substantially the same as that of the outer frame 11. A substantially elliptical window hole 23 is formed in the central portion of the resin base 21. A game board 24 is detachably attached to the resin base 21. The game board 24 is made of plywood, and the game area PA formed on the front surface of the game board 24 is exposed on the front side of the inner frame 13 through the window hole 23 of the resin base 21.

[0017] <Configuration of the game board> Here, the configuration of the game board 24 will be described with reference to FIG. 4. FIG. 4 is a front view of the game board 24.

[0018] An inner rail portion 25 and an outer rail portion 26 are attached to the game board 24 so as to partition a part of the outer edge of the game area PA, and an induction rail as an induction means is constituted by these inner rail portion 25 and outer rail portion 26. The game balls launched from the game ball launching mechanism 27 (see FIG. 2) attached below the window hole 23 in the resin base 21 are guided to the upper part of the game area PA by the induction rail.

[0019] Incidentally, the game ball launching mechanism 27 includes a launching rail 27a extending toward the guiding rail, a ball feeder 27b that supplies the game balls stored in an upper plate 54a described later onto the launching rail 27a, and a solenoid 27c which is an electric actuator that launches the game balls supplied onto the launching rail 27a toward the guiding rail. When a launching operation device (or operation handle) 28 provided on the front door frame 14 is rotationally operated, the solenoid 27c is driven and controlled, and the game balls are launched.

[0020] A plurality of large and small openings penetrating in the front-rear direction are formed in the game board 24. A general winning opening 31, a special electric winning device 32, a first operating opening 33, a second operating opening 34, a through gate 35, a variable display unit 36, a special figure unit 37, a general figure unit 38, etc. are respectively provided in each opening. A total of four general winning openings 31 are provided, and the others are provided one by one.

[0021] Even if a game ball enters the through gate 35, no payout of game balls is executed. On the other hand, when a game ball enters the general winning opening 31, the special electric winning device 32, the first operating opening 33, or the second operating opening 34, a predetermined number of game balls are paid out. Specifically regarding the number of prize balls, when one game ball enters the first operating opening 33 or when one game ball enters the second operating opening 34, one prize ball is paid out. When one game ball enters the general winning opening 31, 10 prize balls are paid out. When one game ball enters the special electric winning device 32, 15 prize balls are paid out.

[0022] Note that the number of the above-mentioned prize balls is arbitrary. For example, the second operating opening 34 may be configured to have fewer prize balls than the first operating opening 33, or the second operating opening 34 may be configured to have more prize balls than the first operating opening 33.

[0023] In addition, an out port 24a is provided at the lowermost part of the game board 24, and game balls that have not entered various winning ports or the like are discharged from the game area PA through the out port 24a. Also, a large number of pins 24b are implanted in the game board 24 to appropriately disperse and adjust the falling direction of the game balls, and various members such as windmills are arranged.

[0024] Here, "entering the ball" means that the game ball passes through a predetermined opening, and it includes not only the mode of being discharged from the game area PA after passing through the opening, but also the mode of continuing to flow down in the game area PA without being discharged from the game area PA after passing through the opening. However, in the following description, in order to clearly distinguish from the entering of the game ball into the out port 24a, the entering of the game ball into the general winning port 31, the special electric winning device 32, the first operating port 33, the second operating port 34, and the through gate 35 is also expressed as "winning".

[0025] The first operating port 33 and the second operating port 34 are unitized as an operating port device and installed on the game board 24. Both the first operating port 33 and the second operating port 34 are open upward. Also, the two operating ports 33, 34 are arranged in the vertical direction with the first operating port 33 on the upper side. A general electric accessory 34a as a guide piece composed of a pair of left and right movable pieces is provided at the second operating port 34. In the closed state of the general electric accessory 34a, the game ball cannot win at the second operating port 34, and when the general electric accessory 34a is in the open state, winning at the second operating port 34 becomes possible.

[0026] A through gate 35 is provided on the upstream side in the flowing direction of the game ball from the second operating port 34. The through gate 35 has a through hole (not shown) penetrating in the vertical direction, and the game ball that has won at the through gate 35 flows down in the game area PA after winning. Thereby, it is possible for the game ball that has won at the through gate 35 to win at the second operating port 34.

[0027] Based on winning the through gate 35, the normal power role 34a of the second operating port 34 is switched from a closed state to an open state. Specifically, an internal lottery is performed with the winning of the through gate 35 as a trigger, and a variable picture display is performed on the normal map display section 38a of the normal map unit 38 provided in the lower right corner of the play area PA, which is an area where the game ball does not pass. Then, when the result of the internal lottery is a win for the electric role opening and the stop result corresponding to the result is displayed and the variable display of the normal map display section 38a is terminated, the state transitions to the normal power opening state. In the normal power opening state, the normal power role 34a is opened in a predetermined manner.

[0028] The map display unit 38a is composed of a segment display in which a plurality of display segments using LEDs are arranged in a predetermined manner, but is not limited thereto, and may be composed of other types of display devices such as a liquid crystal display device, an organic EL display device, a CRT, or a dot matrix display device. As for the pattern displayed variably on the map display unit 38a, a configuration in which a plurality of types of letters are displayed variably, a configuration in which a plurality of types of symbols are displayed variably, a configuration in which a plurality of types of characters are displayed variably, or a configuration in which a plurality of types of colors are displayed in a switched manner may be considered.

[0029] In the normal map unit 38, a normal map reserve display section 38b is provided adjacent to the normal map display section 38a. The number of game balls that enter the through gate 35 is reserved up to a maximum of four, and the number of reserved balls is displayed by lighting up the normal map reserve display section 38b.

[0030] A winning lottery is held by triggering a winning entry into the first operating port 33 or the second operating port 34. The lottery result is then displayed clearly through the display effects on the special symbol unit 37 and the symbol display device 41 of the variable display unit 36.

[0031] Regarding the special figure unit 37 in detail, the special figure unit 37 is provided with a special figure display section 37a. The display area of the special figure display section 37a is narrower than the display surface 41a of the symbol display device 41. In the special figure display section 37a, a hit lottery is conducted triggered by winning in the first operation port 33 or the second operation port 34, and a variable display of the symbol or a predetermined display is performed. Then, a result corresponding to the lottery result is displayed. Note that the special figure display section 37a is constituted by a segment display device in which a plurality of display segments by LEDs are arranged in a predetermined manner, but it is not limited thereto, and it may be constituted by other types of display devices such as a liquid crystal display device, an organic EL display device, a CRT, or a dot matrix display. Also, as the symbol displayed in the special figure display section 37a, a configuration in which a plurality of types of characters are displayed, a configuration in which a plurality of types of symbols are displayed, a configuration in which a plurality of types of characters are displayed, or a configuration in which a plurality of types of colors are displayed, etc. can be considered.

[0032] In the special figure unit 37, a special figure hold display section 37b is provided at a position adjacent to the special figure display section 37a. The number of game balls winning in the first operation port 33 or the second operation port 34 is held up to a maximum of 4, and the held number is displayed by lighting the special figure hold display section 37b.

[0033] Regarding the symbol display device 41 in detail, the symbol display device 41 is configured as a liquid crystal display device equipped with a liquid crystal display, and the display content is controlled by a display control device described later. Note that the symbol display device 41 is not limited to a liquid crystal display device, and it may be another display device having a display screen such as a plasma display device, an organic EL display device, or a CRT, or it may be a dot matrix display.

[0034] In the symbol display device 41, when a winning occurs at the first operation port 33 or a winning occurs at the second operation port 34 and a variable display of symbols or a predetermined display is performed in the special symbol display section 37a, a variable display of symbols or a predetermined display is performed accordingly. For example, on the display surface 41a of the symbol display device 41, three symbol columns, namely, an upper row, a middle row, and a lower row, are set as a plurality of display areas, and main symbols with numbers from "1" to "9" are arranged in ascending or descending order in each symbol column and are scrolled and displayed. In this scroll display, first, the scroll display in all the symbol columns is started, and the scroll display is switched to the standby display in the order of the upper symbol column → the lower symbol column → the middle symbol column, and finally, it ends with a predetermined symbol being statically displayed in each symbol column. Then, in a game round where the game result is a big win result, a combination of predetermined symbols is stopped and displayed on an effective line preset on the display surface 41a of the symbol display device 41. Specifically, when it becomes the most advantageous big win result described later, the same combination of odd symbols is stopped and displayed. When it becomes the low-probability big win result described later, the same combination of even symbols is stopped and displayed. When it becomes the low-win high-probability big win result described later, a combination of symbols that is not the same combination but is not stopped and displayed when it is not the low-win high-probability big win result is stopped and displayed.

[0035] Note that in the symbol display device 41, not only a display effect triggered by a winning at the first operation port 33 or the second operation port 34 but also a display effect during the opening and closing execution mode that is shifted to after winning and winning is performed. Also, based on a winning at any of the operation ports 33, 34, a display is started in the special symbol display section 37a and the symbol display device 41, and one game round corresponds to the period from the start of the display until a predetermined result is displayed and ended. Also, the mode of the variable display of symbols in the symbol display device 41 is not limited to the above and is arbitrary, and the number of symbol columns, the direction of the variable display of symbols in the symbol column, the number of symbols in each symbol column, etc. can be changed as appropriate. Also, the symbols that are variably displayed in the symbol display device 41 are not limited to the symbols as described above, and for example, a configuration in which only numbers are variably displayed as symbols may be used.

[0036] When a jackpot is won in the jackpot lottery based on winning the first winning port 33 or the second winning port 34, the game shifts to the opening / closing execution mode in which winning the special electric winning device 32 becomes possible. The special electric winning device 32 is provided with a large winning port (not shown) that leads to the back side of the game board 24, and is provided with an opening / closing door 32a that opens and closes the large winning port. The opening / closing door 32a is arranged in either a closed state or an open state. Specifically, the opening / closing door 32a is normally in a closed state where game balls cannot win, and is switched to an open state where game balls can win when winning the shift to the opening / closing execution mode in the internal lottery. Incidentally, the opening / closing execution mode is a mode that will shift when a winning result occurs. Note that, in the closed state, winning is not impossible, but it may be configured to be a state where winning is less likely to occur than in the open state.

[0037] <Configuration Regarding Discharge of Game Balls> FIG. 5 is an explanatory diagram for explaining a configuration regarding the discharge of game balls that have flowed down in the game area PA.

[0038] As already explained, game balls that have entered any of the general winning port 31, the special electric winning device 32, the first operation port 33, the second operation port 34, and the out port 24a are discharged from the game area PA. In other words, game balls launched from the game ball launching mechanism 27 and flowing into the game area PA are discharged from the game area PA by entering any of the general winning port 31, the special electric winning device 32, the first operation port 33, the second operation port 34, and the out port 24a. Game balls that have entered any of the general winning port 31, the special electric winning device 32, the first operation port 33, the second operation port 34, and the out port 24a are guided to the back side of the game board 24.

[0039] On the back surface of the game board 24, discharge passage portions 42 to 48 are formed corresponding to the general winning opening 31, the special electric winning device 32, the first operation opening 33, the second operation opening 34, and the out opening 24a, respectively. The game balls that have flowed into the discharge passage portions 42 to 48 flow down the discharge passage portions 42 to 48 into which they have flowed, and are guided to the lower end portion of the game board 24 on the back side of the game board 24 and collected by a discharge ball collection portion (not shown). Then, the game balls collected by the discharge ball collection portion are discharged to a ball circulation device of the island facility where the pachinko machine 10 is installed in the game hall.

[0040] Each of the discharge passage portions 42 to 48 is provided with various detection sensors 42a to 48a for detecting game balls. These discharge passage portions 42 to 48 and detection sensors 42a to 48a will be described below. Since four general winning openings 31 are provided as already described, discharge passage portions 42 to 44 exist corresponding to each of these four. In this case, one detection sensor 42a, 43a is provided for each of the first discharge passage portion 42 corresponding to the leftmost general winning opening 31 and the second discharge passage portion 43 adjacent to the right thereof corresponding to the general winning opening 31. Specifically, the first winning opening detection sensor 42a is provided at an intermediate position in the first discharge passage portion 42 so that a detection range exists, and the second winning opening detection sensor 43a is provided at an intermediate position in the second discharge passage portion 43 so that a detection range exists. A game ball that has entered the leftmost general winning opening 31 is detected by the first winning opening detection sensor 42a while passing through the first discharge passage portion 42, and a game ball that has entered the general winning opening 31 adjacent to the right thereof is detected by the second winning opening detection sensor 43a while passing through the second discharge passage portion 43. Further, a third discharge passage portion 44 is provided so as to merge at an intermediate position with respect to the two general winning openings 31 on the right side. The third discharge passage portion 44 has an entrance side region corresponding to each of the two general winning openings 31, and has one exit side region by the merging of these entrance side regions in the middle. The third winning opening detection sensor 44a is provided at an intermediate position in the exit side region of the third discharge passage portion 44 so that a detection range exists. A game ball that has entered any one of the two general winning openings 31 on the right side is detected by the third winning opening detection sensor 44a while passing through the third discharge passage portion 44.

[0041] There is a fourth discharge passage portion 45 corresponding to the special electric winning device 32. A special electric detection sensor 45a is provided so that a detection range exists at an intermediate position of the fourth discharge passage portion 45. A game ball that has entered the special electric winning device 32 is detected by the special electric detection sensor 45a while passing through the fourth discharge passage portion 45. There is a fifth discharge passage portion 46 corresponding to the first operation port 33. A first operation port detection sensor 46a is provided so that a detection range exists at an intermediate position of the fifth discharge passage portion 46. A game ball that has entered the first operation port 33 is detected by the first operation port detection sensor 46a while passing through the fifth discharge passage portion 46. There is a sixth discharge passage portion 47 corresponding to the second operation port 34. A second operation port detection sensor 47a is provided so that a detection range exists at an intermediate position of the sixth discharge passage portion 47. A game ball that has entered the second operation port 34 is detected by the second operation port detection sensor 47a while passing through the sixth discharge passage portion 47. There is a seventh discharge passage portion 48 corresponding to the out port 24a. An out port detection sensor 48a is provided so that a detection range exists at an intermediate position of the seventh discharge passage portion 48. A game ball that has entered the out port 24a is detected by the out port detection sensor 48a while passing through the seventh discharge passage portion 48.

[0042] In addition, a game ball detected by any one of the various detection sensors 42a to 48a will not be a detection target of the other detection sensors 42a to 48a. Also, a gate detection sensor 49a is provided for the through gate 35, and a game ball passing through the through gate 35 while flowing down in the game area PA is detected by the gate detection sensor 49a.

[0043] As various detection sensors 42a to 49a, electromagnetic induction type proximity sensors are all used, but the sensors to be used are arbitrary as long as they can individually detect the pachinko balls. Also, the various detection sensors 42a to 49a are electrically connected to a main control device 60 described later, and the detection results of the various detection sensors 42a to 49a are output to the main control device 60. Specifically, the various detection sensors 42a to 49a output a LOW level signal when not detecting a pachinko ball, and output a HI level signal when detecting a pachinko ball. Note that it is not limited to this, and the relationship between HI and LOW may be reversed.

[0044] As shown in FIG. 2, a front door frame 14 is provided so as to cover the entire front side of an inner frame 13 to which a game board 24 having the above configuration is attached to a resin base 21. As shown in FIG. 1, a window portion 51 is formed in the front door frame 14 so that substantially the entire game area PA can be visually recognized from the front. The window portion 51 has a substantially elliptical shape, and a window panel 52 is fitted therein. The window panel 52 is formed colorless and transparent by glass, but is not limited thereto, and may be formed colorless and transparent by a synthetic resin, or may be formed colored and transparent as long as the game area PA can be visually recognized through the window panel 52 from the front of the pachinko machine 10.

[0045] Above the window portion 51, a pair of left and right speaker portions 53 for outputting sound effects and the like according to the game state are provided. Also, below the window portion 51, an upper bulging portion 54 bulging forward and a lower bulging portion 55 are arranged side by side vertically. Inside the upper bulging portion 54, an upper tray 54a opened upward is provided, and inside the lower bulging portion 55, a lower tray 55a also opened upward is provided. The upper tray 54a has a function of temporarily storing the pachinko balls paid out from a payout device described later and guiding them to the pachinko ball launching mechanism 27 side while aligning them in a row. Also, the lower tray 55a has a function of storing the surplus pachinko balls in the upper tray 54a.

[0046] As shown in FIG. 1, on the front surface of the front door frame 14, a first decorative substrate 56 is provided at the lower left side of the window portion 51, and a second decorative substrate 57 is provided approximately at the center in the left-right direction above the window portion 51. A plurality of LED chips are mounted on each of the decorative substrates 56 and 57, and light emission effects corresponding to the gaming state are performed by these decorative substrates 56 and 57. The front door frame 14 is provided with a first decorative cover 58 that covers the front of the first decorative substrate 56 and a second decorative cover 59 that covers the front of the second decorative substrate 57. These decorative covers 58 and 59 are formed of a transparent or translucent resin that transmits the light emitted from the LED chips, and bulge toward the front of the pachinko machine 10. Details of the decorative substrates 56 and 57 and the decorative covers 58 and 59 will be described later.

[0047] Next, the configuration on the back side of the gaming machine main body 12 will be described.

[0048] As shown in FIG. 2, on the back surface of the inner frame 13 (specifically, the game board 24), a main control device 60 that controls the main gaming is mounted. FIG. 6 is a front view of the main control device 60.

[0049] <Configuration of the main control device 60> As shown in FIG. 6, the main control device 60 includes a main control board 61 housed in a board box 60a. An MPU 62 is mounted on an element mounting surface, which is one surface of the main control board 61. The board box 60a is formed transparently so that the MPU 62 housed in the board box 60a can be visually observed from the outside of the board box 60a. Although the board box 60a is formed colorless and transparent, it may be formed colored and transparent as long as the MPU 62 housed in the board box 60a can be visually observed from the outside of the board box 60a. The main control device 60 is mounted on the back surface of the resin base 21 such that a facing wall portion 60b facing the element mounting surface of the main control board 61 in the board box 60a faces the rear of the pachinko machine 10. Therefore, by opening the gaming machine body 12 forward with respect to the outer frame 11 to expose the back surface of the resin base 21, the facing wall portion 60b of the board box 60a can be visually observed, and the MPU 62 can be visually observed through the facing wall portion 60b.

[0050] The substrate box 60a is formed by combining a plurality of case bodies 60c front and back. In these plurality of case bodies 60c, there are provided coupling portions 60e for preventing separation of these case bodies 60c and leaving a trace when separating these case bodies 60c. The coupling portions 60e are arranged in parallel on one side of the substantially rectangular parallelepiped-shaped substrate box 60a. Thus, even if the case body 60c is separated by destroying a part of the coupling portions 60e while preventing separation of the case body 60c using a part of the coupling portions 60e, it is possible to prevent separation of the case body 60c again by making another coupling portion 60e in a coupled state later. Further, when the coupling portion 60e is destroyed and a trace remains when separating the case body 60c, it is possible to grasp whether the separation of the case body 60c is being performed illegally by visually checking the coupling portion 60e. Also, a sealing seal 60f is attached across the boundary between the case bodies 60c on the side of the substrate box 60a opposite to the side where the coupling portions 60e are arranged in parallel. When the sealing seal 60f is peeled off, the adhesive layer remains on the case body 60c. Thus, when the sealing seal 60f is peeled off when separating the case body 60c, it is possible to leave a trace.

[0051] In the main control device 60 having the above configuration, on the main control board 61, there are provided a setting key insertion portion 68a into which a setting key owned by the manager of the game hall is inserted and turned on to cause an opportunity to change the setting state of the pachinko machine 10 within the range from "Setting 1" to "Setting 6", an update button 68b that is operated to sequentially change the setting state of the pachinko machine 10 after the ON operation on the setting key insertion portion 68a, a reset button 68c that is operated to clear the data of the main-side RAM 65 provided in the MPU 62 of the main control device 60, which will be described later, and first to third notification display devices 69a to 69c for notifying the management result of the game history. Note that the setting state of the pachinko machine 10 is not limited to six levels from "Setting 1" to "Setting 6" and can be arbitrary as long as there are multiple levels.

[0052] These setting key insertion part 68a, update button 68b, reset button 68c, and first to third notification display devices 69a to 69c are all provided on the element mounting surface of the main control board 61. Also, the element mounting surface of the main control board 61 faces the opposing wall part 60b of the board box 60a as already described, but the setting key insertion part 68a, update button 68b, and reset button 68c are not covered by the opposing wall part 60b. That is, in the opposing wall part 60b, regions facing the setting key insertion part 68a, update button 68b, and reset button 68c respectively are individual openings. Thereby, it is possible to insert the setting key into the setting key insertion part 68a, press the update button 68b, and press the reset button 68c without opening the board box 60a.

[0053] By inserting the setting key into the setting key insertion part 68a and rotating it in a predetermined direction, the setting key insertion part 68a is turned on. By starting the supply of operating power to the pachinko machine 10 in this state (that is, by starting the supply of operating power to the MPU 62 of the main control device 60), a changeable state in which the setting state of the pachinko machine 10 can be changed is obtained. And in this state, each time the update button 68b is pressed once, the setting state of the pachinko machine 10 is changed step by step in ascending order within the range of "Setting 1" to "Setting 6". When the update button 68b is operated in the state of "Setting 6", it is updated to "Setting 1". Also, by rotating the setting key inserted into the setting key insertion part 68a in the direction opposite to the predetermined direction from the ON operation position and returning it to the initial position, the setting key insertion part 68a is turned off. When the setting key insertion part 68a is turned off, the changeable state ends, and a state in which the game can be played with the setting value state at that time is obtained. That is, even if the update button 68b is operated after the changeable state ends, the setting value cannot be changed.

[0054] The ON operation for the setting key insertion part 68a is valid only when the operation power supply to the pachinko machine 10 starts (that is, when the operation power supply to the MPU 62 of the main control device 60 starts). Therefore, even if an ON operation is performed on the setting key insertion part 68a after the processing at the start of the operation power supply in the MPU 62 of the main control device 60 is completed, the set value cannot be changed.

[0055] The setting state of the pachinko machine 10 determines the degree of advantage per unit time in the pachinko machine 10. The larger the value of n in "Setting n" (n is an integer from "1" to "6") (that is, the higher the set value), the higher the degree of advantage. Although details will be described later, there are a low probability mode in which the winning probability is relatively low and a high probability mode in which the winning probability is relatively high as the winning / losing lottery mode that determines the winning probability of the jackpot result. The set value is set so that the winning probability of the jackpot result in the low probability mode becomes higher as the set value is higher. On the other hand, the winning probability of the jackpot result in the high probability mode is constant regardless of the set value.

[0056] The reset button 68c is operated to clear the data in the main side RAM 65 as described above. However, in order to cause the clearing of the data, it is necessary to start the supply of operation power to the pachinko machine 10 with the reset button 68c being pressed (that is, it is necessary to start the supply of operation power to the MPU 62 of the main control device 60). The ON operation for the reset button 68c is valid only when the operation power supply to the pachinko machine 10 starts (that is, when the operation power supply to the MPU 62 of the main control device 60 starts). Therefore, even if the reset button 68c is pressed after the processing at the start of the operation power supply in the MPU 62 of the main control device 60 is completed, the data in the main side RAM 65 cannot be cleared.

[0057] Each of the first to third notification display devices 69a to 69c is a segment display in which seven display segments using LEDs are arranged, but it is not limited to this, and it may be a single light emitter of a multicolor light emission type, a liquid crystal display device, or an organic EL display. The first to third notification display devices 69a to 69c are all installed so that their display surfaces face the direction in which the element mounting surface of the main control board 61 faces, and are covered by the opposing wall portion 60b of the board box 60a. In this case, since the board box 60a is formed transparently, it is possible to visually observe the display surfaces of the first to third notification display devices 69a to 69c accommodated in the board box 60a from the outside of the board box 60a. Also, as already described, the main control device 60 is mounted on the back surface of the resin base 21 such that the opposing wall portion 60b facing the element mounting surface of the main control board 61 in the board box 60a faces the rear of the pachinko machine 10. Therefore, when the game machine main body 12 is opened forward of the pachinko machine 10 with respect to the outer frame 11 and the back surface of the resin base 21 is exposed forward of the pachinko machine 10, it is possible to visually observe the display surfaces of the first to third notification display devices 69a to 69c through the opposing wall portion 60b.

[0058] On the display surface of the first notification display device 69a, various characters including alphabetic characters as well as the numbers from "0" to "9" are displayed. On the other hand, the numbers from "0" to "9" are displayed on the second notification display device 69b and the third notification display device 69c. The management result of the game history is notified using the first to third notification display devices 69a to 69c. Also, in a changeable state in which the setting state of the pachinko machine 10 can be changed, a value corresponding to the current setting value is displayed on the third notification display device 69c. Note that the value corresponding to the setting value may be displayed on the first notification display device 69a, or may be displayed on the second notification display device 69b. Also, the setting value before becoming the changeable state may be displayed on one of the first to third notification display devices 69a to 69c and the current setting value may be displayed on another one of the first to third notification display devices 69a to 69c.

[0059] Above the main control device 60 on the back surface of the inner frame 13, an audio-visual control device 81 is provided. The audio-visual control device 81 executes sound output control, light emission control, and control of the display control device 82 according to instructions from the main control device 60. Further, the audio-visual control device 81 executes light emission control of the LED chips mounted on the first decorative substrate 56 and the second decorative substrate 57.

[0060] As shown in FIG. 3, a back pack unit 15 is installed so as to cover the back side of the inner frame 13 including the main control device 60 and the audio-visual control device 81. The back pack unit 15 includes a back pack 72 formed of a synthetic resin having transparency, and a payout mechanism unit 73 and a control device assembly unit 74 are attached to the back pack 72.

[0061] The payout mechanism unit 73 includes a tank 75 to which game balls supplied from the island equipment in the game hall are sequentially replenished, and a payout device 76 for paying out the game balls stored in the tank 75. The game balls paid out from the payout device 76 are discharged to the upper tray 54a or the lower tray 55a through a payout passage provided on the downstream side of the payout device 76. The payout mechanism unit 73 is supplied with, for example, a main power supply of 24 volts AC, and a back pack substrate having a power switch for performing ON and OFF operations of the power supply is mounted thereon.

[0062] The control device assembly unit 74 includes a payout control device 77 having a function of controlling the payout device 76, and a power supply / launch control device 78 that generates and outputs predetermined electric power required for various control devices and the like, and controls the launching of game balls accompanying the operation of the launch operation device 28 by the player. The payout control device 77 and the power supply / launch control device 78 are arranged one on top of the other in the front-rear direction so that the payout control device 77 is at the rear of the pachinko machine 10.

[0063] FIG. 7 is a front view of the pachinko machine 10 with the decorative covers 58, 59 and the decorative substrates 56, 57 removed. As shown in FIG. 1, on the first decorative cover 58, columnar cover fixing bosses 58a to 58c are integrally formed by raising the upper part, the lower left part, and the lower right part of the back surface of the first decorative cover 58 to the rear of the pachinko machine 10. Further, on the second decorative cover 59, columnar cover fixing bosses 59a, 59b are integrally formed by raising the left part and the right part of the back surface of the second decorative cover 59 to the rear of the pachinko machine 10. Thread holes (not shown) are formed at the end portions of the raised ends of these cover fixing bosses 58a to 58c, 59a, 59b. As shown in FIG. 7, through holes 14a to 14e penetrating the front door frame 14 back and forth are formed in the front door frame 14 corresponding to these cover fixing bosses 58a to 58c, 59a, 59b. As shown in FIG. 1, the first decorative cover 58 and the second decorative cover 59 are fixed to the front door frame 14 by screw-fixing the cover fixing bosses 58a to 58c, 59a, 59b from the back side of the front door frame 14.

[0064] <Configuration of the decorative substrates 56, 57> Next, the configuration of the decorative substrates 56, 57 will be described.

[0065] FIG. 8(a) is a plan view showing the first mounting surface 84 which is one side plate surface of the first decorative substrate 56, FIG. 8(b) is a plan view of the first mounting surface 84 of the first decorative substrate 56 showing an enlarged peripheral region 86 of the bypass capacitor 85 mounted on the first decorative substrate 56, FIG. 8(c) is a plan view of the first mounting surface 84 of the first decorative substrate 56 showing an enlarged peripheral region 88 of the small chip resistor 87 mounted on the first decorative substrate 56, and FIG. 9 is a sectional view taken along the line A-A of FIG. 8(a). Further, FIG. 10(a) is a plan view showing the first mounting surface 89 which is one side plate surface of the second decorative substrate 57, FIG. 10(b) is a plan view of the first mounting surface 89 of the second decorative substrate 57 showing an enlarged peripheral region 98 of the bypass capacitor 97 mounted on the second decorative substrate 57, and FIG. 10(c) is a plan view of the first mounting surface 89 of the second decorative substrate 57 showing an enlarged peripheral region 102 of the small chip resistor 101 mounted on the second decorative substrate 57.

[0066] The decorative substrates 56 and 57 are four-layer substrates having a structure in which conductive layers and insulating layers are alternately laminated. As the insulating layer, a composite material in which a glass cloth base material is impregnated with a thermosetting epoxy resin is used. The conductive layer is formed by etching a copper foil plate disposed above or below the insulating layer.

[0067] As shown in FIG. 9, the first decorative substrate 56 includes, as conductive layers, a first wiring layer 91 disposed on the first mounting surface 84 side of the first decorative substrate 56, and a second wiring layer 92 disposed on the second mounting surface 95 side which is the other board surface of the first decorative substrate 56. Further, the first decorative substrate 56 includes, as conductive layers disposed between the first wiring layer 91 and the second wiring layer 92, a GND plane layer 93 (ground plane layer or ground plane layer) and a power supply plane layer 94. Lands and wiring patterns are formed on the first wiring layer 91 and the second wiring layer 92 by etching a copper foil plate.

[0068] Although illustration is omitted, the second decorative substrate 57 includes, as conductive layers, a first wiring layer disposed on the first mounting surface 89 side and a second wiring layer disposed on the second mounting surface side which is the other board surface of the second decorative substrate 57, in the same manner as the first decorative substrate 56. Further, the second decorative substrate 57 includes, as conductive layers disposed between the first wiring layer and the second wiring layer, a GND plane layer (ground plane layer or ground plane layer) and a power supply plane layer, in the same manner as the first decorative substrate 56. Lands and wiring patterns are formed on the first wiring layer and the second wiring layer by etching a copper foil plate.

[0069] As shown in Fig. 1, a stepped recess 56a corresponding to the lower left part of the curved window 51 is formed in the upper right part of the first decorative substrate 56. Also, a notch 56b is formed in the lower left part of the first decorative substrate 56 to avoid the cover fixing boss 58b of the first decorative cover 58. By providing the notch 56b in the first decorative substrate 56, it is possible to provide the first decorative substrate 56 in a wide area behind the first decorative cover 58 while avoiding the cover fixing boss 58b.

[0070] The first decorative substrate 56 is a deformed substrate having a stepped recess 56a and a notch 56b. The first decorative substrate 56 is not a rectangular or substantially rectangular substrate. As shown in Fig. 8(a), the dimension of the first decorative substrate 56 in the first direction DR1 (the vertical direction in Fig. 8(a)) is larger than the dimension of the first decorative substrate 56 in the second direction DR2 (the horizontal direction in Fig. 8(a)) orthogonal to the first direction DR1.

[0071] As shown in Fig. 10(a), the second decorative substrate 57 is formed in a horizontally long and substantially elliptical shape. The second decorative substrate 57 is not a rectangular or substantially rectangular substrate. The dimension of the second decorative substrate 57 in the major axis direction LD (the horizontal direction in Fig. 10(a)) is larger than the dimension of the second decorative substrate 57 in the minor axis direction SD (the vertical direction in Fig. 10(a)).

[0072] As shown in Fig. 8(a), a protrusion 56c is provided substantially at the center in the vertical direction of the stepped recess 56a. Fixing through holes 56d to 56g are formed in the left side of the upper end part, the protrusion 56c, the left side of the lower end part, and the right side of the lower end part of the first decorative substrate 56 to penetrate the first decorative substrate 56 in the thickness direction so that the first decorative substrate 56 can be screwed and fixed to the front surface of the front door frame 14. Also, as shown in Fig. 10(a), fixing through holes 57a and 57b are formed in the left part and the right part of the second decorative substrate 57 to penetrate the second decorative substrate 57 in the thickness direction so that the second decorative substrate 57 can be screwed and fixed to the front door frame 14.

[0073] As shown in FIG. 7, on the front door frame 14, columnar substrate fixing bosses 103 to 108 for fixing the decorative substrates 56 and 57 (FIGS. 8(a) and 10(a)) are integrally formed on the front surface of the front door frame 14. The substrate fixing bosses 103 to 108 stand up from the front surface of the front door frame 14 toward the front of the pachinko machine 10, and screw holes 103a to 108a for screw-fixing the decorative substrates 56 and 57 are formed at the end portions of the standing tips of the substrate fixing bosses 103 to 108. The decorative substrates 56 and 57 are screw-fixed to the substrate fixing bosses 103 to 108 from the front of the pachinko machine 10 so that the first mounting surfaces 84 and 89 (FIGS. 8(a) and 10(a)) face the front of the pachinko machine 10, and are fixed to the front surface of the front door frame 14 as shown in FIG. 1.

[0074] As described above, the light emission control of the LED chips mounted on the decorative substrates 56 and 57 and the sound output control of the speaker unit 53 are performed by the sound and light emission control device 81 (FIG. 3). As shown in FIG. 8(a), on the first decorative substrate 56, a first connector 111 and a second connector 112 are mounted on a second mounting surface 95 (FIG. 9) which is the plate surface on the side opposite to the first mounting surface 84. Further, as shown in FIG. 10(a), on the second decorative substrate 57, a third connector 113, a fourth connector 114, and a fifth connector 115 are mounted on the second mounting surface which is the plate surface on the side opposite to the first mounting surface 89.

[0075] A harness (not shown) for electrically connecting the voice light control device 81 (Fig. 3) and the first decorative substrate 56 is attached to the first connector 111. A harness (not shown) for electrically connecting the first decorative substrate 56 and the second decorative substrate 57 is attached to the second connector 112 and the third connector 113. Also, a harness (not shown) for electrically connecting the second decorative substrate 57 and the pair of left and right speaker units 53 is attached to the fourth connector 114 and the fifth connector 115. The voice light control device 81 outputs information for controlling the light emission of the LED chips mounted on the first decorative substrate 56 with respect to the first decorative substrate 56. Further, the voice light control device 81 outputs information for controlling the light emission of the LED chips mounted on the second decorative substrate 57 and information for controlling the sound output of the speaker unit 53 with respect to the second decorative substrate 57 via the first decorative substrate 56.

[0076] As shown in Fig. 7, the first to fifth connector insertion holes 14f to 14j that penetrate the front door frame 14 back and forth are formed in the front door frame 14 corresponding to the first to fifth connectors 111 to 115 (Figs. 8(a) and 10(a)). The decorative substrates 56 and 57 (Figs. 8(a) and 10(a)) are fixed to the front door frame 14 in a state where the connectors 111 to 115 are inserted into the corresponding connector insertion holes 14f to 14j and exposed on the back side of the front door frame 14. Attachment and detachment of the harness (not shown) to the first to fifth connectors 111 to 115 are performed from the back side of the front door frame 14.

[0077] As shown in Fig. 8(a), the first decorative substrate 56 is provided with a first light emission circuit section 121, a second light emission circuit section 122, and a third light emission circuit section 123. Also, as shown in Fig. 10(a), the second decorative substrate 57 is provided with a fourth light emission circuit section 124. These light emission circuit sections 121 to 124 include circuits for controlling the light emission of a plurality of LED chips.

[0078] Regarding the specific configuration of the light emission circuit sections 121 to 124, the configuration of the first light emission circuit section 121 will be described as an example.

[0079] FIG. 11 is a wiring diagram of the first light-emitting circuit section 121 on the first decorative substrate 56. As shown in FIG. 11, the first light-emitting circuit section 121 includes an LED driver 126, bypass capacitors 85, sixteen LED chips 127 to 142, and eight small chip resistors 87, 143 to 149. Although not shown, the second to fourth light-emitting circuit sections 122 to 124 also include an LED driver, bypass capacitors, a plurality of LED chips, and a plurality of small chip resistors. Note that the number of LED chips included in each of the light-emitting circuit sections 121 to 124 is arbitrary, and the number of small chip resistors included in each of the light-emitting circuit sections 121 to 124 is determined according to the connection mode between the LED driver and the LED chips.

[0080] As shown in FIG. 11, the LED driver 126 includes a power supply terminal 151, a clock terminal 152, a data terminal 153, a GND terminal 154 (ground terminal or earth terminal), and first to eighth output terminals 155 to 162. A wiring pattern 164 for inputting a clock signal received from the audio light-emitting control device 81 is electrically connected to the clock terminal 152, and a wiring pattern 165 for inputting lighting control data received from the audio light-emitting control device 81 is electrically connected to the data terminal 153. Further, a second wiring pattern 172b for electrically connecting the LED driver 126 to the GND plane layer 93 (FIG. 9) is connected to the GND terminal 154, and a fourth wiring pattern 172d for supplying a driving power supply for the LED driver 126 is electrically connected to the power supply terminal 151.

[0081] Note that the "terminal" in this specification refers to a linear metal part provided on an electronic component (including the small chip component described later) for electrically connecting to the corresponding pad (or pad). For example, the power terminal 151 and the GND terminal 154 (Fig. 8(b)) in the LED driver 126. Also, the "electrode" in this specification, in a narrow sense, refers to a metal part provided on an electronic component (including the small chip component described later) for electrically connecting to the corresponding pad (or pad) in a planar manner. For example, the first electrode 85a and the second electrode 85b (Fig. 8(b)) described later in the bypass capacitor 85, and does not include the above "terminal". On the other hand, the "electrode" in this specification, in a broad sense, refers to a metal part provided on an electronic component (including the small chip component described later) for electrically connecting to the corresponding pad (or pad), and includes the above "terminal".

[0082] The LED driver 126 controls the light emission of the LED chips 127 to 142 connected to the first to eighth output terminals 155 to 162 based on the lighting control data received from the audio light emission control device 81. Two of the above-mentioned 16 LED chips 127 to 142 and one of the above-mentioned eight small chip resistors 87, 143 to 149 are electrically connected to each of the output terminals 155 to 162 of the LED driver 126. The small chip resistors 87, 143 to 149 are provided to limit the current flowing through the LED chips 127 to 142. By providing the small chip resistors 87, 143 to 149, the LED chips 127 to 142 can be driven below the allowable current.

[0083] FIG. 12(a) is a perspective view of the first mounting surface 84 side of the first decorative substrate 56 showing an enlarged view of the periphery of the bypass capacitor 85, and FIG. 12(b) is a perspective view of the first mounting surface 84 side of the first decorative substrate 56 showing an enlarged view of the periphery of the small chip resistor 87. As shown in FIG. 12(a), the bypass capacitor 85 is a surface mount type chip capacitor, specifically, a multilayer ceramic capacitor in which a large number of dielectrics and electrodes are stacked. The bypass capacitor 85 is substantially rectangular parallelepiped and includes a pair of metal first electrodes 85a and second electrodes 85b at both ends in the longitudinal direction.

[0084] The bypass capacitor 85 is a small chip component whose dimension in the longitudinal direction along a plane orthogonal to the thickness direction of the bypass capacitor 85 (hereinafter, also referred to as the "longitudinal direction of the bypass capacitor 85") is 0.1 mm or more and 0.9 mm or less. In this specification, a small chip component is an electronic component whose dimension in the longitudinal direction (hereinafter, also referred to as the "longitudinal direction of the small chip component") is 0.1 mm or more and 0.9 mm or less. Since the dimension of the small chip component in the longitudinal direction is 0.9 mm or less, the area occupied by the small chip component on the first decorative substrate 56 can be suppressed. Thereby, a wider area for mounting electronic components other than the small chip component on the first decorative substrate 56 can be secured. Also, electronic components mounted between the first decorative substrate 56 and a substrate with a high mounting density of electronic components can be made common as small chip components. Since the dimension of the small chip component in the longitudinal direction is 0.1 mm or more, it is possible to prevent the mechanical strength at the connection portion between the small chip component and the first decorative substrate 56 and the mechanical strength of the small chip component itself from decreasing too much. Here, the connection portion of the small chip component includes a pad electrically connected to the electrode of the small chip component, a solder fillet electrically connecting the electrode and the pad, and a wiring pattern drawn out from the pad. Since the dimension of the small chip component in the longitudinal direction is 0.1 mm or more, it is possible to prevent it from becoming difficult to visually confirm the presence or absence of mounting omission of the small chip component. The dimension of the small chip component in the longitudinal direction is preferably 0.3 mm or more and 0.8 mm or less. Since the dimension of the small chip component in the longitudinal direction is 0.8 mm or less, the area occupied by the small chip component on the first decorative substrate 56 can be reduced. Since the dimension of the small chip component in the longitudinal direction is 0.3 mm or more, the mechanical strength at the connection portion between the small chip component and the first decorative substrate 56 and the mechanical strength of the small chip component itself can be increased. Also, the process for confirming the presence or absence of mounting omission of the small chip component can be facilitated. The dimension of the small chip component in the longitudinal direction is more preferably 0.4 mm or more and 0.7 mm or less.Since the longitudinal dimension of the small chip component is 0.7 mm or less, the area occupied by the small chip component on the first decorative substrate 56 can be further reduced. Since the longitudinal dimension of the small chip component is 0.4 mm or more, the mechanical strength at the connection portion between the small chip component and the first decorative substrate 56 and the mechanical strength of the small chip component itself are increased, the possibility that the connection portion is damaged can be reduced, and the possibility that the small chip component itself is damaged can be reduced. Further, since the longitudinal dimension of the small chip component is 0.4 mm or more, the confirmation accuracy when visually checking the presence or absence of mounting omission of the small chip component can be increased.

[0085] The bypass capacitor 85 is a small chip component having a longitudinal dimension along a plane orthogonal to the thickness direction of approximately 0.6 mm, and a lateral dimension (hereinafter, also referred to as the "lateral direction") and a thickness dimension along a plane orthogonal to the thickness direction of approximately 0.3 mm. Since the longitudinal dimension of the bypass capacitor 85 is 0.7 mm or less, the area occupied by the bypass capacitor 85 on the first decorative substrate 56 can be reduced. Since the longitudinal dimension of the bypass capacitor 85 is 0.4 mm or more, the mechanical strength at the connection portion between the bypass capacitor 85 and the first decorative substrate 56 and the mechanical strength of the bypass capacitor 85 itself are increased, the possibility that the connection portion is damaged can be reduced, and the possibility that the bypass capacitor 85 itself is damaged can be reduced. Further, since the longitudinal dimension of the bypass capacitor 85 is 0.4 mm or more, the confirmation accuracy when visually checking the presence or absence of mounting omission of the bypass capacitor 85 can be increased. Note that the longitudinal dimension of the bypass capacitor 85 may be smaller than 0.6 mm (for example, a configuration of 0.4 mm), the lateral dimension of the bypass capacitor 85 may be smaller than 0.3 mm (for example, a configuration of 0.2 mm), and the thickness dimension may be smaller than 0.3 mm (for example, a configuration of 0.2 mm).

[0086] On the first decorative substrate 56, on the side of the first mounting surface 84, there are provided a first pad 171a (or first pat) corresponding to the first electrode 85a of the bypass capacitor 85 and a second pad 171b (or second pat) corresponding to the second electrode 85b. The first pad 171a and the second pad 171b form a pair. Two wiring patterns 172a and 172b are drawn out from the first pad 171a, and two wiring patterns 172c and 172d are drawn out from the second pad 171b. These pads 171a, 171b and the wiring patterns 172a to 172d are integrally formed by etching a single copper foil plate.

[0087] The bypass capacitor 85 is mounted on the side of the first mounting surface 84 of the first decorative substrate 56 by soldering the electrodes 85a, 85b to the corresponding pads 171a, 171b. On the first pad 171a, a solder fillet 173a for electrically connecting the first electrode 85a and the first pad 171a is formed, and on the second pad 171b, a solder fillet 173b for electrically connecting the second electrode 85b and the second pad 171b is formed. The solder fillets 173a, 173b are formed by heating the solder paste applied on the pads 171a, 171b to become molten solder and then cooling and solidifying it. In the longitudinal direction of the bypass capacitor 85, the first electrode 85a is fixed substantially at the center of the first pad 171a, and the second electrode 85b is fixed substantially at the center of the second pad 171b.

[0088] As shown in Fig. 8(b), the first wiring pattern 172a drawn from the first pad 171a connected to the first electrode 85a of the bypass capacitor 85 is electrically connected to the GND plane layer 93 (Fig. 9) through the via hole 174 provided in the first decorative substrate 56, and the second wiring pattern 172b drawn from the first pad 171a is electrically connected to the GND terminal 154 of the LED driver 126. Also, the third wiring pattern 172c drawn from the second pad 171b electrically connected to the second electrode 85b of the bypass capacitor 85 is electrically connected to the power supply plane layer 94 (Fig. 9) through the via hole 175 provided in the first decorative substrate 56, and the fourth wiring pattern 172d drawn from the second pad 171b is electrically connected to the power supply terminal 151 of the LED driver 126. Thus, the first pad 171a is disposed between the GND terminal 154 of the LED driver 126 and the GND plane layer 93, and the second pad 171b is disposed between the power supply terminal 151 of the LED driver 126 and the power supply plane layer 94.

[0089] The bypass capacitor 85 can accumulate electric charges, and reduces the peak portion of the noise components included in the driving power supply of the LED driver 126 by charging and reduces the valley portion of the noise components by discharging. Thus, the bypass capacitor 85 absorbs the noise components included in the driving power supply of the LED driver 126.

[0090] A bypass capacitor 85 is arranged between the power terminal 151 of the LED driver 126 and the power plane layer 94, which can reduce the influence of the noise components contained in the driving power supply supplied from the audio light emission control device 81 to the LED driver 126. As shown in FIG. 8(b), the bypass capacitor 85 is arranged close to the power terminal 151 so that there are no electronic components such as other ICs between the bypass capacitor 85 and the power terminal 151 of the LED driver 126. Thereby, the possibility that the noise components contained in the driving power supply supplied to the power terminal 151 of the LED driver 126 are absorbed by the bypass capacitor 85 can be increased, and the possibility that the LED driver 126 malfunctions due to the influence of the noise components can be reduced. Since there is no other IC between the bypass capacitor 85 and the power terminal 151, the noise components generated from the LED driver 126 can be absorbed by the bypass capacitor 85 to prevent the noise components from causing other ICs to malfunction. Also, since there are no other electronic components between the bypass capacitor 85 and the power terminal 151, the noise components generated from the LED driver 126 can be absorbed by the bypass capacitor 85 to prevent the noise components from causing other electronic components to malfunction.

[0091] As shown in Fig. 12(b), the small chip resistor 87 is substantially a rectangular parallelepiped like the bypass capacitor 85 (Fig. 12(a)), and is provided with a pair of metal first electrodes 87a and second electrodes 87b at both longitudinal ends. The small chip resistor 87 is a small chip component whose dimension in the longitudinal direction (hereinafter, also referred to as the "longitudinal direction of the small chip resistor 87") along the plane orthogonal to the thickness direction of the small chip resistor 87 is 0.1 mm or more and 0.9 mm or less. The small chip resistor 87 is a small chip component whose dimension in the longitudinal direction along the plane orthogonal to the thickness direction is approximately 0.6 mm, and whose dimensions in the short direction (hereinafter, also referred to as the "short direction") and the thickness direction along the plane orthogonal to the thickness direction are approximately 0.3 mm. Since the dimension in the longitudinal direction of the small chip resistor 87 is 0.7 mm or less, the area occupied by the small chip resistor 87 on the first decorative substrate 56 can be reduced. Since the dimension in the longitudinal direction of the small chip resistor 87 is 0.4 mm or more, the mechanical strength at the connection portion between the small chip resistor 87 and the first decorative substrate 56 and the mechanical strength of the small chip resistor 87 itself can be increased, the possibility that the connection portion is damaged can be reduced, and the possibility that the small chip resistor 87 itself is damaged can be reduced. Further, since the dimension in the longitudinal direction of the small chip resistor 87 is 0.4 mm or more, the confirmation accuracy when visually checking the presence or absence of mounting omission of the small chip resistor 87 can be increased. Note that the configuration in which the dimension in the longitudinal direction of the small chip resistor 87 is smaller than 0.6 mm (for example, the configuration of 0.4 mm) may be adopted, the configuration in which the dimension in the short direction of the small chip resistor 87 is smaller than 0.3 mm (for example, the configuration of 0.2 mm) may be adopted, and the configuration in which the dimension in the thickness direction is smaller than 0.3 mm (for example, the configuration of 0.2 mm) may be adopted.

[0092] On the first decorative substrate 56, on the side of the first mounting surface 84, there are provided a first pad 176a (or first pat) corresponding to the first electrode 87a of the small chip resistor 87 and a second pad 176b (or second pat) corresponding to the second electrode 87b. The first pad 176a and the second pad 176b are a pair. One wiring pattern 181a is drawn out from the first pad 176a, and one wiring pattern 181b is drawn out from the second pad 176b. These pads 176a, 176b and wiring patterns 181a, 181b are integrally formed by etching a single copper foil plate.

[0093] The small chip resistor 87 is mounted on the side of the first mounting surface 84 of the first decorative substrate 56 by soldering the electrodes 87a, 87b to the corresponding pads 176a, 176b. On the first pad 176a, a solder fillet 177a for electrically connecting the first electrode 87a and the first pad 176a is formed, and on the second pad 176b, a solder fillet 177b for electrically connecting the second electrode 87b and the second pad 176b is formed. The solder fillets 177a, 177b are formed by heating the solder paste applied on the pads 176a, 176b to become molten solder and then cooling and solidifying it. In the longitudinal direction of the small chip resistor 87, the first electrode 87a is fixed substantially at the center of the first pad 176a, and the second electrode 87b is fixed substantially at the center of the second pad 176b.

[0094] As shown in FIG. 8(c), the LED chip 142 is a surface-mount type chip component. The LED chip 142 is substantially a rectangular parallelepiped and has a pair of metal first electrodes 142a and second electrodes 142b at both ends in the longitudinal direction. Also, on the first decorative substrate 56, there are provided a copper first pad 178a (or first pat) corresponding to these first electrodes 142a and a copper second pad 178b (or second pat) corresponding to the second electrodes 142b. The first pad 178a and the second pad 178b are a pair.

[0095] The first wiring pattern 181a drawn from the first pad 176a of the small chip resistor 87 is electrically connected to the second pad 178b of the LED chip 142. Also, the second wiring pattern 181b drawn from the second pad 176b of the small chip resistor 87 is electrically connected to the eighth output terminal 162 of the LED driver 126.

[0096] As described above, electronic components such as connectors 111 to 115, LED driver 126, LED chips 127 to 142, bypass capacitors 85 and 97, and small chip resistors 87, 101, 143 to 149 are mounted on the decorative substrates 56 and 57. Among these electronic components, the outer dimensions of the small chip components (bypass capacitors 85 and 97 and small chip resistors 87, 101, 143 to 149) are smaller than those of the other electronic components, and the contact area between the electrodes of the small chip components and the pads (or pads) is smaller than the contact area between the electrodes and the pads (or pads) of the other electronic components. For this reason, the connection portions between the small chip components and the decorative substrates 56 and 57 among the various electronic components mounted on the decorative substrates 56 and 57 have lower mechanical strength compared to the connection portions between the other electronic components and the decorative substrates 56 and 57. In this specification, the connection portions between the small chip components and the decorative substrates 56 and 57 include pads electrically connected to the electrodes of the small chip components, solder fillets electrically connecting the electrodes of the small chip components and the pads, and wiring patterns drawn out from the pads. Specifically, the connection portion between the bypass capacitor 85 and the first decorative substrate 56 includes pads 171a and 171b electrically connected to the electrodes 85a and 85b of the bypass capacitor 85, solder fillets 173a and 173b electrically connecting the electrodes 85a and 85b of the bypass capacitor 85 and the pads 171a and 171b, and wiring patterns 172a to 172d drawn out from the pads 171a and 171b. Also, the connection portion between the small chip resistor 87 and the first decorative substrate 56 includes pads 176a and 176b electrically connected to the electrodes 87a and 87b of the small chip resistor 87, solder fillets 177a and 177b electrically connecting the electrodes 87a and 87b of the small chip resistor 87 and the pads 176a and 176b, and wiring patterns 181a and 181b drawn out from the pads 176a and 176b.

[0097] By using small chip components (bypass capacitors 85, 97 and small chip resistors 87, 101, 143 to 149) that are smaller than electronic components such as the LED driver 126 and the LED chips 127 to 142, it is possible to reduce the area occupied by capacitors and resistors on the decorative substrates 56 and 57. However, when distortion occurs in the decorative substrates 56 and 57, breakage is likely to occur at the connection points between the small chip components and the decorative substrates 56 and 57, and breakage of the small chip components themselves is also likely to occur, which poses a problem. In this specification, breakage at the connection points between the small chip components and the decorative substrates 56 and 57 includes breakage where a crack enters the solder fillet that electrically connects the electrodes of the small chip components to the pads (or pads), breakage where the solder fillet peels off, breakage where the pads peel off from the decorative substrates 56 and 57, and breakage where the wiring patterns around the pads peel off from the decorative substrates 56 and 57. Also, in this specification, breakage of the small chip components themselves includes breakage where a crack enters the small chip components and breakage where the internal structure of the small chip components (for example, the laminated structure of the bypass capacitors 85 and 97) is destroyed.

[0098] Examples of cases where distortion can occur in the decorative substrates 56 and 57 with small chip components mounted thereon include when the decorative substrates 56 and 57 are screwed to the front door frame 14, when a harness (not shown) is attached and detached to and from the connectors 111 to 115 mounted on the second mounting surface 95 of the decorative substrates 56 and 57, and when electronic components such as the LED driver 126 and the LED chips 127 to 142 mounted on the first decorative substrate 56 generate heat during use and thermal stress acts on the decorative substrates 56 and 57 due to the heat. Also, in a manufacturing method where after mounting electronic components including small chip components on an assembly substrate including a plurality of decorative substrates 56 and 57, the assembly substrate is divided to take out the plurality of decorative substrates 56 and 57, distortion can also occur in the decorative substrates 56 and 57 with small chip components mounted thereon when dividing the assembly substrate. In these cases, there is a possibility that bending stress acts on the decorative substrates 56 and 57, and there is also a possibility that torsional stress acts on the decorative substrates 56 and 57.

[0099] FIG. 13(a) is a plan view of the first mounting surface 84 of the first decorative substrate 56 showing an enlarged view of the peripheral region 182 (FIG. 8(b)) of the bypass capacitor 85, and FIG. 13(b) is an explanatory diagram for explaining the relationship between the pads 171a and 171b and the solder resist 222 in the peripheral region 182. Further, FIG. 13(c) is an explanatory diagram for explaining the movement mode of the bypass capacitor 85 that may occur in the present embodiment, and FIG. 13(d) is an explanatory diagram for explaining the movement mode of the bypass capacitor 85 that may occur in the comparative example. In FIG. 13(b), the solder resist 222 is shown with hatching.

[0100] As shown in FIG. 13(a), the first pad 171a and the second pad 171b corresponding to the first electrode 85a and the second electrode 85b of the bypass capacitor 85 are formed in a substantially rectangular shape. As shown in FIG. 13(b), the first pad 171a and the second pad 171b have the same shape and the same size as each other. The longitudinal dimension LA1 of the pads 171a and 171b is approximately 0.35 mm, which is larger than the dimension in the short side direction (approximately 0.3 mm) of the bypass capacitor 85. Since the pair of pads 171a and 171b have the same shape and the same size as each other, the amount of solder paste applied onto the pair of pads 171a and 171b can be made substantially the same. Note that the longitudinal dimension LA1 of the pads 171a and 171b may be the same as the dimension in the short side direction of the bypass capacitor 85, or the longitudinal dimension LA1 of the pads 171a and 171b may be smaller than the dimension in the short side direction of the bypass capacitor 85.

[0101] The lateral dimension LA2 of pads 171a and 171b is approximately 0.32 mm. The first pad 171a and the second pad 171b are provided at a predetermined interval LA3 (specifically, approximately 0.28 mm) in the longitudinal direction (the first direction DR1) of the bypass capacitor 85 (Fig. 13(a)). The distance (predetermined interval LA3) between the outer edge of the first pad 171a on the side of the second pad 171b and the outer edge of the second pad 171b on the side of the first pad 171a is set in the range of approximately 1 / 3 (0.2 mm) to approximately 1 / 2 (approximately 0.3 mm) of the dimension (approximately 0.6 mm) in the longitudinal direction of the bypass capacitor 85. Thereby, in the longitudinal direction of the bypass capacitor 85, the bypass capacitor 85 can be mounted on the first decorative substrate 56 in such a manner that the first electrode 85a of the bypass capacitor 85 is located approximately at the center of the first pad 171a and the second electrode 85b is located approximately at the center of the second pad 171b.

[0102] No solder resist 222 is applied between the first pad 171a and the second pad 171b. If the solder resist 222 is applied to the narrow region between the first pad 171a and the second pad 171b, the probability of defective products in which part or all of the pads 171a and 171b are covered by the solder resist 222 increases when there is a deviation in the application area of the solder resist 222 or the like. On the other hand, since the solder resist 222 is not applied between the first pad 171a and the second pad 171b, it is possible to prevent part or all of these pads 171a and 171b from being covered by the solder resist 222 and to attach solder paste to the entire area of these pads 171a and 171b. Thereby, it is possible to secure the connection area between the first pad 171a and the first electrode 85a and ensure the mechanical strength of the connection portion between the first pad 171a and the first electrode 85a, and at the same time, it is possible to secure the connection area between the second pad 171b and the second electrode 85b and ensure the mechanical strength of the connection portion between the second pad 171b and the second electrode 85b.

[0103] As shown in Fig. 13(a), since the pair of pads 171a and 171b are provided at a distance in the first direction DR1 which is the longitudinal direction of the bypass capacitor 85, when the first decorative substrate 56 is conveyed into the reflow furnace in the reflow process, by conveying the first decorative substrate 56 in the second direction DR2 orthogonal to the first direction DR1, the heating of the solder paste applied on the pair of pads 171a and 171b can be started substantially simultaneously.

[0104] The solder paste applied to the pads 171a and 171b is heated in the reflow furnace to become liquid molten solder. The molten solder floats and attracts the electrodes 85a and 85b of the bypass capacitor 85. The solder paste contains a flux component, and the molten solder flows on the pads 171a and 171b. Also, gas is released from the molten solder. If the solder paste melts earlier on one of the pair of pads 171a than on the other pad 171b, only one of the pair of electrodes 85a and 85b of the bypass capacitor 85, i.e., the electrode 85a, is in contact with the molten solder, and the balance of the forces acting on the electrodes 85a and 85b of the bypass capacitor 85 due to the surface tension of the molten solder is disrupted. Then, the rotation of the bypass capacitor 85 around the normal direction of the first decorative substrate 56 as the axis is likely to occur, and the so-called chip stand-up where the bypass capacitor 85 stands up substantially vertically on one of the pads 171a is likely to occur. Thus, when a difference occurs in the timing of melting of the solder paste between the pair of pads 171a and 171b, the rotation and chip stand-up of the bypass capacitor 85 are likely to occur. On the other hand, by conveying the first decorative substrate 56 in the second direction DR2 in the reflow process and starting the heating of the solder paste applied on the pair of pads 171a and 171b substantially simultaneously, the timing of melting of the solder paste between the pair of pads 171a and 171b can be made uniform, and the rotation and chip stand-up of the bypass capacitor 85 can be prevented.

[0105] As shown in FIG. 8(b), the bypass capacitor 85 is mounted on the first decorative substrate 56 in such a manner that the longitudinal direction of the bypass capacitor 85 is parallel to the first direction DR1. As shown in FIG. 8(c), the small chip resistor 87 is mounted on the first decorative substrate 56 in such a manner that the longitudinal direction of the small chip resistor 87 is parallel to the first direction DR1. Although not shown, the small chip resistors 143 to 149 are also mounted on the first decorative substrate 56 in such a manner that the longitudinal directions of the small chip resistors 143 to 149 are parallel to the first direction DR1. Thus, the small chip components (the bypass capacitor 85 and the small chip resistors 87, 143 to 149) are mounted on the first decorative substrate 56 in such a manner that the longitudinal directions of the small chip components are parallel to the first direction DR1.

[0106] As shown in FIGS. 8(b) and 8(c), the separation direction of the pads 171a and 171b corresponding to the electrodes 85a and 85b of the bypass capacitor 85, and the separation direction of the pads 176a and 176b corresponding to the electrodes 87a and 87b of the small chip resistor 87 are the first direction DR1. The separation directions of the pads 171a, 171b, 176a, and 176b are common among the plurality of small chip components. Therefore, by transporting the first decorative substrate 56 in a direction (the second direction DR2) perpendicular or substantially perpendicular to the common separation direction (the first direction DR1) in the reflow process, the timing at which the heating of the solder paste applied on the pair of pads 171a and 171b corresponding to the pair of electrodes 85a and 85b of the bypass capacitor 85 is started can be made uniform, and the timing at which the heating of the solder paste applied on the pair of pads 176a and 176b corresponding to the pair of electrodes 87a and 87b of the small chip resistor 87 is started can be made uniform. Thereby, the rotation and chip standing of the plurality of small chip components can be prevented.

[0107] At pads 171a and 171b corresponding to electrodes 85a and 85b of bypass capacitor 85, the locations where wiring patterns 172a to 172d are drawn out (the drawing positions of wiring patterns 172a to 172d) are prone to heat escaping to wiring patterns 172a to 172d. Therefore, compared with the locations where wiring patterns 172a to 172d are not drawn out, the temperature rise in the initial stage of the heating in the reflow process is likely to be delayed. Also, the first wiring pattern 172a and the third wiring pattern 172c connected to the GND plane layer 93 or the power supply plane layer 94, which have a larger area compared with pads 171a and 171b, have a slower temperature rise in the initial stage of heating compared with the second wiring pattern 172b and the fourth wiring pattern 172d not connected to the GND plane layer 93 or the power supply plane layer 94. For this reason, at the location where the first wiring pattern 172a connected to the GND plane layer 93 is drawn out in the first pad 171a, the temperature rise in the initial stage of heating is likely to be delayed compared with the location where the second wiring pattern 172b is drawn out. Also, at the location where the third wiring pattern 172c connected to the power supply plane layer 94 is drawn out in the second pad 171b, the temperature rise in the initial stage of heating is likely to be delayed compared with the location where the fourth wiring pattern 172d is drawn out. In the reflow process, the temperature distribution within pads 171a and 171b in the initial stage of heating changes under the influence of the number, drawing positions, and connection destinations of wiring patterns 172a to 172d drawn out from the pair of pads 171a and 171b. Also, the drawing directions of wiring patterns 172a to 172d drawn out from the pair of pads 171a and 171b may also affect the temperature distribution within pads 171a and 171b in the initial stage of heating. Although details will be described later, in the first decorative substrate 56 in this embodiment, the number, drawing positions, connection destinations, and drawing directions of wiring patterns 172a to 172d drawn out from the pair of pads 171a and 171b are set so that there is no difference in the temperature distribution within pads 171a and 171b in the initial stage of heating between the pair of pads 171a and 171b.

[0108] As shown in FIG. 13(d), in the bypass capacitor 183 in the comparative example, a first wiring pattern 185a is drawn out from the right end of the first pad 184a (or the first pat) toward the right, and a second wiring pattern 185b is drawn out from the left end of the first pad 184a toward the left. The first wiring pattern 185a in the comparative example is a wiring pattern that is electrically connected to the GND plane layer 93 (FIG. 9) via a via hole 174, similar to the first wiring pattern 172a of the present embodiment already described. The second wiring pattern 185b in the comparative example is a wiring pattern that is electrically connected to the GND terminal 154 of the LED driver 126, similar to the second wiring pattern 172b in the present embodiment already described. Further, a third wiring pattern 185c is drawn out from the lower end of the second pad 184b (or the second pat) downward, and a fourth wiring pattern 185d is drawn out from the left end of the second pad 184b toward the left. The third wiring pattern 185c in the comparative example is a wiring pattern that is electrically connected to the power plane layer 94 (FIG. 9) via a via hole 175, similar to the third wiring pattern 172c of the present embodiment already described. The fourth wiring pattern 172d in the comparative example is a wiring pattern that is electrically connected to the power terminal 151 of the LED driver 126, similar to the fourth wiring pattern 172d of the present embodiment already described. At the first pad 184a, the locations where the first wiring pattern 185a and the second wiring pattern 185b are drawn out (the right end portion and the left end portion of the first pad 184a) are likely to have a delayed temperature rise in the initial stage of heating. In particular, the temperature rise at the location where the first wiring pattern 185a connected to the GND plane layer 93 is drawn out (the left end portion of the first pad 184a) is likely to be delayed. Also, at the second pad 184b, the locations where the third wiring pattern 185c and the fourth wiring pattern 185d are drawn out (the lower end portion and the left end portion of the second pad 184b) are likely to have a delayed temperature rise in the initial stage of heating. In particular, the temperature rise at the location where the third wiring pattern 185c connected to the power plane layer 94 is drawn out (the lower end portion of the second pad 184b) is likely to be delayed. For this reason, in the initial stage of heating in the reflow process, the temperature of the upper right side of the second pad 184b is likely to rise.When the solder paste melts only at the upper right part of the second pad 184b, as shown in FIG. 13(d), the upper right part of the second pad 184b becomes the center of rotation, and the bypass capacitor 183 rotates with the normal direction of the first decorative substrate 56 as the rotation axis, and there is a possibility that the bypass capacitor 183 may be mounted on the first decorative substrate 56 in an inclined state. In this case, since the connection area by the solder fillet 186 between the first pad 184a and the first electrode 183a becomes small, there is a possibility of causing a connection failure. Also, due to the rotation of the bypass capacitor 183, there is a possibility that the bypass capacitor 183 may be mounted in a state where the first pad 184a and the first electrode 183a are not in electrical contact. Furthermore, chip standing is likely to occur in which the bypass capacitor 183 rises on the first pad 184a with only one electrode 183a. Thus, in the comparative example where the extraction positions of the wiring patterns 185a to 185d drawn from the first pad 184a and the second pad 184b are different, mounting failures of the bypass capacitor 183 are likely to occur.

[0109] In contrast, in the first decorative substrate 56 of the present embodiment, as shown in FIG. 13(a), the first wiring pattern 172a is drawn out from the first pad 171a in the right direction, and the third wiring pattern 172c is drawn out from the second pad 171b in the right direction. Also, the second wiring pattern 172b is drawn out from the first pad 171a in the left direction, and the fourth wiring pattern 172d is drawn out from the second pad 171b in the left direction. In a configuration where the same number (specifically, two) of wiring patterns 172a to 172d are drawn out from the first pad 171a and the second pad 171b, the direction (right direction) in which the side of the first pad 171a from which the first wiring pattern 172a is drawn out exists when viewed from the center of the first pad 171a is the same as the direction (right direction) in which the side of the second pad 171b from which the third wiring pattern 172c is drawn out exists when viewed from the center of the second pad 171b, and the direction (left direction) in which the side of the first pad 171a from which the second wiring pattern 172b is drawn out exists when viewed from the center of the first pad 171a is the same as the direction (left direction) in which the side of the second pad 171b from which the fourth wiring pattern 172d is drawn out exists when viewed from the center of the second pad 171b. Thereby, in the initial stage of heating in the reflow process, it is possible to prevent a difference in the temperature distribution within the pair of pads 171a and 171b, and it is also possible to prevent the rotation of the bypass capacitor 85 and the occurrence of chip standing.

[0110] A plurality of capacitors (not shown) having a longitudinal dimension along a plane orthogonal to the thickness direction greater than that of small chip components are mounted on the first decorative substrate 56. In some of these capacitors, the side of the first pad (or first pad) where the first wiring pattern is drawn out as viewed from the center of the first pad electrically connected to the first electrode of the capacitor is different from the direction in which the side of the second pad (second pad) where the third wiring pattern is drawn out as viewed from the center of the second pad electrically connected to the second electrode of the capacitor exists. In the bypass capacitor 85 which is a small chip component, the direction in which the side of the first pad 171a where the first wiring pattern 172a is drawn out as viewed from the center of the first pad 171a is the same as the direction in which the side of the second pad 171b where the third wiring pattern 172c is drawn out as viewed from the center of the second pad 171b, and the direction in which the side of the first pad 171a where the second wiring pattern 172b is drawn out as viewed from the center of the first pad 171a is the same as the direction (left direction) in which the side of the second pad 171b where the fourth wiring pattern 172d is drawn out as viewed from the center of the second pad 171b, thereby preventing the rotation and chip standing of the bypass capacitor 85.

[0111] As shown in FIG. 8(b), in the first pad 171a, the drawing position of the first wiring pattern 172a electrically connected to the GND plane layer 93 (FIG. 9) via the via hole 174 is approximately at the center in the vertical direction at the right end of the first pad 171a, and in the second pad 171b, the drawing position of the third wiring pattern 172c electrically connected to the power supply plane layer 94 (FIG. 9) via the via hole 175 is approximately at the center in the vertical direction at the right end of the second pad 171b. The GND plane layer 93 has a larger area than the first pad 171a, and the power supply plane layer 94 has a larger area than the second pad 171b.

[0112] The first pad 171a is electrically connected to a GND plane layer 93 having an area larger than that of the first pad 171a via a first wiring pattern 172a, and the second pad 171b is electrically connected to a power supply plane layer 94 having an area larger than that of the second pad 171b via a third wiring pattern 172c. In this configuration, the direction (right direction) in which the first wiring pattern 172a is drawn out from the center of the first pad 171a among the four sides of the first pad 171a is the same as the direction (right direction) in which the third wiring pattern 172c is drawn out from the center of the second pad 171b among the four sides of the second pad 171b. As a result, the possibility of a difference in the temperature distribution within the pair of pads 171a and 171b is reduced at the initial stage of heating in the reflow process.

[0113] As shown in FIG. 13(a), the width dimension of the first wiring pattern 172a drawn out rightward from the right end of the first pad 171a is substantially the same as the width dimension of the third wiring pattern 172c drawn out rightward from the right end of the second pad 171b. For this reason, compared with a configuration in which the width dimensions of these wiring patterns 172a and 172c are different, the possibility of a difference in the temperature distribution within the pair of pads 171a and 171b is reduced at the initial stage of heating in the reflow process. Also, the width dimension of the second wiring pattern 172b drawn out leftward from the left end of the first pad 171a is substantially the same as the width dimension of the fourth wiring pattern 172d drawn out leftward from the left end of the second pad 171b. For this reason, compared with a configuration in which the width dimensions of these wiring patterns 172b and 172d are different, the possibility of a difference in the temperature distribution within the pair of pads 171a and 171b is reduced at the initial stage of heating in the reflow process.

[0114] As described above, since the first wiring pattern 172a electrically connected to the GND plane layer 93 is drawn out from the right end of the first pad 171a, the right side of the first pad 171a is more likely to have a slower temperature rise than the left side of the first pad 171a in the initial heating stage. Also, since the third wiring pattern 172c connected to the power supply plane layer 94 is drawn out from the right end of the second pad 171b, the right side of the second pad 171b is more likely to have a slower temperature rise than the left side of the second pad 171b in the initial heating stage. The number of wiring patterns 172a, 172c drawn out from the first pad 171a is the same as the number of wiring patterns 172b, 172d drawn out from the second pad 171b. Also, the direction in which the side from which the first wiring pattern 172a is drawn out exists among the four sides of the first pad 171a when viewed from the center of the first pad 171a is the same direction as the direction in which the side from which the third wiring pattern 172c is drawn out exists among the four sides of the second pad 171b when viewed from the center of the second pad 171b, and the direction in which the side from which the second wiring pattern 172b is drawn out exists among the four sides of the first pad 171a when viewed from the center of the first pad 171a is the same direction as the direction in which the side from which the fourth wiring pattern 172d is drawn out exists among the four sides of the second pad 171b when viewed from the center of the second pad 171b. Thereby, the force acting on the first electrode 85a of the bypass capacitor 85 due to the surface tension of the molten solder on the first pad 171a and the force acting on the second electrode 85b of the bypass capacitor 85 due to the surface tension of the molten solder on the second pad 171b can be balanced. For this reason, even if only the left side portion of the solder paste melts first in the pair of pads 171a, 171b, as shown in FIG. 13(c), the movement mode of the bypass capacitor 85 can be made a parallel movement, and the rotation of the bypass capacitor 85 can be prevented. Thereby, the degree of reduction in the connection area due to the solder fillet 173a between the first pad 171a and the first electrode 85a can be suppressed, and the degree of reduction in the connection area due to the solder fillet 173b between the second pad 171b and the second electrode 85b can be suppressed.

[0115] FIG. 14(a) is a plan view of a first mounting surface 84 of a first decorative substrate 56 showing an enlarged peripheral region 187 (FIG. 8(c)) of a small chip resistor 87, and FIG. 14(b) is an explanatory diagram for explaining the relationship between pads 176a and 176b of the peripheral region 187 and a solder resist 222. Further, FIG. 14(c) is an explanatory diagram for explaining a movement mode of the small chip resistor 87 that may occur in the present embodiment, and FIG. 14(d) is an explanatory diagram for explaining a movement mode of a small chip resistor 191 that may occur in a comparative example. Note that in FIG. 14(b), the solder resist 222 is shown with hatching.

[0116] As shown in FIG. 14(a), first pads 176a and second pads 176b corresponding to a first electrode 87a and a second electrode 87b of the small chip resistor 87 are formed in a substantially rectangular shape. As shown in FIG. 14(b), the first pads 176a and the second pads 176b have the same shape and the same size as each other. A vertical dimension LB1 of the pads 176a and 176b is approximately 0.35 mm, which is larger than a dimension in the short side direction (approximately 0.3 mm) of the small chip resistor 87. Since the pair of pads 176a and 176b have the same shape and the same size as each other, the amount of solder paste applied onto the pair of pads 176a and 176b can be made substantially the same. Note that the configuration may be such that the vertical dimension LB1 of the pads 176a and 176b is the same as the dimension in the short side direction of the small chip resistor 87, or the configuration may be such that the vertical dimension LB1 of the pads 176a and 176b is smaller than the dimension in the short side direction of the small chip resistor 87.

[0117] The lateral dimension LB2 of the pads 176a and 176b is approximately 0.32 mm. The first pad 176a and the second pad 176b are provided at a predetermined interval LB3 (specifically, approximately 0.28 mm) in the longitudinal direction (the first direction DR1) of the small chip resistor 87 (Fig. 14(a)). The distance (predetermined interval LB3) between the outer edge of the first pad 176a on the side of the second pad 176b and the outer edge of the second pad 176b on the side of the first pad 176a is set in the range of approximately 1 / 3 (0.2 mm) to approximately 1 / 2 (approximately 0.3 mm) of the dimension (approximately 0.6 mm) in the longitudinal direction of the small chip resistor 87. Thereby, in the longitudinal direction of the small chip resistor 87, the small chip resistor 87 can be mounted on the first decorative substrate 56 in such a manner that the first electrode 87a of the small chip resistor 87 is located approximately at the center of the first pad 176a and the second electrode 87b is located approximately at the center of the second pad 176b.

[0118] No solder resist 222 is applied between the first pad 176a and the second pad 176b. If the solder resist 222 is applied to the narrow region between the first pad 176a and the second pad 176b, the probability of defective products in which part or all of the pads 176a and 176b are covered by the solder resist 222 increases when there is a shift in the application area of the solder resist 222 or the like. On the other hand, since the solder resist 222 is not applied between the first pad 176a and the second pad 176b, it is possible to prevent part or all of these pads 176a and 176b from being covered by the solder resist 222 and to attach solder paste to the entire area of these pads 176a and 176b. Thereby, it is possible to secure the connection area between the first pad 176a and the first electrode 87a and to secure the mechanical strength of the connection portion between the first pad 176a and the first electrode 87a, and at the same time, it is possible to secure the connection area between the second pad 176b and the second electrode 87b and to secure the mechanical strength of the connection portion between the second pad 176b and the second electrode 87b.

[0119] As shown in Fig. 14(d), in the small chip resistor 191 in the comparative example, the first wiring pattern 193a is drawn out from the right end of the first pad 192a (or the first pat) toward the right, and the second wiring pattern 193b is drawn out from the left end of the second pad 192b (or the second pat) toward the left. The first wiring pattern 193a in the comparative example is a wiring pattern that is electrically connected to the second electrode 142b (Fig. 8(c)) of the LED chip 142, similar to the first wiring pattern 181a of the present embodiment already described. The second wiring pattern 193b in the comparative example is a wiring pattern that is electrically connected to the eighth output terminal 162 of the LED driver 126, similar to the second wiring pattern 181b in the present embodiment already described. The right side of the first pad 192a from which the first wiring pattern 193a is drawn out is likely to have a slower temperature rise in the initial stage of heating in the reflow process compared to the left side where no wiring pattern is drawn out. Also, the left side of the second pad 192b from which the second wiring pattern 193b is drawn out is likely to have a slower temperature rise in the initial stage of heating compared to the right side where no wiring pattern is drawn out. For this reason, in the initial stage of heating, a state is likely to occur where only the left side portion of the solder paste on the first pad 192a and only the right side portion of the solder paste on the second pad 192b are melted. As shown in Fig. 14(d), the small chip resistor 191 may rotate with the normal direction of the first decorative substrate 56 as the rotation axis, and there is a possibility that the small chip resistor 191 may be mounted on the first decorative substrate 56 in a tilted state. When the small chip resistor 191 is mounted in a tilted state, the connection area by the solder fillets 194 between the first pad 184a and the first electrode 183a becomes smaller, and the connection area by the solder fillets 195 between the second pad 184b and the second electrode 183b also becomes smaller. Also, there is a possibility that the small chip resistor 191 may be mounted in a state where the first pad 192a and the first electrode 191a are not in electrical contact due to the rotation of the small chip resistor 191. Furthermore, chip standing is likely to occur where the small chip resistor 191 rises on the first pad 192a with one electrode 191a.Thus, in the comparative example in which the lead-out positions of the wiring patterns 193a and 193b are different in the pair of pads 192a and 192b, defective mounting of the small chip resistor 191 is likely to occur.

[0120] On the other hand, in the first decorative substrate 56 in the present embodiment, as shown in FIG. 14(a), the first wiring pattern 181a is led out from the right end of the first pad 176a toward the right, and the second wiring pattern 181b is led out from the right end of the second pad 176b toward the right. The lead-out position of the first wiring pattern 181a is approximately at the center in the vertical direction at the right end of the first pad 176a, and the lead-out position of the second wiring pattern 181b is approximately at the center in the vertical direction at the right end of the second pad 176b. In the configuration in which the same number (specifically, one) of wiring patterns 181a and 181b are led out from the first pad 176a and the second pad 176b, the direction (right direction) in which the side from which the first wiring pattern 181a is led out exists among the four sides of the first pad 176a when viewed from the center of the first pad 176a is the same as the direction (right direction) in which the side from which the second wiring pattern 181b is led out exists among the four sides of the second pad 176b when viewed from the center of the second pad 176b. Thereby, it is possible to prevent a difference in the temperature distribution within the pair of pads 176a and 176b in the initial stage of heating in the reflow process, and it is possible to prevent rotation and chip standing of the small chip resistor 87.

[0121] A plurality of resistors (not shown) having a longitudinal dimension along a plane orthogonal to the thickness direction larger than that of small chip components are mounted on the first decorative substrate 56. Among these resistors, in some of them, the direction in which the side from which the first wiring pattern is drawn out among the four sides of the first pad (or first pat) electrically connected to the first electrode of the resistor is present, as viewed from the center of the first pad, is different from the direction in which the side from which the second wiring pattern is drawn out among the four sides of the second pad (or second pat) electrically connected to the second electrode of the resistor is present, as viewed from the center of the second pad. In the small chip resistor 87 which is a small chip component, by making the direction in which the side from which the first wiring pattern 181a is drawn out among the four sides of the first pad 176a is present, as viewed from the center of the first pad 176a, the same as the direction in which the side from which the second wiring pattern 181b is drawn out among the four sides of the second pad 176b is present, as viewed from the center of the second pad 176b, the occurrence of rotation and chip standing of the small chip resistor 87 is prevented.

[0122] Since the right end of the first pad 176a is the extraction position of the first wiring pattern 181a, the temperature rise in the initial heating stage is likely to be slower than that at the left end of the first pad 176a. Also, since the right end of the second pad 176b is the extraction position of the second wiring pattern 181b, the temperature rise in the initial heating stage is likely to be slower than that at the left end of the second pad 176b. The number of wiring patterns 181a drawn from the first pad 176a is the same as the number of wiring patterns 181b drawn from the second pad 176b. The direction (right direction) in which the first wiring pattern 181a is drawn from one of the four sides of the first pad 176a when viewed from the center of the first pad 176a is the same direction as the direction in which the second wiring pattern 181b is drawn from one of the four sides of the second pad 176b when viewed from the center of the second pad 176b. Thereby, the force acting on the first electrode 87a of the small chip resistor 87 due to the surface tension of the molten solder on the first pad 176a and the force acting on the second electrode 87b of the small chip resistor 87 due to the surface tension of the molten solder on the second pad 176b can be balanced. For this reason, even if only the left side portions in the solder paste of the pair of first pads 176a and second pads 176b are melted first, as shown in FIG. 14(c), the movement mode of the small chip resistor 87 can be made a parallel movement and the rotation of the small chip resistor 87 can be prevented. Thereby, the degree of reduction in the connection area due to the solder fillet 177a between the first pad 176a and the first electrode 87a can be suppressed, and the degree of reduction in the connection area due to the solder fillet 177b between the second pad 176b and the second electrode 87b can be suppressed.

[0123] As already described, the first pad 176a electrically connected to the first electrode 87a of the small chip resistor 87 is electrically connected to the second pad 178b electrically connected to the second electrode 142b of the LED chip 142 via the first wiring pattern 181a (see FIG. 8(c)). Also, as already described, the second pad 176b electrically connected to the second electrode 87b of the small chip resistor 87 is electrically connected to a pad (or pad, not shown) electrically connected to the eighth output terminal 162 (FIG. 11) of the LED driver 126 (FIG. 8(a)) via the second wiring pattern 181b. As shown in FIGS. 8(a) and 8(c), the second pad 178b as the connection destination seen from the first pad 176a is present upward, and the pad (or pad, not shown) corresponding to the eighth output terminal 162 as the connection destination seen from the second pad 176b is present in the upper left direction. The location where the second wiring pattern 181b is connected to the pad (not shown) corresponding to the eighth output terminal 162 is in the direction of the axis (the second direction DR2 in FIGS. 8(a) and 8(c)) including the drawing direction of the second wiring pattern 181b from the second pad 176b (the right direction in FIGS. 8(a) and 8(c)), and is present in the direction opposite to the drawing direction of the second wiring pattern 181b from the second pad 176b with reference to the second pad 176b. The second wiring pattern 181b is drawn from the second pad 176b in the same direction (right direction) as the drawing direction of the first wiring pattern 181a from the first pad 176a, and is then routed to the opposite side with reference to the second pad 176b when viewed in the direction of the axis (the second direction DR2).

[0124] Even in a configuration where the second wiring pattern 181b is connected to a connection destination at a location that exists in the direction opposite to the drawing-out direction of the second wiring pattern 181b from the second pad 176b with reference to the second pad 176b when viewed in the direction of one axis (second direction DR2), the second wiring pattern 181b is drawn from the second pad 176b in the same direction as the drawing-out direction of the first wiring pattern 181a from the first pad 176a. Thereby, it is possible to reduce the possibility that a difference occurs in the temperature distribution within the pair of first pads 176a and second pads 176b in the initial stage of heating in the reflow process.

[0125] As shown in FIG. 14(a), the width dimension of the first wiring pattern 181a drawn rightward from the right end of the first pad 176a is substantially the same as the width dimension of the second wiring pattern 181 drawn rightward from the right end of the second pad 176b. For this reason, compared with a configuration in which the width dimensions of the wiring patterns 181a and 181b drawn from the pads 176a and 176b are different, the possibility that a difference occurs in the temperature distribution within the pair of pads 176a and 176b in the initial stage of heating in the reflow process is reduced.

[0126] As already described with reference to FIGS. 8(a) to 8(c), in the first decorative substrate 56, the small chip component is mounted on the first decorative substrate 56 in such a manner that the longitudinal direction of the small chip component is parallel to the first direction DR1 (the longitudinal direction of the first decorative substrate 56). For this reason, compared with the case where the small chip component is mounted on the first decorative substrate 56 in such a manner that the longitudinal direction of the small chip component is orthogonal to the first direction DR1 (the longitudinal direction of the first decorative substrate 56), when distortion occurs in the first decorative substrate 56, the maximum value of the stress that can act on the connection portion between the small chip component and the first decorative substrate 56 is reduced, and the maximum value of the stress that can act on the small chip component itself is reduced.

[0127] As described above, a plurality of capacitors (not shown) having a longitudinal dimension along a plane orthogonal to the thickness direction larger than that of the small chip components are mounted on the first decorative substrate 56. Some of these capacitors are mounted on the first decorative substrate 56 in a manner such that the longitudinal direction of the capacitor is not parallel to the first direction DR1. The small chip components are protected by being mounted on the first decorative substrate 56 in a manner such that the longitudinal direction of the small chip component is orthogonal to the first direction DR1.

[0128] As shown in FIG. 10(b), the bypass capacitor 97 is mounted on the second decorative substrate 57 in a manner such that the longitudinal direction of the bypass capacitor 97 is parallel to the major axis direction LD of the second decorative substrate 57. Further, as shown in FIG. 10(c), the small chip resistor 101 is mounted on the second decorative substrate 57 in a manner such that the longitudinal direction of the small chip resistor 101 is parallel to the major axis direction LD of the second decorative substrate 57. Thus, since the small chip components (the bypass capacitor 97 and the small chip resistor 101) are mounted on the second decorative substrate 57 in a manner such that the longitudinal direction of the small chip component is parallel to the major axis direction LD of the second decorative substrate 57, compared with the case where the small chip component is mounted on the second decorative substrate 57 in a manner such that the longitudinal direction of the small chip component is orthogonal to the major axis direction LD of the second decorative substrate 57, when distortion occurs in the second decorative substrate 57, the maximum value of the stress that can act on the connection portion between the small chip component and the second decorative substrate 57 is reduced, and the maximum value of the stress that can act on the small chip component itself is reduced.

[0129] As shown in FIG. 8(b), in the first decorative substrate 56, the first wiring pattern 172a drawn from the first pad 171a and the third wiring pattern 172c drawn from the second pad 171b extend in a direction orthogonal to the longitudinal direction of the bypass capacitor 85 (one of the short-side directions of the bypass capacitor 85). Also, the second wiring pattern 172b drawn from the first pad 171a and the fourth wiring pattern 172d drawn from the second pad 171b extend in a direction orthogonal to the longitudinal direction of the bypass capacitor 85 (the other short-side direction of the bypass capacitor 85). Thus, the wiring patterns 172a to 172d drawn from the pads 171a and 171b of the bypass capacitor 85 extend in a direction orthogonal to the longitudinal direction of the bypass capacitor 85 (the short-side direction). Note that the wiring patterns 172a to 172d drawn from the pads 171a and 171b of the bypass capacitor 85 may be configured to extend in a direction substantially orthogonal to the longitudinal direction of the bypass capacitor 85.

[0130] As described above, the pads 171a and 171b and the wiring patterns 172a to 172d are integrally formed, and the electrodes 85a and 85b of the bypass capacitor 85 are fixed to the pads 171a and 171b by solder fillets 173a and 173b. If the wiring patterns 172a to 172d drawn from the pads 171a and 171b extend in a direction parallel to the longitudinal direction of the bypass capacitor 85, when a force is applied to the first decorative substrate 56 to bend the first decorative substrate 56 about a fold line extending in a direction orthogonal or substantially orthogonal to the longitudinal direction, breakage is likely to occur at the connection portion between the bypass capacitor 85 and the first decorative substrate 56, and breakage of the bypass capacitor 85 itself is also likely to occur. Further, in this configuration, stress acting on the periphery of the bypass capacitor 85 due to distortion of the first decorative substrate 56 is likely to be transmitted to the bypass capacitor 85 itself, and breakage of the bypass capacitor 85 is likely to occur. On the other hand, by configuring the wiring patterns 172a to 172d drawn from the pads 171a and 171b to extend in a direction orthogonal or substantially orthogonal to the longitudinal direction of the bypass capacitor 85, the maximum value of the stress that can act on the connection portion between the bypass capacitor 85 and the first decorative substrate 56 when distortion occurs in the first decorative substrate 56 is reduced, and the maximum value of the stress that can act on the bypass capacitor 85 itself when distortion occurs in the first decorative substrate 56 is reduced. Thereby, breakage at the connection portion between the bypass capacitor 85 and the first decorative substrate 56 can be prevented, and breakage of the bypass capacitor 85 itself can be prevented.

[0131] As described above, a plurality of capacitors (not shown) having a longitudinal dimension larger than that of small chip components along a plane orthogonal to the thickness direction are mounted on the first decorative substrate 56. For some of these capacitors, the drawing direction of the wiring pattern drawn from pads (or pads) electrically connected to the electrodes of the capacitor is drawn in a direction different from the direction orthogonal to and substantially orthogonal to the longitudinal direction of the capacitor. The bypass capacitor 85, which is a small chip component, is protected by configuring the wiring patterns 172a to 172d drawn from the pads 171a and 171b to extend in a direction orthogonal to or substantially orthogonal to the longitudinal direction of the bypass capacitor 85.

[0132] As already described, the wiring patterns 181a and 181b drawn from the pads 176a and 176b of the small chip resistor 87 extend in a second direction DR2 (the short side direction of the small chip resistor 87) orthogonal to the longitudinal direction of the small chip resistor 87. Also, as already described, the small chip resistor 87 is electrically connected to the wiring patterns 181a and 181b by solder fillets 177a and 177b that electrically contact the electrodes 87a and 87b with the pads 176a and 176b. If the wiring patterns 181a and 181b drawn from the pads 176a and 176b extend in a direction parallel to the longitudinal direction of the small chip resistor 87, the stress acting on the periphery of the bypass capacitor 85 due to the distortion of the first decorative substrate 56 is likely to be transmitted to the bypass capacitor 85 itself, and the bypass capacitor 85 is likely to be damaged. On the other hand, by configuring the wiring patterns 181a and 181b drawn from the pads 176a and 176b of the small chip resistor 87 to extend in a direction orthogonal to (the short side direction of the small chip resistor 87) or substantially orthogonal to the longitudinal direction of the small chip resistor 87, the maximum value of the stress that can act on the small chip resistor 87 can be reduced. Thereby, when distortion occurs in the first decorative substrate 56, it is possible to prevent damage to the connection portion between the small chip resistor 87 and the first decorative substrate 56.

[0133] As described above, a plurality of resistors (not shown) having a longitudinal dimension along a plane orthogonal to the thickness direction larger than that of small chip components are mounted on the first decorative substrate 56. In some of these resistors, the wiring pattern drawn out from the pad (or pad) electrically connected to the electrode of the resistor is drawn out in a direction different from the direction orthogonal to and substantially orthogonal to the longitudinal direction of the resistor. The small chip resistor 87, which is a small chip component, is protected by forming the wiring patterns 181a and 181b drawn out from the pads 176a and 176b so as to extend in a direction orthogonal to or substantially orthogonal to the longitudinal direction of the small chip resistor 87.

[0134] As shown in FIGS. 8(a) to 8(c), in the first decorative substrate 56, the small chip components (bypass capacitor 85 and small chip resistors 87, 143 to 149 (FIG. 11)) are mounted only on the first mounting surface 84 side and not on the second mounting surface 95 side. In the configuration in which the small chip components are aggregated on the first mounting surface 84 side of the first decorative substrate 56, the LED chips 127 to 142 (FIG. 11) and the LED driver 126 are also mounted on the first mounting surface 84.

[0135] FIG. 15(a) is a plan view showing the second mounting surface 95 of the first decorative substrate 56, and FIG. 15(b) is a plan view of the second mounting surface 95 of the first decorative substrate 56 showing an enlarged backside region 205 of the first light-emitting circuit portion 121. As shown in FIG. 15(b), small chip components are not mounted in the LED backside corresponding region 201 of the second mounting surface 95. The LED backside corresponding region 201 is a region of the second mounting surface 95 that is located on the backside of the region where the LED chips 127 to 142 (FIG. 9) are mounted on the first mounting surface 84 (FIG. 8(a)) and a region within a distance of 1 mm from the outer edge of the region of the second mounting surface 95. Since small chip components are not mounted in the region of the second mounting surface 95 that is located on the backside of the region where the LED chips 127 to 142 are mounted on the first mounting surface 84, the influence of the thermal stress that can act on the first decorative substrate 56 due to the heat generation of the LED chips 127 to 142 on the small chip components is reduced. The LED backside corresponding region 201 is a region that is repeatedly heated by the heat generated during the driving of the LED chips 127 to 142, and is a region where distortion due to the heat of the first decorative substrate 56 is likely to occur. If small chip components are mounted in the LED backside corresponding region 201, there is a risk that the load of thermal stress accumulates at the connection point between the small chip components and the first decorative substrate 56 due to the repeated execution of the light-emitting effect on the first decorative substrate 56, and there is also a risk that the load of thermal stress accumulates on the small chip components themselves. On the other hand, since the small chip components are mounted avoiding the LED backside corresponding region 201, it is possible to prevent the connection point between the small chip components and the first decorative substrate 56 from being damaged due to the repeated execution of the light-emitting effect on the first decorative substrate 56, and it is possible to prevent the small chip components themselves from being damaged.

[0136] As shown in FIG. 15(b), no small chip component is mounted on the driver back side corresponding region 202 of the second mounting surface 95. The driver back side corresponding region 202 is a region of the second mounting surface 95 that is located on the back side of the region where the LED driver 126 (FIG. 8(a)) is mounted on the first mounting surface 84 (FIG. 8(a)) and the region where pads (or pads) corresponding to the terminals of the LED driver 126 are provided, and a region within 1 mm from the outer edge of the region of the second mounting surface 95. Since no small chip component is mounted on the region of the second mounting surface 95 that is located on the back side of the region where the LED driver 126 is mounted on the first mounting surface 84, the influence of the thermal stress that can act on the first decorative substrate 56 due to the heat generation of the LED driver 126 on the small chip component is reduced. The driver back side corresponding region 202 is a region that is repeatedly heated by the heat generated during the driving of the LED driver 126, and is a region where distortion due to the heat of the first decorative substrate 56 is likely to occur. If a small chip component is mounted on the driver back side corresponding region 202, there is a risk that a thermal stress load will accumulate at the connection point between the small chip component and the first decorative substrate 56 due to the repeated execution of the light emission effect on the first decorative substrate 56, and there is also a risk that a thermal stress load will accumulate on the small chip component itself. On the other hand, since the small chip component is mounted avoiding the driver back side corresponding region 202, it is possible to prevent the connection point between the small chip component and the first decorative substrate 56 from being damaged and the small chip component itself from being damaged due to the repeated execution of the light emission effect on the first decorative substrate 56.

[0137] As shown in FIGS. 8(a) to 8(c), on the first decorative substrate 56, small chip components (bypass capacitor 85 and small chip resistor 87) are arranged at a distance of 1 mm or more from the outer edge of the LED chip 142. By arranging the small chip components at a distance of 1 mm or more from the outer edge of the LED chip 142, it is possible to prevent the connection point between the small chip component and the first decorative substrate 56 from being damaged by thermal stress and to prevent the small chip component itself from being damaged by thermal stress.

[0138] As shown in FIGS. 8(a) to 8(c), in the first decorative substrate 56, the small chip components (bypass capacitor 85 and small chip resistor 87) are arranged at a distance of 1 mm or more from the outer edge of the LED driver 126 and the pads corresponding to the terminals of the LED driver 126. By arranging the small chip components at a distance of 1 mm or more from the outer edge of the LED driver 126 and the pads corresponding to the terminals of the LED driver 126, it is possible to prevent the connection portion between the small chip components and the first decorative substrate 56 from being damaged by thermal stress, and it is also possible to prevent the small chip components themselves from being damaged by thermal stress.

[0139] As shown in FIGS. 8(a) to 8(c), in the first decorative substrate 56, the small chip components (bypass capacitor 85, small chip resistor 87, and 143 to 149 (FIG. 11)) are arranged avoiding the peripheral regions 211a to 211d of the through holes. The peripheral regions 211a to 211d of the through holes are regions where the distance from the outer edge of the fixing through holes 56d to 56g is less than 5 mm. When the first decorative substrate 56 is screw-fixed to the front door frame 14, a force that causes distortion in the first decorative substrate 56 can act on the peripheral regions 211a to 211d of the through holes. By arranging the small chip components at a distance of 5 mm or more from the outer edge of the fixing through holes 56d to 56g, it is possible to prevent the connection portion between the small chip components and the first decorative substrate 56 from being damaged due to the distortion of the first decorative substrate 56 that may occur in the vicinity of the fixing through holes 56d to 56g when the first decorative substrate 56 is screw-fixed to the front door frame 14, and it is also possible to prevent the small chip components themselves from being damaged.

[0140] As shown in FIG. 8(a), the fixing through holes 56d to 56g are provided at the corners of the first decorative substrate 56. Therefore, compared with the configuration in which the fixing through holes 56d to 56g are provided near the center of the first decorative substrate 56, the area of the region where small chip components cannot be mounted on the first decorative substrate 56 is reduced.

[0141] As described above, the fixed through-hole 56e is provided in the protruding portion 56c of the stepped recess 56a. This makes it possible to stably fix the first decorative substrate 56 to the front door frame 14 while securing an area where small chip components can be mounted.

[0142] In a configuration where small chip components are concentrated on the first mounting surface 84, as shown in FIG. 15(a), the connectors 111 and 112 are concentrated on the second mounting surface 95. As shown in FIG. 8(a), on the first mounting surface 84, the small chip components are arranged avoiding the connector back side corresponding regions 203 and 204. The connector back side corresponding regions 203 and 204 are regions of the first mounting surface 84 located on the back side of the regions where the connectors 111 and 112 are mounted on the second mounting surface 95 (FIG. 15(a)) and regions where the distance from the outer edge of the regions of the first mounting surface 84 is less than 5 mm. Since small chip components are not mounted in the regions of the first mounting surface 84 located on the back side of the regions where the connectors 111 and 112 are mounted on the second mounting surface 95, the influence of the stress that can act on the first decorative substrate 56 when the harness is attached to and detached from the connectors 111 and 112 on the small chip components is reduced. The connector back side corresponding regions 203 and 204 are regions where tensile stress is likely to act when a harness (not shown) is attached to the connectors 111 and 112, and regions where compressive stress is likely to act when the harness is pulled out from the connectors 111 and 112. If small chip components are mounted in the connector back side corresponding regions 203 and 204, there is a risk that stress will act on the connection points between the small chip components and the first decorative substrate 56 when the harness is attached to and detached from the connectors 111 and 112, and there is also a risk that stress will act on the small chip components themselves. On the other hand, since the small chip components are arranged avoiding the connector back side corresponding regions 203 and 204, it is prevented that the connection points between the small chip components and the first decorative substrate 56 are damaged when the harness is attached to and detached from the connectors 111 and 112, and it is also prevented that the small chip components themselves are damaged.

[0143] As shown in FIG. 8(a), while the LED driver 126 is disposed in a region including a region less than 10 mm from the outer edge of the first decorative substrate 56, the small chip components (bypass capacitor 85 and small chip resistors 87, 143 to 149 (FIG. 11)) are disposed at a distance of 10 mm or more from the outer edge of the first decorative substrate 56. As already described, among the various electronic components mounted on the first decorative substrate 56, the connection portion between the small chip component and the first decorative substrate 56 has lower mechanical strength compared to the connection portion between other electronic components and the first decorative substrate 56. Since the small chip components are disposed at a distance of 10 mm or more from the outer edge of the first decorative substrate 56, when the first decorative substrate 56 is handled, the possibility that the operator's hand touches the small chip components and the connection portion between the small chip components and the first decorative substrate 56 is damaged is reduced, and the possibility that the small chip components themselves are damaged is also reduced.

[0144] In a configuration where the small chip components (bypass capacitor 85 and small chip resistors 87, 143 to 149 (FIG. 11)) are disposed so as to avoid the regions 211a to 211d around the through holes and the regions less than 10 mm from the outer edge of the first decorative substrate 56, the fixed through holes 56d to 56g are provided in a region less than 10 mm from the outer edge of the first decorative substrate 56. For this reason, compared with a configuration in which the fixed through holes 56d to 56g are provided at a position 10 mm or more away from the outer edge of the first decorative substrate 56, a wider area of the region where the small chip components can be mounted on the first decorative substrate 56 is ensured.

[0145] As shown in FIG. 8(b), on the first decorative substrate 56, around the LED driver 126, there are provided an outer shape silk 213 that enables grasping the mounting position of the LED driver 126, and an identification silk 214 (displayed as "IC1") that enables grasping that the mounted electronic component is the LED driver 126. Also, as shown in FIG. 8(c), around the LED chip 142, there are provided an outer shape silk 215 that enables grasping the mounting position of the LED chip 142, and an identification silk 216 (displayed as "LED16") that enables grasping that the mounted electronic component is the LED chip 142. As shown in FIG. 9, the first wiring layer 91 is coated with a solder resist 222. The outer shape silk 213 and the identification silk 214 are printed in a manner that protrudes from the first mounting surface 84. The printing of the outer shape silks 213, 215 and the identification silks 214, 216 is performed before the electronic components are mounted on the first decorative substrate 56.

[0146] After mounting electronic components including small chip components on the first decorative substrate 56, when visually confirming that there is no mounting omission of the electronic components, the operator can grasp whether the electronic components are mounted at the correct positions by comparing the locations where the outer shape silks 213, 215 are provided with the locations where the electronic components (LED driver 126 and LED chip 142) are mounted. Also, the operator can grasp the types of the mounted electronic components (LED driver 126 and LED chip 142) based on the display contents of the identification silks 214, 216.

[0147] As shown in FIG. 8(b), only the identification silk 217 (displayed as "C1") for confirming that the mounted electronic component is the bypass capacitor 85 is provided around the bypass capacitor 85, and no outline silk for grasping the mounting position of the bypass capacitor 85 is provided. As already described, the external dimensions (length dimension, width dimension, and height dimension) of the bypass capacitor 85 are smaller compared to the external dimensions of electronic components other than small chip components (such as the LED driver 126 and the LED chips 127 to 142). For this reason, if the outline silk of the bypass capacitor 85 is printed on the first decorative substrate 56, there is a risk that the operator may mistakenly recognize that the bypass capacitor 85 is mounted just by looking at the outline silk even though there is actually a mounting omission of the bypass capacitor 85 after the electronic components are mounted. On the other hand, by adopting a configuration in which no outline silk is provided around the bypass capacitor 85, it is possible to easily grasp the mounting omission of the bypass capacitor 85 after the electronic components are mounted. In addition, since the identification silk 217 is provided around the bypass capacitor 85, it is possible to grasp that the components mounted around the identification silk 217 are the bypass capacitor 85.

[0148] As described above, the external dimensions of the small chip resistor 87 are small compared to those of electronic components other than small chip components, similar to the external dimensions of the bypass capacitor 85. As shown in FIG. 8(c), only the identification silk 218 (displayed as "R8") for confirming that the mounted electronic component is the small chip resistor 87 is provided around the small chip resistor 87, and no outer shape silk for confirming the mounting position of the small chip resistor 87 is provided. Thereby, it is possible to easily grasp the mounting omission of the small chip resistor 87. Further, since the identification silk 218 is provided around the small chip resistor 87, it is possible to grasp that the electronic component mounted around the identification silk 218 is the small chip resistor 87. When mounting an electronic component on the first decorative substrate 56 using an automatic mounting device, since the automatic mounting device mounts the electronic component by coordinate control from the reference position on the first decorative substrate 56, even if the outer shape silk is not provided around the small chip component, the mounting position of the small chip component does not shift.

[0149] The character dimensions of the identification silks 217 and 218 provided around the small chip components (bypass capacitor 85 and small chip resistor 87) are the same as the character dimensions of the identification silks 214 and 216 provided around the electronic components (LED driver 126 and LED chip 142) larger than the small chip components. Thereby, visual confirmation of the identification silks 217 and 218 provided around the small chip components is facilitated.

[0150] FIG. 16(a) is a cross-sectional view of the first decorative substrate 56 in the present embodiment, and FIG. 16(b) is a cross-sectional view of the first decorative substrate 224 in the comparative example. As already described, the pair of pads 171a and 171b corresponding to the pair of electrodes 85a and 85b of the bypass capacitor 85 are formed at an interval of approximately 0.28 mm in the longitudinal direction of the bypass capacitor 85. Also, as already described, the solder resist 222 is not applied between the first pad 171a and the second pad 171b (see FIG. 16(a)). In the step of applying the solder paste to the first decorative substrate 56, the first mounting surface 84 and the second mounting surface 95 (FIG. 9) of the first decorative substrate 56 are masked by the metal mask 226 in which the openings are formed. The metal mask 226 is, for example, a metal thin plate having a thickness of approximately 150 μm. The metal mask 226 is provided with openings penetrating in the thickness direction at positions corresponding to the pads (or pads) of the first decorative substrate 56. The solder paste is applied onto the pads through the openings of the metal mask 226. Since the thickness of the metal mask 226 is uniform, it is possible to apply the solder paste uniformly to each pad.

[0151] As shown in FIG. 16(b), since the outer shape silks 225a and 225b are convex with respect to the surface of the solder resist 222, if the outer shape silks 225a and 225b are provided around small chip components (bypass capacitor 85 and small chip resistor 87 (FIGS. 8(b) and 8(c))), the outer shape silks 225a and 225b will exist between the first mounting surface 84 and the metal mask 226, and the distance between the first mounting surface 84 and the metal mask 226 will increase. In such a configuration, the solder paste 227 may creep into the gap existing between the first pad 171a and the second pad 171b, and there is a risk that the first pad 171a and the second pad 171b will be electrically connected. In particular, when the solder paste 221 is continuously applied to a large number of first decorative substrates 56, the solder paste 221 accumulated at the edge of the opening of the metal mask 226 is likely to creep to the back side of the opening, and the first pad 171a and the second pad 171b are likely to be electrically connected. On the other hand, in the present embodiment, as shown in FIG. 16(a), no outer shape silk is provided around the small chip component. Thereby, it is possible to prevent the distance between the first mounting surface 84 and the metal mask 226 from being too large, and it is possible to prevent the occurrence of soldering defects in which the solder paste 221 enters between the pads 171a and 171b. In addition, it is prevented that a part of the small chip component is placed on the outer shape silk and causes soldering defects.

[0152] Next, a method for manufacturing the decorative substrates 56 and 57 will be described.

[0153] As a method for efficiently manufacturing the first decorative substrate 56, after mounting electronic components on a collective substrate (a printed wiring board before the electronic components are mounted) including a plurality of first decorative substrates 56, the collective substrate is divided to take out a plurality of the first decorative substrates 56 with the electronic components mounted thereon at once. Also, as a method for efficiently manufacturing the second decorative substrate 57, after mounting electronic components on a collective substrate (a printed wiring board before the electronic components are mounted) including a plurality of second decorative substrates 57, the collective substrate is divided to take out a plurality of the second decorative substrates 57 with the electronic components mounted thereon at once. By manufacturing the decorative substrates 56 and 57 by these methods, the number of times of performing the process of mounting the electronic components can be reduced and the manufacturing efficiency of the decorative substrates 56 and 57 can be increased as compared with the case of manufacturing the decorative substrates 56 and 57 with the electronic components mounted thereon one by one. Hereinafter, regarding the method for manufacturing the decorative substrates 56 and 57, the method for efficiently manufacturing the first decorative substrate 56 will be described as an example.

[0154] FIG. 17(a) is a plan view showing a first plate surface 268 which is one side plate surface of the collective substrate 231, FIG. 17(b) is an explanatory view for explaining a valley cut for dividing the collective substrate 231 so that the first plate surface 268 becomes a valley shape (concave), and FIG. 17(c) is an explanatory view for explaining a mountain cut for dividing the collective substrate 231 so that the first plate surface 268 becomes a mountain shape (convex). In actuality, a plurality of electronic components are mounted on each of the first decorative substrates 56 included in the collective substrate 231 and wiring patterns and the like are also formed, but FIGS. 17(a) to 17(c) are shown in a simplified manner to avoid complication of the drawing.

[0155] The collective substrate 231 is a four-layer substrate having a structure in which a conductive layer and an insulating layer are alternately laminated, similar to the decorative substrates 56 and 57 described above. As shown in FIG. 17(a), the collective substrate 231 is created by cutting out a part of a single printed wiring board formed in a substantially square shape by router processing or the like in which a drill-like tool (router) with a blade on the side is rotated, and forming dividing grooves 232 to 247 and slits 251 to 258 in the printed wiring board.

[0156] The integrated substrate 231 is partitioned by dividing grooves 232 to 247 and slits 251 to 258 into four first decorative substrates 56 and seven discard substrates 261 to 267. The process of forming the dividing grooves 232 to 247 and the slits 251 to 258 in the integrated substrate 231 is performed before electronic components are mounted on the integrated substrate 231. The integrated substrate 231 is divided using the dividing grooves 232 to 247 and the slits 251 to 258.

[0157] The dividing grooves 232 to 247 are linearly formed by cutting the integrated substrate 231 using, for example, a disk-shaped blade that rotates at high speed. The dividing grooves 232 to 247 have a V-shaped cross section that reduces the plate thickness of the integrated substrate 231, and the bottom of the dividing grooves 232 to 247 is the portion with the smallest plate thickness. The region where the dividing grooves 232 to 247 are formed in the integrated substrate 231 has lower mechanical strength compared to the region where the dividing grooves 232 to 247 are not formed. Therefore, by dividing the integrated substrate 231 with the dividing grooves 232 to 247 as a base point, the stress acting on the first decorative substrate 56 when dividing the integrated substrate 231 can be reduced. As a result, the stress that can act on the connection points between the small chip components (bypass capacitors 85 and small chip resistors 87, 143 to 149) and the first decorative substrate 56 when dividing the integrated substrate 231 can be reduced, and the stress that can act on the small chip components themselves can be reduced. Also, it is possible to prevent the base point of the division from deviating from the dividing grooves 232 to 247. Note that the cross-sectional shape of the dividing grooves 232 to 247 is not limited to a V shape. The cross-sectional shape of the dividing grooves 232 to 247 may be rectangular or U-shaped as long as the integrated substrate 231 can be easily separated by an external force.

[0158] Since the dividing grooves 232 to 247 are linearly formed, the stress that can act on the first decorative substrate 56 when dividing the integrated substrate 231 is reduced compared to a configuration where the dividing grooves 232 to 247 are formed in a curved shape.

[0159] In the present embodiment, the dividing grooves 232 to 247 are formed only on the first plate surface 268 side of the integrated substrate 231 in order to facilitate distinguishing between the first plate surface 268 and the second plate surface 269 (FIG. 17(b)), which is the plate surface opposite to the first plate surface 268, and to improve the workability of the substrate dividing process. The slits 251 to 258 are formed, for example, by the router processing described above. The slits 251 to 258 are in the shape of elongated oblong holes and are formed wider than the dividing grooves 232 to 247.

[0160] As shown in FIG. 17(a), a vertically long substantially rectangular center discard substrate 261 is provided at the center in the left-right direction of the integrated substrate 231. A pair of first decorative substrates 56 are provided on the left side of the center discard substrate 261 with the dividing grooves 232 and 233 interposed therebetween, and a pair of first decorative substrates 56 are provided on the right side of the center discard substrate 261 with the dividing grooves 234 and 235 interposed therebetween. The four first decorative substrates 56 are flush with each other, and the first mounting surfaces 84 of these first decorative substrates 56 are present on the first plate surface 268 side of the integrated substrate 231.

[0161] As already described, the first decorative substrate 56 is formed with a stepped recess 56a and a notch 56b. In the lower left first decorative substrate 56, the stepped recess 56a is provided on the center discard substrate 261 side, and the notch 56b is provided on the left discard substrate 263 side, which will be described later. In the upper left first decorative substrate 56, the stepped recess 56a is provided on the left discard substrate 263 side, and the notch 56b is provided on the center discard substrate 261 side. The stepped recesses 56a of the pair of first decorative substrates 56 face each other. The space between these stepped recesses 56a is cut out, and the stepped recesses 56a are not connected to each other.

[0162] In the lower right first decorative substrate 56, the stepped recess 56a is provided on the side of the right discard substrate 266 described later, and the notch 56b is provided on the side of the central discard substrate 261. In the upper right first decorative substrate 56, the stepped recess 56a is provided on the side of the central discard substrate 261, and the notch 56b is provided on the side of the right discard substrate 266. The stepped recesses 56a of the pair of first decorative substrates 56 face each other. The space between these stepped recesses 56a is cut out, and the stepped recesses 56a are not connected to each other.

[0163] On the left side of the central discard substrate 261, below, on the left side, and above the pair of first decorative substrates 56, a lower left discard substrate 262, a vertically long substantially rectangular left discard substrate 263, and an upper left discard substrate 264 are provided. The lower left discard substrate 262 is connected to the left discard substrate 263 and the central discard substrate 261 via the dividing grooves 236 and 237, and the upper left discard substrate 264 is connected to the left discard substrate 263 and the central discard substrate 261 via the dividing grooves 238 and 239. A slit 251 is formed between the lower left discard substrate 262 and the upper left first decorative substrate 56, and the lower left discard substrate 262 and the upper left first decorative substrate 56 are not connected. Also, a slit 252 is formed between the upper left discard substrate 264 and the upper right first decorative substrate 56, and the upper left discard substrate 264 and the upper right first decorative substrate 56 are not connected. The left discard substrate 263 is connected to the lower left first decorative substrate 56 and the upper left first decorative substrate 56 via the dividing grooves 240 and 241.

[0164] On the right side of the central discard substrate 261, below, to the right, and above a pair of first decorative substrates 56, a lower right discard substrate 265, a vertically long substantially rectangular right side discard substrate 266, and an upper right discard substrate 267 are provided. The lower right discard substrate 265 is connected to the central discard substrate 261 and the right side discard substrate 266 via dividing grooves 242 and 243, and the upper right discard substrate 267 is connected to the central discard substrate 261 and the right side discard substrate 266 via dividing grooves 244 and 245. A slit 253 is formed between the lower right discard substrate 265 and the lower left first decorative substrate 56, and the lower right discard substrate 265 and the lower left first decorative substrate 56 are not connected. Also, a slit 254 is formed between the upper right discard substrate 267 and the lower right first decorative substrate 56, and the upper right discard substrate 267 and the lower right first decorative substrate 56 are not connected. The right side discard substrate 266 is connected to the lower left first decorative substrate 56 and the lower right first decorative substrate 56 via dividing grooves 246 and 247.

[0165] In this way, discard substrates 262 to 267 are provided over the entire circumference on the outer periphery of the integrated substrate 231, and the four first decorative substrates 56 are surrounded by the discard substrates 262 to 267. As a result, it is possible to handle the integrated substrate 231 without touching the electronic components mounted on the first decorative substrate 56 after the electronic components are mounted. Therefore, it is possible to prevent the electronic components from being damaged due to the operator's hand coming into contact with the electronic components. Note that the number of the first decorative substrates 56 included in the integrated substrate 231 is not limited to "4". A configuration in which the number of the first decorative substrates 56 included in the integrated substrate 231 is more than "4" (for example, "6") may be adopted, or a configuration in which the number of the first decorative substrates 56 included in the integrated substrate 231 is less than "4" (for example, "2") may be adopted.

[0166] A pair of first decorative substrates 56 are provided with stepped recesses 56a facing the left side of the central discard substrate 261, and a pair of first decorative substrates 56 are provided with stepped recesses 56a facing the right side of the central discard substrate 261, whereby the vertical dimension of the integrated substrate 231 including the four first decorative substrates 56 is reduced.

[0167] Next, regarding the manufacturing process of the decorative substrates 56 and 57, the manufacturing process of the first decorative substrate 56 will be described by way of example.

[0168] In the manufacturing process of the first decorative substrate 56, first, with the second board surface 269 of the collective substrate 231 (the second mounting surface 95 side, see Fig. 17(b)) facing upward, a solder paste application process of applying solder paste to the pads (or pads) provided on the second board surface 269 of the collective substrate 231, an adhesive application process of applying an adhesive for fixing the connector, a component mounting process of mounting the connectors 111 and 112 (Fig. 8(a)) on the second board surface 269 side of the collective substrate 231 using an automatic mounting device (not shown), a reflow process of conveying the collective substrate 231 to a reflow furnace and heating it, and a cooling process of cooling the collective substrate 231 to room temperature are performed. Thereby, the connectors 111 and 112 are mounted on the second board surface 269 side of the collective substrate 231. When the adhesive cures, the dropping of the connectors 111 and 112 is prevented in the second reflow process.

[0169] Thereafter, with the first board surface 268 of the collective substrate 231 facing upward, a solder paste application process of applying solder paste onto the lands provided on the first board surface 268 side (the first mounting surface 84 side) of the collective substrate 231, a component mounting process of mounting electronic components including small chip components on the first board surface 268 side of the collective substrate 231 using an automatic mounting device (not shown), a reflow process of conveying the collective substrate 231 to a reflow furnace and heating it, a cooling process of cooling the collective substrate 231 to room temperature, a substrate splitting process of splitting the collective substrate 231 after the electronic components are mounted, and an implementation confirmation process of visually checking whether there is any omission in the mounting of the electronic components on the first decorative substrate 56 are performed. Thereby, the electronic components including small chip components are mounted on the first board surface 268 side of the collective substrate 231.

[0170] As shown in Fig. 17(a), the left discard substrate 263 and the right discard substrate 266 are formed with a first mounting reference hole 271 and a second mounting reference hole 272 that penetrate the integrated substrate 231 in the thickness direction. The first mounting reference hole 271 is used for aligning the integrated substrate 231 in the component mounting process of mounting electronic components on the first board surface 268 side, and the second mounting reference hole 272 is used for aligning the integrated substrate 231 in the component mounting process of mounting electronic components on the second board surface 269 side. After aligning the integrated substrate 231, the automatic mounting device sets the small chip component on the first decorative substrate 56 so that the electrodes of the small chip component are placed on the solder paste applied to the corresponding pads (or pads) by coordinate control.

[0171] As methods for dividing the integrated substrate 231, a method in which an operator manually breaks the integrated substrate 231 and a method in which the integrated substrate 231 is mechanically cut using a press or the like are known. Among these, by adopting the manual division method, it is possible to respond flexibly to multiple types of integrated substrates while suppressing equipment costs.

[0172] As ways of dividing the integrated substrate 231, there are valley cutting in which the integrated substrate 231 is cut so that the first board surface 268 where small chip components are aggregated with the dividing grooves 232 to 247 as the basis becomes a valley shape (concave), and mountain cutting in which the integrated substrate 231 is cut so that the first board surface 268 becomes a mountain shape (convex). In the substrate division process, as shown in Fig. 17(b), the integrated substrate 231 is divided by valley cutting in which the first board surface 268 is made into a valley shape (concave) with the dividing grooves 232 to 247 as the basis, and a plurality of (specifically, four) first decorative substrates 56 are taken out.

[0173] As already described, in the first decorative substrate 56, small chip components (bypass capacitor 85 and small chip resistors 87, 143 to 149) are concentrated on the first mounting surface 84 side. In the integrated substrate 231, small chip components are concentrated on the first board surface 268 side (the first mounting surface 84 side) and are not mounted on the second board surface 269 side (the second mounting surface 95 side). Also, as already described, the connection portion between the small chip component and the first decorative substrate 56 has lower mechanical strength than the connection portion between other electronic components and the first decorative substrate 56. When the integrated substrate 231 is split as shown in FIG. 17(c), the force that can act on the first board surface 268 side (the first mounting surface 84 side) of the integrated substrate 231 is tensile stress, and the force that can act on the second board surface 269 side (the second mounting surface 95 side) is compressive stress. On the other hand, when the integrated substrate 231 is split into valleys as shown in FIG. 17(b), the force that can act on the first board surface 268 side (the first mounting surface 84 side) of the integrated substrate 231 is compressive stress, and the force that can act on the second board surface 269 side (the second mounting surface 95 side) is tensile stress.

[0174] The stress when splitting the integrated substrate 231 acts more greatly on the board surface having a mountain shape (convex) than on the board surface having a valley shape (concave). By splitting the integrated substrate 231 into valleys so that the first board surface 268 side (the first mounting surface 84 side) where small chip components are concentrated becomes a valley shape (concave), the stress that can act on the connection portion between the small chip component and the first decorative substrate 56 during the splitting of the integrated substrate 231 can be reduced, and the stress that can act on the small chip component itself can be reduced. As a result, the possibility that the connection portion between the small chip component and the first decorative substrate 56 is damaged can be reduced, and the possibility that the small chip component itself is damaged can be reduced. In this way, by reducing the possibility of contact failure of the small chip component occurring in the substrate splitting process, the manufacturing efficiency of the first decorative substrate 56 can be improved.

[0175] Among the small chip components, the multilayer ceramic capacitor used as the bypass capacitor 85 is vulnerable to tensile stress. When tensile stress acts on the bypass capacitor 85, cracks are likely to occur in the bypass capacitor 85 itself. By grooving the assembly substrate 231 so that the side of the first board surface 268 (the first mounting surface 84 side) where the small chip components including the bypass capacitor 85 are aggregated becomes valley-shaped (concave), the force that can act on the bypass capacitor 85 can be made compressive stress, and the action of tensile stress on the bypass capacitor 85 can be avoided. Thereby, the possibility that the bypass capacitor 85 itself is damaged during the division of the assembly substrate 231 can be reduced.

[0176] As described above, by dividing the assembly substrate 231 with the dividing grooves 232 to 247 as the basis, the stress that can act on the connection portion between the small chip component and the first decorative substrate 56 can be minimized, and the stress that can act on the small chip component can be minimized. On the other hand, if the basis of the division deviates from the dividing grooves 232 to 247, these stresses will increase. In order to prevent the basis of the division from deviating from the dividing grooves 232 to 247 and improve the workability of the substrate division process, a dividing jig is used.

[0177] FIG. 18(a) is a perspective view of a dividing jig 281 used for dividing the assembly substrate 231 in the present embodiment, FIG. 18(b) is a front view of the dividing jig 281, and FIG. 18(c) is an explanatory diagram for explaining the state of dividing the assembly substrate 231 using the dividing jig 281. As shown in FIG. 18(a), the dividing jig 281 includes a thin metal blade 282 that serves as a fulcrum when contacting the dividing grooves 232 to 247 to divide the assembly substrate 231, and a base portion 283 that supports the thin blade 282. The base portion 283 includes a resin-made base portion 283a formed in a horizontally long rectangular parallelepiped shape, and a rectangular parallelepiped-shaped upright portion 283b that stands up from one side plate surface of the base portion 283a and is integrally formed.

[0178] The thin blade 282 includes a plate-shaped blade portion 282a and a flange portion 282b. The thin blade 282 is fixed to the base portion 283 by screwing the flange portion 282b to the upright portion 283b. The blade portion 282a protrudes upward from the upper plane of the upright portion 283b and extends in the longitudinal direction of the upright portion 283b.

[0179] At approximately the center in the longitudinal direction of the upright portion 283b, a protrusion 283c for assisting the alignment of the assembly substrate 231 with respect to the blade portion 282a is integrally formed so that the blade portion 282a abuts against the dividing grooves 232 to 247. The protrusion 283c protrudes upward from the upper plane of the upright portion 283b with a protruding dimension larger than that of the blade portion 282a. As shown in Fig. 17(a), recesses 284 and 285 through which the protrusion 283c can be inserted are provided between the pair of first decorative substrates 56 in the right part of the left discarded substrate 263 and the left part of the central discarded substrate 261. Also, recesses 286 and 287 through which the protrusion 283c can be inserted are provided between the pair of first decorative substrates 56 in the right part of the central discarded substrate 261 and the left part of the right discarded substrate 266.

[0180] As shown in Fig. 18(c), the operator turns the first plate surface 268 (the first mounting surface 84) of the assembly substrate 231 downward and fixes any one of the central discarded substrate 261, the left discarded substrate 263, and the right discarded substrate 266 (the central discarded substrate 261 in Fig. 18(c)) on the upright portion 283b. At this time, by inserting the protrusion 283c into the recesses 284 to 287 (Fig. 17(a)) provided in the discarded substrates 261, 263, and 266, a state in which the dividing grooves 232 to 247 serving as the basis for division are in contact with the blade portion 282a can be easily created. In this state, by applying a downward force to the second plate surface 269 side and pushing downward the portion protruding to the right from the upright portion 283b, the assembly substrate 231 can be divided into valleys with the dividing grooves 232 to 247 as the basis in a manner in which the first plate surface 268 becomes valley-shaped (concave).

[0181] The operator first divides the collective substrate 231 (Fig. 17(a)) into a first unit including a pair of left-side first decorative substrates 56, a lower-left discard substrate 262, a left-side discard substrate 263, and an upper-left discard substrate 264, and a second unit including a pair of right-side first decorative substrates 56, a center discard substrate 261, a lower-right discard substrate 265, a right-side discard substrate 266, and an upper-right discard substrate 267. Then, in the first unit, two first decorative substrates 56 can be taken out by dividing the pair of first decorative substrates 56 and the left-side discard substrate 263. Also, in the second unit, two first decorative substrates 56 can be taken out by dividing the pair of first decorative substrates 56 and the center discard substrate 261, and by dividing the pair of first decorative substrates 56 and the right-side discard substrate 266. Note that the order of dividing the collective substrate 231 to take out the four first decorative substrates 56 is arbitrary.

[0182] With the blade portion 282a in contact with the dividing grooves 232 to 247 serving as the dividing base points, by valley-dividing the collective substrate 231 with the blade portion 282a as the fulcrum, it is possible to prevent the dividing base points from shifting from the dividing grooves 232 to 247. Thereby, when dividing the collective substrate 231, the stress that can act on the connection portion between the small chip components and the first decorative substrate 56 can be minimized, and the stress that can act on the small chip components themselves can be minimized.

[0183] Since the configuration is such that the collective substrate 231 is valley-divided by pushing the second mounting surface 95 downward, compared with the configuration in which the collective substrate 231 is valley-divided by pulling the second mounting surface 95 upward, it is easier for the operator to apply a force to divide the collective substrate 231. Also, in the center discard substrate 261, the left-side discard substrate 263, and the right-side discard substrate 266, since the recesses 284 to 287 (Fig. 17(a)) are provided between the pair of first decorative substrates 56, it is possible to fix the collective substrate 231 to the dividing jig 281 while preventing the stress acting on the electronic components mounted on the first decorative substrate 56 from increasing.

[0184] As described above with reference to FIG. 8(a), the first decorative substrate 56 is provided with fixing through holes 56d to 56g, and the small chip components are arranged avoiding the peripheral regions 211a to 211d of the through holes. Therefore, as shown in FIG. 18(c), with the first plate surface 268 (the first mounting surface 84) facing downward, when a downward force is applied to the second plate surface 269 side in a state where any one of the center discard substrate 261, the left discard substrate 263, and the right discard substrate 266 is fixed to the standing portion 283b and the portion protruding from the standing portion 283b is pushed downward to divide the integrated substrate 231, the vicinity of the fixing through holes 56d to 56g can be selected as the portion to be pushed downward. Thereby, the stress that can act on the small chip components mounted on the first plate surface 268 side (the first mounting surface 84 side) can be minimized.

[0185] As described above, the dividing grooves 232 to 247 are formed only on the first plate surface 268 side of the integrated substrate 231 and are not formed on the second plate surface 269 side. For this reason, the operator only needs to set the integrated substrate 231 on the dividing jig 281 with the plate surface (the first plate surface 268) on which the dividing grooves 232 to 247 are formed facing downward, and the possibility of accidentally splitting the integrated substrate 231 in a mountain shape is reduced.

[0186] As shown in FIG. 17(a), the 16 dividing grooves 232 to 247 existing in the integrated substrate 231 extend in the first direction DR1. The extending directions of these dividing grooves 232 to 247 are parallel to each other. Also, as described above with reference to FIGS. 8(a) to 8(c), the small chip components (the bypass capacitor 85 and the small chip resistors 87, 143 to 149 (FIG. 11)) are mounted on the first decorative substrate 56 in such a manner that the longitudinal direction of the small chip components is parallel to the 16 dividing grooves 232 to 247 existing in the integrated substrate 231. Therefore, compared with a configuration in which the longitudinal direction of the small chip components is orthogonal to the extending direction of the dividing grooves 232 to 247, the stress that can act on the connection portion between the small chip components and the first decorative substrate 56 when the integrated substrate 231 is divided with the dividing grooves 232 to 247 as a base point is reduced, and the stress that can act on the small chip components themselves is reduced.

[0187] As shown in FIG. 17(a), in the integrated substrate 231, slits 255 to 258 are provided at positions corresponding to the region where the bypass capacitor 85 is mounted. As already described, the slits 255 to 258 are in the shape of elongated slots and are formed wider than the dividing grooves 233, 234, 240, and 247. When the integrated substrate 231 is split with the dividing grooves 232 to 247 as a basis, the stress that can act on the periphery of the slits 255 to 258 is smaller than the stress that can act on the periphery of the dividing grooves 232 to 247. By providing the slits 255 to 258 at the corresponding positions of the mounting region of the bypass capacitor 85, the stress that can act on the connection portion between the bypass capacitor 85 and the first decorative substrate 56 when the integrated substrate 231 is split is reduced, and the stress that can act on the bypass capacitor 85 itself is reduced.

[0188] As shown in FIGS. 8(a) and (b), the bypass capacitor 85 is arranged on the side of the stepped recess 56a rather than the LED driver 126. As already described with reference to FIG. 17(a), the dividing grooves 233, 234, 240, and 247 are not provided on the side of the stepped recess 56a in the integrated substrate 231. Since the bypass capacitor 85 is arranged on the opposite side of the dividing grooves 233, 234, 240, and 247 with the LED driver 126 interposed therebetween, when the integrated substrate 231 is split with the dividing grooves 233, 234, 240, and 247 as a basis, the stress that can act on the connection portion between the bypass capacitor 85 and the first decorative substrate 56 can be reduced, and the stress that can act on the bypass capacitor 85 itself can be reduced. Thereby, when the integrated substrate 231 is split, the possibility that the connection portion between the bypass capacitor 85 and the first decorative substrate 56 is broken is reduced, and the possibility that the bypass capacitor 85 itself is broken is reduced.

[0189] As already described with reference to FIGS. 8(b) and 8(c), the separation direction of pads 171a and 171b corresponding to electrodes 85a and 85b of bypass capacitor 85, and the separation direction of pads 176a and 176b corresponding to electrodes 87a and 87b of small chip resistor 87 are the first direction DR1. By transporting the assembly substrate 231 in the direction (second direction DR2) perpendicular or substantially perpendicular to the common separation direction (first direction DR1) in the reflow process, it is possible to align the timing at which the heating of the solder paste applied on the pair of pads 171a and 171b corresponding to the pair of electrodes 85a and 85b of the bypass capacitor 85 starts, and it is also possible to align the timing at which the heating of the solder paste applied on the pair of pads 176a and 176b corresponding to the pair of electrodes 87a and 87b of the small chip resistor 87 starts. Thereby, it is possible to prevent the rotation and chip standing of a plurality of small chip components. As shown in FIG. 17(a), on the first plate surface 268 side of the left discard substrate 263, a recognition mark 288 is provided to enable confirmation of the transport direction of the assembly substrate 231 in the reflow process. Also, although not shown, a recognition mark for enabling confirmation of the transport direction of the assembly substrate 231 in the reflow process is also provided on the second plate surface 269 side of the left discard substrate 263. Thereby, the possibility that the operator mistakes the transport direction of the assembly substrate 231 is reduced.

[0190] As described above with reference to FIG. 8(a), in the configuration where the LED driver 126 is disposed in a region including a region less than 10 mm from the outer edge of the first decorative substrate 56, the small chip components (bypass capacitor 85 and small chip resistors 87, 143 to 149 (FIG. 11)) are disposed at a distance of 10 mm or more from the outer edge of the first decorative substrate 56. As described above, among the various electronic components mounted on the first decorative substrate 56, the connection portion between the small chip component and the first decorative substrate 56 has lower mechanical strength compared to the connection portion between other electronic components and the first decorative substrate 56. Further, the region within 10 mm from the outer edge of the first decorative substrate 56 is a region that may be present in the vicinity of the dividing grooves 232 to 247 (FIG. 17) in the collective substrate 231 (FIG. 17), and is a region where a force may be applied to split the collective substrate 231. By disposing the small chip components at a distance of 10 mm or more from the outer edge of the first decorative substrate 56, the maximum value of the stress that can act on the connection portion between the small chip component and the first decorative substrate 56 during the splitting of the collective substrate 231 is reduced, and the maximum value of the stress that can act on the small chip component itself is reduced.

[0191] <Electrical Configuration of Pachinko Machine 10> FIG. 19 is a block diagram showing the electrical configuration of the pachinko machine 10.

[0192] The main control device 60 includes a main control board 61 that controls the main game and a power failure monitoring board 67 that monitors the power supply. An MPU 62 is mounted on the main control board 61. In addition to the main side CPU 63, which is an arithmetic processing device including a control unit and an arithmetic unit, a main side ROM 64 and a main side RAM 65 are built in the MPU 62. In addition to the above elements, the MPU 62 includes an interrupt circuit, a timer circuit, a data input / output circuit, and various counter circuits as random number generators.

[0193] The main-side ROM 64 is a memory that does not require external power supply for data retention, such as a NOR-type flash memory and a NAND-type flash memory (i.e., non-volatile storage means), and is used as read-only. The main-side ROM 64 stores various control programs and fixed-value data executed by the main-side CPU 63.

[0194] The main-side RAM 65 is a memory that requires external power supply for data retention, such as an SRAM and a DRAM (i.e., volatile storage means), and is used for both reading and writing. The main-side RAM 65 allows random access and has a shorter read time than the main-side ROM 64 when compared with the same data capacity. The main-side RAM 65 temporarily stores various data for the execution of the control programs stored in the main-side ROM 64.

[0195] Processing for managing the game history is executed by the main-side CPU 63. The main-side CPU 63 grasps the entry history of game balls into the general winning opening 31, the special electric winning device 32, the first operation opening 33, the second operation opening 34, and the out opening 24a, and grasps the entry frequencies into the general winning opening 31, the special electric winning device 32, the first operation opening 33, and the second operation opening 34 according to the grasped entry history. In addition, the main-side CPU 63 grasps the occurrence frequencies of the opening / closing execution mode and the high-frequency support mode described later.

[0196] The MPU 62 is provided with an input port and an output port respectively. On the input side of the MPU 62, a power failure monitoring board 67 and a payout control device 77 provided in the main control device 60 are connected. A power supply / transmission control device 78 having a function of supplying operating power is connected to the power failure monitoring board 67, and operating power is supplied to the MPU 62 via the power failure monitoring board 67.

[0197] On the input side of the MPU62, various sensors such as the respective ball-in detection sensors 42a to 49a are connected. As already described, the respective ball-in detection sensors 42a to 49a include the first winning port detection sensor 42a, the second winning port detection sensor 43a, the third winning port detection sensor 44a, the special electricity detection sensor 45a, the first activation port detection sensor 46a, the second activation port detection sensor 47a, the out port detection sensor 48a, and the gate detection sensor 49a. Based on the detection results of these ball-in detection sensors 42a to 49a, the main CPU 63 performs a ball-in determination for each ball-in section. Also, in the main CPU 63, various lotteries are executed based on winning in the first activation port 33 and various lotteries are executed based on winning in the second activation port 34.

[0198] On the input side of the MPU62, a setting key insertion part 68a, an update button 68b, and a reset button 68c provided on the main control board 61 are provided. A sensor (not shown) is provided in the setting key insertion part 68a, and the sensor detects whether the setting key insertion part 68a is arranged at the ON operation position or the OFF operation position. Then, the main CPU 63 specifies whether the setting key insertion part 68a is arranged at the ON operation position or the OFF operation position based on the detection result from the sensor. A sensor (not shown) is provided in the update button 68b, and the sensor detects whether the update button 68b is being pressed. Then, the main CPU 63 specifies whether the update button 68b is being pressed based on the detection result from the sensor. A sensor (not shown) is provided in the reset button 68c, and the sensor detects whether the reset button 68c is being pressed. Then, the main CPU 63 specifies whether the reset button 68c is being pressed based on the detection result from the sensor.

[0199] On the output side of the MPU62, a power failure monitoring board 67, a payout control device 77, and an audio-visual control device 81 are connected. For example, based on the fact that a game ball has entered the prize ball corresponding ball entry section among the above-mentioned ball entry sections where the occurrence of ball entry corresponds to the payout of game balls, a prize ball command is output to the payout control device 77. Various commands such as a variation command, a type command, and an opening command are output to the audio-visual control device 81.

[0200] On the output side of the MPU62, a special power drive unit 32b for opening and closing the opening / closing door 32a of the special power winning device 32, a general power drive unit 34b for opening and closing the general power accessory 34a of the second operation port 34, a special diagram unit 37, and a general diagram unit 38 are connected. Incidentally, the special diagram unit 37 is provided with a special diagram display section 37a and a special diagram hold display section 37b, and all of these are connected to the output side of the MPU62. Similarly, the general diagram unit 38 is provided with a general diagram display section 38a and a general diagram hold display section 38b, and all of these are connected to the output side of the MPU62. The main control board 61 is provided with various driver circuits, and through the driver circuits, the MPU62 executes drive control of various drive units and various display sections.

[0201] That is, in the opening / closing execution mode, the main CPU 63 executes drive control of the special power drive unit 32b so that the special power winning device 32 is opened and closed. Further, when the general power accessory 34a wins in the open state, the main CPU 63 executes drive control of the general power drive unit 34b so that the general power accessory 34a is opened and closed. Further, in each game round, the main CPU 63 executes display control of the special figure display unit 37a. Further, when indicating the lottery result of whether or not to set the general power accessory 34a to the open state, the main CPU 63 executes display control of the general figure display unit 38a. Further, when a winning occurs in the first operation port 33 or the second operation port 34, or when variable display starts in the special figure display unit 37a, the main CPU 63 executes display control of the special figure hold display unit 37b. When a winning occurs in the through gate 35, or when variable display starts in the general figure display unit 38a, the main CPU 63 executes display control of the general figure hold display unit 38b.

[0202] The first to third notification display devices 69a to 69c are connected to the output side of the MPU 62. The first to third notification display devices 69a to 69c display the management results of the game history. Further, when changing the setting state of the pachinko machine 10, the current setting value is displayed on the third notification display device 69c. The first to third notification display devices 69a to 69c are controlled for display by the main CPU 63.

[0203] The power failure monitoring board 67 relays the main control board 61 and the power supply / transmission control device 78, and monitors the voltage of 24 VDC stabilized direct current, which is the maximum voltage output from the power supply / transmission control device 78. The payout control device 77 performs payout control of prize balls and loan balls by the payout device 76 based on the prize ball command received from the main control device 60.

[0204] The power supply and emission control device 78 is connected to, for example, a commercial power supply (external power supply) in a game hall or the like. And, based on the external power supplied from the commercial power supply, it generates the necessary operating power for the main control board 61, the payout control device 77, etc., respectively, and supplies the generated operating power. Incidentally, the power supply and emission control device 78 is provided with a power supply unit for power failure such as a backup capacitor, and even when the power of the pachinko machine 10 is in the OFF state, power for storage and retention is supplied from the power supply unit for power failure to the main side RAM 65 of the main control device 60 and the payout control device 77. Also, the power supply and emission control device 78 is responsible for the emission control of the game ball emission mechanism 27, and the game ball emission mechanism 27 is driven when predetermined emission conditions are met. Further, as already described, the payout mechanism unit 73 is provided with a power switch, and when the power switch is turned ON, the supply of operating power to the pachinko machine 10 is started, and when the power switch is turned OFF, the supply of operating power to the pachinko machine 10 is stopped.

[0205] The voice and light emission control device 81 drives and controls the speaker unit 53 provided on the front door frame 14 based on various commands received from the main control device 60. Also, as already described, the voice and light emission control device 81 controls the light emission of the LED chips 127 to 142 mounted on the first decorative board 56 and the LED chips mounted on the second decorative board 57. Furthermore, the voice and light emission control device 81 controls the display control device 82. The display control device 82 executes the display control of the symbol display device 41 based on the commands received from the voice and light emission control device 81.

[0206] <Electrical configuration for performing various lotteries by the main side CPU 63> Next, the electrical configuration for performing various lotteries by the main side CPU 63 will be described with reference to FIG. 20.

[0207] During the game, the main CPU 63 uses various counter information to perform jackpot occurrence lottery, setting the display of the special figure display unit 37a, setting the symbol display of the symbol display device 41, setting the display of the normal figure display unit 38a, etc. Specifically, as shown in Fig. 20, a jackpot random number counter C1 used for the lottery of jackpot occurrence, a jackpot type counter C2 used for determining the jackpot type, a reach random number counter C3 used for the reach occurrence lottery when the symbol display device 41 fluctuates out of range, a random number initial value counter CINI used for setting the initial value of the jackpot random number counter C1, and a variation type counter CS for determining the display duration in the special figure display unit 37a and the symbol display device 41 are used. Furthermore, a general electric accessory release counter C4 used for the lottery of whether to set the general electric accessory 34a of the second operation port 34 to the general electric open state is used. Note that the above counters C1 to C3, CINI, CS, and C4 are provided in various counter areas 65b of the main RAM 65.

[0208] Each of the counters C1 to C3, CINI, CS, and C4 is a loop counter that adds 1 to the previous value each time it is updated and returns to "0" after reaching the maximum value. Each counter is updated at short time intervals. Information corresponding to the jackpot random number counter C1, the jackpot type counter C2, and the reach random number counter C3 is stored in a reserved storage area 65a provided as acquisition information storage means in the main RAM 65 when a winning occurs at the first operation port 33 or the second operation port 34.

[0209] The reserved storage area 65a includes a reserved area RE and an execution area AE. The reserved area RE includes a first reserved area RE1, a second reserved area RE2, a third reserved area RE3, and a fourth reserved area RE4. According to the winning history at the first operation port 33 or the second operation port 34, combinations of numerical information of the jackpot random number counter C1, the jackpot type counter C2, and the reach random number counter C3 are stored as reserved information in any of the reserved areas RE1 to RE4.

[0210] In this case, when a winning at the first operation port 33 or the second operation port 34 occurs continuously a plurality of times, the numerical information is stored in time series in the order of the first holding area RE1 → the second holding area RE2 → the third holding area RE3 → the fourth holding area RE4. By providing the four holding areas RE1 to RE4 in this way, the winning history of the game balls at the first operation port 33 or the second operation port 34 can be stored in holding memory up to a maximum of four.

[0211] Note that the number that can be stored in holding memory is not limited to four and can be arbitrary, and can be other plural numbers such as two, three, or five or more, or can be a single number.

[0212] The execution area AE is an area for moving the numerical information stored in the first holding area RE1 of the holding area RE when starting the variable display of the special drawing display unit 37a. At the start of one game round, a win / loss determination or the like is performed based on the various numerical information stored in the execution area AE.

[0213] The above-mentioned counters will be described in detail.

[0214] First, the general power accessory release counter C4 will be described. The general power accessory release counter C4 is configured to be incremented by 1 in order within a range of, for example, 0 to 250, and return to "0" after reaching the maximum value. The general power accessory release counter C4 is updated periodically and is stored in the general power holding area 65c of the main side RAM 65 at the timing when a game ball wins at the through gate 35. Then, at a predetermined timing, a lottery is performed to determine whether to control the general power accessory 34a to an open state based on the value of the stored general power accessory release counter C4.

[0215] In this pachinko machine 10, a plurality of types of support modes are set so that the support modes by the ordinary electric accessory 34a are different from each other. Specifically, in the support modes, when compared with the situation where the shooting of the game balls continues in the same mode in the game area PA, the high-frequency support mode and the low-frequency support mode are set so that the frequency of the ordinary electric accessory 34 of the second operation port 34 being in the open state per unit time is relatively high or low.

[0216] In the high-frequency support mode and the low-frequency support mode, the probability of winning the ordinary electric open state in the ordinary electric open lottery using the ordinary electric open counter C4 is the same (for example, both are 4 / 5). However, in the high-frequency support mode, compared with the low-frequency support mode, the number of times the ordinary electric accessory 34a is in the open state when winning the ordinary electric open state is set to be larger, and further, the opening time for one time is set to be longer. In this case, when winning the ordinary electric open state in the high-frequency support mode and the open state of the ordinary electric accessory 34a occurs multiple times, the closing time from the end of one open state to the start of the next open state is set to be shorter than the opening time for one time. Furthermore, in the high-frequency support mode, compared with the low-frequency support mode, the guaranteed time (that is, the display duration for one time in the general drawing display unit 38a) that is minimally guaranteed when the next ordinary electric open lottery is performed after one ordinary electric open lottery is performed is set to be shorter.

[0217] As described above, in the high-frequency support mode, the probability of winning the second operation port 34 is higher than that in the low-frequency support mode. In other words, in the low-frequency support mode, the probability of winning the first operation port 33 is higher than that of the second operation port 34. However, in the high-frequency support mode, the probability of winning the second operation port 34 is higher than that of the first operation port 33. And when winning the second operation port 34 occurs, a predetermined number of game balls are paid out. Therefore, in the high-frequency support mode, the player can play the game while not reducing the number of balls in hand too much.

[0218] Note that the configuration for making the frequency of the general power release state per unit time higher in the high-frequency support mode than in the low-frequency support mode is not limited to the above, and for example, it may be a configuration for increasing the probability of winning the general power release state in the general power release lottery. Further, in a configuration in which a plurality of types of guaranteed times (for example, the time of the variable display executed by the general drawing display unit 38a based on winning in the through gate 35) are prepared for the next general power release lottery after one general power release lottery is performed, in the high-frequency support mode, a shorter guaranteed time may be more likely to be selected or the average guaranteed time may be set to be shorter than in the low-frequency support mode. Furthermore, by applying any one condition or an arbitrary combination of conditions among increasing the number of release times, increasing the release time, shortening the guaranteed time ensured for the next general power release lottery after one general power release lottery is performed, shortening the average time of such guaranteed times, and increasing the winning probability, the advantage of the high-frequency support mode over the low-frequency support mode may be enhanced.

[0219] Here, as already described, the pachinko machine 10 has setting states of "Setting 1" to "Setting 6". However, the release frequency and release mode of the general power device 34a in the low-frequency support mode are the same regardless of the set value, and the release frequency and release mode of the general power device 34a in the high-frequency support mode are also the same regardless of the set value. However, the present invention is not limited to this, and at least one of the release frequency and release mode of the general power device 34a may vary according to the setting state of the pachinko machine 10 for at least one of the low-frequency support mode and the high-frequency support mode. For example, the higher the set value, the higher the release frequency of the general power device 34a in the low-frequency support mode may be, or the higher the probability of a game ball entering the second operation port 34 when the general power device 34a is in the one-time release state in the low-frequency support mode may be. Also, the higher the set value, the higher the release frequency of the general power device 34a in the high-frequency support mode may be, or the higher the probability of a game ball entering the second operation port 34 when the general power device 34a is in the one-time release state in the high-frequency support mode may be.

[0220] Next, the hit random number counter C1 will be described. The hit random number counter C1 is configured to be incremented by 1 in order within a range of, for example, 0 to 7,999, and to return to "0" after reaching the maximum value. In particular, when the hit random number counter C1 makes one round, the value of the random number initial value counter CINI at that time is read as the initial value of the hit random number counter C1. The random number initial value counter CINI is a loop counter similar to the hit random number counter C1 (value = 0 to 7,999). The hit random number counter C1 is updated periodically and stored in the reserved storage area 65a of the main side RAM 65 at the timing when the game ball wins the first activation port 33 or the second activation port 34.

[0221] The value of the random number for a big win is stored as a hit or miss table in the main side ROM 64. As shown in FIG. 19, a hit or miss table storage area 64a is provided in the main side ROM 64. In the hit or miss table storage area 64a, as a hit or miss table, a low probability hit or miss table for the low probability mode and a high probability hit or miss table for the high probability mode are stored.

[0222] The low probability hit or miss table is provided in one-to-one correspondence with the setting states of "Setting 1" to "Setting 6". That is, the low probability hit or miss table for Setting 1 to be referred to when the setting state of the pachinko machine 10 is "Setting 1", the low probability hit or miss table for Setting 2 to be referred to when the setting state of the pachinko machine 10 is "Setting 2", the low probability hit or miss table for Setting 3 to be referred to when the setting state of the pachinko machine 10 is "Setting 3", the low probability hit or miss table for Setting 4 to be referred to when the setting state of the pachinko machine 10 is "Setting 4", the low probability hit or miss table for Setting 5 to be referred to when the setting state of the pachinko machine 10 is "Setting 5", and the low probability hit or miss table for Setting 6 to be referred to when the setting state of the pachinko machine 10 is "Setting 6" exist.

[0223] These low win / loss tables are set such that the higher the setting value, the higher the winning probability of a jackpot result. Specifically, when the low win / loss table for setting 1 is referenced, the jackpot result occurs at a rate of 1 / 320; when the low win / loss table for setting 2 is referenced, the jackpot result occurs at a rate of approximately 1 / 308; when the low win / loss table for setting 3 is referenced, the jackpot result occurs at a rate of approximately 1 / 278; when the low win / loss table for setting 4 is referenced, the jackpot result occurs at a rate of approximately 1 / 286; when the low win / loss table for setting 5 is referenced, the jackpot result occurs at a rate of approximately 1 / 276; and when the low win / loss table for setting 6 is referenced, the jackpot result occurs at a rate of approximately 1 / 267. As a result, the higher the setting state of the pachinko machine 10, the more likely a jackpot result is to occur in the low probability mode, which is advantageous for the player.

[0224] On the other hand, only one type of high win / loss table is provided so as to be common for any setting state from "setting 1" to "setting 6". The high win / loss table is set such that the winning probability of a jackpot result is higher than that of the low win / loss table for any setting state from "setting 1" to "setting 6". Specifically, when the high win / loss table is referenced, the jackpot result occurs at a rate of approximately 1 / 30. As a result, it becomes possible to make the high probability mode more advantageous than the low probability mode regardless of the setting state of the pachinko machine 10. Also, even in the lowest setting state of "setting 1", by being in the high probability mode, it becomes possible to increase the probability of getting a jackpot result compared to the low probability mode of the highest setting state of "setting 6". In addition, it becomes possible to prevent any advantage or disadvantage due to the setting state of the pachinko machine 10 in the high probability mode, and it becomes possible to reduce the storage capacity for preliminarily storing the high win / loss table in the main side ROM 64.

[0225] The jackpot type counter C2 is configured to be incremented by 1 in sequence within the range of 0 to 29 and return to "0" after reaching the maximum value. The jackpot type counter C2 is updated periodically and stored in the hold storage area 65a at the timing when the game ball wins at the first activation port 33 or the second activation port 34.

[0226] In this pachinko machine 10, a plurality of jackpot results are set. These plurality of jackpot results are set by providing differences in three conditions: (1) the opening / closing control mode of the special electric winning device 32 in the opening / closing execution mode, (2) the lottery mode in the winning / losing lottery means after the end of the opening / closing execution mode, and (3) the support mode in the general electric accessory 34a of the second operation port 34 after the end of the opening / closing execution mode.

[0227] As the opening / closing control mode of the special electric winning device 32 in the opening / closing execution mode, a high-frequency winning mode and a low-frequency winning mode are set so that the frequency of winning in the special electric winning device 32 becomes relatively high or low from the start to the end of the opening / closing execution mode. Specifically, in either the high-frequency winning mode or the low-frequency winning mode, the round games are executed with a predetermined number of rounds as the upper limit.

[0228] A round game is a game that continues until either a predetermined upper limit duration elapses or a predetermined upper number of game balls win in the special electric winning device 32. Also, the number of rounds of the round game in the opening / closing execution mode triggered by the jackpot result is the same fixed number of rounds regardless of the type of jackpot result that triggered the transition. Specifically, the upper limit number of rounds of the round game is set to 15 rounds regardless of which jackpot result occurs.

[0229] Also, in this pachinko machine 10, a plurality of types are set by making the opening duration of the special electric winning device 32 different each time it is opened. Specifically, a long-duration mode set to 29 seconds with a long opening duration and a short-duration mode set to 0.06 seconds, which is shorter than the long duration, are set.

[0230] In this pachinko machine 10, when the firing operation device 28 is being operated by a player, the game ball firing mechanism 27 is driven and controlled so that one game ball is fired toward the game area PA every 0.6 seconds. Also, the upper limit number of end conditions for the round game is set to 9. Then, in the long-time mode among the above opening modes, an opening continuation time longer than the product of the game ball firing cycle and one round game is set. On the other hand, in the short-time mode, an opening continuation time shorter than the product of the game ball firing cycle and one round game, more specifically, shorter than the game ball firing cycle, is set. Therefore, when one opening is performed in the long-time mode, it is expected that winnings corresponding to the upper limit number in one round game will occur for the special electric winning device 32, and when one opening is performed in the short-time mode, it is expected that no winnings will occur for the special electric winning device 32 or, if winnings do occur, they will be about one.

[0231] In the high-frequency winning mode, the special electric winning device 32 is opened once in each round game in the long-time mode. On the other hand, in the low-frequency winning mode, the special electric winning device 32 is opened once in each round game in the short-time mode.

[0232] Note that the number of opening and closing operations of the special electric winning device 32, the number of round games, the opening continuation time for one opening, and the upper limit number in one round game in the high-frequency winning mode and the low-frequency winning mode are not limited to the above values and are arbitrary as long as the frequency of winnings occurring for the special electric winning device 32 from the start to the end of the opening and closing execution mode is higher in the high-frequency winning mode than in the low-frequency winning mode.

[0233] As shown in FIG. 19, the main-side ROM 64 is provided with a distribution table storage area 64b. The distribution table storage area 64b stores a distribution table in which the destination for distributing the jackpot result for the jackpot type counter C2 is set. In the distribution table, as the destination for distributing the jackpot result when a jackpot result occurs, a low-probability jackpot result, a low-win high-probability jackpot result, and a most advantageous jackpot result are set.

[0234] The low-probability jackpot result is a jackpot result in which the opening / closing execution mode becomes the high-frequency winning mode, and after the end of the opening / closing execution mode, the win / loss lottery mode becomes the low-probability mode and the support mode becomes the high-frequency support mode. However, this high-frequency support mode shifts to the low-frequency support mode when the number of game times reaches the end reference number of times (specifically, 100 times) after the shift.

[0235] The low-win high-probability jackpot result is a jackpot result in which the opening / closing execution mode becomes the low-frequency winning mode, and after the end of the opening / closing execution mode, the win / loss lottery mode becomes the high-probability mode and the support mode becomes the high-frequency support mode. These high-probability mode and high-frequency support mode continue until the lottery result in the win / loss lottery becomes a jackpot state win and a transition to the jackpot state occurs.

[0236] The most advantageous jackpot result is a jackpot result in which the opening / closing execution mode becomes the high-frequency winning mode, and after the end of the opening / closing execution mode, the win / loss lottery mode becomes the high-probability mode and the support mode becomes the high-frequency support mode. These high-probability mode and high-frequency support mode continue until the lottery result in the win / loss lottery becomes a jackpot state win and a transition to the jackpot state occurs.

[0237] Note that the normal game state in relation to each of the above game states refers to a state where the opening / closing execution mode is not in effect, the winning / losing lottery mode is the low-probability mode, and the support mode is the low-frequency support mode. Also, as a game result configuration, a low-win high-probability big win result may not be set. Further, in the opening / closing execution mode for the low-win high-probability big win result, the number of rounds of the round game may be less than that in the case of the low-probability big win result and the most advantageous big win result.

[0238] In the distribution table, among the values of the big win type counter C2 from "0 to 29", "0 to 9" correspond to the low-probability big win result, "10 to 14" correspond to the low-win high-probability big win result, and "15 to 29" correspond to the most advantageous big win result.

[0239] There is only one type of distribution table provided to be common regardless of the setting state from "Setting 1" to "Setting 6". This makes it possible to prevent the setting state of the pachinko machine 10 from causing advantages or disadvantages in the distribution mode of the big win result, and also makes it possible to suppress the storage capacity for pre-storing the distribution table in the main-side ROM64.

[0240] Note that the distribution mode of the big win result may vary according to the setting state of the pachinko machine 10. For example, a configuration where the probability of being distributed to the most advantageous big win result is higher for higher setting values may be adopted, or a configuration where the probability of being distributed to the most advantageous big win result or the low-win high-probability big win result is higher for higher setting values may be adopted. In this case, it becomes possible to increase the probability of entering the high-probability mode after achieving a big win result for higher setting values. Also, a configuration where the probability of being distributed to the low-win high-probability big win result is lower for higher setting values may be adopted, or a configuration where it is not distributed to the low-win high-probability big win result for higher setting values but can be distributed to the low-win high-probability big win result for lower setting values may be adopted. In this case, it becomes possible to increase the probability of the opening / closing execution mode of the high-frequency winning mode for higher setting values.

[0241] Next, the reach random number counter C3 will be described. The reach random number counter C3 is configured to be incremented by 1 in sequence within a range of, for example, 0 to 238, and to return to "0" after reaching the maximum value. In this pachinko machine 10, an expected effect is set as a type of display effect in the symbol display device 41. The expected effect refers to a gaming machine equipped with a symbol display device 41 capable of performing variable display of symbols, and in a game round resulting in a predetermined jackpot, the display state that makes the player think that it is a variable display state in which the resulting corresponding result is likely to be given, in the stage before the stop result is derived and displayed after the variable display of the symbols in the symbol display device 41 is started. Specifically, for the resulting corresponding result, a combination of symbols with the same number assigned on any of the valid lines is stopped and displayed.

[0242] Two types of expected effects are set: a reach display and a preview display for expecting the occurrence of the reach display and the occurrence of the resulting corresponding result in the stage before the reach display occurs.

[0243] The reach display includes a display state in which, for some of the symbol columns displayed on the display surface 41a of the symbol display device 41, the symbols are stopped and displayed to display a combination of reach symbols, and in that state, variable display of the symbols is performed in the remaining symbol columns. Also, in the state where the combination of reach symbols is displayed as described above, while performing variable display of the symbols in the remaining symbol columns, a reach effect is performed by displaying a predetermined character or the like as a video on the background screen, or a reach effect is performed by reducing or hiding the combination of reach symbols and then displaying a predetermined character or the like as a video on substantially the entire display surface 41a.

[0244] The preliminary display includes a mode of displaying a character separately from the symbols on the symbol column in the situation where the variable display of symbols starts on the display surface 41a of the symbol display device 41, in the situation where symbols are variably displayed in all symbol columns, or in the situation where symbols are variably displayed in some symbol columns and a plurality of symbol columns. Also included are those that change the background screen to a predetermined mode different from the previous mode, and those that change the symbols on the symbol column to a predetermined mode different from the previous mode. Such a preliminary display can occur in any game round whether or not a reach display is performed, but it is set to occur with a higher probability in the case where a reach display is performed than in the case where a reach display is not performed.

[0245] The reach display is executed regardless of the value of the reach random number counter C3 in a game round where the same combination of symbols is finally stopped and displayed. Also, in a game round corresponding to a jackpot result where the same combination of symbols is not stopped and displayed, it is not executed regardless of the value of the reach random number counter C3. Further, in a game round corresponding to a non-winning result, it is executed when the reach random number counter C3 obtained at a predetermined timing by referring to the reach table stored in the main ROM 64 corresponds to the occurrence of the reach display.

[0246] On the other hand, the decision of whether to perform the preliminary display is not made by the main control device 60, but by the audio-visual control device 81. In this case, the audio-visual control device 81 executes a lottery process for the preliminary display so as to satisfy at least one of the conditions that a preliminary display is more likely to occur in a game round corresponding to any jackpot result than in a game round corresponding to a non-winning result, and that a preliminary display with a low appearance rate is more likely to occur. Incidentally, the result of this lottery is reflected when an effect for the game is executed on the symbol display device 41.

[0247] Here, the probability of the occurrence of the reach display in a game turn resulting in a losing outcome is the same regardless of the setting state among "Setting 1" to "Setting 6". This makes it possible to prevent any advantage or disadvantage due to the setting state of the pachinko machine 10 regarding the probability of the occurrence of the reach display in a game turn resulting in a losing outcome. However, it is not limited to this, and a configuration may be adopted in which the higher the setting value, the higher the probability of the occurrence of the reach display in a game turn resulting in a losing outcome.

[0248] Next, the variable type counter CS will be described. The variable type counter CS is configured to be incremented by 1 in order within a range of, for example, 0 to 198, and return to "0" after reaching the maximum value. The variable type counter CS is used in determining, by the main CPU 63, the display duration in the special figure display unit 37a and the display duration of the symbols in the symbol display device 41. The variable type counter CS is updated once each time the timer interrupt process described later is executed once, and is repeatedly updated even within the remaining time until the next timer interrupt process is executed. Then, the buffer value of the variable type counter CS is acquired when determining the variable pattern at the start of the variable display in the special figure display unit 37a and at the start of the symbol variation by the symbol display device 41.

[0249] <Regarding the processing configuration of the main CPU 63> Next, each process executed by the main CPU 63 to advance the game will be described. Such processes of the main CPU 63 are roughly classified into a main process that is started when the power is turned on and a timer interrupt process that is started periodically (in this embodiment, at a cycle of 4 milliseconds).

[0250] <Main process> First, the main process will be described with reference to the flowchart of FIG. 21.

[0251] In the main process, first, a power-on wait process is executed (step S101). In this power-on wait process, for example, the process waits without proceeding to the next process until a predetermined time for waiting (specifically, 1 second) has elapsed since the main process was started. During the execution period of such a power-on wait process, the operation start and initial setting of the symbol display device 41 will be completed. After that, access to the main-side RAM 65 is permitted (step S102).

[0252] After that, it is determined whether the setting key insertion part 68a is in the ON operation (step S103). When the setting key insertion part 68a is not in the ON operation (step S103: NO), it is determined whether the reset button 68c is being pressed (step S104). When the reset button 68c is being pressed (step S104: YES), except for the area in the main-side RAM 65 where the information of the set value indicating the setting state of the pachinko machine 10 is set, each area of the main-side RAM 65 is cleared to "0" and initial setting is performed on the "0"-cleared area (step S105). That is, when the supply of operating power to the pachinko machine 10 is started while pressing the reset button 68c without the ON operation of the setting key insertion part 68a, the clear process of the main-side RAM 65 is executed while maintaining the information of the set value in the state before the supply of operating power to the pachinko machine 10 is stopped, and initial setting is performed on the storage area where the clear process is executed. As a result, it becomes possible to initialize other areas of the main-side RAM 65 without requiring a change in the set value. Note that in step S105, various registers of the main CPU 63 are also cleared to "0" and then initial setting is performed.

[0253] When the reset button 68c is not being pressed (step S104: NO), it is determined whether the power failure flag is set to "1" (step S106). The power failure flag is provided in the main-side RAM 65, and when the power supply to the main-side CPU 63 is stopped and the predetermined power failure processing is executed normally, the power failure flag is set to "1". When the power failure flag is set to "1", it is determined whether the calculated checksum matches the checksum saved at the time of power-off, that is, the validity of the stored data is determined (step S107). When the process of step S105 is executed, or when an affirmative determination is made in step S107, it is determined whether the set values of the pachinko machine 10 are normal by checking the main-side RAM 65 (step S108). Specifically, when the set value is any one of "Setting 1" to "Setting 6", it is determined to be normal, and when it is "0" or 7 or more, it is determined to be abnormal.

[0254] When a negative determination is made in any of steps S106 to S108, operation prohibition processing is executed. In the operation prohibition processing, after executing error notification processing for notifying the occurrence of an error to the hall manager or the like (step S109), it enters an infinite loop. The operation prohibition processing is released when the all clear processing (step S115) described later is executed.

[0255] When affirmative determinations are made in all of steps S106 to S108, power-on setting processing is executed (step S110). In the power-on setting processing, a predetermined area of the main-side RAM 65 such as initialization of the power failure flag is set to the initial value, and a command corresponding to the current game state is transmitted to the audio-visual control device 81.

[0256] The main CPU 63 is configured to periodically execute timer interrupt processing, but the generation of timer interrupt processing is prohibited at the stage when the main processing is started. The state in which the generation of this timer interrupt processing is prohibited is released at the timing before the processing of step S110 is completed and the processing of step S111 is executed, and the execution of the timer interrupt processing is permitted. Thereby, when the supply of operating power to the main CPU 63 is started, the power-on setting process of step S110 ends, and the timer interrupt processing is not executed until the stage before the processing of step S111 is started. Therefore, until such a situation occurs, the process for advancing the game by the main CPU 63 is not started.

[0257] Thereafter, the process proceeds to the remaining processes of steps S111 to S114. That is, although the main CPU 63 is configured to periodically execute timer interrupt processing, a remaining time will occur between one timer interrupt processing and the next timer interrupt processing. This remaining time will vary according to the processing completion time of each timer interrupt processing, but the remaining processes of steps S111 to S114 are repeatedly executed using such irregular time. In this regard, it can be said that the remaining processes of steps S111 to S114 are non-periodic processes that are executed non-periodically.

[0258] In the residual process, first, in step S111, an interrupt disable setting is performed to prohibit the occurrence of timer interrupt processing. In the subsequent step S112, a random number initial value update process for updating the random number initial value counter CINI is executed, and in step S113, a variable counter update process for updating the variation type counter CS is executed. In these update processes, the current numerical information is read from the corresponding counter in the main-side RAM 65, and after executing the process of adding 1 to the read numerical information, the process of overwriting the original counter is executed. In this case, when the counter value exceeds the maximum value, each is cleared to "0". Then, in step S114, an interrupt enable setting is performed to switch from the state where the occurrence of timer interrupt processing is prohibited to the enabled state. When the process of step S114 is executed, it returns to step S111, and the processes of steps S111 to S114 are repeated.

[0259] On the other hand, when the setting key insertion part 68a is in the ON operation state (step S103: YES), an all clear process is executed (step S115). In the all clear process, all areas of the main-side RAM 65 are cleared to "0", including the area where the information of the setting value indicating the setting state of the pachinko machine 10 is set in the main-side RAM 65, and initial settings are performed on the cleared areas. That is, when an operation for changing the setting state of the pachinko machine 10 is performed, all areas of the main-side RAM 65 are cleared to "0" and initial settings are performed on the storage areas where the clear process has been executed, even if the reset button 68c has not been pressed. Also, in step S115, various registers of the main-side CPU 63 are cleared to "0" and then initial settings are performed. Note that this is not limited thereto, and even when an operation for changing the setting state of the pachinko machine 10 is performed and the reset button 68c has not been pressed, the all clear process of the main-side RAM 65 may not be executed, and the all clear process may be executed when an operation for changing the setting state of the pachinko machine 10 is performed and the reset button 68c has been pressed.

[0260] After executing the setting value update process in step S116, the process proceeds to the process of step S110. In the setting value update process (step S116), first, "1" is set to the setting value counter provided in the main-side RAM 65. The setting value counter is a counter for the main-side CPU 63 to identify which setting value the setting state of the pachinko machine 10 is. When "1" is set to the setting value counter, the setting value becomes "Setting 1" regardless of the previous setting value when the setting value update process is executed. Thereafter, the third notification display device 69c is controlled to display the number "1" corresponding to "Setting 1". The administrator of the game hall can grasp the current setting state of the pachinko machine 10 by checking the third notification display device 69c when changing the setting value. Thereafter, the update execution process is executed.

[0261] In the update execution process, on the condition that the setting key insertion part 68a has not been turned off, it is determined whether the update button 68b has been pressed once. When the update button 68b has been pressed once, the value of the setting value counter in the main-side RAM 65 is incremented by 1. Also, when the value of the setting value counter after the addition of 1 exceeds "6", "1" is set to the setting value counter. Thereby, each time the update button 68b is pressed once, the setting value is updated to the next higher level, and when the update button 68b is pressed once in the situation of "Setting 6", it returns to "Setting 1". In the update execution process, when the value of the setting value counter is updated, the third notification display device 69c is controlled to display the number corresponding to the value of the setting value counter in the main-side RAM 65. The administrator of the game hall can grasp the setting state of the pachinko machine 10 after pressing the update button 68b by checking the third notification display device 69c. In the setting value update process (step S116), the update execution process is repeatedly executed until the OFF operation of the setting key insertion part 68a is performed. When the OFF operation of the setting key insertion part 68a is performed, the display of the setting value on the third notification display device 69c is terminated, and this setting value update process is terminated.

[0262] <Timer Interrupt Process> Next, the timer interrupt process will be described with reference to the flowchart of FIG. 22. The timer interrupt process is executed periodically (for example, at a cycle of 4 milliseconds).

[0263] In the timer interrupt process, first, a power failure information storage process is executed (step S201). In the power failure information storage process, it is monitored whether a power failure signal corresponding to the occurrence of a power cut is received from the power failure monitoring board 67. When the occurrence of a power failure is identified, an infinite loop occurs after executing the power failure process. In the power failure process, a "1" is set in the power failure flag of the main-side RAM 65, and a checksum is calculated and the calculated checksum is saved.

[0264] Thereafter, a lottery random number update process is executed (step S202). In the lottery random number update process, the update of the winning random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the general power accessory release counter C4 is executed. Specifically, the current numerical information is sequentially read out from the winning random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the general power accessory release counter C4, and after executing the process of adding 1 to each of the read numerical information, the process of overwriting the original counter is executed. In this case, when the counter value exceeds the maximum value, it is cleared to "0" respectively. Thereafter, in step S203, a random number initial value update process is executed in the same manner as step S112, and in step S204, a variable counter update process is executed in the same manner as step S113.

[0265] Thereafter, an illegal detection process is executed to monitor whether a predetermined event set as a monitoring target for illegal use has occurred (step S205). In the illegal detection process, the occurrence of a plurality of types of events is monitored, and by confirming that a predetermined event has occurred, a "1" is set in the game stop flag provided in the main-side RAM 65. In the subsequent step S206, it is determined whether the game is in a stopped state by determining whether a "1" is set in the game stop flag. When a negative determination is made in step S206, the processes after step S207 are executed.

[0266] In step S207, port output processing is executed. In the port output processing, when output information is set in the previous timer interrupt processing, processing for performing an output corresponding to the output information to various drive units 32b and 34b is executed. For example, when information for switching the special electric winning device 32 to the open state is set, output of a drive signal to the special electric drive unit 32b is started, and when information for switching to the closed state is set, output of the drive signal is stopped. Also, when information for switching the general electric accessory 34a of the second operating port 34 to the open state is set, output of a drive signal to the general electric drive unit 34b is started, and when information for switching to the closed state is set, output of the drive signal is stopped.

[0267] Thereafter, reading processing is executed (step S208). In the reading processing, signals other than the power failure signal and the winning signal are read, and the read information is stored for use in subsequent processing.

[0268] Thereafter, ball entry detection processing is executed (step S209). In the ball entry detection processing, signals received from the respective ball entry detection sensors 42a to 49a are read, and based on the read result, the presence or absence of ball entry into the out port 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, the second operating port 34, and the through gate 35 is specified.

[0269] Thereafter, timer update processing for collectively updating numerical information of a plurality of types of timer counters provided in the main side RAM 65 is executed (step S210). In this case, timer counters whose stored numerical information is updated by being subtracted are aggregated and handled, but it may also be configured to collectively perform both the update of the subtraction type timer counter and the update of the addition type timer counter.

[0270] Thereafter, a launch control process for controlling the launch of game balls is executed (step S211). In a situation where the launch operation to the launch operation device 28 continues, one game ball is launched at a predetermined launch cycle of 0.6 seconds. In the subsequent step S212, as an input state monitoring process, based on the information read in the reading process of step S208, disconnection confirmation of each ball entry detection sensor 42a to 49a and opening confirmation of the game machine main body 12 and the front door frame 14 are performed.

[0271] Thereafter, a special drawing and special power control process for executing the execution control of the game round and the execution control of the opening / closing execution mode is executed (step S213). The special drawing and special power control process will be described in detail later.

[0272] Thereafter, a normal drawing and normal power control process is executed (step S214). In the normal drawing and normal power control process, when a winning entry to the through gate 35 occurs, a process for acquiring the hold information on the normal drawing side is executed, and when the hold information on the normal drawing side is stored, an opening determination is made for the hold information, and further, a process for performing an effect for the normal drawing is executed based on the result of the opening determination. Also, based on the result of the opening determination, a process for opening and closing the normal power accessory 34a of the second operation port 34 is executed. In this case, if the support mode is the low-frequency support mode, the corresponding process is executed, and if the support mode is the high-frequency support mode, the corresponding process is executed. Also, in the case of the opening / closing execution mode, even if the immediately preceding support mode was the high-frequency support mode, it becomes the low-frequency support mode.

[0273] In the subsequent step S215, based on the processing results of the immediately preceding steps S213 and S214, output information for reflecting the increase or decrease in the number of pending information related to the special drawing display section 37a in the special drawing pending display section 37b is set, and output information for reflecting the increase or decrease in the number of pending information related to the general drawing display section 38a in the general drawing pending display section 38b is set. Also, in step S215, based on the processing results of the immediately preceding steps S213 and S214, output information for updating the display content of the special drawing display section 37a is set, and output information for updating the display content of the general drawing display section 38a is set.

[0274] Thereafter, the content of the commands and signals received from the payout control device 77 is confirmed, and a payout state reception process for performing processing corresponding to the confirmation result is executed (step S216). Also, a payout output process for setting the payout command as an output target is executed (step S217). Also, an external information setting process for controlling the start and end of the output of an external signal according to the processing results of various processes executed in this timer interrupt process is executed (step S218). Thereafter, a management process for displaying information corresponding to the result of the ball entry in the game area PA on the first to third notification display devices 69a to 69c is executed (step S219), and this timer interrupt process is terminated.

[0275] <Special Drawing and Special Electric Control Process> Next, the special drawing and special electric control process of step S213 will be described with reference to the flowchart of FIG. 23.

[0276] First, the process of acquiring hold information is executed (step S301). In the process of acquiring hold information, it is determined whether a winning has occurred at the first operation port 33 or the second operation port 34. If a winning has occurred, it is determined whether the number of holds in the hold storage area 65a is less than the upper limit value (in this embodiment, "4"). If the number of holds is less than the upper limit value, the number of holds is incremented by 1, and the numerical information of the hit random number counter C1, jackpot type counter C2, and reach random number counter C3 updated in the previous step S202 is stored in the first available hold area among the available hold areas RE1 to RE4 in the hold area RE. In addition, when winnings occur simultaneously at the first operation port 33 and the second operation port 34, within the range of executing the process of acquiring hold information once, the process for acquiring the above hold information is executed multiple times. Also, when new hold information is acquired, the corresponding acquisition command is transmitted to the audio-visual control device 81. When the audio-visual control device 81 receives the command, it causes the display of the image indicating the number of hold information in the symbol display device 41 to be updated to the display content corresponding to the increase in hold information.

[0277] After that, the information of the special figure special power counter provided in the main-side RAM 65 is read (step S302), and the special figure special power address table provided in the main-side ROM 64 is read (step S303). Then, the start address corresponding to the information of the special figure special power counter is acquired from the special figure special power address table (step S304), and a jump is made to the process indicated by the acquired start address among the processes of steps S306 to S312 (step S305). The special figure special power counter is a counter for the main-side CPU 63 to grasp which of the various processes of steps S306 to S312 should be executed, and the special figure special power address table has the start address of the program for executing the processes of steps S306 to S312 set corresponding to the numerical information of the special figure special power counter.

[0278] In step S306, the special figure variation start process is executed. FIG. 24 is a flowchart showing the special figure variation start process.

[0279] In the special drawing change start process, on the condition that the number of pending information stored in the pending area RE is 1 or more (step S401: YES), data setting processing is executed (step S402). In the data setting process, first, the number of pendings is decremented by 1, and the data stored in the first pending area RE1 of the pending area RE is moved to the execution area AE. After that, a process of shifting the data stored in each of the pending areas RE1 to RE4 of the pending area RE is executed. This data shift process is a process of shifting the data stored in the first pending area RE1 to the fourth pending area RE4 in order to the lower area side. Specifically, after shifting the data in each area such as the second pending area RE2 → the first pending area RE1, the third pending area RE3 → the second pending area RE2, and the fourth pending area RE4 → the third pending area RE3, the fourth pending area RE4 is cleared to "0". At this time, a shift command for recognizing that the data in the pending area has been shifted is transmitted to the voice and light control device 81. When the voice and light control device 81 receives the command, it updates the display of the image indicating the number of pending information on the symbol display device 41 to the display content corresponding to the decrease in the pending information.

[0280] After executing the data setting process, the pass / fail table is read from the pass / fail table storage area 64a of the main side ROM64 (step S403). As already described, in the pass / fail table storage area 64a, the low-probability pass / fail tables for setting 1 to setting 6 and the high-probability pass / fail table are stored as the pass / fail table. In step S403, first, the current pass / fail lottery mode is grasped by reading the information indicating the pass / fail lottery mode of the main side RAM65. When it is the high-probability mode, the high-probability pass / fail table is read from the pass / fail table storage area 64a. On the other hand, when it is the low-probability mode, the setting state of the pachinko machine 10 is grasped by reading the value of the setting value counter of the main side RAM65. Then, the low-probability pass / fail table corresponding to the grasped setting value is read from the pass / fail table storage area 64a.

[0281] Thereafter, a win / loss determination process is executed with reference to the win / loss table read in step S403 (step S404). In the win / loss determination process, it is determined whether or not numerical information related to the hit random number counter C1, which is information for win / loss determination among the information stored in the execution area AE, matches the jackpot numerical information set in the win / loss table read in step S403.

[0282] If the result of the win / loss determination process is a jackpot winning result (step S405: YES), a distribution determination process is executed (step S406). In the distribution determination process, numerical information related to the distribution determination, that is, numerical information related to the jackpot type counter C2, among the information stored in the execution area AE is read. Then, with reference to the distribution table provided in the distribution table storage area 64b of the main ROM 64, it is specified which jackpot result the read numerical information related to the jackpot type counter C2 corresponds to. Specifically, it is specified which of the low-probability jackpot result, the low-win high-probability jackpot result, and the most advantageous jackpot result it corresponds to.

[0283] Thereafter, a stop result setting process for the jackpot result is executed (step S407). Specifically, information on the pattern state that is finally stopped and displayed on the special figure display unit 37a in the game round related to the start of the current variation is specified from the stop result table for the jackpot result pre-stored in the main ROM 64, and the specified information is written to the main RAM 65. In this stop result table for the jackpot result, information on the pattern state to be stopped and displayed on the special figure display unit 37a is set to be different for each type of jackpot result.

[0284] Thereafter, a flag setting process corresponding to the distribution determination result is executed (step S408). Specifically, flags corresponding to each type of jackpot result are provided in the main RAM 65, and in step S408, "1" is set for the flag corresponding to the result of the distribution determination process in step S406 among the flags corresponding to each type of jackpot result.

[0285] On the other hand, when it is determined in step S405 that the result is not a jackpot winning result, a stop result setting process for a losing result is executed (step S409). Specifically, information on the pattern state to be finally stopped and displayed on the special figure display unit 37a in the game round related to the start of the current variation is specified from the stop result table for losing results stored in advance in the main ROM 64, and the specified information is written into the main RAM 65. The information on the pattern state selected in this case is different from the information on the pattern state selected in the case of a jackpot result.

[0286] After executing either the process of step S408 or step S409, a process for grasping the continuation period of the game round is executed (step S410). In such a process, numerical information of the variation type counter CS is acquired. Also, it is determined whether or not a reach display occurs on the symbol display device 41 in the current game round. Specifically, when the game round related to the start of the current variation is a low-probability jackpot result or a most advantageous jackpot result, it is determined that a reach display occurs. Also, when it is not any jackpot result and the numerical information related to the reach random number counter C3 stored in the execution area AE is numerical information corresponding to the occurrence of a reach, it is determined that a reach display occurs.

[0287] When it is determined that a reach display occurs, the continuation period of the game round corresponding to the numerical information of the current variation type counter CS is acquired with reference to the reach occurrence continuation period table stored in the main ROM 64. On the other hand, when it is determined that a reach display does not occur, the continuation period of the game round corresponding to the numerical information of the current variation type counter CS is acquired with reference to the reach non-occurrence continuation period table stored in the main ROM 64. Incidentally, the continuation period of the game round that can be acquired by referring to the reach non-occurrence continuation period table is different from the continuation period of the game round that can be acquired by referring to the reach occurrence continuation period table.

[0288] Note that the duration of a game round when a reach does not occur is set such that the longer the number of hold information stored in the hold area RE, the shorter the duration of the game round. Also, in a situation where the support mode is the high-frequency support mode, compared to a situation where it is the low-frequency support mode, when the number of hold information is the same, the reach non-occurrence duration table is set so that a shorter game round duration is selected. However, it is not limited to this, and the configuration may be such that the duration of the game round does not vary according to the number of hold information or the support mode, or it may be the reverse of the above relationship. Furthermore, the above configuration may be applied to the duration of a game round when a reach occurs. Also, for each case of various jackpot results, a duration table may be set individually for each case of an off-reach, an off result when a reach does not occur. In this case, the duration of the game round corresponding to each game result will be allocated.

[0289] Thereafter, the information on the duration of the game round obtained in step S410 is set in the special figure special power timer counter provided in the main side RAM65 (step S411). The update of the numerical information set in the special figure special power timer counter is executed in the timer update process (step S210). Incidentally, as an effect for the game, a variable display of the pattern in the special figure display unit 37a and a variable display of the pattern in the pattern display device 41 are performed. When each of these variable displays ends, the stop result of that game round is displayed, and the final stop display is performed for a final stop period (for example, 0.5 seconds) in a state where a predetermined combination of patterns is waiting on the effective line in the pattern display device 41. In this case, the duration of the game round obtained in step S410 is the total time for one game round.

[0290] Thereafter, the variable command and the type command are transmitted to the voice and light control device 81 (step S412). The variable command includes information on the duration of the game round. Here, since the duration of the game round obtained by referring to the non-reach occurrence duration table as described above is different from the duration of the game round obtained by referring to the reach occurrence duration table, even if the variable command does not include information on the presence or absence of a reach, the voice and light control device 81 can specify the presence or absence of a reach from the information on the duration of the game round. In this regard, it can be said that the variable command includes information indicating the presence or absence of a reach. Note that the variable command may directly include information indicating the presence or absence of a reach. Also, the type command includes information on the game result.

[0291] When the voice and light control device 81 receives the variable command and the type command from the main CPU 63, the decorations on the decorative substrates 56 and 57, the speaker unit 53, and the symbol display device 41 are made to perform game-related effects. In this case, the game-related effects are performed in a manner corresponding to the contents of the variable command and the type command. Also, on the symbol display device 41, variable display of symbols is performed as a game-related effect, and when the game-related effect ends, the combination of symbols corresponding to the results of the win / loss determination process and the distribution determination process is stopped and displayed.

[0292] Thereafter, the variable display of the picture on the special figure display unit 37a is started (step S413). Then, the special figure special power counter is incremented by 1 (step S414), and this special figure variable start process is terminated. The numerical information of the special figure special power counter when the special figure variable start process is executed is "0". By adding "1" in step S414, the numerical information of the special figure special power counter becomes "1".

[0293] Returning to the description of the special drawing special power control process (FIG. 23), in step S307, a process during special drawing variation is executed. In the process during special drawing variation, it is determined whether it is during the duration of the game round and before the final stop display timing. If it is before the final stop display, a process for regularly changing the display mode of the pattern in the special drawing display unit 37a is executed. When it becomes the timing to perform the final stop display, the numerical information of the special drawing special power counter is incremented by 1, and the numerical information of the counter is updated from the one corresponding to the process during special drawing variation to the one corresponding to the process during special drawing determination. Note that in this embodiment, the main CPU 63 does not transmit a final stop command to the audio and light emission control device 81.

[0294] In step S308, a process during special drawing determination is executed. In the process during special drawing determination, the display mode of the pattern in the special drawing display unit 37a is set to the display mode corresponding to the lottery result of the current game round. Also, in the process during special drawing determination, it is determined whether the final stop period has elapsed. If the period has elapsed, it is determined whether a transition to the opening / closing execution mode occurs. If the transition to the opening / closing execution mode does not occur, the numerical information of the special drawing special power counter is cleared to "0". If the transition to the opening / closing execution mode occurs, the numerical information of the special drawing special power counter is incremented by 1, and the numerical information of the counter is updated from the one corresponding to the process during special drawing determination to the one corresponding to the special power start process.

[0295] In step S309, the special power supply start process is executed. In the special power supply start process, if the process for starting the opening period in the current opening / closing execution mode has not been executed yet, the setting process for the opening period is executed. Also, an opening command is transmitted to the audio-visual control device 81. The audio-visual control device 81 causes an opening effect to be executed by the decorative substrates 56, 57, the speaker unit 53, and the symbol display device 41 upon receiving the opening command. If the opening period has elapsed, the start process for starting the first round game is executed. In the start process, the special power supply winning device 32 is set to the open state and the end condition for the round game is set. When setting this end condition, the upper limit continuation period when the special power supply winning device 32 is to be continuously set to the open state in the first round game of this time is set, and the upper limit number of game balls that can win the special power supply winning device 32 in the first round game of this time is set to the winning number counter provided in the main side RAM 65.

[0296] In step S310, the special power supply open process is executed. In the special power supply open process, it is determined whether the end condition for the round game is satisfied. If the end condition is satisfied, the special power supply winning device 32 is set to the closed state. Then, if the round game that has ended this time is not the last execution round of the round game, the numerical information of the special figure special power supply counter is incremented by 1 to update the numerical information of the counter from the one corresponding to the special power supply open process to the one corresponding to the special power supply closed process, and if the round game that has ended this time is the last execution round of the round game, the numerical information of the special figure special power supply counter is incremented by 2 to update the numerical information of the counter from the one corresponding to the special power supply open process to the one corresponding to the special power supply end process.

[0297] In step S311, the special power-off closing process is executed. In the special power-off closing process, it is determined whether or not the interval period between round games has elapsed. The interval period is set when the previous round game ends. When the interval period has elapsed, the special power winning device 32 is set to the open state and the end condition of the round game is set. Then, by subtracting 1 from the numerical information of the special figure special power counter, the numerical information of the counter is updated from that corresponding to the special power-off closing process to that corresponding to the special power-open process.

[0298] In step S312, the special power end process is executed. In the special power end process, if the process for starting the ending period in the current opening / closing execution mode has not been executed yet, an ending period (for example, 5 seconds) is set and an ending command is transmitted to the voice and light control device 81. When the voice and light control device 81 receives the ending command, an ending effect is executed by the decorative substrates 56, 57, the speaker unit 53, and the symbol display device 41. When the ending period has elapsed, each of the win / loss lottery mode and the support mode after the end of the opening / closing execution mode is set to the mode corresponding to the jackpot result that triggered the start of the current opening / closing execution mode.

[0299] According to the present embodiment described in detail above, the following excellent effects are achieved.

[0300] In the first decorative substrate 56, the same number (specifically, two) of wiring patterns 172a to 172d are drawn out from a pair of pads 171a and 171b corresponding to a pair of electrodes 85a and 85b of the bypass capacitor 85. Among the four sides of the first pad 171a, the direction (right direction) in which the first wiring pattern 172a is drawn out as viewed from the center of the first pad 171a is the same as the direction (right direction) in which the third wiring pattern 172c is drawn out among the four sides of the second pad 171b as viewed from the center of the second pad 171b. Also, among the four sides of the first pad 171a, the direction (left direction) in which the second wiring pattern 172b is drawn out as viewed from the center of the first pad 171a is the same as the direction (left direction) in which the fourth wiring pattern 172d is drawn out among the four sides of the second pad 171b as viewed from the center of the second pad 171b. Thereby, in the initial stage of heating in the reflow process, it is possible to prevent a difference in temperature distribution within the pair of pads 171a and 171b, and it is possible to prevent the rotation of the bypass capacitor 85 and the occurrence of chip standing.

[0301] The bypass capacitor 85 is a small chip component having a dimension in the longitudinal direction of approximately 0.6 mm, and dimensions in the short-side direction and the thickness direction of approximately 0.3 mm. Since the dimension in the longitudinal direction along the plane orthogonal to the thickness direction of the bypass capacitor 85 is 0.7 mm or less, the area occupied by the bypass capacitor 85 on the first decorative substrate 56 can be reduced. Since the dimension in the longitudinal direction of the bypass capacitor 85 is 0.4 mm or more, the mechanical strength at the connection portion between the bypass capacitor 85 and the first decorative substrate 56 and the mechanical strength of the bypass capacitor 85 itself can be enhanced, the possibility that the connection portion is damaged can be reduced, and the possibility that the bypass capacitor 85 itself is damaged can be reduced. Also, since the dimension in the longitudinal direction of the bypass capacitor 85 is 0.4 mm or more, the confirmation accuracy when visually checking the presence or absence of mounting omission of the bypass capacitor 85 can be enhanced.

[0302] In a configuration where the same number (specifically, one) of wiring patterns 181a and 181b are drawn from a pair of pads 176a and 176b corresponding to a pair of electrodes 87a and 87b of the small chip resistor 87, among the four sides of the first pad 176a, the direction (right direction) in which the first wiring pattern 181a is drawn as seen from the center of the first pad 176a is the same as the direction (right direction) in which the second wiring pattern 181b is drawn as seen from the center of the second pad 176b among the four sides of the second pad 176b. Thereby, it is possible to prevent a difference in temperature distribution within the pair of pads 176a and 176b at the initial stage of heating in the reflow process, and it is possible to prevent the rotation of the small chip resistor 87 and the occurrence of chip standing.

[0303] The small chip resistor 87 is a small chip component whose longitudinal dimension (the longitudinal dimension of the small chip resistor 87) along the longitudinal direction in a plane orthogonal to the thickness direction of the component is 0.1 mm or more and 0.9 mm or less, similar to the bypass capacitor 85. The small chip resistor 87 is a small chip component whose longitudinal dimension is approximately 0.6 mm, and whose lateral dimension and thickness dimension are approximately 0.3 mm. Since the longitudinal dimension of the small chip resistor 87 is 0.7 mm or less, the area occupied by the small chip resistor 87 on the first decorative substrate 56 can be reduced. Since the longitudinal dimension of the small chip resistor 87 is 0.4 mm or more, the mechanical strength at the connection portion between the small chip resistor 87 and the first decorative substrate 56 and the mechanical strength of the small chip resistor 87 itself can be increased, the possibility of damage to the connection portion can be reduced, and the possibility of damage to the small chip resistor 87 itself can be reduced. Also, since the longitudinal dimension of the small chip resistor 87 is 0.4 mm or more, the confirmation accuracy when visually checking the presence or absence of mounting omission of the small chip resistor 87 can be increased.

[0304] The first pad 171a corresponding to the first electrode 85a of the bypass capacitor 85 is electrically connected to the GND plane layer 93 having an area larger than that of the first pad 171a via the first wiring pattern 172a, and the second pad 171b corresponding to the second electrode 85b of the bypass capacitor 85 is electrically connected to the power supply plane layer 94 having an area larger than that of the second pad 171b via the third wiring pattern 172c. The direction (right direction) in which the first wiring pattern 172a is drawn out from the side of the four sides of the first pad 171a when viewed from the center of the first pad 171a is the same as the direction (right direction) in which the third wiring pattern 172c is drawn out from the side of the four sides of the second pad 171b when viewed from the center of the second pad 171b. Thereby, in the initial stage of heating in the reflow process, the possibility of a difference in the temperature distribution within the pair of pads 171a and 171b is reduced.

[0305] The width dimension of the first wiring pattern 172a drawn out from the first pad 171a corresponding to the first electrode 85a of the bypass capacitor 85 is substantially the same as the width dimension of the third wiring pattern 172c drawn out from the second pad 171b corresponding to the second electrode 85b. For this reason, compared with a configuration in which the width dimensions of these wiring patterns 172a and 172c are different, the possibility of a difference in the temperature distribution within the pair of pads 171a and 171b in the initial stage of heating in the reflow process is reduced. Also, the width dimension of the second wiring pattern 172b drawn out from the first pad 171a is substantially the same as the width dimension of the fourth wiring pattern 172d drawn out from the second pad 171b. For this reason, compared with a configuration in which the width dimensions of these wiring patterns 172b and 172d are different, the possibility of a difference in the temperature distribution within the pair of pads 171a and 171b in the initial stage of heating in the reflow process is reduced.

[0306] The width dimension of the first wiring pattern 181a drawn from the first pad 176a corresponding to the first electrode 87a of the small chip resistor 87 is substantially the same as the width dimension of the second wiring pattern 181 drawn from the second pad 176b corresponding to the second electrode 87b. For this reason, compared with a configuration in which the width dimensions of the wiring patterns 181a and 181b drawn from the pads 176a and 176b are different, the possibility of a difference in the temperature distribution within the pair of pads 176a and 176b at the initial stage of heating in the reflow process is reduced.

[0307] Since the number and the drawing positions of the wiring patterns 172a to 172d drawn from the pair of pads 171a and 171b corresponding to the pair of electrodes 85a and 85b of the bypass capacitor 85 are made common, the force acting on the first electrode 85a of the bypass capacitor 85 due to the surface tension of the molten solder on the first pad 171a and the force acting on the second electrode 85b of the bypass capacitor 85 due to the surface tension of the molten solder on the second pad 171b can be balanced. For this reason, even if only the left side portion of the solder paste melts first in the pair of pads 171a and 171b, the movement mode of the bypass capacitor 85 can be made a parallel movement, and the rotation of the bypass capacitor 85 can be prevented. Thereby, the degree of reduction in the connection area due to the solder fillet 173a between the first pad 171a and the first electrode 85a can be suppressed, and the degree of reduction in the connection area due to the solder fillet 173b between the second pad 171b and the second electrode 85b can be suppressed.

[0308] Since the number and extraction positions of the wiring patterns 181a and 181b drawn from the pair of pads 176a and 176b corresponding to the pair of electrodes 87a and 87b of the small chip resistor 87 are made common, the force acting on the first electrode 87a of the small chip resistor 87 due to the surface tension of the molten solder on the first pad 176a and the force acting on the second electrode 87b of the small chip resistor 87 due to the surface tension of the molten solder on the second pad 176b can be balanced. Therefore, even if only the left side portions of the solder pastes of the pair of first pads 176a and second pads 176b are melted first, the movement mode of the small chip resistor 87 can be made a parallel movement, and the rotation of the small chip resistor 87 can be prevented. As a result, the degree of decrease in the connection area due to the solder fillet 177a between the first pad 176a and the first electrode 87a can be suppressed, and the degree of decrease in the connection area due to the solder fillet 177b between the second pad 176b and the second electrode 87b can be suppressed.

[0309] The small chip components (bypass capacitor 85 and small chip resistor 87) are mounted on the first decorative substrate 56 such that the longitudinal direction of the small chip components is parallel to the first direction DR1. The dimension of the first decorative substrate 56 in the first direction DR1 is larger than the dimension of the first decorative substrate 56 in the second direction DR2 that is orthogonal to the first direction DR1. If the small chip components are mounted on the first decorative substrate 56 such that the longitudinal direction of the small chip components is orthogonal to the first direction DR1, when a force that bends the first decorative substrate 56 acts on the first decorative substrate 56 with the boundary line extending in the first direction DR1 as a reference point, there is a risk that a stress that may damage the connection portion between the small chip components and the first decorative substrate 56 acts on the connection portion, and there is also a risk that a stress that may damage the small chip components themselves acts on the small chip components. On the other hand, since the small chip components are mounted on the first decorative substrate 56 such that the longitudinal direction of the small chip components is orthogonal to the first direction DR1, the maximum value of the stress that can act on the connection portion between the small chip components and the first decorative substrate 56 is reduced, and the maximum value of the stress that can act on the small chip components is reduced. Therefore, damage to the connection portion between the small chip components and the first decorative substrate 56 is prevented, and damage to the small chip components themselves is prevented.

[0310] The small chip components (bypass capacitor 97 and small chip resistor 101) are mounted on the second decorative substrate 57 such that the longitudinal direction of the small chip component is parallel to the major axis direction LD. The dimension of the second decorative substrate 57 in the major axis direction LD is larger than the dimension in the minor axis direction SD orthogonal to the major axis direction LD of the second decorative substrate 57. If the small chip component is mounted on the second decorative substrate 57 such that the longitudinal direction of the small chip component is orthogonal to the major axis direction LD, when a force acts on the second decorative substrate 57 to bend the second decorative substrate 57 with the boundary line extending in the major axis direction LD as a reference point, there is a risk that a stress that may damage the connection point acts on the connection point between the small chip component and the second decorative substrate 57, and there is also a risk that a stress that may damage the small chip component itself acts on the small chip component. On the other hand, since the small chip component is mounted on the second decorative substrate 57 such that the longitudinal direction of the small chip component is orthogonal to the major axis direction LD, the maximum value of the stress that can act on the connection point between the small chip component and the second decorative substrate 57 is reduced, and the maximum value of the stress that can act on the small chip component is reduced. Therefore, damage to the connection point between the small chip component and the second decorative substrate 57 is prevented, and damage to the small chip component itself is prevented.

[0311] The electrodes 85a and 85b of the bypass capacitor 85 are fixed to the pads 171a and 171b by solder fillets 173a and 173b. The pads 171a and 171b and the wiring patterns 172a to 172d are integrally formed by etching a copper foil plate. The wiring patterns 172a to 172d drawn from the pads 171a and 171b extend in a direction (short-side direction) orthogonal or substantially orthogonal to the longitudinal direction of the bypass capacitor 85. If the wiring patterns 172a to 172d drawn from the pads 171a and 171b extend in a direction parallel to the longitudinal direction of the bypass capacitor 85, when distortion occurs in the first decorative substrate 56 in the direction of bending the first decorative substrate 56 with reference to a boundary line orthogonal or substantially orthogonal to the long-side direction of the bypass capacitor 85, there is a risk that stress that may damage the connection portion between the bypass capacitor 85 and the first decorative substrate 56 will act on the connection portion, and there is also a risk that stress that may damage the bypass capacitor 85 itself will act on the bypass capacitor 85. On the other hand, by configuring the wiring patterns 172a to 172d drawn from the pads 171a and 171b to extend in a direction orthogonal or substantially orthogonal to the longitudinal direction of the bypass capacitor 85, it is possible to reduce the maximum value of the stress that can act on the connection portion between the bypass capacitor 85 and the first decorative substrate 56 when distortion occurs in the first decorative substrate 56, and it is also possible to reduce the maximum value of the stress that can act on the bypass capacitor 85 itself.

[0312] The electrodes 87a and 87b of the small chip resistor 87 are fixed to the pads 176a and 176b by solder fillets 177a and 177b. The pads 176a and 176b and the wiring patterns 181a and 181b are integrally formed by etching a copper foil plate. The wiring patterns 181a and 181b drawn from the pads 176a and 176b extend in a direction (short side direction) orthogonal or substantially orthogonal to the longitudinal direction of the small chip resistor 87. If the wiring patterns 181a and 181b drawn from the pads 176a and 176b extend in a direction parallel to the longitudinal direction of the small chip resistor 87, when a bending stress that bends the first decorative substrate 56 acts on the first decorative substrate 56 with a line or a substantially orthogonal line orthogonal to the long side direction of the small chip resistor 87 as a boundary, there is a risk that a stress that damages the connection portion may act on the connection portion between the small chip resistor 87 and the first decorative substrate 56, and there is also a risk that a stress that damages the small chip resistor 87 itself may act on the small chip resistor 87. On the other hand, by configuring the wiring patterns 181a and 181b drawn from the pads 176a and 176b to extend in a direction orthogonal or substantially orthogonal to the longitudinal direction of the small chip resistor 87, when distortion occurs in the first decorative substrate 56, the maximum value of the stress that can act on the connection portion between the small chip resistor 87 and the first decorative substrate 56 can be reduced, and the maximum value of the stress that can act on the small chip resistor 87 itself can be reduced.

[0313] The first pad 176a electrically connected to the first electrode 87a of the small chip resistor 87 is electrically connected to the second pad 178b that is electrically connected to the second electrode 142b of the LED chip 142 via the first wiring pattern 181a (see FIG. 8(c)). Further, the second pad 176b electrically connected to the second electrode 87b of the small chip resistor 87 is electrically connected to a pad (not shown) that is electrically connected to the eighth output terminal 162 (FIG. 11) of the LED driver 126 (FIG. 8(a)) via the second wiring pattern 181b. The location where the second wiring pattern 181b is connected to the pad (not shown) corresponding to the eighth output terminal 162 is in the direction of the axis including the drawing direction of the second wiring pattern 181b from the second pad 176b (the right direction in FIGS. 8(a) and (c)) (the second direction DR2 in FIGS. 8(a) and (c)), and is present in the direction opposite to the drawing direction of the second wiring pattern 181b from the second pad 176b with reference to the second pad 176b. After the second wiring pattern 181b is drawn from the second pad 176b in the same direction (right direction) as the drawing direction of the first wiring pattern 181a from the first pad 176a, it is routed to the opposite side with reference to the second pad 176b when viewed in the direction of the axis (the second direction DR2). Even in the configuration where the second wiring pattern 181b is connected to the connection destination at a location where it is present in the direction opposite to the drawing direction of the second wiring pattern 181b from the second pad 176b with reference to the second pad 176b when viewed in the direction of the axis (the second direction DR2), the second wiring pattern 181b is drawn from the second pad 176b in the same direction as the drawing direction of the first wiring pattern 181a from the first pad 176a. Thereby, it is possible to reduce the possibility of a difference in temperature distribution occurring in the pair of the first pad 176a and the second pad 176b in the initial stage of heating in the reflow process.

[0314] A pair of pads corresponding to a pair of electrodes of a small chip component have the same shape and the same size as each other. Therefore, the amount of solder paste applied onto the pair of pads in the solder application process can be made uniform, and the amount of molten solder generated on the pair of pads can be made uniform. As a result, the balance between the force acting on the first electrode of the small chip component due to the surface tension of the molten solder on the first pad and the force acting on the second electrode of the small chip component due to the surface tension of the molten solder on the second pad can be achieved. Thus, rotation of the small chip component and chip standing of the small chip component can be prevented.

[0315] The bypass capacitor 85 is mounted on the first decorative substrate 56 such that the longitudinal direction of the bypass capacitor 85 is parallel to the first direction DR1. A pair of pads 171a, 171b corresponding to a pair of electrodes 85a, 85b of the bypass capacitor 85 are provided so as to be spaced apart in the longitudinal direction of the bypass capacitor 85. Further, the small chip resistor 87 is mounted on the first decorative substrate 56 such that the longitudinal direction of the small chip resistor 87 is parallel to the first direction DR1. A pair of pads 176a, 176b corresponding to a pair of electrodes 87a, 87b of the small chip resistor 87 are provided so as to be spaced apart in the longitudinal direction of the small chip resistor 87. Thus, in a plurality of small chip components (the bypass capacitor 85 and the small chip resistor 87), the separation direction of the pair of pads 176a, 176b is common. Therefore, by transporting the first decorative substrate 56 in a direction orthogonal or substantially orthogonal to the common separation direction in the reflow process, the timing at which heating of the solder paste applied onto a pair of pads 171a, 171b corresponding to a pair of electrodes 85a, 85b of the bypass capacitor 85 is started can be made uniform, and the timing at which heating of the solder paste applied onto a pair of pads 176a, 176b corresponding to a pair of electrodes 87a, 87b of the small chip resistor 87 is started can be made uniform. As a result, generation of rotation and chip standing of the plurality of small chip components can be prevented.

[0316] In a configuration where small chip components (bypass capacitor 85 and small chip resistor 87) are aggregated on the first mounting surface 84 of the first decorative substrate 56, the connectors 111 and 112 are mounted only on the second mounting surface 95 of the first decorative substrate 56. On the first mounting surface 84, the small chip components are arranged avoiding the connector backside corresponding regions 203 and 204 (regions of the first mounting surface 84 corresponding to the regions where the connectors 111 and 112 are mounted on the second mounting surface 95 and the peripheral regions thereof). Thereby, when attaching the harness to the connectors 111 and 112, the maximum value of the tensile stress that can act on the connection portion between the small chip components and the first decorative substrate 56 can be reduced, and the maximum value of the tensile stress that can act on the small chip components themselves can be reduced. Also, when pulling out the harness from the connectors 111 and 112, the maximum value of the compressive stress that can act on the connection portion between the small chip components and the first decorative substrate 56 can be reduced, and the maximum value of the compressive stress that can act on the small chip components themselves can be reduced.

[0317] On the first decorative substrate 56, the small chip components (bypass capacitor 85 and small chip resistors 87 and 143 to 149 (FIG. 11)) are arranged at a distance of 5 mm or more from the outer edges of the fixing through-holes 56d to 56g. The small chip components are not mounted in the through-hole peripheral regions 211a to 211d. By arranging the small chip components at a distance of 5 mm or more from the outer edges of the fixing through-holes 56d to 56g, it is possible to prevent the connection portion between the small chip components and the first decorative substrate 56 from being damaged due to the distortion of the first decorative substrate 56 that may occur in the vicinity of the fixing through-holes 56d to 56g when the first decorative substrate 56 is screwed to the front door frame 14, and it is also possible to prevent the small chip components themselves from being damaged.

[0318] No small chip components are mounted on the LED backside corresponding area 201 on the second mounting surface 95 of the first decorative substrate 56. The LED backside corresponding area 201 is the area of the second mounting surface 95 located on the backside of the area where the LED chips 127 to 142 are mounted on the first mounting surface 84 and the area within 1 mm from the outer edge of the area of the second mounting surface 95. Since no small chip components are mounted on the area of the second mounting surface 95 located on the backside of the area where the LED chips 127 to 142 are mounted on the first mounting surface 84, the influence of the thermal stress that can act on the first decorative substrate 56 due to the heat generation of the LED chips 127 to 142 on the small chip components is reduced. By mounting the small chip components avoiding the LED backside corresponding area 201, it is possible to prevent the connection part between the small chip components and the first decorative substrate 56 from being damaged due to the repeated execution of the light emission effect on the first decorative substrate 56, and it is also possible to prevent the small chip components themselves from being damaged.

[0319] No small chip components are mounted on the driver backside corresponding area 202 of the second mounting surface 95. The driver backside corresponding area 202 is the area of the second mounting surface 95 located on the backside of the area where the LED driver 126 is mounted on the first mounting surface 84 and the area where pads corresponding to the terminals of the LED driver 126 are provided, and the area within 1 mm from the outer edge of the area of the second mounting surface 95. Since no small chip components are mounted on the area of the second mounting surface 95 located on the backside of the area where the LED driver 126 is mounted on the first mounting surface 84 and the area where pads corresponding to the terminals of the LED driver 126 are provided, the influence of the thermal stress that can act on the first decorative substrate 56 due to the heat generation of the LED driver 126 on the small chip components is reduced. By mounting the small chip components avoiding the driver backside corresponding area 202, it is possible to prevent the connection part between the small chip components and the first decorative substrate 56 from being damaged due to the repeated execution of the light emission effect on the first decorative substrate 56, and it is also possible to prevent the small chip components themselves from being damaged.

[0320] In the first decorative substrate 56, the small chip components (bypass capacitor 85 and small chip resistor 87) are arranged at a distance of 1 mm or more from the outer edge of the LED chip 142. By arranging the small chip components at a distance of 1 mm or more from the outer edge of the LED chip 142, the influence of thermal stress on the connection portion between the small chip components and the first decorative substrate 56 can be minimized, and the influence of thermal stress on the small chip components themselves can be minimized. Also, by arranging the small chip components at a distance of 1 mm or more from the outer edge of the LED chip 142, it is possible to prevent the connection portion between the small chip components and the first decorative substrate 56 from being damaged due to thermal stress, and it is possible to prevent the small chip components themselves from being damaged due to thermal stress.

[0321] In the first decorative substrate 56, the small chip components (bypass capacitor 85 and small chip resistor 87) are arranged at a distance of 1 mm or more from the outer edge of the LED driver 126 and the pads corresponding to the terminals of the LED driver 126. By arranging the small chip components at a distance of 1 mm or more from the outer edge of the LED driver 126 and the pads corresponding to the terminals of the LED driver 126, it is possible to prevent the connection portion between the small chip components and the first decorative substrate 56 from being damaged due to thermal stress, and it is possible to prevent the small chip components themselves from being damaged due to thermal stress.

[0322] In the first decorative substrate 56, the small chip components (bypass capacitor 85 and small chip resistor 87, 143 to 149 (FIG. 11)) are arranged avoiding the through-hole peripheral regions 211a to 211d. The through-hole peripheral regions 211a to 211d are regions where the distance from the outer edge of the fixed through-holes 56d to 56g is less than 5 mm. By arranging the small chip components at a distance of 5 mm or more from the outer edge of the fixed through-holes 56d to 56g, it is possible to prevent the connection portion between the small chip components and the first decorative substr...

Claims

1. In a gaming machine including a predetermined substrate on which a first predetermined electronic component and a second predetermined electronic component smaller than the first predetermined electronic component are mounted, the first predetermined electronic component is mounted on a first predetermined plate surface side which is one plate surface side of the predetermined substrate, the second predetermined electronic component is mounted on a second predetermined plate surface side which is opposite to the first predetermined plate surface of the predetermined substrate, in a region on the second predetermined plate surface which is the back side of the region on the first predetermined plate surface where the first predetermined electronic component is mounted, the second predetermined electronic component is not mounted, a specific electronic component larger than the second predetermined electronic component is mounted on the second predetermined plate surface side of the predetermined substrate, the specific electronic component is mounted in a region on the second predetermined plate surface which is the back side of the region on the first predetermined plate surface where the first predetermined electronic component is mounted, as the second predetermined electronic component, a predetermined second predetermined electronic component and a specific second predetermined electronic component are provided, the predetermined second predetermined electronic component is formed such that a longitudinal direction and a lateral direction are generated along a plane orthogonal to the thickness direction of the predetermined second predetermined electronic component, the specific second predetermined electronic component is formed such that a longitudinal direction and a lateral direction are generated along a plane orthogonal to the thickness direction of the specific second predetermined electronic component, the predetermined second predetermined electronic component and the specific second predetermined electronic component are mounted on the predetermined substrate such that the longitudinal direction of the predetermined second predetermined electronic component and the longitudinal direction of the specific second predetermined electronic component are in the same direction, a predetermined control component is mounted on the second predetermined plate surface side of the predetermined substrate, among the plurality of electrodes of the specific second predetermined electronic component, the plurality of connection portions to which the plurality of electrodes are electrically connected include a predetermined connection portion to which a predetermined electrode of the plurality of electrodes of the specific second predetermined electronic component is electrically connected, the predetermined substrate includes a specific connection portion to which a predetermined terminal of the predetermined control component is electrically connected, the predetermined connection portion and the specific connection portion are electrically connected, a control component is not disposed between the predetermined terminal and the specific second predetermined electronic component, the predetermined second predetermined electronic component includes a first predetermined electrode and a second predetermined electrode as a pair of electrodes, the predetermined substrate includes a first predetermined connection portion to which the first predetermined electrode is electrically connected, a first predetermined wiring pattern drawn from the first predetermined connection portion, a second predetermined connection portion to which the second predetermined electrode is electrically connected; a second predetermined wiring pattern drawn out from the second predetermined connection portion; and comprising: The direction in which the side of the first predetermined connection portion from which the first predetermined wiring pattern is drawn out exists when viewed from the center of the first predetermined connection portion is the same as the direction in which the side of the second predetermined connection portion from which the second predetermined wiring pattern is drawn out exists when viewed from the center of the second predetermined connection portion. A gaming machine characterized by this.

2. In a gaming machine including a predetermined substrate on which a first predetermined electronic component and a second predetermined electronic component smaller than the first predetermined electronic component are mounted, the first predetermined electronic component is mounted on a first predetermined plate surface side which is one plate surface side of the predetermined substrate, the second predetermined electronic component is mounted on a second predetermined plate surface side which is the opposite side of the first predetermined plate surface of the predetermined substrate, In the area on the back side of the area where the first predetermined electronic component is mounted on the first predetermined plate surface on the second predetermined plate surface, the second predetermined electronic component is not mounted. The predetermined substrate is provided with a predetermined substrate fixing portion for fixing the predetermined substrate, In an area where the distance from the predetermined substrate fixing portion is less than a predetermined distance, the second predetermined electronic component is not mounted. The first predetermined electronic component is mounted in an area less than the predetermined distance, As the second predetermined electronic component, a predetermined second predetermined electronic component and a specific second predetermined electronic component are provided, The predetermined second predetermined electronic component is formed so as to have a longitudinal direction and a short transverse direction along a plane orthogonal to the thickness direction of the predetermined second predetermined electronic component, The specific second predetermined electronic component is formed so as to have a longitudinal direction and a short transverse direction along a plane orthogonal to the thickness direction of the specific second predetermined electronic component, The predetermined second predetermined electronic component and the specific second predetermined electronic component are mounted on the predetermined substrate such that the longitudinal direction of the predetermined second predetermined electronic component and the longitudinal direction of the specific second predetermined electronic component are in the same direction. A predetermined control component is mounted on the second predetermined plate surface side of the predetermined substrate, Among the plurality of electrodes of the specific second predetermined electronic component, the plurality of connection portions to which the plurality of electrodes of the specific second predetermined electronic component are electrically connected include a predetermined connection portion to which a predetermined electrode of the plurality of electrodes of the specific second predetermined electronic component is electrically connected. The predetermined substrate includes a specific connection portion to which a predetermined terminal of the predetermined control component is electrically connected. The predetermined connection portion and the specific connection portion are electrically connected. A configuration is adopted in which no control component is arranged between the predetermined terminal and the specific second predetermined electronic component. The predetermined second predetermined electronic component includes a first predetermined electrode and a second predetermined electrode as a pair of electrodes. The predetermined substrate includes a first predetermined connection portion to which the first predetermined electrode is electrically connected, a first predetermined wiring pattern drawn from the first predetermined connection portion, a second predetermined connection portion to which the second predetermined electrode is electrically connected, a second predetermined wiring pattern drawn from the second predetermined connection portion, and a gaming machine, characterized in that a direction in which a side of the first predetermined connection portion from which the first predetermined wiring pattern is drawn exists, as viewed from the center of the first predetermined connection portion, is the same as a direction in which a side of the second predetermined connection portion from which the second predetermined wiring pattern is drawn exists, as viewed from the center of the second predetermined connection portion.

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