Image sensor and manufacturing method thereof

Abstract

To provide an inspection system capable of detecting high-energy photons and charged particles.SOLUTION: An image sensor for short-wavelength light and charged particles includes a semiconductor membrane, circuit elements formed on one surface of the semiconductor membrane, and a pure boron layer on the other surface of the semiconductor membrane. This image sensor has high efficiency and good stability even under continuous use at high flux for multiple years. The image sensor may be fabricated using CCD (charge coupled device) or CMOS (complementary metal oxide semiconductor) technology. The image sensor may be a two-dimensional area sensor, or a one-dimensional array sensor. The image sensor can be included in an electron-bombarded image sensor and / or in an inspection system.SELECTED DRAWING: Figure 3G

Description

Technical Field

[0001] Related Applications This application claims priority based on U.S. Provisional Patent Application No. 61 / 622,295, entitled "BACK-ILLUMINATED CCD WITH PURE-BORON COATING FOR EUV AND VUV APPLICATION IN MASK AND WAFER INSPECTION," filed on Apr. 10, 2012 by Chern et al., and U.S. Provisional Patent Application No. 61 / 658,758, entitled "ELECTRON-BOMBARDED CCD AND INSPECTION SYSTEMS USING ELECTRON-BOMBARDED CCD DETECTORS," filed on Jun. 12, 2012 by Chuang et al., both of which are hereby incorporated by reference in their entirety.

[0002] This application also relates to U.S. Patent Application No. 13 / 710,315, filed Dec. 10, 2012, by Chuang et al., entitled "ELECTRON-BOMBARDED CHARGE-COUPLED DEVICE AND INSPECTION SYSTEMS USING EBCCD DETECTORS", which claims priority based on U.S. Provisional Patent Application No. 61 / 569,611, filed Dec. 12, 2011, by Chuang et al., entitled "ELECTRON-BOMBARDED CHARGE-COUPLED DEVICE AND INSPECTION SYSTEMS USING EBCCD DETECTORS". This application also relates to U.S. Provisional Patent Application No. 61 / 735,427, filed Dec. 10, 2012, by Brown et al., entitled "METHOD AND APPARATUS FOR HIGH SPEED ACQUISITION OF MOVING IMAGES USING PULSED ILLUMINATION". All of these applications are hereby incorporated by reference into this document.

[0003] This application relates to image sensors suitable for sensing radiation in the deep ultraviolet (DUV), vacuum ultraviolet (VUV), and extreme ultraviolet (EUV) wavelengths, and methods of fabricating such image sensors. Some embodiments of the sensors are suitable for sensing electrons and other charged particles. All of these sensors are suitable for use in photomask, reticle, or wafer inspection systems. BACKGROUND OF THE INVENTION

[0004] The integrated circuit industry increasingly requires inspection tools with higher resolution in order to resolve novel smaller structures such as integrated circuits, photomasks, reticles, solar cells, charge-coupled devices, etc., and to detect defects having sizes on the order of or smaller than the size of those structures.

[0005] Inspection systems operating at short wavelengths, e.g., wavelengths shorter than about 250 nm, can often provide such resolution. In other cases, electrons or other charged particles, e.g., helium (He) nuclei (i.e., α - particles), etc. can be used. Specifically, for photomask or reticle inspection, it is desirable to perform inspection using a wavelength the same as or close to the wavelength used in lithography, i.e., a wavelength close to 193.4 nm for current - generation lithography and a wavelength close to 13.5 nm for future EUV lithography, because the phase shift of the inspection light caused by the pattern is the same as or very close to the phase shift that occurs during lithography. For inspecting a patterned semiconductor wafer, an inspection system operating over a relatively wide wavelength range such as a wavelength range including wavelengths in the near - ultraviolet, DUV, and / or VUV ranges can be advantageous because the wide wavelength range can reduce the sensitivity to small changes in layer thickness or pattern dimensions that can cause large changes in reflectivity at individual wavelengths.

[0006] To detect small defects or particles on photomasks, reticles, and semiconductor wafers, a high signal - to - noise ratio is required. Since the statistical variation (Poisson noise) of the number of detected photons is the fundamental limit of the signal - to - noise ratio, a high photon or particle flux density is required to ensure a high signal - to - noise ratio in the case of high - speed inspection. Often, more than about 100,000 photons per pixel are required. Since inspection systems are typically used 24 hours a day with only short stops, detectors are exposed to large amounts of radiation even after only a few months of operation.

[0007] Photons with a vacuum wavelength of 250 nm have an energy of approximately 5 eV. The bandgap of silicon dioxide is approximately 10 eV. Photons of such wavelengths do not seem to be absorbed by silicon dioxide, but silicon dioxide grown on the silicon surface has a certain degree of dangling bonds at the interface with silicon because the silicon dioxide structure cannot be perfectly aligned with the silicon crystal structure. Furthermore, since silicon dioxide is amorphous, dangling bonds probably also exist within the material. In fact, a non-negligible density of defects and impurities capable of absorbing photons with deep ultraviolet wavelengths, especially wavelengths shorter than approximately 250 nm, will exist not only in the oxide but also at the interface with the underlying semiconductor. Furthermore, under a high radiation flux density, two high-energy photons may reach near the same position within a very short time interval (nanoseconds or picoseconds), which can generate electrons excited in the conduction band of silicon dioxide by two consecutive absorption events at high speed or two-photon absorption. EUV photons have very high energy (a wavelength of 13.5 nm corresponds to a photon energy close to 92 eV), and can not only break silicon-oxygen bonds, but also strongly interact with defects and contaminants in the oxide. Electron and charged particle detectors usually have to detect electrons or charged particles with energies of several hundred eV or more. Energies greater than 10 eV can easily break silicon-oxygen bonds.

[0008] As described above, high-energy photons and particles can break bonds and ionize atoms in the silicon dioxide layer. Since silicon dioxide is a good insulator, the free electrons generated in silicon dioxide can have a lifetime of milliseconds or longer before recombination. Some of these electrons can move into the semiconductor material. These electrons generate an electric field within the silicon dioxide and at the interface between the silicon dioxide and the semiconductor. These electric fields move the electrons generated in the semiconductor by photon absorption to the surface of the semiconductor, where they recombine, thereby causing signal loss and a reduction in the quantum efficiency of the detector. Since new free charges are generated at the same or greater rate than they recombine, nearly continuous use of the device can mean that there is little or no time for the detector to recover.

[0009] High-energy particles and photons can cause irreversible changes in silicon dioxide. Such changes can include the rearrangement of atomic bonds or the movement of small atoms within the silicon dioxide. Usually, at the normal operating temperature of the detector, which ranges from near room temperature to about 50 °C, these changes will not recover. In particular, conventional silicon photodiodes used as EUV detectors are known to degrade in efficiency with use.

[0010] The silicon dioxide layer on the surface of the semiconductor detector greatly reduces the efficiency of these detectors for low-energy (less than about 2 kV) electrons. Some low-energy electrons are absorbed by the silicon dioxide, thereby charging the silicon dioxide and deflecting later-arriving electrons. Since a native oxide always forms on the exposed silicon surface, silicon detectors necessarily have some oxide on their surface. The growth or deposition of an alternative dielectric material (instead of oxide) on the surface of the semiconductor creates a much higher density of defect states at the silicon dioxide-semiconductor interface. These defects reduce the quantum efficiency of the detector, particularly for photons or charged particles absorbed near the surface of the semiconductor.

[0011] A further cause of EUV sensor degradation is that in an EUV system, a thin layer of carbon deposits over time on any surface exposed to EUV radiation, including the surfaces of the image sensor and optical elements. As this carbon layer thickens, it absorbs EUV radiation, reducing the sensor's sensitivity and the reflectivity of the optical elements in the light path. In EUV systems, all surfaces exposed to EUV are routinely cleaned to remove carbon. This cleaning is typically done using activated hydrogen (a mixture of atomic hydrogen and hydrogen radicals), which is very effective at removing carbon. However, hydrogen radicals can affect the oxides on the surface of silicon detectors and can also cause degradation of the performance of those sensors.

[0012] Diode detectors suitable for detecting EUV and / or electrons are known in the art. Exemplary diode detectors are described in U.S. Patent No. 8,138,485, issued to Nihtianov on March 20, 2012; U.S. Patent No. 7,586,108, issued to Nihtianov on September 8, 2009; U.S. Patent Application Publication No. 2012 / 0268722 (filed by Nihtianov), published on October 25, 2012; and U.S. Patent Application Publication No. 2011 / 0169116 (filed by Nanver), published on July 14, 2011. These diode detectors include a thin layer (1 nm to 20 nm) of boron directly above the silicon surface. U.S. Patent Application Publication No. 2011 / 0169116 further describes a coarse mesh of metal conductors on the surface of such detectors.

Prior Art Documents

Patent Documents

[0013]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

[0014] These prior art detectors have contacts formed on the upper (light or electron incident) surface. The disadvantage of having contacts and conductors on the illuminated surface is that it is impossible to form detectors with a large number (thousands or millions) of detection elements (pixels) while maintaining high detector efficiency. Each detector element requires a plurality of control signals, which are usually shared with other detector elements. For a full well capacity of 100,000 electrons or more, the dimensions of the detector elements can typically range from about 10 μm to 20 μm. It is impossible to create hundreds or thousands of interconnects that connect these control signals to each other and drive the circuit without covering a significant proportion of the surface area. Since DUV, VUV, and EUV photons and low-energy particles do not penetrate layers of conductors such as metals and polysilicon, the areas covered by these conductors have low sensitivity or zero sensitivity.

[0015] Therefore, there is a need for an image sensor that can detect high-energy photons or charged particles while overcoming the above disadvantages. MEANS FOR SOLVING THE PROBLEM

[0016] Methods for manufacturing an image sensor for imaging DUV, VUV, and / or EUV radiation and / or charged particles having high quantum efficiency are described. Image sensors manufactured according to these methods are capable of long-term operation under high fluxes of DUV, VUV, EUV, and / or charged particles. These methods include processing steps of forming photo-sensitive active and / or passive circuit elements in a layer on a semiconductor (preferably silicon) wafer.

[0017] An exemplary method of manufacturing an image sensor includes forming an epitaxial layer on a substrate, and forming a gate layer on the epitaxial layer, where the gate layer includes one or more layers of a dielectric material such as silicon dioxide and silicon nitride; forming circuit elements on the gate layer having polysilicon and a dielectric material but no metal film or metal interconnects; creating a thinned substrate (also referred to herein as a membrane), and thinning the substrate to expose at least a portion of the epitaxial layer; and directly forming a pure boron layer on the exposed portion of the epitaxial layer. In the usage of this document, the term "circuit element" refers to photosensitive devices such as charge-coupled devices and photodiodes, and other semiconductor devices such as transistors, diodes, resistors, and capacitors, and the interconnects (often referred to as interconnects) between them. In this first exemplary embodiment, the circuit elements formed prior to boron deposition do not include any metal interconnects. These circuit elements are formed using standard semiconductor manufacturing processes including, but not limited to, photolithography, deposition, etching, ion implantation, and annealing. Thinning of the sample (e.g., wafer) can be performed using chemical etching and / or polishing. In particular, this thinning can increase the sensitivity of the image sensor to light incident on the back surface. An antireflection coating or a conductive coating can be formed on the boron layer. This antireflection or conductive coating can increase the transmission of the desired wavelength to the image sensor and / or protect the image sensor. In one embodiment, after thinning of the substrate and prior to formation of the boron layer, at least one exposed portion of the epitaxial layer can be doped. After the boron layer is deposited on the back surface, the circuit on the front surface can be completed, including formation of metal interconnects.

[0018] Other ways to manufacture an image sensor include forming an epitaxial layer on a substrate and then forming circuit elements on the epitaxial layer. This step may include the formation of metal interconnects. Either a handling wafer or a protective layer may be formed on the circuit elements. Thereafter, the substrate is thinned so as to expose at least a portion of the epitaxial layer. As described above, this thinning can increase the sensitivity of the image sensor to light incident on the back surface. A pure boron layer is formed on the surface of the epitaxial layer exposed in the thinning process. An anti-reflection coating or a conductive coating may be formed on the boron layer. This anti-reflection or conductive coating can increase the transmission of the desired wavelength to the image sensor and / or protect the image sensor.

[0019] Image sensors with high quantum efficiency and long-life operation for DUV, VUV and / or EUV radiation and / or charged particles are described. Since these image sensors are thinned from the back side, they are very sensitive to radiation or charged particles incident on the back side of the image sensor (where the image sensor is back-illuminated). Deposited directly on the back surface of the epitaxial layer is a thin layer of high-purity amorphous boron (e.g., with a thickness between about 2 nm and about 20 nm). In some embodiments, additional layers of material may be coated on the boron. The thickness and material of each layer can be selected to increase the transmission of the desired wavelength to the image sensor and / or to protect the image sensor.

[0020] The image sensors described in this document can be manufactured using CCD (Charge-Coupled Device) or CMOS (Complementary Metal-Oxide-Semiconductor) technology. The image sensor can be a two-dimensional area sensor or a one-dimensional array sensor.

[0021] An electron bombardment type image sensor is described in this book. The electron bombardment type image sensor includes a photocathode that emits electrons when it absorbs photons or charged particles. The emitted electrons are accelerated towards a solid state image sensor such as a CCD image sensor or a CMOS image sensor. The image sensor includes a pure boron layer directly deposited on a thinned substrate as described above, so that almost all electrons colliding with it are ensured to penetrate the device. This high level of penetration enables the electron bombardment type image sensor to use a low acceleration voltage (for example, an acceleration voltage less than 2 kV or less than 1 kV, etc.), thereby realizing better image resolution and longer sensor life.

[0022] A system for inspecting a sample is also described. This system includes a light source for irradiating the sample and two illumination relays. The image relay optical components are configured to direct the light output of the sample, i.e., reflection and / or transmission, to the image mode relay of the first channel when the light output corresponds to the illumination relay of the first channel, and to the image mode relay of the second channel when the light output corresponds to the illumination relay of the second channel. The sensor is configured to receive the relay outputs of the image mode relays of the first channel and the second channel. The sensor includes a semiconductor film, where circuit elements are formed on one surface of this film, and a boron layer is deposited on the opposite surface of this film. In this configuration, the sensor can simultaneously detect two images of the same sample.

[0023] An exemplary inspection system is also described. This inspection system includes a light source, optical components, and a detector. The optical components are configured to direct and focus radiation from the light source onto the sample. The detector is configured to receive the light reflected or scattered from the sample, where the optical components are further configured to collect, direct, and focus the light reflected or scattered onto the detector. The detector may include one or more image sensors. At least one image sensor includes a semiconductor film, where the semiconductor film includes circuit elements formed on one surface of the semiconductor film, and the boron layer is deposited on the opposite surface of the semiconductor film.

Brief Description of the Drawings

[0024]

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DETAILED DESCRIPTION OF THE INVENTION

[0025] FIG. 1 shows an exemplary technique 100 for manufacturing an image sensor. In step 101, circuit elements can be formed using standard semiconductor processing steps such as lithography, deposition, ion implantation, annealing, and etching. Also, during step 101, CCD and / or CMOS sensor elements and devices can also be formed. These circuit elements are formed in an epitaxial layer on the front surface of the wafer and are thus also referred to as front-side circuit elements. In a preferred embodiment, the epitaxial (epi) layer is about 20 μm to 40 μm thick. In a preferred embodiment, both the epi layer and the substrate are doped with a p-type dopant (e.g., boron), however, the epi layer has a much lower dopant concentration than the bulk wafer (hereinafter and in the figures, p + doping, referred to as), and the epi layer has a very low dopant concentration (hereinafter and in the figures, p -It has (referred to as doping). Typically, the resistivity of the epitaxial layer is about 10 to 100 Ωcm, and the resistivity of the substrate is less than about 0.01 Ωcm. Although polysilicon interconnects can be formed in step 101, metal interconnects are generally not formed because the metal is damaged in subsequent high-temperature processing steps.

[0026] In step 103, the active sensor area or even the entire wafer can be thinned from the back side. This thinning typically includes a combination of polishing and etching to expose the epi layer. In one embodiment, the wafer is polished from the back side until it reaches a thickness of about 200 μm to 300 μm. Then, the front surface and the frame area around the active sensor area are protected with a material such as photoresist or other suitable material. At this time, a chemical etchant is used to etch away the bulk wafer on the active sensor area, thereby exposing the active sensor area. Since the bulk wafer has a much higher dopant concentration and defect density than the epi layer, the etching rate of the bulk semiconductor material is much higher than that of the epi layer. The etching process slows down when it reaches the epi layer, thereby creating a film area with a uniform thickness. In other embodiments, the image sensor wafer is bonded to a handling wafer that can be made of quartz, silicon, sapphire, or other materials. Then, a polishing process is used to polish the entire wafer until only the epi layer remains.

[0027] In step 105, between steps 107 to 111, a protective layer can be deposited on the front surface to protect the front-side circuit elements. In particular, since boron has a tendency to deposit preferentially on silicon, any exposed silicon or polysilicon on the front surface needs to be protected. In some embodiments, step 105 can be performed before step 103 so that the protective layer can provide additional protection to the front surface during the back-side thinning process (step 103). In some embodiments, the protective layer can have a silicon nitride layer deposited using, for example, plasma-enhanced CVD deposition.

[0028] In step 107, the backside surface can be cleaned and prepared for boron deposition. During this cleaning, any contaminants including native oxides, organic compounds, and metals should be removed from the backside surface. In one preferred embodiment, the cleaning can be performed using a diluted HF solution or an RCA cleaning process (which is a well-known set of wafer cleaning steps including removal of organic contaminants, thin oxide layers, and ionic contaminants). After cleaning and during preparation, the wafer is preferably dried using a Marangoni drying technique (a surface tension-based drying technique) or a similar technique to dry the surface and make it watermark-free. In a preferred embodiment, the wafer is protected in a controlled atmosphere (e.g., using dry nitrogen) between steps 107 and 109 to minimize regrowth of native oxides.

[0029] In step 109, the wafer can be held at a high temperature for several minutes in a reducing environment such as diluted hydrogen gas or low-pressure hydrogen gas. In a preferred embodiment, the wafer can be held at a temperature of about 800 °C for about 4 minutes. This high temperature can remove any native oxide layer that may have regrown after step 107.

[0030] In step 111, an amorphous layer of pure boron is deposited on the back surface. In one preferred embodiment, this deposition can be carried out using a mixed gas of diborane and hydrogen gas at a temperature of about 700 to 800 °C to form a high-purity amorphous boron layer. The thickness of the boron layer depends on the intended use for the sensor. Typically, the thickness of the boron layer is between about 2 nm and 20 nm. The minimum thickness is generally limited by the need for a uniform film without pinholes. The maximum thickness generally depends on the absorption of photons or desired charged particles by the boron. Steps 109 and 111 can be carried out in the same process equipment, preferably in the same process chamber, such that steps 109 and 111 can be carried out successively and reliably without the possibility of surface contamination or oxide growth between the steps. Further details regarding boron deposition can be found in Sarubbi et al., "Chemical vapor deposition of a-boron layers on silicon for controlled nanometer-deep p + -n junction formation", J. Electron. Material, vol. 39, pp. 162 - 173, 2010. + -n junction formation”).

[0031] The purity and absence of pinholes in the boron layer are important for the sensitivity and lifetime of the image sensors disclosed herein. If any native oxide film is not removed from the epi-layer surface prior to boron deposition, that native oxide is affected by DUV, VUV, and EUV photons and by charged particles, causing degradation of the sensor performance during use. Even if all native oxides are removed prior to boron deposition, if pinholes are present in the boron layer, after processing, oxygen can reach the epi-layer through those pinholes and oxidize the surface of that layer.

[0032] In some embodiments, during or immediately after step 111, other layers may also be deposited on the boron layer. These other layers may include an anti-reflection coating having one or more materials such as silicon dioxide, silicon nitride, magnesium fluoride, and lithium fluoride. These other layers may also include a protective layer having a thin (a few nm) layer of a refractory metal. Even if the anti-reflection coating may be affected by DUV, VUV, or EUV radiation, the presence of the boron layer between the anti-reflection coating and the epi-layer protects the epi-layer from traps and charges in the anti-reflection coating, ensuring that the sensitivity of the image sensor does not significantly deteriorate.

[0033] In step 113, the front protective layer may be removed or patterned in preparation for the fabrication of the interconnections on the front surface. In some embodiments, since the boron layer is relatively resistant to diluted HF, this removal / patterning may include etching the front surface in diluted HF.

[0034] In step 115, the interconnections on the front surface may be patterned and fabricated. These interconnections may be formed of Al, Cu, or other metals. After the interconnection fabrication is completed, a passivation layer may be deposited on the front surface to protect these interconnections.

[0035] In step 117, the completed circuit element may be packaged. The package may include flip-chip bonding or wire bonding of the chip to a substrate. The package may include a window for transmitting a desired wavelength or may have a flange or seal for the interface to a vacuum seal. In embodiments of an electron bombardment type image sensor, the package may include not only other elements such as a photocathode but also a sealed evacuated tube.

[0036] Figure 2 shows an alternative exemplary technique 200 for manufacturing an image sensor. In this embodiment, the circuit elements can be formed in step 201 using standard semiconductor processing steps including lithography, deposition, ion implantation, annealing, and etching. In one embodiment, CCD and / or CMOS sensor elements and devices can be formed in step 201. These circuit elements are formed in the epitaxial layer on the front surface of the wafer. In a preferred embodiment, the epitaxial layer is about 20 μm to 40 μm thick. The epitaxial layer has a low dopant concentration (p - ). In one embodiment, interconnections such as metal interconnections can also be formed in step 201.

[0037] In step 203, the front surface of the wafer can be protected. This protection can include the deposition of one or more protective layers on top of the circuit elements formed during step 201. This protection can additionally or alternatively include attaching the wafer to a handling wafer such as a silicon wafer, a quartz wafer, or a wafer made of other materials.

[0038] Step 205 includes thinning the wafer from the back side such that the epitaxial layer is exposed, at least within the active sensor area. This step can include polishing, etching, or both. In some embodiments, the entire wafer is thinned from the back side. In other embodiments, only the active sensor area is thinned until the epitaxial layer is reached.

[0039] Step 207 includes cleaning and preparing the back side surface prior to boron deposition. During this cleaning, any contaminants including native oxide, organic compounds, and metals should be removed from the back side surface. In one embodiment, this cleaning can be performed using a diluted HF solution or an RCA cleaning process. After cleaning and during preparation, the wafer can be dried, preferably using a Marangoni drying technique or a similar technique, such that the surface is dry and free of watermarks.

[0040] In step 209, the wafer can be transferred to the deposition equipment in a protective environment, thereby enabling the protection of the wafer during step 211. In one embodiment, for example, the protective environment is a dry nitrogen atmosphere that minimizes the regrowth of native oxides. The time spent to perform step 209 should be kept to a minimum value and is preferably less than about 5 minutes.

[0041] In step 211, boron is deposited on the backside surface of the wafer. In one preferred embodiment, this deposition can be performed using a mixture of diborane and hydrogen gas at a temperature of about 400 - 450 °C, thereby forming a high-purity amorphous boron layer. The thickness of the deposited boron layer depends on the intended use for the sensor. Typically, the thickness of the boron layer is between about 2 nm and 10 nm. The minimum thickness is set by the need for a uniform film without pinholes, while the maximum thickness depends on the absorption of photons or desired charged particles by the boron and, when metal interconnects are on the front side, the longest time the wafer can be held at a high temperature.

[0042] In some embodiments, in step 211, other layers can be deposited on the boron layer. These other layers can include an anti-reflection coating having one or more materials such as silicon dioxide, silicon nitride, magnesium fluoride, and lithium fluoride. These other layers can also include a protective layer having a thin layer of a refractory metal. In some embodiments, the thickness of this refractory metal layer can be between about 1 nm and about 10 nm.

[0043] In one embodiment, the protective front side layer can be removed in step 213. In other embodiments, in step 213, it is possible to drill holes or vias in the protective front side layer, or to expose silicon through vias around the ends of the device, thereby enabling connection to the circuit structure.

[0044] In step 215, the resulting structure can be packaged in a suitable package. The packaging step can have flip-chip bonding or wire bonding of the device to the substrate. The package can include a window for transmitting a desired wavelength or can have a flange or seal for the interface with a vacuum seal. In an embodiment of an electron bombardment type image sensor, the package can include other components such as a photocathode and can have a sealed evacuated tube.

[0045] Figures 3A - 3F show exemplary cross-sections of a wafer according to method 100 (Figure 1). Figure 3A shows an epitaxial (epi) layer 302 formed on the front side of a substrate 301. In one embodiment, the substrate 301 is a p + (i.e., highly p-doped) substrate, and the epi layer 302 is p -It is an epi layer (i.e., a layer having a low concentration of p dopant). FIG. 3B shows a gate oxide layer 303 formed on the epi layer 302, a silicon nitride (Si3N4) gate layer 304 formed on the gate oxide layer 303, and a front-side circuit element 305 (step 101) formed on the gate layer 304. Note that depending on the type of image sensor technology, the gate dielectric may have one, two, or three layers. The formation of the front-side circuit element includes implanting or doping the front-side portion of the epi layer and may also include patterning of the gate layer. FIG. 3C shows the substrate 301 thinned at least in a specific area on its back-side surface to form a thinned substrate 301A (step 103), and a protective layer 305A formed on the front-side circuit element 305 (step 105). FIG. 3D shows an optional doped layer 302A that may be formed in the portion of the epi layer 302 exposed by the thinned substrate 301A. This doping can be formed by ion implantation and subsequent thermal activation, by plasma doping, by plasma-assisted doping, or similar techniques. In one embodiment, this doping can be performed during step 107 as part of the back-side surface preparation and before the high-temperature surface treatment of step 109. FIG. 3E shows a pure boron layer 306 formed on the thinned substrate 301A and the exposed epi layer 302 (step 111). Since a portion of the boron diffuses several nanometers into the epi layer, some embodiments do not need to include a separate doped layer 303A. FIG. 3F shows that after the protective layer 305A is removed or opened (step 113), a front-side metal (i.e., interconnect) 307 can be formed on the front-side circuit element 305. FIG. 3G shows one optional embodiment in which a cap layer 308 can be formed on the boron layer 306. The cap layer 308 can be formed at any time after step 111 (deposition of the boron layer) and before step 117 (packaging).

[0046] FIGS. 4A-4G show cross-sections of an exemplary wafer according to method 120 (FIG. 1B). FIG. 4A shows an epitaxial (epi) layer 402 formed on the front side of a substrate 401. In one embodiment, the substrate 401 is a p + substrate, and the epi layer 402 is a p- It is an epitaxial layer. In one embodiment, the substrate is a silicon-on-insulator (SOI) wafer having a buried oxide layer 402A between the substrate 401 and the epitaxial layer 402. SOI wafers are commercially available from Soitec (Bernin, France) and other suppliers. In other embodiments, the epitaxial layer is grown directly on the substrate 401 without any buried oxide layer 402A. FIG. 4B shows various circuit elements 403 (step 121) including interconnections that can be formed on the epitaxial layer. (Note that the epitaxial layer is shown but not labeled so as not to overly complicate the drawing.) Since the interconnections are formed on the wafer before backside thinning to reach the epitaxial layer, these interconnections can be formed using normal sub-micron CMOS processing techniques and may include multiple layers of high-density metal interconnections. In some embodiments, a plurality of through-silicon vias (TSVs) 403A are formed around one or more ends of the image sensor array to enable connection to the circuit elements 403. FIG. 4C shows a handling wafer 404 attached to the top of the circuit elements 403 (step 123). Note that the through-silicon vias are shown but not labeled so as not to overly complicate the drawing. In other embodiments, a protective layer may be used instead of the handling wafer 404. FIG. 4D shows the wafer after the substrate 401 has been backside thinned to the epitaxial layer 402. In one embodiment, this backside thinning exposes the buried oxide layer 402A. FIG. 4E shows the wafer after cleaning and preparation of the backside surface (step 127), whereby etched oxide 402B is formed that is patterned to protect the TSVs 403A while exposing the epitaxial layer in the image sensor array area. FIG. 4F shows the pure boron layer 406 after being formed on the backside surface of the epitaxial layer 402 (step 131). In some embodiments, an anti-reflection coating or a metal coating or a cap layer (not shown) may be deposited on top of the pure boron layer. FIG. 4G shows the wafer after the etched oxide 402B is removed and replaced with metal pads 407 to enable electrical connection to the TSVs 403A (step 131).

[0047] FIG. 5 shows an exemplary electron impact type image sensor system 501. In this embodiment, the entire assembly can be housed within an encapsulation tube 505 (substantially similar to, for example, the encapsulation tubes of standard image intensifiers and electron bombardment type CCD (EBCCD) devices). The upper surface 507 of the tube 505 can include a window that is transparent at a desired wavelength. For UV-sensitive electron impact type image sensors, this window preferably has high-purity grade quartz, fused silica, or alumina (sapphire). In one preferred embodiment, the outer surface of the window is coated with an anti-UV reflection coating. Such a coating can have a single layer of a low-index material such as MgF2, or can have a multi-layer coating.

[0048] Coating the inner surface of the window, or disposed immediately adjacent to its inner surface, is a photocathode 504. The photocathode material can be substantially similar to any photocathode material known in the art for use in photomultiplier tubes, image intensifiers, or prior art EBCCD detectors. In a preferred embodiment, the photocathode can have one or more alkali metals such as cesium and / or can have a semiconductor such as GaN, GaAs, or silicon. The photocathode 504 can be held at a negative voltage 503 with respect to a solid state image sensor 502 disposed near the bottom surface of the encapsulation tube 505. In some embodiments, the negative voltage 503 can be about 500V, and in other embodiments, it can be several hundred volts or about 1000V. In a preferred embodiment, the negative voltage 503 is between 100V and 1500V.

[0049] The solid-state image sensor 502 can be a thinned CCD or CMOS image sensor oriented such that electrons first impinge on its back surface. The back side of the solid-state image sensor 502 includes a layer of boron deposited directly on the epi-layer of the image array as described above. In some embodiments, a thin (a few nm) layer of a conductive material such as a refractory metal is deposited on the boron layer to prevent charging of the sensor surface. Refractory metals such as titanium, tungsten, tantalum, rhodium, ruthenium, vanadium or chromium have advantages compared to non-refractory metals, which is because the hardness of the refractory metal gives resistance to sputtering by electrons and also because the refractory metal is relatively resistant to oxidation at room temperature. In some embodiments, the solid-state image sensor 502 is a time delay integration (TDI) CCD. In some embodiments, the solid-state image sensor 502 has a linear array of electron sensing elements. In other embodiments, the solid-state image sensor 502 has a two-dimensional array of electron sensing elements. In a preferred embodiment, the solid-state image sensor 502 is held near ground potential (shown).

[0050] When light 510 impinges on the electron bombardment type image sensor system 501, one or more photoelectrons 520 are emitted from the photocathode 504. These photoelectrons are emitted in substantially all directions, but they are accelerated towards the solid-state image sensor 502 by the potential difference between the photocathode 504 and the solid-state image sensor 502. In a preferred embodiment, the gap between the photocathode 504 and the solid-state image sensor 502 is less than 1 mm. In some embodiments, the gap is about 500 μm.

[0051] Since electrons can pass through the boron layer more easily than through the silicon dioxide layer, by incorporating a solid-state image sensor 502 having one of the structures described herein and / or manufactured according to any of the methods described herein, the electron bombardment type image sensor system 501 can operate with a high gain and at a low potential difference between the photocathode 504 and the solid-state image sensor 502. Since all of boron-doped silicon, boride, and boron are at least partially conductive, the charging of the surface under electron bombardment is minimized or avoided. As described herein, the sensitivity to charge can be further reduced by a conductive or metal layer on top of the boron layer.

[0052] In the sensors of prior art EBCCDs, the gap between the photocathode and the image sensor is typically 1 to 2 mm. Such a large gap allows significant lateral motion of the electrons as they travel from the photocathode to the image sensor due to the energy of the electrons when they are emitted from the photocathode. A gap of 1 to 2 mm or more is required due to the large potential difference (typically about 2000 V or more) between the photocathode and the image sensor. By reducing the potential difference between the photocathode and the image sensor, it becomes possible to use a smaller gap. Further, the lower energy of the electrons means that the diffusion of the electrons generated within the solid-state image sensor is small.

[0053] The low energy of the electrons reaching the solid-state image sensor 502 means that the probability of atoms being removed from the surface of the solid-state image sensor 502 is reduced to zero. Further, the energy of the electrons reaching the solid-state image sensor 502 is not sufficient to generate X-rays from silicon, thereby avoiding the generation of spurious signals in the neighboring pixels of the image sensor 502.

[0054] The ions created by the collisions of low-energy electrons with residual gas atoms in the vacuum formed within the sealing tube 505 are fewer compared to the case of high-energy electrons. Further, due to the low potential difference between the photocathode 504 and the solid-state image sensor 502, the kinetic energy when those ions collide with the photocathode is smaller, and less photocathode material is removed.

[0055] Further details of the electron-bombarded image sensor that can be incorporated into the electron-bombarded image sensor 501 can be found in U.S. Patent Application No. 13 / 710,315, filed on December 10, 2012, by Chuang et al., entitled "ELECTRON-BOMBARDED CHARGE-COUPLED DEVICE AND INSPECTION SYSTEMS USING EBCCD DETECTORS", which is incorporated herein by reference. A photocathode structure suitable for use in the electron-bombarded image sensor system 501 is described in U.S. Provisional Patent Application No. 61 / 679,200, filed on August 3, 2012, by Chuang et al., entitled "PHOTOCATHODE WITH LOW NOISE AND HIGH QUANTUM EFFICIENCY, HIGH SPATIAL RESOLUTION LOW-NOISE IMAGE SENSOR AND INSPECTION SYSTEMS INCORPORATING AN IMAGE SENSOR", which is incorporated herein by reference.

[0056] FIG. 6 shows an exemplary drive voltage for the clock signal of any of the image sensors described in this book incorporating a CCD. In a CCD, the charge needs to be transferred from one storage element to another until it reaches the output amplifier. Multiple clock signals are required for the transfer of charge. Depending on the design of the CCD, typically two, three, or four clock signals are required. In one preferred embodiment, rather than the substantially square waveform used in conventional CCD devices, the shape of these clock signals is a sine wave, or a substantially sine wave. The advantage of using a sine wave waveform is that the charge transfer is smoother (which is particularly advantageous for allowing the TDI sensor to track the movement of the image more accurately), and for the harmonic components of the minimum fundamental frequency, the electrical noise and heat generated by the clock signal are reduced. FIG. 6 shows the clock voltage for a three-phase CCD. Clock signal 601 shows the voltage of the first clock signal as a function of time. Clock signal 601 has a substantially sine wave waveform. The second clock signal 602 also changes as a function of time, but has a voltage that is substantially 120° out of phase with respect to clock signal 601. The voltage of the third clock signal 603 also changes as a function of time, but is substantially 120° out of phase with respect to clock signal 602, and thus is substantially 240° out of phase with respect to clock signal 601. Line 604 shows the sum of the three clock signals 601, 602, and 603, which is substantially always zero. A substantially zero sum voltage means that little current flows from the clock signals to the ground signal of the solid-state image sensor 502, and thus a lower electrical noise level is achieved. This is in contrast to the sum of three out-of-phase square wave clock signals, which would have a sum voltage that is substantially non-zero at all times.

[0057] In an image sensor including a two-phase CCD (not shown), the two clock signals are substantially 180° out of phase with each other. In a four-phase CCD (not shown), the second clock signal is substantially 90° out of phase with the first clock signal, the third clock signal is substantially 180° out of phase with the first clock signal, and the fourth clock signal will be substantially 270° out of phase with the first clock signal.

[0058] Further details regarding the use of sine waves and other clock signals to drive a CCD image sensor can be found in U.S. Patent No. 7,952,633, entitled “Apparatus for continuous clocking of TDI sensors” by Brown et al., issued on May 31, 2011, and U.S. Patent No. 7,952,633, entitled “Continuous clocking of TDI sensors” by Brown et al., issued on October 27, 2009. Both of these patents are incorporated herein by reference.

[0059] FIG. 7A shows an exemplary split readout image sensor 700 that includes two sets of readout circuits 701A and 701B disposed on both sides of an image region 703. The image region 703 includes a pure boron layer on its photosensitive surface, as described herein. The readout circuits 701A and 701B may include serial registers 702A and 702B and readout amplifiers 704A and 704B, as well as other components such as transfer gates. Exemplary embodiments of the readout circuits 701A and 701B and other components of the sensor 700 are described in U.S. Patent No. 7,609,309, entitled "Continuous Clocking of TDI Sensors," issued on October 27, 2009, which is incorporated herein by reference. The image region 703 is a two-dimensional (2D) array of pixels, and each line of the image is read out simultaneously in each of directions A and B. Each line is then, in the simplest case, read out one pixel at a time. Thus, in a preferred embodiment, the serial registers 702A and 702B can be divided into a plurality of register segments (e.g., FIG. 7A shows each serial register divided into six segments), thereby enabling parallel readout using a plurality of amplifiers 704A and 704B.

[0060] Note that the readout circuits 701A and 701B can be operated independently, thereby enabling the image sensor 700 to provide two readout directions A and B. In split readout mode, each side of the image region 703 (i.e., sides 703A and 703B) can be clocked synchronously, and one image line can be read out to each of their respective output channels. In one embodiment, the image region 703 may have 1000 lines where each line is formed by a row of pixels. Thus, during split readout mode, 500 lines can be read out in direction A and simultaneously 500 lines can be read out in direction B.

[0061] This split readout mode is possible based on the timing activation of the charge-coupled device (CCD) driver of the image sensor. For example, a plurality of CCD drivers P1a, P2a, P3a, P1b, P2b, and P3b may be used to provide phases. As shown in FIG. 7B, the CCD drivers P1a, P2a, P3a, P1b, P2b, and P3b may be characterized as a driving set of gate electrodes (hereinafter referred to as gates), where each set has six gates. In one preferred embodiment of the image sensor, three gates are provided for each pixel to provide three phases. FIG. 7B shows two pixels 710 and 711, where gates 731, 732, and 733 are disposed on pixel 710, and gates 734, 735, and 736 are disposed on pixel 711. In the image sensor, pixels 710 and 711 are aligned along the readout axis and form part of a column of a 2D array of pixels that form image region 703.

[0062] The image area 703 can be implemented as an optical sensor or a charged particle sensor. In one embodiment of an optical sensor, the image area 703 can include a photosensitive p-type silicon substrate 714 and an n-type buried channel type 713. The electrostatic force within the silicon substrate 714 is determined by the voltage level applied to a specific gate by a clock input signal (e.g., one of the clock signals from CCD drivers P1a, P2a, P3a, P1b, P2b, and P3b). A high-level voltage induces the formation of a potential "well" under the gate, while a low-level voltage forms a potential barrier against the movement of electrons. To ensure that the charge from one pixel does not mix with other pixels, the gate voltage is made high when the adjacent gate voltage is made low. In the initial state at time 770, the gates 731 and 734 of pixels 710 and 711 respectively have a high-level voltage that forms a potential well by the integrated charge (i.e., electrons), and the gates 732, 733 (of pixel 710) and 735, 736 (of pixel 711) have a low-level voltage that forms a potential barrier. At a subsequent time 721, the gates 732 and 735 of pixels 710 and 711 respectively have a high-level voltage that forms a potential well by the integrated charge (i.e., electrons), and the gates 731, 733 (of pixel 710) and 734, 736 (of pixel 711) have a low-level voltage that forms a potential barrier. At a further subsequent time 771, the gates 733 and 736 of pixels 710 and 711 respectively have a high-level voltage that forms a potential well by the integrated charge (i.e., electrons), and the gates 731, 732 (of pixel 710) and 734, 735 (of pixel 711) have a low-level voltage that forms a potential barrier. It should be noted that it is preferable for adjacent gates to both have a high-level voltage for a short time to facilitate charge transfer when shifting the charge. Thus, from time 770 to time 771, the charge is shifted from left to right, i.e., from pixel 710 to pixel 711. From time 771 to time 772, a similar directional movement of the charge can occur.

[0063] Further details of the split readout image sensor 700 are provided in U.S. Provisional Patent Application No. 61 / 735,427, filed December 10, 2012, by David Brown et al., entitled "METHOD AND APPARATUS FOR HIGH SPEED ACQUISITION OF MOVING IMAGES USING PULSED ILLUMINATION", which is incorporated herein by reference. Further details regarding other exemplary image sensors are provided in U.S. Patent No. 7,528,943, issued May 5, 2009, to Brown et al., entitled "METHOD AND APPARATUS FOR SIMULTANEOUS HIGH-SPEED ACQUISITION OF MULTIPLE IMAGES", which is incorporated herein by reference.

[0064] FIG. 8 shows a reticle, photomask, or wafer inspection system 800 that simultaneously detects two channels of an image or signal on one sensor 870. The image sensor 870 has a split readout image sensor as described above. The light source 809 may incorporate a 193 nm or sub-200 nm laser. The two channels may have reflected and transmitted intensities when the object 830 being inspected is transmissive (e.g., a reticle or photomask), or may have two different illumination modes, such as, for example, the angle of incidence, polarization state, wavelength range, or any combination thereof. The light is directed to the object 830 to be inspected using the illumination relay 815 for channel 1 and the illumination relay 820 for channel 2.

[0065] The object to be inspected 830 can be a reticle, a photomask, a semiconductor wafer, or other article to be inspected. The image relay optical component 840 can direct light reflected and / or transmitted by the object to be inspected 830 to the image mode relay 855 of channel 1 and the image mode relay of channel 2. The image mode relay 855 of channel 1 is adjusted to detect the reflection / transmission corresponding to the illumination relay 815 of channel 1, while the image mode relay sensor 860 of channel 2 is adjusted to detect the reflection / transmission corresponding to the illumination relay 820 of channel 2. The image mode relay 855 of channel 1 and the image mode relay sensor 860 of channel 2 then direct their outputs to the sensor 870. Data corresponding to the signals or images detected for the two channels is presented as data 890 and transmitted to a computer (not shown) for processing.

[0066] Other details of reticle and photomask inspection systems and methods that can be configured to measure light transmitted and, reflected from a reticle or photomask are described in U.S. Patent No. 7,352,457 issued to Kvamme et al. on April 1, 2008 and U.S. Patent No. 5,563,702 issued to Emery et al. on October 8, 1996, both of which are incorporated herein by reference.

[0067] FIG. 9 shows an exemplary detector assembly 900 incorporating an image sensor 904, a silicon interposer 902, and other electronic devices according to a particular embodiment of the present invention.

[0068] In one aspect of the present invention, the detector assembly 900 can include one or more photosensitive sensors 904 disposed on the surface of the interposer 902. In some embodiments, one or more interposers 902 of the assembly 100 can include, but are not limited to, silicon interposers. In a further aspect of the present invention, one or more photosensitive sensors 904 of the assembly 900 are backside thinned and configured for backside illumination, including a boron layer deposited on the back surface as described above.

[0069] In other aspects of the present invention, the various circuit elements of the assembly 900 can be disposed on or incorporated into the interposer 902. In one embodiment, one or more amplifier circuits (e.g., a charge conversion amplifier) (not shown) can be disposed on or incorporated into the interposer 902. In other embodiments, one or more conversion circuits 908 (e.g., an analog-to-digital conversion circuit, i.e., digitizer 908) can be disposed on or incorporated into the interposer 902. In other embodiments, one or more driver circuits 906 can be disposed on or incorporated into the interposer 902. For example, one or more driver circuits 906 can include a timing / serial drive circuit. For example, one or more driver circuits 906 can include, but are not limited to, a clock driver circuit or a reset driver circuit. In other embodiments, one or more decoupling capacitors (not shown) can be disposed on or incorporated into the interposer 902. In still other embodiments, one or more serial transmitters (not shown in FIG. 9) can be disposed on or incorporated into the interposer 102.

[0070] In another aspect of the present invention, one or more support structures can be disposed between the bottom surface of the photosensitive array sensor 904 and the top surface of the interposer 902 to provide physical support for the sensor 904. In one embodiment, a plurality of solder balls 916 can be disposed between the bottom surface of the photosensitive array sensor 904 and the top surface of the interposer 902 to provide physical support for the sensor 904. The imaging region of the sensor 904 may not include external electrical connections, but it is recognized herein that the backside thinning of the sensor 904 may cause the sensor 904 to become more flexible. Thus, solder balls 916 can be utilized to connect the sensor 904 to the interposer 902 in a manner that reinforces the imaging portion of the sensor 904. In an alternative embodiment, an underfill material can be disposed between the bottom surface of the photosensitive array sensor 904 and the top surface of the interposer 902 to provide physical support for the sensor 904. For example, an epoxy resin can be disposed between the bottom surface of the photosensitive array sensor 904 and the top surface of the interposer 902.

[0071] In another aspect of the present invention, the interposer 902 and various additional circuits (e.g., amplifier circuits, driver circuit 906, digitizer circuit 908, etc.) are disposed on the surface of the substrate 910. In a further aspect, the substrate 910 includes a substrate having a high thermal conductivity (e.g., a ceramic substrate). In this regard, the substrate 910 is configured to provide physical support to the sensor 904 / interposer 902 assembly while providing means for efficiently conducting away heat from the imaging sensor 904 and various other circuits (e.g., digitizer 906, driver circuit 908, amplifier, etc.) to the assembly 900. It is recognized herein that the substrate can include any rigid high thermal conductivity substrate material known in the art. For example, the substrate 910 can include, but is not limited to, a ceramic substrate. For example, the substrate 110 can include, but is not limited to, aluminum nitride.

[0072] In other embodiments, the substrate 910 may be configured to provide an interface to a socket or underlying printed circuit board (PCB). For example, as shown in FIG. 9, the substrate 910 may provide an interconnection between the interposer 902 and the socket or PCB via the interconnection 912. Those skilled in the art will recognize that the substrate 910 is operatively coupled to the underlying PCB and may be further electrically coupled to the socket or PCB in various ways that are all construed to be within the scope of the present invention.

[0073] Further details of a detector assembly incorporating an image sensor, a silicon interposer, and other electronic circuits can be found in U.S. Patent Application No. 13 / 622,155, filed September 18, 2012, by Brown et al., entitled "INTERPOSER BASED IMAGING SENSOR FOR HIGH-SPEED IMAGE ACQUISITION AND INSPECTION SYSTEMS", which is incorporated herein by reference.

[0074] FIG. 10 shows an exemplary sensor module array 1000 that includes a plurality of time delay integration (TDI) sensor modules 1001. Each sensor module 1001 includes one of the above-described image sensors. In some embodiments, the image sensor may have a coating of Ru or other heat-resistant metal with a thickness of several nm (such as 1 or 2 nm, etc.) on top of the boron to protect the boron during cleaning. In one embodiment, each TDI sensor module 1001 may include localized drive and signal processing circuitry. This circuitry may include a TDI sensor (central block), processing circuitry for processing signals from the TDI sensor, timing and serial drive circuitry, and pixel gate driver circuitry. The drive / processing circuitry is disposed around the TDI sensor. Thus, adjacent rows of TDI sensors may be aligned such that at least 100% image coverage is achieved when used in a continuous scan arrangement.

[0075] For example, in the embodiment shown in FIG. 10, the upper row 1002 may be offset with respect to the lower row 1004 such that the TDI sensors are disposed within gaps formed by drive / processing circuits in adjacent rows. To ensure image coverage without gaps, the width of each TDI sensor is the same as or greater than the spacing between the TDI sensors. In this arrangement, when the wafer / mask / reticle being inspected moves in the TDI image scan direction 1006, the sensor module array 1000 can ensure 100% image capture at EUV wavelengths. In one embodiment, a certain minimum overlap between TDI sensors from adjacent rows can provide redundant data. This redundant data can ensure, for example, accurate alignment of the image data generated by the TDI sensor module 1001. In one embodiment of the minimum overlap, the inspection system can arbitrarily select data from one TDI sensor module used for the end pixels. In other embodiments, the detection system can combine and align data from multiple TDI sensor modules using sub-pixel digital processing to obtain improved quality data in the vicinity of the end pixels.

[0076] Further details of the EUV inspection system detector array can be found in U.S. Patent Application Publication No. 2011 / 0116077, entitled "EUV High Throughput Inspection System for Defect Detection on Patterned EUV Masks, Mask Blanks, and Wafers", published on May 19, 2011, by Chuang et al., which is incorporated herein by reference.

[0077] FIG. 11 shows an exemplary inspection system 1100 configured to measure a sample 1108 such as a wafer, reticle, or photomask. The sample 1108 is placed on a stage 1112 to facilitate movement to different regions of the sample 1108 under the optical components. The stage 1112 may have an X-Y stage or an R-θ stage. In some embodiments, the stage 1112 may adjust the height of the sample 1108 for focus maintenance during inspection. In other embodiments, the objective lens 1105 may be adjusted for focus maintenance.

[0078] The light source 1102 may have one or more lasers and / or broadband light sources. The light source 1102 may emit DUV and / or VUV radiation. The optical components 1103 including the objective lens 1105 may direct the radiation towards the sample 1108 and focus it onto the sample 1108. The optical components 1103 may also have mirrors, lenses, and / or beam splitters. The light reflected or scattered from the sample 1108 may be collected, directed, and focused by the optical components 1103 onto the detector 1106 within the detector assembly 1104.

[0079] The detector 1106 may include one or more image sensors described herein, including an electron bombardment type image sensor incorporating a boron-coated back-illuminated CCD sensor, a boron-coated back-illuminated CMOS sensor, and a boron-coated back-thinned solid-state image sensor. The detector 1106 may include a two-dimensional array sensor or a one-dimensional line sensor. In one embodiment, the output of the detector 1106 may be provided to a computing system 1114 that analyzes the output. The computing system 1114 may be configured by program instructions 1118 that may be stored on a carrier medium 1116.

[0080] In one embodiment, the light source 1102 can be a continuous light source such as an arc lamp, a laser-excited plasma light source, or a CW laser. In other embodiments, the light source 1102 can be a pulsed light source such as a mode-locked laser, a Q-switched laser, or a plasma light source excited by a Q-switched laser. In some embodiments of the inspection system 1100 incorporating a Q-switched laser, the (one or more) image sensors in the detector 1106 are synchronized with the laser pulses. In such embodiments, the image sensors can operate in TDI mode during the laser pulses and then read out data via a plurality of outputs on both sides of the sensor in the middle of the laser pulses.

[0081] Some embodiments of the inspection system 1100 illuminate a line on the sample 1108 and collect the light scattered and / or reflected in one or more dark-field and / or bright-field collection channels. In such embodiments, the image sensor can be a line sensor or an electron-bombarded type line sensor.

[0082] Some embodiments of the inspection system 1100 illuminate a plurality of points on the sample 1108 and collect the light scattered and / or reflected in one or more dark-field and / or bright-field collection channels. In such embodiments, the image sensor can be a two-dimensional array sensor or an electron-bombarded type two-dimensional array sensor.

[0083] Further details of various embodiments of inspection system 1100 incorporating one or more images described herein can be found in U.S. Provisional Patent Application No. 61 / 506,892, entitled "SAMPLE INSPECTION SYSTEM," filed Jul. 12, 2011 by Romanovsky et al., U.S. Patent Application No. 13 / 554,954, entitled "WAFER INSPECTION SYSTEM," filed Jul. 9, 2012 by Romanovsky et al., U.S. Patent Application Publication No. 2009 / 0180176, published Jul. 16, 2009 by Armstrong et al., U.S. Patent Application Publication No. 2007 / 0002465, published Jan. 4, 2007 by Chuang et al., U.S. Patent No. 5,999,310, issued Dec. 7, 1999 by Shafer et al., and U.S. Patent No. 7,525,649, issued Apr. 28, 2009 by Leong et al. All of these patents and patent applications are incorporated herein by reference.

[0084] The various embodiments of the structures and methods of the present invention described above are illustrative only of the principles of the present invention and are not intended to limit the scope of the present invention to the specific embodiments described. For example, additional steps can be added to the flowcharts shown in FIGS. 1 and 2, or some of the steps shown can be performed in an order different from the order shown. Accordingly, the present invention is limited only by the following claims and their equivalents. It is noted that the embodiments include the following. (1) A method of manufacturing an image sensor, the method comprising: forming an epitaxial layer on a substrate; forming a gate layer on the substrate; forming a circuit element layer on the gate layer; thinning the substrate to create a thinned substrate, the thinned substrate exposing at least a portion of the epitaxial layer; forming a pure boron layer on the exposed portion of the epitaxial layer; A method having... (2) The method according to (1) above, further comprising the step of forming an antireflection coating on the pure boron layer. (3) The method according to (1) above, further comprising the step of forming a conductive layer on the pure boron layer. (4) The method according to (1) above, further comprising the step of forming a protective layer on the circuit element layer. (5) After the step of thinning the substrate and before the step of forming the pure boron layer, the method according to (1) above, further comprising the step of doping at least one of the exposed portions of the epitaxial layer. (6) A method for manufacturing an image sensor, the method comprising: forming an epitaxial layer on a substrate; forming a circuit element on the epitaxial layer; attaching a handling wafer to the circuit element; thinning the substrate to expose the epitaxial layer; forming a pure boron layer on the exposed surface of the epitaxial layer; A method having... (7) The method according to (6) above, further comprising the step of forming an antireflection coating on the pure boron layer. (8) The method according to (6) above, further comprising the step of forming a conductive layer on the pure boron layer.

Claims

1. An image sensor that senses at least one of deep ultraviolet (DUV) radiation, vacuum ultraviolet (VUV) radiation, extreme ultraviolet (EUV) radiation, and charged particles, wherein the image sensor comprises: A semiconductor film comprising an epitaxial layer including a first surface and an opposite second surface, the semiconductor film having a circuit element formed on the first surface and a pure boron layer formed on the second surface.

2. The image sensor according to claim 1, wherein the epitaxial layer has a thickness exceeding about 20 μm.

3. The image sensor according to claim 2, further comprising a doped layer formed on the second surface of the film.

4. The image sensor according to claim 1, wherein the pure boron layer has a thickness between 2 nm and 20 nm.

5. The image sensor according to claim 1, further comprising an antireflection coating deposited on the boron layer.

6. The image sensor according to claim 1, further comprising a conductive coating deposited on the boron layer to form a cap layer.

7. The image sensor according to claim 1, further comprising a handling wafer attached to the circuit element.

8. The image sensor according to claim 1, further comprising a protective layer formed on the circuit element.

9. The image sensor according to claim 4, wherein the image sensor has a charge-coupled device (CCD) or a CMOS device.

10. A method of manufacturing an image sensor, the method comprising: Forming an epitaxial layer on a substrate; Forming a gate layer on the substrate; Forming a circuit element layer on the gate layer; Thinning the substrate to create a thinned substrate that exposes at least a portion of the epitaxial layer; Forming a pure boron layer on the exposed portion of the epitaxial layer. And a method having the above steps.

11. The method according to claim 10, further comprising forming an antireflection coating on the pure boron layer.

12. The method according to claim 10, further comprising forming a conductive layer on the pure boron layer.

13. The method according to claim 10, further comprising forming a protective layer on the circuit element layer.

14. The method according to claim 10, further comprising the step of doping at least one of the exposed portions of the epitaxial layer after the step of thinning the substrate and before the step of forming the pure boron layer.

15. A method of manufacturing an image sensor, the method comprising: forming an epitaxial layer on a substrate; forming circuit elements on the epitaxial layer; attaching a handling wafer to the circuit elements; thinning the substrate to expose the epitaxial layer; forming a pure boron layer on the exposed surface of the epitaxial layer; A method having the above steps.

16. The method according to claim 15, further comprising the step of forming an anti-reflection coating on the pure boron layer.

17. The method according to claim 15, further comprising the step of forming a conductive layer on the pure boron layer.

Images