Signal processing device, signal processing method, and program

Abstract

To execute signal processing in a state where noise is included, without conducting spectrum analysis.SOLUTION: A signal processing device executes signal processing in accordance with a neural network. The signal processing device includes an input layer, an intermediate layer, and an output layer. The intermediate layer acquires one or more intermediate input signals corresponding to input signals, and generates a plurality of intermediate signals based on the one or more intermediate input signals. The output layer acquires a plurality of intermediate output signals and outputs output signals corresponding to the plurality of intermediate output signals. The intermediate layer includes N intermediate neurons and a plurality of intermediate synapses. Each of the intermediate synapses generates a corresponding intermediate signal of the plurality of intermediate signals in accordance with a state value outputted from any one of the N intermediate neurons. The N intermediate neurons include P types that are different in update rules.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to a signal processing apparatus, a signal processing method, and a program.

Background Art

[0002] It has been proposed to detect anomalies in time-series data measured by continuously operating medical devices or infrastructure facilities. It has also been proposed to perform such detection of anomalies in time-series data using artificial intelligence in a terminal device provided near a medical device or infrastructure facilities. By detecting anomalies in the terminal device, for example, the amount of data transmitted to the cloud can be suppressed. However, the computing resources available to the terminal device are limited. Therefore, the terminal device must detect anomalies using artificial intelligence with a low computational cost.

[0003] In addition, time-series data measured by medical devices or infrastructure facilities may have noise superimposed depending on the measurement location. When detecting anomalies from time-series data with noise superimposed, the detection accuracy decreases. Therefore, for example, when an information processing device detects anomalies from time-series data with noise superimposed, it must perform spectral analysis such as fast Fourier transform on the time-series data to remove the noise. However, spectral analysis has a very high computational cost. Therefore, when detecting anomalies in time-series data in a terminal device provided near a medical device or infrastructure facilities, it has been difficult to perform noise removal using spectral analysis.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005]

Non-Patent Document 1

Non-Patent Document 2

Non-Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0006] The problem to be solved by the present invention is to execute signal processing in a state including noise without performing spectrum analysis on an input signal by a digital processing circuit even when the input signal includes noise.

Means for Solving the Problems

[0007] The signal processing device according to the embodiment executes signal processing according to a neural network. The signal processing device includes an input layer, an intermediate layer, and an output layer. The input layer acquires M input signals (M is an integer of 1 or more). The intermediate layer acquires one or more intermediate input signals corresponding to the M input signals, and generates a plurality of intermediate signals based on the one or more intermediate input signals. The output layer acquires a plurality of intermediate output signals, and outputs an output signal corresponding to the plurality of intermediate output signals. The intermediate layer includes N intermediate neurons (N is an integer of 2 or more) each of which outputs a state value, and a plurality of intermediate synapses that generate the plurality of intermediate signals. Each of the plurality of intermediate synapses generates a corresponding intermediate signal among the plurality of intermediate signals according to the state value output from any one of the N intermediate neurons. Each of the plurality of intermediate output signals is a signal corresponding to the state value output from any one of the N intermediate neurons. Each of the N intermediate neurons changes the state value according to a predetermined update rule over time according to at least one of the one or more intermediate input signals and the plurality of intermediate signals. The N intermediate neurons include P types (P is an integer of 2 or more and N or less) with different update rules.

Brief Description of Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Embodiments for Carrying Out the Invention

[0009] (First Embodiment) First, the signal processing device 10 according to the first embodiment will be described.

[0010] FIG. 1 is a diagram showing the configuration of the signal processing device 10 according to the first embodiment.

[0011] The signal processing device 10 according to the first embodiment acquires a time-series input signal and outputs an output signal representing an abnormal component included in the input signal.

[0012] The signal processing device 10 may execute signal processing by digital operations using a computer, or may execute signal processing by an analog circuit or a digital circuit. Further, in the signal processing device 10, a digital circuit and an analog circuit may be mixed. The signal processing device 10 may acquire a digital input signal or an analog input signal. The digital input signal may be a signal representing digital values with a predetermined number of resolutions, a signal representing binary values, or a signal representing discrete values of two or more at each sampling time. The analog input signal may be a signal whose level represents a continuous value, or a signal whose pulse width changes according to the level.

[0013] The signal processing device 10 executes signal processing according to a neural network. More specifically, the signal processing device 10 executes signal processing according to a recurrent neural network.

[0014] In the present embodiment, the signal processing device 10 executes processing according to a neural network including an input layer 22, an intermediate layer 24, an input-intermediate synapse part 26, an output layer 28, and an intermediate-output synapse part 30.

[0015] The input layer 22 acquires an input signal. The input layer 22 includes input neurons 40. The input neurons 40 change an input state value represented by a real number according to the passage of time in accordance with the input signal. Then, the input neurons 40 output the input state value to the input-intermediate synapse part 26. Note that the input neurons 40 may output the value of the input signal as the input state value as it is.

[0016] The intermediate layer 24 acquires one or more intermediate input signals corresponding to the input signal via the input-intermediate synapse part 26. The intermediate layer 24 generates a plurality of intermediate signals based on the acquired one or more intermediate input signals.

[0017] The intermediate layer 24 includes N intermediate neurons 42 and a plurality of intermediate synapses 44. N is an integer of 2 or more.

[0018] Each of the N intermediate neurons 42 stores a state value and outputs the state value. In the present embodiment, the state value represents a binary value of 0 or 1. Note that the state value may be a continuous value or a discrete value of two or more values.

[0019] The plurality of intermediate synapses 44 generate a plurality of intermediate signals. The plurality of intermediate synapses 44 correspond one-to-one to the plurality of intermediate signals generated in the intermediate layer 24. Each of the plurality of intermediate synapses 44 generates a corresponding intermediate signal among the plurality of intermediate signals according to the state value output from any one of the N intermediate neurons 42.

[0020] More specifically, an intermediate synapse load is set for each of the plurality of intermediate synapses 44. The intermediate synapse load is represented by either a positive real value, a negative real value, or zero. The intermediate synapse load may be a continuous value or a discrete value of two or more values.

[0021] For each of the plurality of intermediate synapses 44, any one of the N intermediate neurons 42 is set as the previous neuron, and any one of the N intermediate neurons 42 is set as the subsequent neuron. The previous neuron and the subsequent neuron may be the same. Each of the plurality of intermediate synapses 44 outputs, as a corresponding intermediate signal among the plurality of intermediate signals, a signal obtained by multiplying the state value output from the previous neuron, which is any one of the N intermediate neurons 42, by the set intermediate synapse load, to any one of the N intermediate neurons 42, which is the subsequent neuron.

[0022] Note that, so that a recurrent neural network is configured, the previous neuron and the subsequent neuron connected to each of the plurality of intermediate synapses 44 are set in the intermediate layer 24. That is, for at least one of the N intermediate neurons 42, an intermediate signal is fed back from the other intermediate neuron 42 to which the state value output by itself has been propagated via one or more intermediate synapses 44.

[0023] In this embodiment, the intermediate layer 24 includes (N×N) intermediate synapses 44 as a plurality of intermediate synapses 44. The (N×N) intermediate synapses 44 correspond to (N×N) combinations of a front-stage neuron and a rear-stage neuron, which are realized by N intermediate neurons 42.

[0024] Also, at least a part of the plurality of intermediate synapses 44 may update the set intermediate synapse weights over time. For example, at least a part of the plurality of intermediate synapses 44 may update the intermediate synapse weights according to, for example, spike-timing-dependent plasticity (STDP). Also, at least a part of the plurality of intermediate synapses 44 may update the intermediate synapse weights according to, for example, the Fusi rule (SDSP rule). Details of STDP and the Fusi rule will be described later. Each of the plurality of intermediate synapses 44 may have the intermediate synapse weights randomly set at the start or the like, and may not update the intermediate synapse weights after being set.

[0025] In this embodiment, each of the N intermediate neurons 42 acquires at least one of one or more intermediate input signals output from the input-intermediate synapse unit 26 and a plurality of intermediate signals generated by the plurality of intermediate synapses 44. Each of the N intermediate neurons 42 changes a state value over time based on a predetermined update rule according to at least one of one or more intermediate input signals and a plurality of intermediate signals. Then, each of the N intermediate neurons 42 outputs the stored state value.

[0026] The input - intermediate synapse part 26 includes one or more input - intermediate synapses 46. The one or more input - intermediate synapses 46 correspond one - to - one to one or more intermediate input signals output to the intermediate layer 24. For each of the one or more input - intermediate synapses 46, an input - intermediate synapse weight is set. The input - intermediate synapse weight is represented by either a positive real value, a negative real value, or zero. The input - intermediate synapse weight may be a continuous value or a discrete value of two or more values.

[0027] For each of the one or more input - intermediate synapses 46, an input neuron 40 is set as the previous - stage neuron, and any one of the N intermediate neurons 42 included in the intermediate layer 24 is set as the next - stage neuron. For each of the one or more input - intermediate synapses 46, a signal obtained by multiplying the input state value output from the previous - stage neuron by the set input - intermediate synapse weight is output to the next - stage neuron as the corresponding intermediate input signal among the one or more intermediate input signals.

[0028] In the present embodiment, the input - intermediate synapse part 26 includes N input - intermediate synapses 46 as the one or more input - intermediate synapses 46. The N input - intermediate synapses 46 correspond one - to - one to the N intermediate neurons 42. Each of the N input - intermediate synapses 46 outputs an intermediate input signal to the corresponding intermediate neuron 42 among the N intermediate neurons 42.

[0029] Here, in the present embodiment, each of the N intermediate neurons 42 changes the state value over time according to at least one of one or more intermediate input signals and a plurality of intermediate signals, and a constancy signal that changes the state value in the direction of the target value with a set intensity.

[0030] More specifically, when the intermediate layer 24 performs digital processing, the N intermediate neurons 42 output a state value as shown in Equation (1).

Equation

[0031] t is an integer that increases by 1 each time and is an index representing time.

[0032] X(t) and X(t - 1) represent matrices with N rows and 1 column. X(t) contains N state values output from N intermediate neurons 42 at time t. X(t - 1) contains N state values output from N intermediate neurons 42 at time (t - 1). The state value of the nth intermediate neuron 42 (where n is an integer from 1 to N) among the N intermediate neurons 42 is included in the nth row of X(t) and X(t - 1).

[0033] W (in) represents a matrix with N rows and 1 column. W (in) contains N input - intermediate synapse weights set for N input - intermediate synapses 46. The input - intermediate synapse weight set for the input - intermediate synapse 46 with the nth intermediate neuron 42 among the N input - intermediate synapses 46 having the subsequent neuron is included in the nth row of W (in)

[0034] u(t) represents the input signal at time t.

[0035] W (res) represents a matrix with N rows and N columns. W (res) contains (N×N) intermediate synapse weights set for (N×N) intermediate synapses 44. The element in the mth row and nth column of W (res) contains the intermediate synapse weight set for the intermediate synapse 44 where the nth intermediate neuron 42 among the N intermediate neurons 42 is the previous neuron and the mth intermediate neuron 42 is the subsequent neuron (where m is an integer from 1 to N).

[0036] T IP (t) represents a matrix with N rows and 1 column. T IP (t) contains the values of N constancy signals used for N intermediate neurons 42 at time t. The value of the constancy signal for the nth intermediate neuron 42 is included in the nth row of T IP (t).​

[0037] V threshold represents a predetermined real value.

[0038] θ(A) represents an activation function with A as an argument. In this embodiment, the activation function is a step function. Note that the activation function may be a Heaviside function.

[0039] The constancy signal is represented by Equation (2).

Equation

[0040] T IP (t - 1) includes the values of N constancy signals at time (t - 1).

[0041] Target IP represents an N-row, 1-column matrix. Target IP includes N target values set for N intermediate neurons 42. The target value of the nth intermediate neuron 42 is the IP nth row of Target IP,n and is represented as.

[0042] η IP represents an N-row, 1-column matrix. η IP represents N set intensities set for N intermediate neurons 42. Each of the N set intensities is a real number. The set intensity of the nth intermediate neuron 42 is the IP nth row of η IP,n and is represented as.

[0043] Such a constancy signal functions to change the state value in the direction of the target value with the set intensity over time. For example, the constancy signal acts on the state value like a spring that vibrates with a predetermined spring force (set intensity) to position an object at a steady position (target value).

[0044] When the intermediate layer 24 processes an analog signal, when the intermediate layer 24 processes multi-valued discrete values, or when the intermediate layer 24 processes a continuous-valued digital signal, the N intermediate neurons 42 output state values as shown in Equation (3).

Equation

[0045] α represents the leakage rate and is a real value greater than 0 and less than 1. tanh(A) is an activation function with A as the argument and is the hyperbolic tangent function. Note that Equation (3) may be another function such as a sigmoid function, ReLU function, Softmax function, or identity function instead of the hyperbolic tangent function.

[0046] Thus, in this embodiment, each of the N intermediate neurons 42 generates an internal state value based on at least one of one or more intermediate input signals and a plurality of intermediate signals and a constancy signal, and generates a state value by applying the internal state value to an activation function. Also, in each of the N intermediate neurons 42, since the constancy signal changes the state value in the direction of the target value with the set intensity, for example, even if the input signal is constant, the state value can be changed over time.

[0047] Furthermore, in this embodiment, the N intermediate neurons 42 include P types with different predetermined update rules. P is an integer of 2 or more and N or less. That is, each of the N intermediate neurons 42 is of one of the P types.

[0048] In this embodiment, the update rule for each of the N intermediate neurons 42 corresponds to the arithmetic expression of the constancy signal. More specifically, in this embodiment, each of the P types of intermediate neurons 42 has a constancy signal different from that of other types of intermediate neurons 42. More specifically, for example, each of the P types of intermediate neurons 42 has η which is the adjustment intensity in Equation (3) IP or Target which is the target valueIP The value of

[0049] η, which is the adjustment intensity IP may be 0. However, for η IP which is the adjustment intensity, when it is 0, no matter what value the target value Target IP is, the value of the constancy signal will be 0. Therefore, when η IP which is the adjustment intensity, is 0, no matter what value the target value Target IP is, the constancy signals will be the same.

[0050] For example, the example in FIG. 1 shows the case where P = 3. In the example of FIG. 1, each of the N intermediate neurons 42 is of either the first type, the second type, or the third type. The first type of intermediate neuron 42 (IP1) has a target value Target IP,1 of -0.1 and an adjustment intensity η IP,1 of 10 -4 . The second type of intermediate neuron 42 (IP2) has a target value Target IP,2 of 1 and an adjustment intensity η IP,2 of 10 -4 . The third type of intermediate neuron 42 (IP3) has a target value Target IP,2 of 1 and an adjustment intensity η IP,2 of 10 -5 .

[0051] Even when the same signal is input to each of these P types of intermediate neurons 42 and they store the same state value, when the state value changes over time, they can output different state values from other types.

[0052] The output layer 28 acquires a plurality of intermediate output signals via an intermediate-output synapse section 30. Each of the plurality of intermediate output signals is a signal corresponding to a state value output by any one of N intermediate neurons 42 acquired via the intermediate-output synapse section 30. Then, the output layer 28 outputs an output signal corresponding to the plurality of intermediate output signals.

[0053] In the example of FIG. 1, the output layer 28 acquires, as a plurality of intermediate output signals, N intermediate output signals corresponding to N state values output from N intermediate neurons 42. That is, the N intermediate output signals correspond one-to-one to the N intermediate neurons 42. Accordingly, each of the N intermediate output signals is a signal corresponding to the state value output from the corresponding intermediate neuron 42 among the N intermediate neurons 42.

[0054] The output layer 28 includes P output neurons 50, a plurality of output synapses 52, and a final output neuron 54.

[0055] The P output neurons 50 correspond one-to-one to P types of intermediate neurons 42 included in the N intermediate neurons 42. In the example of FIG. 1, the output layer 28 includes, as the P output neurons 50, a first output neuron 50-1, a second output neuron 50-2, and a third output neuron 50-3. The first output neuron 50-1 corresponds to the first type of intermediate neuron 42 (IP1). The second output neuron 50-2 corresponds to the second type of intermediate neuron 42 (IP2). The third output neuron 50-3 corresponds to the third type of intermediate neuron 42 (IP3).

[0056] Each of the P output neurons 50 outputs a combined signal representing an output state value obtained by linearly combining the state values of one or more corresponding types of intermediate neurons 42 among the N intermediate neurons 42. The output state value is represented by a real number.

[0057] More specifically, each of the P output neurons 50 acquires one or more intermediate output signals corresponding to the state values output from each of one or more intermediate neurons 42 of the corresponding type among the N intermediate neurons 42 via the intermediate-output synapse section 30. Each of the P output neurons 50 changes the output state value in accordance with the passage of time according to the acquired one or more intermediate output signals. For example, each of the P output neurons 50 sets the value obtained by adding the acquired one or more intermediate output signals as the output state value. Then, each of the P output neurons 50 outputs a coupling signal representing the output state value.

[0058] For example, in the example of FIG. 1, the first output neuron 50-1 outputs a first coupling signal obtained by linearly combining the state values output from each of one or more intermediate neurons 42 (IP1) of the first type. The second output neuron 50-2 outputs a second coupling signal obtained by linearly combining the state values output from each of one or more intermediate neurons 42 (IP2) of the second type. The third output neuron 50-3 outputs a third coupling signal obtained by linearly combining the state values output from each of one or more intermediate neurons 42 (IP3) of the third type.

[0059] The plurality of output synapses 52 correspond to any one of the P output neurons 50. An output synapse load is set for each of the P output synapses 52. The output synapse load is represented by a positive real value or a negative real value. Also, the output synapse load may be a signed continuous value or a signed discrete value of two or more values. Each of the plurality of output synapses 52 outputs a signal obtained by multiplying the coupling signal output from the corresponding output neuron 50 among the P output neurons 50 by the preset output synapse load.

[0060] In this embodiment, the output layer 28 includes P output synapses 52 as a plurality of output synapses. Each of the P output synapses 52 has a corresponding output neuron 50 among the P output neurons 50 set as the previous-stage neuron and the final output neuron 54 set as the subsequent-stage neuron. Then, each of the P output synapses 52 outputs a signal obtained by multiplying the connection signal output from the previous-stage neuron by the set output synapse load to the subsequent-stage neuron.

[0061] For example, in the example of FIG. 1, the output layer 28 includes, as P output synapses 52, a first output synapse 52-1, a second output synapse 52-2, and a third output synapse 52-3. The first output synapse 52-1 outputs a signal obtained by multiplying the first connection signal output from the first output neuron 50-1 by the set output synapse load to the final output neuron 54, which is the subsequent-stage neuron. The second output synapse 52-2 outputs a signal obtained by multiplying the second connection signal output from the second output neuron 50-2 by the set output synapse load to the final output neuron 54, which is the subsequent-stage neuron. The third output synapse 52-3 outputs a signal obtained by multiplying the third connection signal output from the third output neuron 50-3 by the set output synapse load to the final output neuron 54, which is the subsequent-stage neuron.

[0062] Here, the first output synapse 52-1, which is any one of the plurality of output synapses 52, outputs a signal obtained by inverting the sign of the first connection signal output from the first output neuron 50-1 by multiplying the set output synapse load.

[0063] Also, any second output synapse 52-2 different from the first output synapse 52-1 among the plurality of output synapses 52 outputs a signal that does not invert the sign of the second connection signal output from the second output neuron 50-2.

[0064] That is, the output synapse load set for the first output synapse 52-1 and the output synapse load set for the second output synapse 52-2 are represented by real numbers with inverted signs. Note that the absolute value of the output synapse load set for the first output synapse 52-1 and the absolute value of the output synapse load set for the second output synapse 52-2 may be the same or different.

[0065] Also, among the plurality of output synapses 52, the output synapses 52 other than the first output synapse 52-1 and the second output synapse 52-2 may or may not invert the positive and negative of the connection signal output from the corresponding output neuron 50.

[0066] The final output neuron 54 adds the signals output from each of the plurality of output synapses 52 to generate an output signal, and outputs the generated output signal. That is, the final output neuron 54 generates and outputs an output signal by linearly combining the connection signals output from each of the P output neurons 50.

[0067] Note that the final output neuron 54 may output an output signal obtained by further performing an activation function operation on the value obtained by adding the signals output from each of the plurality of output synapses 52. Also, the final output neuron 54 may output an output signal binarized by a preset threshold value with respect to the value obtained by adding the signals output from each of the plurality of output synapses 52, or the value obtained by performing an activation function operation.

[0068] The intermediate-output synapse part 30 includes a plurality of intermediate-output synapses 56. The plurality of intermediate-output synapses 56 correspond one-to-one to the plurality of intermediate output signals output from the intermediate layer 24 to the output layer 28.

[0069] Each of the plurality of intermediate-output synapses 56 acquires a state value output from any one of the N intermediate neurons 42. A synaptic weight for each of the plurality of intermediate-output synapses 56 is set. The synaptic weight for the intermediate-output synapse is represented by either a positive real value, a negative real value, or zero. The synaptic weight for the intermediate-output synapse may be a continuous value or a discrete value of two or more values.

[0070] Each of the plurality of intermediate-output synapses 56 outputs, as a corresponding intermediate output signal among the plurality of intermediate output signals, a signal obtained by multiplying the state value output from a preceding neuron, which is any one of the N intermediate neurons 42, by the set synaptic weight for the intermediate-output synapse. Further, each of the plurality of intermediate-output synapses 56 outputs the corresponding intermediate output signal to an output neuron 50 among the P output neurons 50 that corresponds to the type of the preceding neuron.

[0071] More specifically, for each of the plurality of intermediate-output synapses 56, any one of the N intermediate neurons 42 is set as the preceding neuron, and an output neuron 50 among the P output neurons 50 that corresponds to the type of the preceding neuron is set as the succeeding neuron. For example, in the example of FIG. 1, for the intermediate-output synapse 56 in which the first type of intermediate neuron 42 (IP1) is set as the preceding neuron, the first output neuron 50-1 is set as the succeeding neuron. For the intermediate-output synapse 56 in which the second type of intermediate neuron 42 (IP2) is set as the preceding neuron, the second output neuron 50-2 is set as the succeeding neuron. For the intermediate-output synapse 56 in which the third type of intermediate neuron 42 (IP3) is set as the preceding neuron, the third output neuron 50-3 is set as the succeeding neuron. Then, each of the plurality of intermediate-output synapses 56 outputs, as a corresponding intermediate output signal among the plurality of intermediate output signals, a signal obtained by multiplying the state value output from the preceding neuron by the set synaptic weight for the intermediate-output synapse, to the succeeding neuron.

[0072] In this embodiment, the intermediate-output synapse unit 30 includes, as a plurality of intermediate-output synapses 56, N intermediate-output synapses 56 that correspond one-to-one to N intermediate neurons 42. Each of the N intermediate-output synapses 56 has the corresponding intermediate neuron 42 among the N intermediate neurons 42 as the preceding neuron.

[0073] Here, the intermediate-output synapse weights set for each of the plurality of intermediate-output synapses 56 are set to optimal values in advance by learning. The intermediate-output synapse weights set for each of the plurality of intermediate-output synapses 56 are such that when a normal input signal is input, the combined signals output from each of the P output neurons 50 are signals at a preset time after the signal in the normal input signal, for example, the signal at t pred time steps after the input normal input signal, are learned.

[0074] Alternatively, the intermediate-output synapse weights set for each of the plurality of intermediate-output synapses 56 may be learned so that the difference signal representing the difference between the combined signals output from each of the P output neurons 50 and the signal at a preset time after the normal input signal becomes 0 when a normal input signal is input.

[0075] The intermediate-output synapse weights are set to optimal values by updating them by linear regression, ridge regression, gradient descent method, or stochastic gradient descent method. Note that t pred is an integer and represents the time corresponding to t shown in Equations (1) and (2).

[0076] The signal processing apparatus 10 according to the first embodiment as described above can output an output signal that predicts a normal input signal at a preset time after each of the P output neurons 50.

[0077] Furthermore, in the signal processing apparatus 10 according to the first embodiment, the intermediate layer 24 includes P types of intermediate neurons 42, and the output layer 28 generates a combined signal obtained by linearly combining the state values output from the intermediate neurons 42 for each of the P types. Then, in the signal processing apparatus 10, the output layer 28 outputs an output signal obtained by inverting the sign of the first combined signal corresponding to the first type among the P types and linearly combining the second combined signal corresponding to the second type among the P types without inverting the sign.

[0078] Thereby, the signal processing apparatus 10 according to the first embodiment can generate P types of combined signals with different responses to abnormal components due to the differences in the state values associated with the type differences of the P types of intermediate neurons 42. Then, the signal processing apparatus 10 generates an output signal obtained by inverting the sign of the first combined signal among the P types of combined signals and linearly combining the second combined signal without inverting the sign, thereby removing common components such as noise and outputting an output signal that emphasizes the abnormal components.

[0079] The signal processing apparatus 10 according to the first embodiment can perform signal processing in a state including noise without performing spectrum analysis on the input signal by a digital processing circuit. Thereby, the signal processing apparatus 10 can detect abnormalities in time-series data measured by, for example, medical devices or infrastructure facilities that continuously operate, in a terminal device with low processing capacity provided near the medical devices or infrastructure facilities.

[0080] (Second Embodiment) Next, the signal processing apparatus 10 according to the second embodiment will be described. In the second embodiment, components having substantially the same functions and configurations as the components described in the first embodiment are denoted by the same reference numerals, and detailed descriptions thereof are omitted except for the differences. The same applies to the third embodiment and subsequent embodiments.

[0081] FIG. 2 is a diagram showing the configuration of the signal processing apparatus 10 according to the second embodiment.

[0082] The signal processing device 10 according to the second embodiment acquires M time-series input signals and outputs an output signal representing an abnormal component included in the M input signals. M is an integer of 1 or more. In the example of FIG. 2, the signal processing device 10 acquires a first input signal in time series and a second input signal in time series.

[0083] The input layer 22 acquires M input signals. The input layer 22 includes M input neurons 40. The M input neurons 40 correspond one-to-one to the M input signals. Each of the M input neurons 40 acquires the corresponding input signal among the M input signals. In the example of FIG. 2, the input layer 22 includes, as M input neurons 40, a first input neuron 40-1 that acquires the first input signal and a second input neuron 40-2 that acquires the second input signal. Then, each of the M input neurons 40 outputs an input state value corresponding to the corresponding input signal.

[0084] The intermediate layer 24 acquires one or more intermediate input signals corresponding to the M input signals via the input-intermediate synapse part 26. The intermediate layer 24 generates a plurality of intermediate signals based on the acquired one or more intermediate input signals.

[0085] In the present embodiment, the input-intermediate synapse part 26 includes N input-intermediate synapses 46 for each of the M input neurons 40 as one or more input-intermediate synapses 46. That is, in the present embodiment, the input-intermediate synapse part 26 includes (M×N) input-intermediate synapses 46.

[0086] In the example of FIG. 2, the N input-intermediate synapses 46 having the first input neuron 40-1 as the preceding neuron correspond one-to-one to the N intermediate neurons 42. The N input-intermediate synapses 46 having the second input neuron 40-2 as the preceding neuron correspond one-to-one to the N intermediate neurons 42.

[0087] The output layer 28 includes (M×P) output neurons 50, M group final neurons 62, (M×P) output synapses 52, M final output synapses 64, and a final output neuron 54.

[0088] (M×P) output neurons 50 are grouped into M groups. The M groups correspond one-to-one to the M input signals. In the example of FIG. 2, (M×P) output neurons 50 are grouped into two groups: a first group corresponding to the first input signal and a second group corresponding to the second input signal.

[0089] Each of the M groups includes P output neurons 50. The P output neurons 50 included in each of the M groups correspond one-to-one to the P types of intermediate neurons 42 included in the N intermediate neurons 42.

[0090] In the example of FIG. 2, each of the M groups includes, as P output neurons 50, a first output neuron 50-1, a second output neuron 50-2, and a third output neuron 50-3. The first output neuron 50-1 corresponds to the first type of intermediate neuron 42 (IP1). The second output neuron 50-2 corresponds to the second type of intermediate neuron 42 (IP2). The third output neuron 50-3 corresponds to the third type of intermediate neuron 42 (IP3).

[0091] (M×P) output synapses 52 correspond one-to-one to (M×P) output neurons 50. (M×P) output synapses 52 are grouped into M groups, each of which includes P output synapses 52, corresponding to the (M×P) output neurons 50.

[0092] Each of the (M×P) output synapses 52 has a corresponding output neuron 50 among the (M×P) output neurons 50 set as the previous neuron, and a group final neuron 62 grouped into the same group as the previous neuron among the M group final neurons 62 is set as the subsequent neuron. Each of the (M×P) output synapses 52 outputs to the subsequent neuron a signal obtained by multiplying the connection signal output from the previous neuron by the set output synapse load.

[0093] Here, the first output synapse 52-1 included in each of the M groups outputs a signal obtained by inverting the sign of the first connection signal output from the first output neuron 50-1 by multiplying by the set output synapse load. Note that the first output synapse 52-1 included in each of the M groups is any one of the P output synapses 52 included in the corresponding group.

[0094] Also, the second output synapse 52-2 included in each of the M groups outputs a signal that does not invert the sign of the second connection signal output from the second output neuron 50-2 by multiplying by the set output synapse load. Note that the second output synapse 52-2 included in each of the M groups is any one of the P output synapses 52 included in the corresponding group that is different from the first output synapse 52-1.

[0095] That is, for each of the M groups, the output synapse load set for the first output synapse 52-1 and the output synapse load set for the second output synapse 52-2 are represented by real numbers with inverted signs.

[0096] Also, among the P output synapses 52 included in each of the M groups, the output synapses 52 other than the first output synapse 52-1 and the second output synapse 52-2 may or may not invert the sign of the connection signal output from the corresponding output neuron 50.

[0097] The M group final neurons 62 correspond one-to-one to M groups corresponding to the (M×P) output neurons 50. Each of the M group final neurons 62 acquires the combined signals output from each of the P output synapses 52 included in the same group. Then, each of the M group final neurons 62 adds the combined signals output from each of the P output synapses 52 included in the same group to generate an intermediate output value and outputs the generated intermediate output value. That is, each of the M group final neurons 62 generates and outputs an intermediate output value by linearly combining the combined signals output from each of the P output neurons 50 included in the same group.

[0098] The M final output synapses 64 correspond one-to-one to the M group final neurons 62. An intermediate output synapse load is set for each of the M final output synapses 64. The intermediate output synapse load is represented by a positive real value or a negative real value. For each of the M final output synapses 64, the corresponding group final neuron 62 among the M group final neurons 62 is set as the previous-stage neuron, and the final output neuron 54 is set as the subsequent-stage neuron. Each of the M final output synapses 64 outputs, to the subsequent-stage neuron, a signal obtained by multiplying the intermediate output value output from the previous-stage neuron by the set intermediate output synapse load.

[0099] The final output neuron 54 adds the signals output from each of the M final output synapses 64 to generate an output signal, and outputs the generated output signal. That is, the final output neuron 54 generates an output signal by linearly combining the connection signals output from each of the (M×P) output neurons 50. Note that the final output neuron 54 may output an output signal obtained by further performing an activation function operation on the value obtained by adding the signals output from each of the M final output synapses 64. Further, the final output neuron 54 may output an output signal binarized by a preset threshold value with respect to the value obtained by adding the signals output from each of the M final output synapses 64, or the value obtained by performing an activation function operation.

[0100] In the present embodiment, the intermediate-output synapse part 30 includes (M×N) intermediate-output synapses 56. The (M×N) intermediate-output synapses 56 are grouped into M groups each including N intermediate-output synapses 56 corresponding to the (M×P) output neurons 50. The N intermediate-output synapses 56 in each of the M groups correspond one-to-one to the N intermediate neurons 42. Each of the N intermediate-output synapses 56 in one group has the corresponding intermediate neuron 42 among the N intermediate neurons 42 set as the previous-stage neuron. The N intermediate-output synapses 56 in one group correspond one-to-one to the N output neurons 50 in the corresponding group among the (M×P) output neurons 50. Each of the N intermediate-output synapses 56 in one group has the corresponding output neuron 50 among the N output neurons 50 included in the corresponding group set as the subsequent-stage neuron.

[0101] Here, the intermediate-output synapse loads set for each of the (M×N) intermediate-output synapses 56 are set to optimal values in advance by learning. The intermediate-output synapse loads set for each of the (M×N) intermediate-output synapses 56 are such that when M normal input signals are input, for each of the M groups, the combined signals output from each of the P output neurons 50 are the signals at a preset time after the corresponding normal input signal among the M normal input signals, that is, for example, the signal at time t pred after the time step of the corresponding normal input signal, and are learned accordingly.

[0102] Also, the intermediate-output synapse loads set for each of the plurality of intermediate-output synapses 56 may be learned such that when M normal input signals are input, for each of the M groups, the difference signal representing the difference between the combined signals output from each of the P output neurons 50 and the signals at a preset time after the corresponding normal input signal among the M normal input signals becomes 0.

[0103] The signal processing device 10 according to the second embodiment as described above can output an output signal that predicts M normal input signals at a preset time after each of the P output neurons 50.

[0104] Furthermore, in the signal processing device 10 according to the second embodiment, the intermediate layer 24 includes P types of intermediate neurons 42, and the output layer 28 generates a combined signal by linearly combining the state values output from the intermediate neurons 42 for each of the P types for each of the M groups corresponding to the M input signals. Then, in the signal processing device 10, the output layer 28 outputs an output signal obtained by linearly combining the first combined signal corresponding to the first type among the P types with the sign reversed and the second combined signal corresponding to the second type among the P types without reversing the sign for each of the M groups.

[0105] As a result, the signal processing device 10 according to the second embodiment can generate P types of coupling signals with different responses to abnormal components for each of the M groups due to the difference in state values associated with the type differences of the P types of intermediate neurons 42. Then, for each of the M groups, the signal processing device 10 generates an output signal obtained by linearly combining while inverting the sign of the first coupling signal among the P types of coupling signals and not inverting the sign of the second coupling signal, thereby removing common components such as noise and outputting an output signal that emphasizes the abnormal components.

[0106] Similar to the first embodiment, the signal processing device 10 according to the second embodiment can execute signal processing in a state including noise without performing spectrum analysis on the input signal by a digital processing circuit. As a result, the signal processing device 10 can detect an abnormality in time-series data measured by, for example, a medical device or infrastructure equipment that continuously operates, in a terminal device with low processing power provided near the medical device or infrastructure equipment.

[0107] (Third Embodiment) Next, the signal processing device 10 according to the third embodiment will be described.

[0108] FIG. 3 is a diagram showing the configuration of the signal processing device 10 according to the third embodiment. Among the N intermediate neurons 42 according to the third embodiment, the constancy signal in any one type of the P types of intermediate neurons 42 is 0.

[0109] For example, in the intermediate neuron 42 of the type where the constancy signal is 0, the value of the corresponding row in η in Equation (2) IP is set to 0. Note that the value of the corresponding row of Target in Equation (2) IP for the intermediate neuron 42 of the type where the constancy signal is 0 may be any value.

[0110] That is, when the intermediate layer 24 performs digital processing, the intermediate neuron 42 of the type in which the constancy signal is 0 has the value of the corresponding row of T IP (t) in Equation (1) set to 0. Also, when the intermediate layer 24 processes an analog signal, the intermediate neuron 42 of the type in which the constancy signal is 0 has the value of the corresponding row of T IP (t) in Equation (3) set to 0.

[0111] Note that P is shown as 3 in FIG. 3, but it may be 4 or more. Also, FIG. 3 shows an example when one input signal is input, but in the signal processing device 10 according to the third embodiment, two or more input signals may be input. In this case, the output layer 28 includes P output neurons 50 and P output synapses 52 for each of M groups corresponding to M input signals. Then, the P output neurons 50 and P output synapses 52 included in each of the M groups operate in the same manner as when one input signal is input.

[0112] (Fourth Embodiment) Next, the signal processing device 10 according to the fourth embodiment will be described.

[0113] FIG. 4 is a diagram showing the configuration of the signal processing device 10 according to the fourth embodiment. The signal processing device 10 according to the fourth embodiment has a configuration when P = 2. Therefore, the N intermediate neurons 42 include two types of intermediate neurons 42 as P types of intermediate neurons 42. Also, the output layer 28 according to the fourth embodiment includes two output neurons 50 as P output neurons 50 and two output synapses 52 as P output synapses 52. In this case, the first output synapse 52-1, which is one of the two output synapses 52, outputs a signal obtained by inverting the sign of the first coupling signal output from the first output neuron 50-1. Also, the second output synapse 52-2, which is different from the first output synapse 52-1 among the two output synapses 52, outputs a signal without inverting the sign of the second coupling signal output from the second output neuron 50-2.

[0114] 4 shows an example in which one input signal is input, but two or more input signals may be input to the signal processing device 10 according to the fourth embodiment. In this case, the output layer 28 includes two output neurons 50 and two output synapses 52 for each of M groups corresponding to the M input signals. The two output neurons 50 and the two output synapses 52 included in each of the M groups operate in the same manner as in the case in which one input signal is input.

[0115] Fifth embodiment Next, a signal processing device 10 according to a fifth embodiment will be described.

[0116] 5 is a diagram showing the configuration of a signal processing device 10 according to the fifth embodiment. The signal processing device 10 according to the fifth embodiment is configured for the case where P=2. Furthermore, of the N intermediate neurons 42 according to the fifth embodiment, the homeostatic signal in one type (first type) of the two types of intermediate neurons 42 is 0, and the homeostatic signal in the other type (second type) of intermediate neurons 42 changes over time.

[0117] For example, the first type of intermediate neuron 42 is represented by η IP The value of the corresponding row of is set to 0. The second type of hidden neuron 42 is IP The value of the corresponding row of is set to a non-zero real number, and Target IP The values in the corresponding rows of are set to arbitrary real numbers.

[0118] Furthermore, the output layer 28 according to the fifth embodiment includes two output neurons 50 as the P output neurons 50, and includes two output synapses 52 as the P output synapses 52, similarly to the third embodiment.

[0119] Note that, in FIG. 5, an example where one input signal is input is shown. However, in the signal processing apparatus 10 according to the fifth embodiment, M input signals may be input. In this case, the output layer 28 includes two output neurons 50 and two output synapses 52 for each of the M groups corresponding to the M input signals. Then, the two output neurons 50 and the two output synapses 52 included in each of the M groups operate in the same manner as when one input signal is input.

[0120] (Sixth Embodiment) Next, the signal processing apparatus 10 according to the sixth embodiment will be described.

[0121] FIG. 6 is a diagram showing the configuration of the signal processing apparatus 10 according to the sixth embodiment. In the intermediate layer 24 according to the sixth embodiment, N intermediate neurons 42 independently form a recurrent neural network for each type. Therefore, each of the N intermediate neurons 42 according to the sixth embodiment changes its state value over time in accordance with at least one of one or more intermediate input signals and one or more intermediate signals of the same type of intermediate neuron 42 having a previous-stage neuron. That is, each of the N intermediate neurons 42 according to the sixth embodiment does not acquire an intermediate signal from an intermediate synapse 44 having a previous-stage neuron of a type different from its own type.

[0122] For example, among the (N×N) intermediate synapses 44, the intermediate synapses 44 in which the type of the previous-stage neuron and the type of the subsequent-stage neuron are different have the intermediate synapse load fixed to 0 and are not updated. Thereby, the (N×N) intermediate synapses 44 can be configured to not transmit an intermediate signal to a subsequent-stage neuron of a type different from the previous-stage neuron, and the N intermediate neurons 42 can be configured to independently form a recurrent neural network for each type.

[0123] Note that in FIG. 6, P is shown as 3, but it may be 4 or more. FIG. 6 shows an example where one input signal is input, but in the signal processing device 10 according to the sixth embodiment, M input signals may be input. In this case, the output layer 28 includes P output neurons 50 and P output synapses 52 for each of the M groups corresponding to the M input signals. Then, the P output neurons 50 and the P output synapses 52 included in each of the M groups operate in the same manner as when one input signal is input.

[0124] (Seventh Embodiment) Next, the signal processing device 10 according to the seventh embodiment will be described. Note that for components having substantially the same functions and configurations as those described in the sixth embodiment in the seventh embodiment, the same reference numerals are given, and detailed descriptions thereof are omitted except for the differences. The same applies to the eighth and ninth embodiments.

[0125] FIG. 7 is a diagram showing the configuration of the signal processing device 10 according to the seventh embodiment. Among the N intermediate neurons 42 according to the seventh embodiment, the constancy signal in any one type of the P types of intermediate neurons 42 is 0.

[0126] For example, in the type of intermediate neuron 42 where the constancy signal is 0, the value of the corresponding row of η in Equation (2) is set to 0. For the type of intermediate neuron 42 where the constancy signal is 0, the value of the corresponding row of Target in Equation (2) may be any value. IP That is, when the intermediate layer 24 performs digital processing, for the type of intermediate neuron 42 where the constancy signal is 0, the value of the corresponding row of T(t) in Equation (1) is set to 0. Also, when the intermediate layer 24 processes an analog signal, for the type of intermediate neuron 42 where the constancy signal is 0, the value of the corresponding row of T(t) in Equation (3) is set to 0. IP That is, for the type of intermediate neuron 42 where the constancy signal is 0, the value of the corresponding row of Target in Equation (2) may be any value.

[0127] That is, when the intermediate layer 24 performs digital processing, for the type of intermediate neuron 42 where the constancy signal is 0, the value of the corresponding row of T(t) in Equation (1) is set to 0. Also, when the intermediate layer 24 processes an analog signal, for the type of intermediate neuron 42 where the constancy signal is 0, the value of the corresponding row of T(t) in Equation (3) is set to 0. IP When the intermediate layer 24 processes an analog signal, for the type of intermediate neuron 42 where the constancy signal is 0, the value of the corresponding row of T(t) in Equation (3) is set to 0. IP When the intermediate layer 24 processes an analog signal, for the type of intermediate neuron 42 where the constancy signal is 0, the value of the corresponding row of T(t) in Equation (3) is set to 0.

[0128] Note that in FIG. 7, P is shown as 3, but it may be 4 or more. Also, in FIG. 7, an example in the case where one input signal is input is shown, but in the signal processing device 10 according to the seventh embodiment, two or more input signals may be input. In this case, the output layer 28 includes P output neurons 50 and P output synapses 52 for each of M groups corresponding to M input signals. Then, the P output neurons 50 and the P output synapses 52 included in each of the M groups operate in the same manner as in the case where one input signal is input.

[0129] (Eighth Embodiment) Next, the signal processing device 10 according to the eighth embodiment will be described.

[0130] FIG. 8 is a diagram showing the configuration of the signal processing device 10 according to the eighth embodiment. The signal processing device 10 according to the eighth embodiment has a configuration when P = 2. Further, among the N intermediate neurons 42 according to the eighth embodiment, the constancy signals in one type (first type) of the two types of intermediate neurons 42 and the constancy signals in the other type (second type) of intermediate neurons 42 both change over time.

[0131] For example, in the first type of intermediate neuron 42, the value of the corresponding row of η in Equation (2) is set to 10 IP and the value of the corresponding row of Target -4 is set to -0.1. Also, in the second type of intermediate neuron 42, the value of the corresponding row of η in Equation (2) is set to 10 IP and the value of the corresponding row of Target IP is set to 10 -2 and the value of the corresponding row of Target IP is set to 0.

[0132] Furthermore, the output layer 28 according to the eighth embodiment includes two output neurons 50 as P output neurons 50 and two output synapses 52 as P output synapses 52, in the same manner as in the seventh embodiment.

[0133] Note that, in FIG. 8, an example in the case where one input signal is input is shown. However, in the signal processing apparatus 10 according to the eighth embodiment, M input signals may be input. In this case, the output layer 28 includes two output neurons 50 and two output synapses 52 for each of the M groups corresponding to the M input signals. Then, the two output neurons 50 and the two output synapses 52 included in each of the M groups operate in the same manner as in the case where one input signal is input.

[0134] (Ninth Embodiment) Next, the signal processing apparatus 10 according to the ninth embodiment will be described.

[0135] FIG. 9 is a diagram showing the configuration of the signal processing apparatus 10 according to the ninth embodiment. The signal processing apparatus 10 according to the ninth embodiment has a configuration when P = 2. That is, the P types of intermediate neurons 42 are the first type of intermediate neuron 42-1 and the second type of intermediate neuron 42-2.

[0136] Furthermore, for the N intermediate neurons 42 according to the ninth embodiment, the constancy signal in the first type of intermediate neuron 42-1, which is one of the two types of intermediate neurons 42, is 0, and the constancy signal in the second type of intermediate neuron 42-2, which is different from the first type, changes over time.

[0137] For example, in the first type of intermediate neuron 42, the value of the corresponding row of η in Equation (2) IP is set to 0. Also, in the second type of intermediate neuron 42, the value of the corresponding row of η in Equation (2) IP is set to a non-zero real number, and the value of the corresponding row of Target IP is set to an arbitrary real number.

[0138] That is, the first type of intermediate neuron 42-1 changes the state value over time in response to at least one of one or more intermediate input signals and at least one of one or more intermediate signals corresponding to the respective state values of the first type of intermediate neuron 42-1 among the plurality of intermediate signals, without using the constancy signal.

[0139] On the other hand, the second type of intermediate neuron 42-2 changes the state value over time in response to at least one of one or more intermediate input signals, at least one of one or more intermediate signals having the second type of intermediate neuron 42-2 as the preceding neuron, and the constancy signal.

[0140] Furthermore, the output layer 28 according to the ninth embodiment includes two output neurons 50 as P output neurons and two output synapses 52 as P output synapses, similar to the third embodiment.

[0141] Note that FIG. 9 shows an example in the case where one input signal is input, but in the signal processing apparatus 10 according to the ninth embodiment, M input signals may be input. In this case, the output layer 28 includes two output neurons 50 and two output synapses 52 for each of M groups corresponding to the M input signals. Then, the two output neurons 50 and the two output synapses 52 included in each of the M groups operate in the same manner as in the case where one input signal is input.

[0142] (Update of Intermediate Synaptic Weights According to STDP) FIG. 10 is a diagram for explaining the update of the intermediate synaptic weights according to STDP.

[0143] In each of the first to ninth embodiments, at least a part of the plurality of intermediate synapses 44 may update the set intermediate synaptic weights according to STDP.

[0144] For example, the intermediate synapse weight at the first time (t) set for an intermediate synapse 44 with the j-th intermediate neuron 42-j among the N intermediate neurons 42 as the preceding neuron and the i-th intermediate neuron 42-i among the N intermediate neurons 42 as the succeeding neuron is denoted as w ij (res) (t). Also, the intermediate synapse weight at the second time (t - t pre ) before a predetermined time step from the first time (t) set for the intermediate synapse 44 with the j-th intermediate neuron 42-j as the preceding neuron and the i-th intermediate neuron 42-i as the succeeding neuron is denoted as w ij (res) (t - t pre ). Note that i and j are integers from 1 to N inclusive.

[0145] In this case, when performing update according to STDP, w ij (res) (t) is represented by Equation (4).

Equation

[0146] η STDP is a predetermined constant. x j (t) represents the state value output from the preceding neuron at the first time (t). x j (t - t pre ) represents the state value output from the preceding neuron at the second time (t - t pre ). x i (t) represents the state value output from the succeeding neuron at the first time (t). x i (t - t pre ) represents the state value output from the succeeding neuron at the second time (t - t pre ).

[0147] That is, as shown in Equation (4), the intermediate synapse 44 that performs updates according to STDP calculates a first value obtained by multiplying the state value (x j (t)) output from the previous neuron at the first time (t) by the state value x pre (t - t i ) output from the subsequent neuron at the second time (t - t pre ) one time step before the first time (t). Also, the intermediate synapse 44 that performs updates according to STDP calculates a second value obtained by multiplying the state value (x pre (t - t j )) output from the previous neuron at the second time (t - t pre ) by the state value x i (t) output from the subsequent neuron at the first time (t). Then, the intermediate synapse 44 that performs updates according to STDP calculates the intermediate synapse weight (w STDP ) at the first time (t) by adding a value obtained by multiplying the difference between the first value and the second value by a predetermined constant (η pre ) to the intermediate synapse weight (w ij (res) (t - t pre )) at the second time (t - t ij (res) ).

[0148] Note that some of the plurality of intermediate synapses 44 do not have to update the intermediate synapse weight according to STDP. For example, some of the plurality of intermediate synapses 44 may have a fixed intermediate synapse weight at a constant value.

[0149] (Update of Intermediate Synapse Weight According to Fusi's Rule) FIG. 11 is a diagram for explaining the update of the intermediate synapse weight according to Fusi's rule (SDSP rule).

[0150] In each of the first to ninth embodiments, at least some of the plurality of intermediate synapses 44 may update the set intermediate synapse weight according to Fusi's rule (SDSP rule).

[0151] When updating the intermediate synapse load based on the Fusi rule, each of the plurality of intermediate synapses 44 obtains the membrane potential held by the subsequent neuron.

[0152] For example, the membrane potential at the first time (t) held by N intermediate neurons 42 is represented as V m (t). In this case, V m (t) is represented by Equation (5).

Equation

[0153] V m (t) represents a matrix with N rows and 1 column.

[0154] For the intermediate synapse 44 where the j-th intermediate neuron 42-j is the previous neuron and the i-th intermediate neuron 42-i is the subsequent neuron, the intermediate synapse load (w ij (res) (t)) at the first time (t) is represented by Equation (6).

Equation

[0155] w ij (res) (t - 1) represents the intermediate synapse load one time step before the first time (t). LR represents the learning rate and is a predetermined constant. v m,i (t) represents the membrane potential of the subsequent neuron. For example, the membrane potential of the i-th intermediate neuron 42-i is included in the i-th row of V m (t).

[0156] Also, H(u) is represented by the function shown in Equation (7).

Equation

[0157] H(u) is such that when u is VUP_threshold becomes 1 when the above condition is met, and u is V DOWN_threshold becomes -1 when the following condition is met. H(u) is such that u is V DOWN_threshold greater than, and V UP_threshold less than, it becomes 0. V UP_threshold represents the upper threshold value. V DOWN_threshold represents the lower threshold value.

[0158] That is, the intermediate synapse 44 that updates according to the Fusi rule increases the intermediate synapse load (w ij (res) (t)) when the membrane potential of the subsequent neuron is greater than or equal to the upper threshold value, and decreases the intermediate synapse load (w ij (res) (t)) when the membrane potential of the subsequent neuron is less than or equal to the lower threshold value. Also, the intermediate synapse 44 that updates according to the Fusi rule does not change the intermediate synapse load (w ij (res) (t)) when the membrane potential of the subsequent neuron is less than the upper threshold value and greater than the lower threshold value.

[0159] Note that some of the plurality of intermediate synapses 44 do not have to update the intermediate synapse load according to the Fusi rule. For example, some of the plurality of intermediate synapses 44 may have the intermediate synapse load fixed at a constant value.

[0160] (Modification example of the output neuron 50) FIG. 12 is a diagram showing a modification example of the output neuron 50.

[0161] In the first, third to ninth embodiments, each of the P output neurons 50 included in the output layer 28 outputs a combined signal and a signal (u(t + t predA difference signal representing the difference from )) may be further generated. And in this case, the intermediate-output synapse weights set for each of the plurality of intermediate-output synapses 56 are learned so that the difference signal calculated by each of the P output neurons 50 becomes 0. Thereby, the intermediate-output synapse weights set for each of the plurality of intermediate-output synapses 56 are learned so that when a normal input signal is input, an abnormal component included in the input signal after a preset time is output from each of the P output neurons 50.

[0162] Also, when M input signals are input in the second embodiment or each of the third to ninth embodiments, each of the (M×P) output neurons 50 included in the output layer 28 may also output a similar difference signal. In this case, each of the (M×P) output neurons 50 generates a difference signal representing the difference between the combined signal to be output and the signal after a preset time with respect to the corresponding input signal among the M input signals. And the intermediate-output synapse weights set for each of the plurality of intermediate-output synapses 56 are learned so that the difference signals of each of the M groups become 0.

[0163] Note that each of the P output neurons 50 included in the output layer 28 may output the absolute value of the difference between the combined signal output before a preset time and the input signal input at the current time. And in this case, the intermediate-output synapse weights set for each of the plurality of intermediate-output synapses 56 may be learned so that the absolute value of the difference calculated in this way becomes 0. When M input signals are input, each of the (M×P) output neurons 50 may similarly calculate the absolute value of the difference.

[0164] (Modification example of the output layer 28) FIG. 13 is a diagram showing a modification example of the output layer 28.

[0165] In the first, third to ninth embodiments, the output layer 28 had a two-stage configuration that output the input signal via two neurons. However, the output layer 28 may have a multi-stage configuration of three or more stages that output the input signal via three or more neurons.

[0166] In this modification, the output layer 28 has a three-stage configuration of neurons. In this case, the output layer 28 further includes a plurality of output layer intermediate neurons 72 and a plurality of output layer intermediate synapses 74.

[0167] In this modification, for any of the plurality of output synapses 52, any one of the P output neurons 50 is set as the previous stage neuron, and any one of the plurality of output layer intermediate neurons 72 is set as the subsequent stage neuron. Then, each of the plurality of output synapses 52 outputs to the subsequent stage neuron a signal obtained by multiplying the combined signal output from the previous stage neuron by the set output synapse weight.

[0168] Each of the plurality of output layer intermediate neurons 72 adds the signals output from each of two or more output neurons 50 having itself as the subsequent stage neuron among the plurality of output synapses 52 to generate an output layer intermediate signal, and outputs the generated output layer intermediate signal.

[0169] The plurality of output layer intermediate synapses 74 correspond one-to-one to the plurality of output layer intermediate neurons 72. A predetermined load is set for each of the plurality of output layer intermediate synapses 74. For each of the plurality of output layer intermediate synapses 74, the corresponding output layer intermediate neuron 72 among the plurality of output layer intermediate neurons 72 is set as the previous stage neuron, and the final output neuron 54 is set as the subsequent stage neuron. Each of the plurality of output layer intermediate synapses 74 outputs to the subsequent stage neuron a signal obtained by multiplying the output layer intermediate signal output from the previous stage neuron by the set load.

[0170] In this modification example, the final output neuron 54 generates an output signal corresponding to the signals output from each of the plurality of output layer intermediate synapses 74, and outputs the generated output signal.

[0171] Even with such a configuration, the final output neuron 54 can generate and output an output signal by linearly combining the connection signals output from each of the P output neurons 50.

[0172] Also, the configuration from the plurality of output layer intermediate neurons 72 to the final output neuron 54 in the output layer 28 may be a multi-layer structure via even more neurons. Also, each of the plurality of output layer intermediate neurons 72 may execute activation function processing and processing using input signals. Also, the configuration from the plurality of output layer intermediate neurons 72 to the final output neuron 54 in the output layer 28 may be a deep learning model, a recurrent neural network, or a reservoir computing having the final output neuron 54 as the output stage layer.

[0173] Note that FIG. 13 shows a modification example of the output layer 28 when one input signal is input. However, the signal processing device 10 may receive M input signals. In this case, for each of the M groups corresponding to the M input signals, the multi-stage configuration between the P output neurons 50 and the group final neuron 62 is the same as when one input signal is input.

[0174] (Modification Example of Input-Intermediate Synapse Unit 26) FIG. 14 is a diagram showing a modification example of the input-intermediate synapse unit 26.

[0175] In the intermediate layer 24 according to the sixth to ninth embodiments, N intermediate neurons 42 independently form a recurrent neural network for each type. Therefore, in the sixth to ninth embodiments, one or more input-intermediate synapses 46 included in the input-intermediate synapse unit 26 are grouped into P synapse groups for each type of subsequent neuron.

[0176] In this modified example, each of the P synaptic groups includes Q input-intermediate synapses 46. Therefore, the number of Q input-intermediate synapses 46 in each synaptic group is the same. Further, for each of the Q input-intermediate synapses 46 included in each of the P synaptic groups, a set of Q input-intermediate synaptic weights that are the same for each other is set.

[0177] For example, the intermediate layer 24 includes intermediate neurons 42 of the first type (IP1) and intermediate neurons 42 of the second type (IP2). In this case, the input-intermediate synapse section 26 includes a first synaptic group corresponding to the intermediate neurons 42 of the first type (IP1) and a second synaptic group corresponding to the intermediate neurons 42 of the second type (IP2).

[0178] Let the Q input-intermediate synaptic weights set for the Q input-intermediate synapses 46 included in the first synaptic group be represented as W1 (in) and the Q input-intermediate synaptic weights set for the Q input-intermediate synapses 46 included in the second synaptic group be represented as W2 (in) In this case, W1 (in) = W2 (in) holds.

[0179] The signal processing device 10 according to such a modified example can avoid an increase in the input difference for each of the P types with respect to the N intermediate neurons 42 and can accurately detect an abnormality.

[0180] Note that when M input signals are input, for each of the M input signals, P synaptic groups are set in the input-intermediate synapse section 26. And in this case, for each of the M input signals, for the Q input-intermediate synapses 46 included in each of the P synaptic groups, a set of Q input-intermediate synaptic weights that are the same for each other is set.

[0181] Note that the input-intermediate synapse unit 26 according to the first to fifth embodiments may also be grouped into P synapse groups. In this case, each of the P synapse groups has the same number (for example, Q). Further, for each of the Q input-intermediate synapses 46 included in each of the P synapse groups, a set of Q input-intermediate synapse weights that are the same as each other is set. In this way, the input-intermediate synapse unit 26 according to the modification example shown in FIG. 4 can also be applied to the first to fifth embodiments.

[0182] (Modification Example of Update Rule of Intermediate Neuron 42) Next, a modification example of the update rule of the intermediate neuron 42 will be described.

[0183] In each of the first to ninth embodiments, each of the N intermediate neurons 42 may operate according to a leaky integrate-and-fire model. In this case, each of the N intermediate neurons 42 holds a membrane potential, sets the state value to 1 when the membrane potential exceeds a preset threshold potential, and resets the held membrane potential. Each of the N intermediate neurons 42 sets the state value to 0 when the membrane potential does not exceed the preset threshold potential.

[0184] Each of the N intermediate neurons 42 operating according to the leaky integrate-and-fire model changes the membrane potential over time. For example, each of the N intermediate neurons 42 changes the membrane potential over time based on Equation (8). [Number]

[0185] V m (t) represents the membrane potential at time t. V rest represents the resting membrane potential. R m represents the membrane resistance. I(t) represents the input current at time t. τ m represents the time constant.

[0186] When operating according to the leaky integration firing model in this way, for each of the P types, the N intermediate neurons 42 have a time constant τ m which may be different. As a result, for each type, the response frequency of the N intermediate neurons 42 changes, and the update rule of the state value changes. Therefore, the N intermediate neurons 42 operating according to the leaky integration firing model have a time constant τ m which is different, and can include P types of intermediate neurons 42 with different update rules.

[0187] Also, in each of the first to ninth embodiments, when the intermediate layer 24 processes an analog signal, or when the intermediate layer 24 processes a multi-valued discrete or continuous digital signal, the N intermediate neurons 42 may output state values as shown in Equation (9).

Number

[0188] In this case, for each of the P types, the leakage rate α of the N intermediate neurons 42 may be different. As a result, for each type, the update rule of the state value of the N intermediate neurons 42 changes. Therefore, when the intermediate layer 24 processes an analog signal, or when the intermediate layer 24 processes a multi-valued discrete or continuous digital signal, the N intermediate neurons 42 can include P types of intermediate neurons 42 with different leakage rates α, thereby including P types of intermediate neurons 42 with different update rules.

[0189] Also, in each of the first to ninth embodiments, each of the N intermediate neurons 42 may be an output-limited neuron whose output is limited.

[0190] For example, the state value of an output-limited neuron with an upper limit set is expressed as in Equation (10).

Number

[0191] X + threshold represents a matrix of N rows and 1 column. X + threshold includes the upper limit values of the N state values output from the N intermediate neurons 42. Note that X + threshold the values included in are real numbers greater than or equal to 0. The upper limit value of the n-th intermediate neuron 42 is X + threshold contained in the n-th row of.

[0192] In this case, for each of the P types of the N intermediate neurons 42, the set upper limit values are different. As a result, for each type, the update rule of the state value of the N intermediate neurons 42 changes. Note that each of the N intermediate neurons 42 can function as a neuron whose output is substantially not restricted by setting the upper limit value to the maximum value that the state value can take.

[0193] Also, for example, the state value of an output-limiting neuron with a set lower limit value is expressed as in Equation (11).

Equation

[0194] X - threshold represents a matrix of N rows and 1 column. X - threshold includes the lower limit values of the N state values output from the N intermediate neurons 42. Note that X - threshold the values included in are real numbers less than or equal to 0. The lower limit value of the n-th intermediate neuron 42 is X - threshold contained in the n-th row of.

[0195] In this case, for each of the N intermediate neurons 42, the set lower limit values are different for each of the P types. As a result, for each type, the update rule of the state value changes for the N intermediate neurons 42. Note that each of the N intermediate neurons 42 can function as a neuron whose output is substantially not restricted by setting the lower limit value to the minimum value that the state value can take.

[0196] Also, for example, the state value of an output-limiting neuron for which an upper limit value and a lower limit value are set is expressed as in Equation (12).

Equation

[0197] In this case, for each of the N intermediate neurons 42, the combination of the set lower limit value and upper limit value is different for each of the P types. As a result, for each type, the update rule of the state value changes for the N intermediate neurons 42. Note that each of the N intermediate neurons 42 can function as a neuron whose output is substantially not restricted by setting the upper limit value to the maximum value that the state value can take and setting the lower limit value to the minimum value that the state value can take.

[0198] Also, for example, when the absolute value of the upper limit value and the absolute value of the lower limit value are the same and the upper limit value and the lower limit value are set, the state value of the output-limiting neuron is expressed as in Equation (13).

Equation

[0199] X threshold represents a matrix of N rows and 1 column. X threshold includes the absolute value of the upper limit value (or the absolute value of the lower limit value) of the N state values output from the N intermediate neurons 42. Note that the values included in X threshold are real numbers of 0 or more. The absolute value of the upper limit value (or the absolute value of the lower limit value) of the n-th intermediate neuron 42 is included in the n-th row of X threshold .

[0200] In this case, for each of the P types, the upper limit value (lower limit value) set for the N intermediate neurons 42 is different. As a result, for each type, the update rule of the state value of the N intermediate neurons 42 changes. Note that each of the N intermediate neurons 42 can function as a neuron whose output is substantially not restricted by setting the absolute value of the upper limit value (or the absolute value of the lower limit value) to the maximum value that the state value can take.

[0201] In this way, the N intermediate neurons 42 can include P types of intermediate neurons 42 with different upper limit values or lower limit values for output limitation, and can include P types of intermediate neurons 42 with different update rules.

[0202] (Simulation) The simulation results when an input signal including an abnormal waveform is given to the signal processing device 10 configured in the ninth embodiment that has been learned will be described.

[0203] FIG. 15 is a waveform diagram of the input signal used in the simulation. The input signal used in the simulation is a signal in which an abnormal waveform is superimposed on white noise with a standard deviation of 0.721. The portion surrounded by a circle in FIG. 15 is the abnormal waveform.

[0204] FIG. 16 is a waveform diagram of the signal representing the simulation results.

[0205] A in FIG. 16 represents the first combined signal. That is, A in FIG. 16 represents a signal obtained by linearly combining the state values of a plurality of first-type intermediate neurons 42 when the constancy signal T IP (t) is set to 0. As shown in the portion surrounded by a circle in A of FIG. 16, the first combined signal shows a signal component of the abnormal waveform.

[0206] B in FIG. 16 represents the second combined signal. That is, B in FIG. 16 represents the constancy signal T IPIt represents a signal obtained by linearly combining the state values of a plurality of second-type intermediate neurons 42 for which (t)) is not zero. As shown in the portion surrounded by the circle in FIG. 16B, no signal component of an abnormal waveform appears in the second combined signal.

[0207] FIG. 16C represents a signal obtained by subtracting the input signal after a predetermined time from the first combined signal. As shown in FIG. 16C, only the component of white noise appears in the signal obtained by subtracting the input signal after a predetermined time from the first combined signal, and no signal component of an abnormal waveform appears.

[0208] FIG. 16D represents a signal obtained by subtracting the input signal after a predetermined time from the second combined signal. As shown in FIG. 16D, the signal obtained by subtracting the input signal after a predetermined time from the second combined signal has a signal component of an abnormal waveform superimposed on the component of white noise.

[0209] FIG. 16E represents the output signal output from the final output neuron 54. That is, FIG. 16E represents a signal obtained by linearly adding after inverting the sign of the signal obtained by subtracting the input signal after a predetermined time from the first combined signal and without inverting the sign of the signal obtained by subtracting the input signal after a predetermined time from the second combined signal.

[0210] As shown in FIG. 16E, the output signal includes a signal component that emphasizes the signal component of the abnormal waveform. Therefore, for example, a device subsequent to the final output neuron 54 or the final output neuron 54 can detect whether or not the input signal includes an abnormal component by comparing the output signal with a threshold value.

[0211] (Abnormality detection system 100) FIG. 17 is a diagram showing the configuration of an abnormality detection system 100 to which the signal processing device 10 is applied.

[0212] The abnormality detection system 100 includes an observation target device 110 and an abnormality detection device 120. When an abnormality occurs in the observation target device 110, the abnormality detection system 100 notifies, for example, an administrator or another device that the abnormality has occurred.

[0213] The device under observation 110 operates continuously. For example, the device under observation 110 is a medical device or infrastructure equipment, etc. The device under observation 110 is not limited to such devices, and any device that operates continuously may be used.

[0214] The abnormality detection device 120 includes a signal processing device 10 and a notification device 130.

[0215] The signal processing device 10 has the same configuration as the signal processing device 10 according to the first to ninth embodiments described above. The signal processing device 10 detects abnormalities in the device under observation 110. For example, the signal processing device 10 detects abnormalities that occur instantaneously in the device under observation 110. Even during a period when the device under observation 110 is operating normally, it may occasionally and instantaneously exhibit behaviors or operations that are different from the normal state. Such behaviors or operations may be precursors to malfunctions or significant decreases in performance in the device under observation 110, for example. The signal processing device 10 can detect such instantaneous abnormalities in the device under observation 110 continuously in real time, thereby discovering precursors to malfunctions or significant decreases in performance in the device under observation 110.

[0216] The signal processing device 10 acquires one or more input signals whose values change in the time direction, that is, one or more input signals in a time series, obtained by observing the device under observation 110. Based on the acquired input signals, the signal processing device 10 outputs an output signal representing the abnormal component that has occurred in the device under observation 110.

[0217] The notification device 130 acquires the output signal from the signal processing device 10. The notification device 130 determines whether it is abnormal based on the output signal, and notifies the administrator by, for example, displaying the determination result on a display device or outputting a voice from a voice output device. Further, the notification device 130 may transmit the output signal or the determination result based on the output signal to another device such as a server via a network, for example.

[0218] The abnormality detection system 100 with such a configuration uses the signal processing device 10 according to the first to ninth embodiments, so it can execute signal processing on the input signal in a state including noise without performing spectrum analysis by a digital processing circuit, and can detect the abnormality of the observation target device 110 with high accuracy in a simple configuration. Further, since the configuration of the signal processing device 10 is simple, the abnormality detection system 100 with such a configuration can detect an abnormality in, for example, a terminal device with low processing power near the observation target device 110.

[0219] (Hardware configuration of the information processing device) FIG. 18 is a diagram showing an example of the hardware configuration of the information processing device 20.

[0220] Instead of an analog circuit or a digital circuit, the signal processing device 10 may be realized by a computer (information processing device 20) having a hardware configuration as shown in FIG. 18, for example. In this case, the information processing device 20 includes a CPU (Central Processing Unit) 301, a RAM (Random Access Memory) 302, a ROM (Read Only Memory) 303, an operation input device 304, a display device 305, a storage device 306, and a communication device 307. And these respective parts are connected by a bus.

[0221] The CPU 301 is a processor that executes arithmetic processing, control processing, etc. according to a program. The CPU 301 uses a predetermined area of the RAM 302 as a work area and executes various processes in cooperation with programs stored in the ROM 303, the storage device 306, etc.

[0222] The RAM 302 is a memory such as an SDRAM (Synchronous Dynamic Random Access Memory). The RAM 302 functions as a work area for the CPU 301. The ROM 303 is a memory that stores programs and various information in a non-rewritable manner.

[0223] The operation input device 304 is an input device such as a mouse and a keyboard. The operation input device 304 receives information input by the user as an instruction signal and outputs the instruction signal to the CPU 301.

[0224] The display device 305 is a display device such as an LCD (Liquid Crystal Display). The display device 305 displays various information based on the display signal from the CPU 301.

[0225] The storage device 306 is a device that writes and reads data to and from a semiconductor storage medium such as a flash memory, or a storage medium that can be magnetically or optically recorded. The storage device 306 writes and reads data to and from the storage medium according to the control from the CPU 301. The communication device 307 communicates with an external device via a network according to the control from the CPU 301.

[0226] The program executed by the computer has a module configuration including an input layer module, an intermediate layer module, an input-intermediate synapse module, an output layer module, and an intermediate-output synapse module.

[0227] This program is expanded and executed on the RAM 302 by the CPU 301 (processor), causing the computer to function as an input layer 22, an intermediate layer 24, an input-intermediate synapse part 26, an output layer 28, and an intermediate-output synapse part 30. Note that part or all of the input layer 22, the intermediate layer 24, the input-intermediate synapse part 26, the output layer 28, and the intermediate-output synapse part 30 may be realized by a hardware circuit.

[0228] Also, the program executed by the computer is a file in an installable or executable format for the computer and is provided by being recorded on a computer-readable recording medium such as a CD-ROM, a flexible disk, a CD-R, or a DVD (Digital Versatile Disk).

[0229] Alternatively, the program may be stored on a computer connected to a network such as the Internet and provided by allowing it to be downloaded via the network. Further, the program may be configured to be provided or distributed via a network such as the Internet. Additionally, the program executed by the information processing apparatus 20 may be configured to be provided by being pre - incorporated into a ROM 303 or the like.

[0230] As described above, embodiments of the present invention have been explained. However, the above - described embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These novel embodiments and their modifications are included in the scope and gist of the invention and are also included in the invention described in the claims and the equivalent scope thereof.

[0231] (Supplementary Note) Incidentally, the above - described embodiments can be summarized into the following technical proposals.

[0232] [Technical Proposal 1] A signal processing apparatus that executes signal processing according to a neural network, an input layer that acquires M input signals (M is an integer of 1 or more), an intermediate layer that acquires one or more intermediate input signals corresponding to the M input signals and generates a plurality of intermediate signals based on the one or more intermediate input signals, an output layer that acquires a plurality of intermediate output signals and outputs an output signal corresponding to the plurality of intermediate output signals and the intermediate layer includes N intermediate neurons (N is an integer of 2 or more) each of which outputs a state value, and a plurality of intermediate synapses that generate the plurality of intermediate signals, each of the plurality of intermediate synapses generates a corresponding intermediate signal among the plurality of intermediate signals according to the state value output from any one of the N intermediate neurons. Each of the plurality of intermediate output signals is a signal corresponding to a state value output by any one of the N intermediate neurons, Each of the N intermediate neurons changes the state value over time based on a predetermined update rule according to at least one of the one or more intermediate input signals and the plurality of intermediate signals, The N intermediate neurons include P types with different update rules (P is an integer greater than or equal to 2 and less than or equal to N) Signal processing device.

[0233] [Technical solution 2] Each of the N intermediate neurons changes the state value over time according to at least one of the one or more intermediate input signals and the plurality of intermediate signals, and a constancy signal that changes the state value in the direction of the target value with a set intensity, For each of the P types of intermediate neurons, the set intensity or the target value in the constancy signal is different from that of other types of intermediate neurons The signal processing device according to Technical solution 1.

[0234] [Technical solution 3] The constancy signal in any one type of the P types of intermediate neurons among the N intermediate neurons is 0 The signal processing device according to Technical solution 2.

[0235] [Technical solution 4] The output layer includes (M×P) output neurons, a final output neuron that outputs the output signal, and includes The (M×P) output neurons are grouped into M groups, each of which includes P output neurons, The M groups correspond one-to-one to the M input signals, Each of the P output neurons included in each of the M groups corresponds one-to-one to the P types of intermediate neurons, Each of the P output neurons included in each of the M groups outputs a coupling signal representing an output state value obtained by linearly combining the state values of the corresponding one or more intermediate neurons among the N intermediate neurons, The final output neuron generates the output signal by linearly combining the coupling signals output from each of the (M×P) output neurons. The signal processing device according to Technical Solution 2 or 3.

[0236] [Technical Solution 5] The output layer further includes a plurality of output synapses, Each of the plurality of output synapses corresponds to one of the (M×P) output neurons, and outputs a signal obtained by multiplying the coupling signal output from the corresponding output neuron by an output synapse weight which is a preset real number, The final output neuron generates the output signal by linearly adding the signals output from each of the plurality of output synapses, For each of the M groups, The first output synapse among the plurality of output synapses outputs a signal obtained by inverting the sign of the coupling signal output from the first output neuron among the P output neurons included in the corresponding group, The second output synapse among the plurality of output synapses outputs a signal without inverting the sign of the coupling signal output from the second output neuron among the P output neurons included in the corresponding group. The signal processing device according to Technical Solution 4.

[0237] [Technical Solution 6] For each of the M groups, the output signal includes a component obtained by adding a signal obtained by inverting the sign of a first coupling signal, which is the coupling signal output from a first output neuron among the P output neurons, and a signal obtained by not inverting the sign of a second coupling signal, which is the coupling signal output from a second output neuron different from the first output neuron among the P output neurons. The signal processing device according to Technical Proposal 4.

[0238] [Technical Proposal 7] For each of the plurality of intermediate synapses, an intermediate synapse load is set, and a signal obtained by multiplying the set intermediate synapse load by a state value output from a previous neuron, which is any one of the N intermediate neurons, is output as a corresponding one of the plurality of intermediate signals to a subsequent neuron, which is any one of the N intermediate neurons. The signal processing device according to Technical Proposal 5 or 6.

[0239] [Technical Proposal 8] For each of the N intermediate neurons, the state value is changed over time in response to at least one of the one or more intermediate input signals and one or more intermediate signals of the same type of intermediate neuron having a previous neuron among the plurality of intermediate signals. The signal processing device according to Technical Proposal 7.

[0240] [Technical Proposal 9] The P types of intermediate neurons are a first type of intermediate neuron and a second type of intermediate neuron. The first type of intermediate neuron changes the state value over time in response to at least one of the one or more intermediate input signals and one or more of the first type of intermediate signals having the first type of intermediate neuron as a previous neuron among the plurality of intermediate signals. The second type of intermediate neuron changes the state value over time according to at least one of the one or more intermediate input signals, and at least one of the second type of intermediate signals among the plurality of intermediate signals, with the second type of intermediate neuron as the previous neuron, and the constancy signal. The signal processing device according to Technical Proposal 8.

[0241] [Technical Proposal 10] Further comprising a plurality of intermediate-output synapses, For each of the plurality of intermediate-output synapses, a signal obtained by multiplying the state value output from a previous neuron, which is any one of the N intermediate neurons, by the set intermediate-output synapse load is output as a corresponding intermediate output signal among the plurality of intermediate output signals. For each of the plurality of intermediate-output synapses, among the (M×P) output neurons, the intermediate output signal is output to the output neuron corresponding to the type of the previous neuron. The signal processing device according to any one of Technical Proposals 7 to 9.

[0242] [Technical Proposal 11] The intermediate-output synapse load set for each of the plurality of intermediate-output synapses is learned such that, when the normal M input signals are input, for each of the M groups, the combined signal output from each of the P output neurons becomes the signal at a preset time after the corresponding normal input signal among the normal M input signals. The signal processing device according to Technical Proposal 10.

[0243] [Technical Proposal 12] In the output layer, each of the P output neurons included in each of the M groups generates a difference signal representing the difference between the combined signal to be output and the signal at a preset time after the corresponding input signal among the M input signals. The intermediate-output synapse load set for each of the plurality of intermediate-output synapses is learned so that when the normal M input signals are input, the difference signals of each of the M groups become 0. The signal processing device according to Technical Proposal 10.

[0244] [Technical Proposal 13] The input layer includes M input neurons corresponding one-to-one to the M input signals, Each of the M input neurons acquires the corresponding input signal among the M input signals and outputs an input state value corresponding to the corresponding input signal. The signal processing device according to any one of Technical Proposals 7 to 12.

[0245] [Technical Proposal 14] Further includes one or more input-intermediate synapses, For each of the one or more input-intermediate synapses, an input-intermediate synapse load is set, and a signal obtained by multiplying the input state value output from any one of the M input neurons by the set input-intermediate synapse load is used as the corresponding intermediate input signal among the one or more intermediate input signals and output, The one or more input-intermediate synapses are grouped into P synapse groups corresponding to the P types of intermediate neurons, Each of the P synapse groups includes Q input-intermediate synapses (Q is an integer of 2 or more), The Q input-intermediate synapses included in each of the P synapse groups are set with the same set of Q input-intermediate synapse loads. The signal processing device according to Technical Proposal 13.

[0246] [Technical Proposal 15] At least a part of the plurality of intermediate synapses Update the intermediate synaptic weight according to the difference between the value obtained by multiplying the state value output from the previous neuron at the first time and the state value output from the subsequent neuron at the second time, which is a predetermined time step before the first time, and the value obtained by multiplying the state value output from the previous neuron at the second time and the state value output from the subsequent neuron at the first time. The signal processing device according to any one of Technical Solutions 7 to 14.

[0247] [Technical Solution 16] At least a part of the plurality of intermediate synapses updates the intermediate synaptic weight according to the membrane potential generated by the subsequent neuron. The signal processing device according to any one of Technical Solutions 7 to 14.

[0248] [Technical Solution 17] A signal processing method for executing signal processing according to a neural network by an information processing device, The information processing device executes processing according to an input layer that acquires M input signals (M is an integer of 1 or more), The information processing device executes processing according to an intermediate layer that acquires one or more intermediate input signals corresponding to the M input signals and generates a plurality of intermediate signals based on the one or more intermediate input signals. The information processing device executes processing according to an output layer that acquires a plurality of intermediate output signals and outputs an output signal corresponding to the plurality of intermediate output signals. The intermediate layer includes N intermediate neurons (N is an integer of 2 or more) each of which outputs a state value, and a plurality of intermediate synapses that generate the plurality of intermediate signals. Each of the plurality of intermediate synapses generates a corresponding intermediate signal among the plurality of intermediate signals according to the state value output from any one of the N intermediate neurons. Each of the plurality of intermediate output signals is a signal corresponding to the state value output by any one of the N intermediate neurons. Each of the N intermediate neurons changes the state value over time based on a predetermined update rule in response to at least one of the one or more intermediate input signals and the plurality of intermediate signals. The N intermediate neurons include P types with different update rules (P is an integer greater than or equal to 2 and less than or equal to N). Signal processing method.

[0249] [Technical Proposal 18] A program for causing a computer to function as a signal processing device that executes signal processing according to a neural network, causing the computer to an input layer that acquires M input signals (M is an integer greater than or equal to 1), an intermediate layer that acquires one or more intermediate input signals corresponding to the M input signals and generates a plurality of intermediate signals based on the one or more intermediate input signals, an output layer that acquires a plurality of intermediate output signals and outputs an output signal corresponding to the plurality of intermediate output signals to function, The intermediate layer includes N intermediate neurons each of which outputs a state value, and a plurality of intermediate synapses that generate the plurality of intermediate signals, Each of the plurality of intermediate synapses generates a corresponding intermediate signal among the plurality of intermediate signals according to the state value output from any one of the N intermediate neurons. Each of the plurality of intermediate output signals is a signal corresponding to the state value output by any of the N intermediate neurons. Each of the N intermediate neurons changes the state value over time based on a predetermined update rule in response to at least one of the one or more intermediate input signals and the plurality of intermediate signals. The N intermediate neurons include P types with different update rules (P is an integer greater than or equal to 2 and less than or equal to N). Program.

Explanation of Signs

[0250] 10 Signal processing device 22 Input layer 24 Intermediate layer 26 Input-intermediate synapse part 28 Output layer 30 Intermediate-output synapse part 40 Input neuron 42 Intermediate neuron 44 Intermediate synapse 46 Input-intermediate synapse 50 Output neuron 52 Output synapse 54 Final output neuron 56 Intermediate-output synapse

Claims

1. A signal processing apparatus that executes signal processing according to a neural network, comprising: an input layer that acquires M input signals (M is an integer of 1 or more); an intermediate layer that acquires one or more intermediate input signals corresponding to the M input signals and generates a plurality of intermediate signals based on the one or more intermediate input signals; an output layer that acquires a plurality of intermediate output signals and outputs an output signal corresponding to the plurality of intermediate output signals; The intermediate layer includes N intermediate neurons (N is an integer of 2 or more) each of which outputs a state value, and a plurality of intermediate synapses that generate the plurality of intermediate signals; each of the plurality of intermediate synapses generates a corresponding intermediate signal among the plurality of intermediate signals according to the state value output from any one of the N intermediate neurons; each of the plurality of intermediate output signals is a signal corresponding to the state value output by any one of the N intermediate neurons; each of the N intermediate neurons changes the state value over time based on a predetermined update rule according to at least one of the one or more intermediate input signals and the plurality of intermediate signals; the N intermediate neurons include P types (P is an integer of 2 or more and N or less) with different update rules; A signal processing apparatus.

2. each of the N intermediate neurons changes the state value over time according to at least one of the one or more intermediate input signals and the plurality of intermediate signals, and a constancy signal that changes the state value in the direction of a target value with a set intensity; for each of the P types of intermediate neurons, the set intensity or the target value in the constancy signal is different from that of other types of intermediate neurons; The signal processing apparatus according to claim 1.

3. The signal processing apparatus according to claim 2, wherein the constancy signal in any one type of the P types of intermediate neurons among the N intermediate neurons is 0.

4. The output layer includes: (M×P) output neurons; a final output neuron that outputs the output signal; The (M×P) output neurons are grouped into M groups each including P output neurons, and the M groups correspond one-to-one to the M input signals. ​ ​ ​ Each of the P output neurons included in each of the M groups corresponds one-to-one to the P types of intermediate neurons, Each of the P output neurons included in each of the M groups outputs a coupling signal representing an output state value obtained by linearly combining the state values of each of one or more intermediate neurons of the corresponding type among the N intermediate neurons, The final output neuron generates the output signal by linearly combining the coupling signals output from each of the (M×P) output neurons. The signal processing device according to claim 2.

5. The output layer, further includes a plurality of output synapses, Each of the plurality of output synapses corresponds to any one of the (M×P) output neurons, and outputs a signal obtained by multiplying the coupling signal output from the corresponding output neuron by an output synapse weight which is a preset real number, The final output neuron generates the output signal by linearly adding the signals output from each of the plurality of output synapses, For each of the M groups, The first output synapse among the plurality of output synapses outputs a signal obtained by inverting the sign of the coupling signal output from the first output neuron among the P output neurons included in the corresponding group, The second output synapse among the plurality of output synapses outputs a signal without inverting the sign of the coupling signal output from the second output neuron among the P output neurons included in the corresponding group. The signal processing device according to claim 4.

6. For each of the M groups, the output signal includes a component obtained by adding a signal obtained by inverting the sign of a first coupling signal which is the coupling signal output from the first output neuron among the P output neurons and a signal obtained by not inverting the sign of a second coupling signal which is the coupling signal output from a second output neuron different from the first output neuron among the P output neurons. The signal processing device according to claim 4.

7. Each of the plurality of intermediate synapses has an intermediate synapse load set thereon, and outputs, as a corresponding one of the plurality of intermediate signals, a signal obtained by multiplying the state value output from any one of the N intermediate neurons, which is a previous-stage neuron, by the set intermediate synapse load, to any one of the N intermediate neurons, which is a subsequent-stage neuron. The signal processing device according to claim 5. **Claim 8** Each of the N intermediate neurons changes the state value over time in response to at least one of the one or more intermediate input signals and one or more intermediate signals of the same type of intermediate neuron among the plurality of intermediate signals, where the same type of intermediate neuron has a previous-stage neuron. The signal processing device according to claim 7. **Claim 9** The P types of intermediate neurons are a first type of intermediate neuron and a second type of intermediate neuron. The first type of intermediate neuron changes the state value over time in response to at least one of the one or more intermediate input signals and at least one of the one or more first-type intermediate signals of the first type of intermediate neuron among the plurality of intermediate signals, where the first type of intermediate neuron has a previous-stage neuron. The second type of intermediate neuron changes the state value over time in response to at least one of the one or more intermediate input signals, at least one of the one or more second-type intermediate signals of the second type of intermediate neuron among the plurality of intermediate signals, where the second type of intermediate neuron has a previous-stage neuron, and the constancy signal. The signal processing device according to claim 8. **Claim 10** Further comprising a plurality of intermediate-output synapses. Each of the plurality of intermediate-output synapses has an intermediate-output synapse load set thereon, and outputs, as a corresponding intermediate output signal among the plurality of intermediate output signals, a signal obtained by multiplying the state value output from any one of the N intermediate neurons, which is a previous-stage neuron, by the set intermediate-output synapse load. Each of the plurality of intermediate-output synapses outputs the intermediate output signal to an output neuron corresponding to the type of the previous-stage neuron among the (M × P) output neurons. The signal processing device according to claim 7. **Claim 11** The intermediate-output synapse load set for each of the plurality of intermediate-output synapses is learned such that, when the M normal input signals are input, for each of the M groups, the combined signal output from each of the P output neurons becomes the signal at a preset time after the corresponding normal input signal among the M normal input signals. The signal processing device according to claim 10.

12. In the output layer, each of the P output neurons included in each of the M groups generates a difference signal representing the difference between the combined signal to be output and the signal at a preset time after the corresponding input signal among the M input signals. The intermediate-output synapse load set for each of the plurality of intermediate-output synapses is learned such that, when the M normal input signals are input, the difference signals of each of the M groups become zero. The signal processing device according to claim 10.

13. The input layer includes M input neurons that correspond one-to-one to the M input signals. Each of the M input neurons acquires the corresponding input signal among the M input signals and outputs an input state value corresponding to the corresponding input signal. The signal processing device according to claim 7.

14. Further comprising one or more input-intermediate synapses. For each of the one or more input-intermediate synapses, an input-intermediate synapse load is set, and a signal obtained by multiplying the input state value output from any one of the M input neurons by the set input-intermediate synapse load is output as the corresponding intermediate input signal among the one or more intermediate input signals. The one or more input-intermediate synapses are grouped into P synapse groups corresponding to the P types of intermediate neurons. Each of the P synapse groups includes Q input-intermediate synapses (Q is an integer of 2 or more). For the Q input-intermediate synapses included in each of the P synapse groups, a set of Q input-intermediate synapse loads that are the same as each other is set. The signal processing device according to claim 13.

15. At least a part of the plurality of intermediate synapses A value obtained by multiplying the state value output from the previous neuron at the first time by the state value output from the subsequent neuron at a second time that is a predetermined time step before the first time, and the state value output from the previous neuron at the second time, and a value obtained by multiplying the state value output from the subsequent neuron at the first time. The intermediate synaptic weight is updated according to the difference between the two values. The signal processing device according to claim 7.

16. At least a part of the plurality of intermediate synapses updates the intermediate synaptic weight according to the membrane potential generated by the subsequent neuron. The signal processing device according to claim 7.

17. A signal processing method for executing signal processing according to a neural network by an information processing device, The information processing device executes processing according to an input layer that acquires M input signals (M is an integer of 1 or more), The information processing device acquires one or more intermediate input signals corresponding to the M input signals, and executes processing according to an intermediate layer that generates a plurality of intermediate signals based on the one or more intermediate input signals. The information processing device acquires a plurality of intermediate output signals, and executes processing according to an output layer that outputs an output signal corresponding to the plurality of intermediate output signals. The intermediate layer includes N intermediate neurons (N is an integer of 2 or more) each of which outputs a state value, and a plurality of intermediate synapses that generate the plurality of intermediate signals. Each of the plurality of intermediate synapses generates a corresponding intermediate signal among the plurality of intermediate signals according to the state value output from any one of the N intermediate neurons. Each of the plurality of intermediate output signals is a signal corresponding to the state value output by any one of the N intermediate neurons. Each of the N intermediate neurons changes the state value over time based on a predetermined update rule according to at least one of the one or more intermediate input signals and the plurality of intermediate signals. The N intermediate neurons include P types with different update rules (P is an integer of 2 or more and N or less). Signal processing method.

18. A program for causing a computer to function as a signal processing device that executes signal processing according to a neural network, The computer is caused to An input layer that acquires M input signals (M is an integer of 1 or more), obtaining one or more intermediate input signals corresponding to the M input signals, and an intermediate layer that generates a plurality of intermediate signals based on the one or more intermediate input signals; obtaining a plurality of intermediate output signals, and an output layer that outputs an output signal corresponding to the plurality of intermediate output signals functioning as such; the intermediate layer includes N intermediate neurons (N is an integer of 2 or more) each of which outputs a state value, and a plurality of intermediate synapses that generate the plurality of intermediate signals; each of the plurality of intermediate synapses generates a corresponding intermediate signal among the plurality of intermediate signals according to the state value output from any one of the N intermediate neurons; each of the plurality of intermediate output signals is a signal corresponding to the state value output by any one of the N intermediate neurons; each of the N intermediate neurons changes the state value over time based on a predetermined update rule according to at least one of the one or more intermediate input signals and the plurality of intermediate signals; the N intermediate neurons include P types with different update rules (P is an integer of 2 or more and N or less) program.

Images