Semiconductor device and method of manufacturing semiconductor device

Abstract

To provide a semiconductor device that has, on one semiconductor substrate, a gate-all-around transistor and a high breakdown voltage transistor which are provided minimizing increase in processes.SOLUTION: A semiconductor device is constituted which has a semiconductor substrate, a nanosheet laminate provided on the semiconductor substrate, a gate-all-around transistor constituted using the nanosheet laminate, and a planar type transistor constituted using the nanosheet laminate, wherein the planar type transistor comprises a gate insulation film provided at the upper part of the nanosheet laminate, a gate electrode provided on the gate insulating film, and a source / drain diffusion layer provided to the nanosheet laminate on both sides of the gate insulation film and the gate electrode.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

Background Art

[0002] As a technology related to a semiconductor device and a method for manufacturing a semiconductor device, Non-Patent Document 1 below discloses a configuration in which a bulk FinFET and a bulk planar FET are provided on the same wafer. Further, Non-Patent Document 1 below describes, as a manufacturing process of a semiconductor device having such a configuration, patterning a silicon substrate using a silicon nitride hard mask and then removing the hard mask in the planar FET region using a polysilicon gate electrode as a mask.

Prior Art Documents

Non-Patent Documents

[0003]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, for the purpose of further enhancing the functionality of semiconductor devices, a gate all around (GAA) field effect transistor (FET) has been proposed, in which the entire periphery of a semiconductor thin film having a nanosheet structure is surrounded by a gate insulating film and a gate electrode. Such a gate all around transistor has low breakdown voltage characteristics because the gate insulating film is very thin. However, in the circuit design of semiconductor devices, high breakdown voltage transistors are essential for forming circuits with high breakdown voltage characteristics, such as input / output circuits. In addition, in order to reduce wafer costs and obtain compatibility in circuit design, a technology for forming a gate all around transistor and a high breakdown voltage transistor on the same semiconductor substrate while minimizing the increase in processes is required.

[0005] Therefore, an object of the present invention is to provide a semiconductor device having a gate all around transistor and a high breakdown voltage transistor provided on the same semiconductor substrate while minimizing the increase in processes, and a method for manufacturing the semiconductor device.

Means for Solving the Problems

[0006] The present invention for achieving such an object includes a semiconductor substrate, a nanosheet laminate provided on the semiconductor substrate, a gate all around transistor configured using the nanosheet laminate, and a planar transistor configured using the nanosheet laminate. The planar transistor includes a gate insulating film provided on the upper part of the nanosheet laminate, a gate electrode provided on the gate insulating film, and source / drain diffusion layers provided in the nanosheet laminate on both sides of the gate insulating film and the gate electrode.

Effects of the Invention

[0007] According to the present invention, it is possible to provide a semiconductor device having a gate all around transistor and a high breakdown voltage transistor provided while minimizing the increase in processes, and a method for manufacturing the semiconductor device.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Figure 28

Figure 29

Figure 30

Figure 31

Figure 32

Embodiments for Carrying Out the Invention

[0009] Hereinafter, each embodiment to which the present invention is applied will be described in detail with reference to the drawings. In each of the embodiments described below, the same reference numerals are given to the same components, and redundant descriptions are omitted.

[0010] <<First Embodiment>> <Configuration of Semiconductor Device 1 of the First Embodiment> FIG. 1 is a cross-sectional view of a main part of a semiconductor device 1 according to the first embodiment. The semiconductor device 1 shown in FIG. 1 has a full-around gate transistor 1a and a planar transistor 1b on one main surface of a semiconductor substrate 100. FIG. 1 shows a cross-section in the gate length direction [Lg] and a cross-section in the gate width direction [Wd] of the full-around gate transistor 1a and the planar transistor 1b.

[0011] These full-around gate transistor 1a and planar transistor 1b are configured using a nanosheet stack 103 formed on one main surface of the semiconductor substrate 100.

[0012] Among these, the full-around gate transistor 1a is used, for example, as a device constituting a logic circuit. Such a full-around gate transistor 1a is configured using a plurality of silicon layers 102 constituting the nanosheet stack 103. The plurality of silicon layers 102 are stacked with a gap therebetween, and the full-around gate transistor 1a has a Gate All Around (GAA) structure in which a gate insulating film 123i and a gate electrode 124g are provided so as to surround the entire circumference of each of these silicon layers 102. The full-around gate transistor 1a also has source / drains 114sd erected on the semiconductor substrate 100 at both ends in the gate length direction [Lg] of the silicon layer 102.

[0013] On the other hand, the planar transistor 1b is used as a high-voltage device that constitutes an input / output circuit. Such a planar transistor 1b has a gate insulating film 107i and a gate electrode 108g provided on a nanosheet laminate 103 in which a silicon germanium layer 101 and a silicon layer 102 are alternately laminated. The silicon layer 102 is the same layer as the silicon layer 102 of the all-around gate transistor 1a. The gate insulating film 107i is a thick film as compared with the gate insulating film 123i of the all-around gate transistor 1a. Also, the planar transistor 1b has source / drain diffusion layers 103sd provided in the nanosheet laminate 103 on both sides in the gate length direction [Lg] of the gate insulating film 107i and the gate electrode 108g.

[0014] <Method of manufacturing a semiconductor device according to the first embodiment> Figs. 2 to 17 are process diagrams (Part 1) to (Part 16) showing the method of manufacturing a semiconductor device according to the first embodiment. Hereinafter, the detailed configuration of the semiconductor device 1 described above will be described in the order of the manufacturing process of the semiconductor device 1 shown in Figs. 2 to 17.

[0015] First, as shown in Fig. 2, a nanosheet laminate 103 in which a silicon germanium layer 101 and a silicon layer 102 are alternately laminated (for example, three layers at a time) is formed on one main surface of a semiconductor substrate 100 made of single crystal silicon. Thereafter, the nanosheet laminate 103 is patterned and separated into an active region (hereinafter referred to as GAA region 10a) for forming the all-around gate transistor 1a and an active region (hereinafter referred to as planar region 10b) for forming the planar transistor 1b. Here, the nanosheet laminate 103 is separated in both the gate length direction [Lg] and the gate width direction [Wd]. At this time, the one main surface side of the semiconductor substrate 100 is also etched back to form a groove 100a.

[0016] Next, as shown in FIG. 3, the trench 100a provided on one main surface side of the semiconductor substrate 100 is filled with an insulating material to form a trench-type element isolation (Shallow Trench Isolation: STI) 104. Then, a silicon oxide film 105 is formed so as to cover the surfaces of the nanosheet laminate 103 and the trench-type element isolation 104. Next, a resist pattern 106 having a shape that covers the GAA region 10a and exposes the planar region 10b is formed on the upper part of the silicon oxide film 105. Next, a channel diffusion layer 103ch is formed in the surface layer of the nanosheet laminate 103 in the planar region 10b by ion implantation (Ion Implantation: I / I) using the resist pattern 106 as a mask. After the ion implantation for forming the channel diffusion layer 103ch, the resist pattern 106 is removed.

[0017] In addition, in the formation of the channel diffusion layer 103ch, ion implantation using individual masks is to be performed in the formation region of the n-channel transistor and the formation region of the p-channel transistor. After the ion implantation, the silicon oxide film 105 is removed.

[0018] Next, as shown in FIG. 4, an insulating film 107, a gate electrode layer 108, a first hard mask layer 109, and a second hard mask layer 110 are formed in this order on one main surface of the semiconductor substrate 100 on which the nanosheet laminate 103 is formed. These are, for example, the insulating film 107 is silicon oxide, the gate electrode layer 108 is polysilicon containing impurities, the first hard mask layer 109 is silicon nitride, and the second hard mask layer 110 is silicon oxide.

[0019] Next, using a resist pattern (not shown here) as a mask, the second hard mask layer 110 and the first hard mask layer 109 are etched, and further the gate electrode layer 108 and the insulating film 107 are etched. Thereby, gate patterns 110a and 110b are formed in the GAA region 10a and the planar region 10b.

[0020] Next, as shown in FIG. 5, a high-k dielectric film 111 is formed on one main surface of the semiconductor substrate 100 so as to cover the gate patterns 110a and 110b. Then, a resist pattern 112 having a shape that covers the planar region 10b and exposes the GAA region 10a is formed on the high-k dielectric film 111. Next, using the resist pattern 112 as a mask, the high-k dielectric film 111 is etched to form sidewalls 111sw of the high-k dielectric film 111 on the sidewalls of the gate pattern 110a in the GAA region 10a. After the sidewalls 111sw are formed, the resist pattern 112 is removed.

[0021] Next, as shown in FIG. 6, the nanosheet stack 103 in the GAA region 10a is etched using the high-k dielectric film 111, the sidewalls 111sw, and the gate pattern 110a as masks.

[0022] Next, as shown in FIG. 7, the silicon germanium layer 101 exposed on the sidewalls of the nanosheet stack 103 is selectively thinned by isotropic etching. Next, inner spacers 113sp are formed on the exposed sidewalls of the silicon germanium layer 101 so as to fill the spaces between the silicon layers 102. The inner spacers 113sp are formed by first depositing a silicon nitride film by isotropic deposition so as to fill the spaces between the silicon layers 102. Then, the silicon nitride film is etched back by anisotropic etching. As a result, the silicon nitride film remains only between the silicon layers 102, and the silicon nitride film remaining between the silicon layers 102 is formed as the inner spacers 113sp.

[0023] Next, as shown in FIG. 8, source / drains 114sd are formed at both ends in the gate length direction [Lg] of the nanosheet stack 103 in the GAA region 10a. At this time, source / drains 114sd made of silicon containing impurities are formed by epitaxial growth from the exposed surfaces of the silicon layers 102 and the semiconductor substrate 100. Also, after the epitaxial growth process, a process of cutting the unnecessary epitaxial layer is performed.

[0024] In forming the source / drain 114sd, epitaxial growth using individual masks is to be performed in the formation regions of n-channel transistors and p-channel transistors.

[0025] Thereafter, a liner film 115 made of silicon nitride is formed so as to cover the upper side of one main surface side of the semiconductor substrate 100.

[0026] Next, as shown in FIG. 9, the liner film 115 and the high-k dielectric film 111 in the planar region 10b are etched back by anisotropic etching. Thereby, the gate pattern 110b and the nanosheet laminate 103 on both sides in the channel length direction [Lg] of the gate pattern 110b are exposed. Thereafter, a source / drain diffusion layer 103sd is formed by ion implantation on the surface side of the exposed nanosheet laminate 103.

[0027] Note that the above steps are performed in a state where the GAA region 10a is covered with a resist pattern (not shown here). Also, in forming the source / drain diffusion layer 103sd, ion implantation using individual resist patterns as masks is to be performed in the formation regions of n-channel transistors and p-channel transistors. After the steps are completed, the resist pattern is removed.

[0028] Next, as shown in FIG. 10, a second liner film 116 made of silicon nitride is formed so as to cover the upper side of one main surface side of the semiconductor substrate 100, and further, the upper side of one main surface side of the semiconductor substrate 100 is filled with a buried insulating film 117 made of silicon oxide. Thereafter, planarization processing is performed by chemical mechanical polishing (CMP) until the first hard mask layer 109 made of silicon nitride is exposed.

[0029] Next, as shown in FIG. 11, a third hard mask layer 118 made of silicon nitride is formed above one main surface side of the semiconductor substrate 100, and a resist pattern 119 is formed on the upper portion thereof. The resist pattern 119 is a pattern for determining the size in the gate width direction [Wd] of the planar transistor formed in the planar region 10b. By etching using this resist pattern 119 as a mask, the third hard mask layer 118, the first hard mask layer 109, the gate electrode layer 108, the insulating film 107, and the nanosheet laminate 103 in the planar region 10b are patterned.

[0030] Thereby, a gate insulating film 107i formed by patterning the insulating film 107 and a gate electrode 108g formed by patterning the gate electrode layer 108 are formed in the planar region 10b. Also thereby, a planar transistor 1b is formed in the planar region 10b.

[0031] Next, as shown in FIG. 12, a liner film 120 made of silicon nitride is formed on the exposed sidewall in the gate width direction [Wd] in the planar region 10b and the exposed surface of the semiconductor substrate 100. Thereafter, the etched portion of the planar region 10b is filled with a buried insulating film 121 made of silicon oxide. Thereafter, the resist pattern 119 is removed.

[0032] Next, as shown in FIG. 13, a planarization process is performed by CMP until the first hard mask layer 109 is exposed.

[0033] Next, as shown in FIG. 14, a resist pattern 122 is formed so as to cover the planar region 10b. Thereafter, the sidewall 111sw composed of the second liner film 116, the liner film 115, the first hard mask layer 109, and the high-k dielectric film 111 made of silicon nitride is selectively etched using the resist pattern 122 as a mask to expose the gate electrode layer 108. Further, the gate electrode layer 108 made of polysilicon containing impurities is selectively etched and removed to expose the insulating film 107 made of silicon oxide.

[0034] Next, as shown in FIG. 15, in the GAA region 10a, the insulating film 107 made of silicon oxide and the silicon germanium layer 101 of the nanosheet laminate 103 are selectively removed. Thereafter, the resist pattern 122 is removed.

[0035] Next, as shown in FIG. 16, in the GAA region 10a, an insulating film 123 in which a silicon oxide layer and a high-k dielectric film are laminated is isotropically formed over the entire main surface side of the semiconductor substrate 100 in a state of covering the entire circumference of the exposed silicon layer 102. Next, an electrode material layer 124 is formed on the insulating film 123 so as to fill the space between the silicon layers 102 in the GAA region 10a, and the exposed surface of the silicon layer 102 is covered with the electrode material layer 124 via the insulating film 123.

[0036] Next, as shown in FIG. 17, the insulating film 123 and the electrode material layer 124 are patterned to form a gate insulating film 123i and a gate electrode 124g in the GAA region 10a. Further, in the GAA region 10a, an electrode material layer 125 connected to the gate electrode 124g and a buried plug 126 are patterned. Thereby, a full-around gate transistor 1a is formed in the GAA region 10a.

[0037] Thereafter, as shown in FIG. 1, a cap insulating film 127 is formed so as to cover the upper side of the main surface side of the semiconductor substrate 100. Thereafter, a source / drain 114sd and a gate electrode 124g of the full-around gate transistor 1a, and further a via 128 connected to the source / drain diffusion layer 103sd and the gate electrode 108g of the planar transistor 1b are formed to obtain the semiconductor device 1 described above.

[0038] <Effect of the First Embodiment> According to the first embodiment described above, the all-around gate transistor 1a and the planar transistor 1b can be formed on the same semiconductor substrate 100 using the same nanosheet laminate 103. Further, since the gate insulating film 107i of the planar transistor 1b is formed in a process different from that of the gate insulating film 123i of the all-around gate transistor 1a, there is a high degree of freedom in adjusting the film thickness. Therefore, the film thickness of the gate insulating film 107i can be increased to form a planar transistor 1b with high breakdown voltage.

[0039] As a result, by using the same nanosheet laminate 103, it is possible to obtain the semiconductor device 1 in which the all-around gate transistor 1a and the high-breakdown-voltage planar transistor 1b are provided on the same semiconductor substrate 100 while minimizing the increase in the process.

[0040] <<Second Embodiment>> The second embodiment is a modified example of the manufacturing method of the semiconductor device 1 described in the first embodiment, and is an example in which the timing of separating the planar region 10b is different. FIGS. 18 to 20 are process diagrams (Part 1) to (Part 3) showing the characteristic portions of the manufacturing method of the semiconductor device of the second embodiment. Hereinafter, the manufacturing method of the second embodiment, which is a modified example of the manufacturing method of the semiconductor device 1 described above, will be described with reference to FIGS. 18 to 20.

[0041] First, as shown in FIG. 18, a nanosheet laminate 103 in which a silicon germanium layer 101 and a silicon layer 102 are alternately laminated (for example, three layers at a time) is formed on one main surface of the semiconductor substrate 100. Then, the nanosheet laminate 103 is patterned and separated into an active region (hereinafter referred to as the GAA region 10a) for forming the all-around gate transistor 1a and an active region (hereinafter referred to as the planar region 10b) for forming the planar transistor 1b. At this time, for the planar region 10b, separation is performed only in the gate length direction [Lg], and the gate width direction [Wd] is left continuous without separation.

[0042] Thereafter, the steps described with reference to FIGS. 3 to 17 in the first embodiment may be performed in the same manner as described in the first embodiment.

[0043] In this case, in the process shown in FIG. 19 corresponding to the process shown in FIG. 10 of the first embodiment, similar to the first embodiment, the upper part on one main surface side of the semiconductor substrate 100 is planarized.

[0044] And in the process shown in FIG. 20 corresponding to the process shown in FIG. 11 of the first embodiment, by etching using the resist pattern 119 as a mask, the third hard mask layer 118, the first hard mask layer 109, the gate electrode layer 108, the insulating film 107, and the nanosheet laminate 103 in the plainer region 10b are patterned. This process is also carried out in the same manner as in the first embodiment, but in this process, the gate width direction [Wg] in the plainer region 10b is separated.

[0045] <Effect of the Second Embodiment> Even with the above-described process procedure, the same semiconductor device 1 as in the first embodiment can be obtained, and the same effects can be obtained.

[0046] ≪Third Embodiment≫ The third embodiment is a modification of the first embodiment and is an example in which the formation procedure of the channel diffusion layer 103ch of the plainer type transistor 1b is different. FIGS. 21 to 25 are process diagrams (Part 1) to (Part 5) showing the characteristic parts of the manufacturing method of the semiconductor device of the third embodiment. Hereinafter, the manufacturing method of the third embodiment, which is a modification of the manufacturing method of the semiconductor device 1 described above, will be described with reference to the drawings used in the description of the first embodiment and FIGS. 21 to 25.

[0047] First, as described with reference to FIG. 2 in the first embodiment, the region separation between the GAA region 10a and the plainer region 10b is performed. Then, without performing the formation of the channel diffusion layer 103ch described with reference to FIG. 3, the processes described with reference to FIGS. 4 to 13 are performed.

[0048] Next, as shown in FIG. 21, in both the GAA region 10a and the planar region 10b, the second liner film 116, the liner film 115, the first hard mask layer 109, and the high-k dielectric film 111 made of silicon nitride are selectively etched to expose the gate electrode layer 108. Further, the gate electrode layer 108 made of polysilicon containing impurities is selectively etched, and subsequently, the insulating film 107 made of silicon oxide is also etched and removed.

[0049] Next, as shown in FIG. 22, a resist pattern 301 is formed to cover the GAA region 10a. Next, after forming a sacrificial oxide film (not shown here), a channel diffusion layer 103ch is formed in the silicon layer 102 that constitutes the surface layer of the nanosheet stack 103 in the planar region 10b by ion implantation through the sacrificial oxide film. Then, after removing the sacrificial oxide film, an insulating film 107 made of silicon oxide is formed again in the planar region 10b and used as the gate insulating film 107i of the planar transistor.

[0050] Thereafter, in the first embodiment, the steps described with reference to FIGS. 15 to 17 may be similarly implemented. However, when forming the gate insulating film and the gate electrode in the GAA region 10a, the gate insulating film and the gate electrode are also formed in the planar region 10b in the same process.

[0051] In this case, first, as shown in FIG. 23, a resist pattern 122 is formed to cover the planar region 10b. Using this resist pattern 122 as a mask, the silicon germanium layer 101 of the nanosheet stack 103 in the GAA region 10a is selectively removed. Thereafter, the resist pattern 122 is removed.

[0052] Next, as shown in FIG. 24, in the GAA region 10a, an insulating film 123 in which a silicon oxide layer and a high-k dielectric film are laminated is isotropically formed on the entire main surface side of the semiconductor substrate 100 in a state of covering the entire circumference of the exposed silicon layer 102. As a result, in the planar region 10b, an insulating film 123 in which a silicon oxide layer and a high-k dielectric film are laminated is formed on the insulating film 107 made of silicon oxide.

[0053] Next, an electrode material layer 124 is formed on the insulating film 123 so as to fill the space between the silicon layers 102 in the GAA region 10a, and the exposed surface of the silicon layer 102 is covered with the electrode material layer 124 via the insulating film 123. As a result, in the planar region 10b, an electrode material layer 124 is formed on the insulating film 123.

[0054] Next, as shown in FIG. 25, the electrode material layer 124 and the insulating film 123 are patterned to form a gate electrode 124g and a gate insulating film 123i in the GAA region 10a, and a gate electrode 124g' and a gate insulating film 107i' in the planar region 10b. The gate insulating film 107i' in the planar region 10b is composed of a laminated film of the insulating films 107 and 123.

[0055] Furthermore, electrode material layers 125 and 125' connected to the gate electrodes 124g and 124g', and buried plugs 126 and 126' are patterned. As a result, a fully surrounded gate transistor 1a is formed in the GAA region 10a, and a planar transistor 1b is formed in the planar region 10b.

[0056] <Effect of the Third Embodiment> With the procedure of the steps of the above-described third embodiment, a semiconductor device 1 similar to that of the first embodiment can be obtained, in which the gate electrodes 124g and 124g' have the same configuration in the fully surrounded gate transistor 1a and the planar transistor 1b. In addition, since the gate insulating film 107i' of the planar transistor 1b is composed of a laminated film of the insulating films 107 and 123, it is easier to adjust the film thickness (increase the film thickness).

[0057] <<Fourth Embodiment>> The fourth embodiment is a modification of the third embodiment. In the p-channel planar transistor 1b, an example is given where the formation position of the channel diffusion layer 103ch is the silicon germanium layer 101. FIGS. 26 to 27 are process diagrams (Part 1) to (Part 2) showing the characteristic parts of the manufacturing method of the semiconductor device according to the fourth embodiment. Hereinafter, the manufacturing method of the fourth embodiment, which is a modification of the manufacturing method of the semiconductor device 1 described above, will be described with reference to the drawings used in the description of the first embodiment and FIGS. 26 to 27.

[0058] First, as described with reference to FIG. 2 in the first embodiment, the region separation between the GAA region 10a and the planar region 10b is performed. Thereafter, the formation of the channel diffusion layer 103ch described with reference to FIG. 3 is not performed, and the processes described with reference to FIGS. 4 to 13 are performed.

[0059] Next, as shown in FIG. 26, in both the GAA region 10a and the planar region 10b, the second liner film 116, the liner film 115, the first hard mask layer 109, and the high-k dielectric film 111 made of silicon nitride are selectively etched to expose the gate electrode layer 108. Further, the gate electrode layer 108 made of polysilicon containing impurities is selectively etched, and subsequently, the insulating film 107 made of silicon oxide is also etched and removed.

[0060] Thereafter, a resist pattern 302 is formed to cover the formation regions of the n-channel transistors in the GAA region 10a and the planar region 10b and expose the formation region of the p-channel transistor in the planar region 10b. Next, using this resist pattern 302 as a mask, the silicon layer 102 under the insulating film 107 in the formation region of the p-channel transistor in the planar region 10b is etched and removed. As a result, the silicon germanium layer 101 is exposed in the formation region of the p-channel transistor in the planar region 10b.

[0061] Next, as shown in FIG. 27, an insulating film 107 made of silicon oxide is formed again in the planar region 10b, and this is used as the gate insulating film 107i of the planar transistor.

[0062] Thereafter, a p-type channel diffusion layer 103ch’ is formed in the silicon germanium layer 101 of the surface layer of the nanosheet laminate 103 by ion implantation using the resist pattern 302 as a mask. Note that in the formation region of the n-channel transistor in the plainer region 10b, an insulating film 107 is formed using a different mask, and an n-channel diffusion layer is formed in the silicon layer 102 constituting the surface layer of the nanosheet laminate 103 by ion implantation.

[0063] Thereafter, in the third embodiment, the steps described with reference to FIGS. 23 to 25 may be similarly performed.

[0064] <Effect of the Fourth Embodiment> According to the fourth embodiment described above, by forming the p-type channel diffusion layer 103ch’ in the silicon germanium layer 101, in addition to the effects of the first embodiment, a plainer-type transistor 1b of a p-channel with high mobility can be obtained.

[0065] ≪Fifth Embodiment≫ FIG. 28 is a cross-sectional view of a main part of a semiconductor device 5 according to the fifth embodiment, showing a cross-section in the channel length direction [Lg] of the transistor included in the semiconductor device 5. The difference between the semiconductor device 5 shown in FIG. 28 and the semiconductor device 1 of the first embodiment is that the plainer-type transistor 1b’ is provided in a silicon laminate 303 formed using a nanosheet laminate. The configuration of the all-around gate transistor 1a is the same as that of the first embodiment.

[0066] The planar transistor 1b’ is used as a high-voltage device constituting an input / output circuit. Such a planar transistor 1b’ is provided in a silicon laminate 303. The silicon laminate 303 has a structure in which single-crystalline silicon layers 303a are laminated, and is formed by processing a nanosheet laminate in which silicon germanium layers and silicon layers are alternately laminated as will be described hereinafter. The planar transistor 1b’ has a gate insulating film 107i’ and a gate electrode 124g’ provided on the silicon laminate 303. Further, the planar transistor 1b’ has source / drain diffusion layers 303sd provided in the silicon laminate 303 as a nanosheet laminate on both sides in the gate length direction [Lg] of the gate insulating film 107i’ and the gate electrode 124g’.

[0067] <Manufacturing Method of Semiconductor Device of Fifth Embodiment> Figs. 29 to 32 are process diagrams (Part 1) to (Part 4) showing the characteristic parts of the manufacturing method of the semiconductor device 5 of the fifth embodiment. Hereinafter, the manufacturing method of the semiconductor device 5 of the fifth embodiment described above will be described with reference to the drawings used in the description of the first embodiment and Figs. 29 to 32.

[0068] First, as described with reference to Fig. 2 in the first embodiment, the region separation between the GAA region 10a and the planar region 10b is performed. Thereafter, the formation of the channel diffusion layer 103ch described with reference to Fig. 3 is not performed, and the processes described with reference to Figs. 4 to 13 are performed.

[0069] Next, as shown in Fig. 29, in both the GAA region 10a and the planar region 10b, the second liner film 116, the liner film 115, the first hard mask layer 109, and the high-k dielectric film 111 made of silicon nitride are selectively etched to expose the gate electrode layer 108. Further, the gate electrode layer 108 made of polysilicon containing impurities is selectively etched, and subsequently, the insulating film 107 made of silicon oxide is also etched and removed.

[0070] Next, as shown in FIG. 30, in the GAA region 10a and the planar region 10b, the silicon germanium layer 101 of the nanosheet laminate 103 is selectively removed, leaving only the silicon layer 102. As a result, the source / drain diffusion layer 103sd formed in the planar region 10b is in a state of being divided in the stacking direction of the nanosheet laminate 103.

[0071] Next, as shown in FIG. 31, a resist pattern 304 is formed so as to cover the GAA region 10a. Then, using the resist pattern 304 as a mask, silicon is epitaxially grown from the silicon layer 102 of the planar region 10b and the semiconductor substrate 100. As a result, a silicon laminate 303 is formed in which a single crystal silicon layer 303a made of single crystal silicon is stacked on the semiconductor substrate 100 in the planar region 10b. This silicon laminate 303 has an interface surface of the upper and lower silicon layers 102 (see FIG. 30) and the single crystal silicon layer 303a epitaxially grown from the semiconductor substrate 100. Also, in the silicon laminate 303, impurities are diffused from the divided source / drain diffusion layer 103sd into the epitaxially grown portion. As a result, a source / drain diffusion layer 303sd continuous in the depth direction of the silicon laminate 303 is formed.

[0072] Next, as shown in FIG. 32, after forming a sacrificial oxide film (not shown here), a channel diffusion layer 303ch is formed in the surface layer of the silicon laminate 303 in the planar region 10b by ion implantation through the sacrificial oxide film. Then, after removing the sacrificial oxide film, an insulating film 107 made of silicon oxide is formed again in the planar region 10b, and this is used as the gate insulating film 107i of the planar type transistor.

[0073] Thereafter, in the third embodiment, the steps described with reference to FIGS. 23 to 25 may be similarly implemented. <Effect of the Fifth Embodiment> According to the fifth embodiment described above, since the planar transistor 1b is formed in the silicon laminate 303 in which the single crystal silicon layer 303a is laminated, in addition to the effects of the first embodiment, it is possible to obtain capabilities comparable to those of a planar transistor formed on a normal semiconductor substrate. In particular, an improvement in punch-through resistance is expected.

Explanation of Signs

[0074] 1, 5… Semiconductor device 1a… All-around gate transistor 1b, 1b’… Planar transistor 10a… GAA region 10b… Planar region 100… Semiconductor substrate 101… Silicon germanium layer 102… Silicon layer 103… Nanosheet laminate 103ch… Channel diffusion layer 103ch’… p-type channel diffusion layer 103sd… Source / drain diffusion layer 107… Insulating film 107i, 107i’… Gate insulating film 108… Gate electrode layer 108g… Gate electrode 110a, 110b… Gate pattern 111… High-k dielectric film 114sd… Source / drain 123… Insulating film 123i… Gate insulating film 124… Electrode material layer 124g… Gate electrode 124g’… Gate electrode 125… Electrode material layer 303… Silicon laminate 303a… Single crystal silicon layer 303ch… Channel diffusion layer 303sd… Source / drain diffusion layer

Claims

1. A semiconductor substrate, a nanosheet laminate provided on the semiconductor substrate, a full-around gate transistor configured using the nanosheet laminate, and a planar-type transistor configured using the nanosheet laminate, wherein the planar-type transistor includes a gate insulating film provided on top of the nanosheet laminate, a gate electrode provided on the gate insulating film, and source / drain diffusion layers provided in the nanosheet laminate on both sides of the gate insulating film and the gate electrode a semiconductor device.

2. The nanosheet laminate constituting the full-around gate transistor and the nanosheet laminate constituting the planar-type transistor are configured using the same silicon layer, the full-around gate transistor has a gate insulating film surrounding the entire circumference of the silicon layer, and the gate insulating film of the planar-type transistor is thicker than the gate insulating film of the full-around gate transistor The semiconductor device according to claim 1.

3. The nanosheet laminate constituting the full-around gate transistor has a structure in which a plurality of silicon layers are stacked with intervals therebetween, the nanosheet laminate constituting the planar-type transistor has a structure in which a plurality of silicon layers and a plurality of silicon germanium layers are alternately stacked, and the nanosheet laminate constituting the full-around gate transistor and the nanosheet laminate constituting the planar-type transistor are configured using the same silicon layer The semiconductor device according to claim 1.

4. The semiconductor substrate is provided with a plurality of the planar-type transistors, wherein among the plurality of planar-type transistors, the n-channel transistor has an n-type channel diffusion layer in the silicon layer, and the gate insulating film is provided in contact with the n-type channel diffusion layer, and among the plurality of planar-type transistors, the p-channel transistor has a p-type channel diffusion layer in the silicon germanium layer, and the gate insulating film is provided in contact with the p-type channel diffusion layer The semiconductor device according to claim 3.

5. The nanosheet laminate constituting the full-around gate transistor has a structure in which a plurality of silicon layers are stacked with intervals therebetween, and the nanosheet laminate constituting the planar-type transistor has a structure in which a plurality of silicon layers are stacked The semiconductor device according to claim 1.

6. The nano-sheet laminate constituting the planar transistor has a structure in which single-crystalline silicon layers are laminated. The semiconductor device according to claim 5.

7. The gate electrode of the all-around gate transistor and the gate electrode of the planar transistor are made of the same electrode material layer. The semiconductor device according to claim 1.

8. A step of forming a nano-sheet laminate in which a first semiconductor layer and a second semiconductor layer on a semiconductor substrate are alternately laminated; A step of forming a gate pattern in an all-around gate region and a planar region on the nano-sheet laminate; A step of patterning the nano-sheet laminate in the all-around gate region using the gate pattern as a mask, and forming source / drain by epitaxial growth from the exposed surface of the second semiconductor layer; A step of forming a source / drain diffusion layer in the nano-sheet laminate in the planar region by ion implantation using the gate pattern as a mask; Removing the gate pattern in the all-around gate region, and further selectively removing the first semiconductor layer with respect to the second semiconductor layer, and then forming a gate insulating film and a gate electrode surrounding the entire circumference of the second semiconductor layer in the all-around gate region; A step of forming a gate insulating film and a gate electrode on the upper part of the nano-sheet laminate in the planar region. A method of manufacturing a semiconductor device.

9. The gate pattern has an insulating layer provided in contact with the nano-sheet laminate and an electrode layer on the upper part thereof, In the planar region, a gate insulating film made of the insulating layer and a gate electrode made of the electrode layer are formed. The method of manufacturing a semiconductor device according to claim 8.

10. Before forming the gate pattern on the nano-sheet laminate, a step of forming a channel diffusion layer in the surface layer of the nano-sheet laminate in the planar region is included. The method of manufacturing a semiconductor device according to claim 8.

11. Before forming the gate pattern on the nano-sheet laminate, a step of patterning the nano-sheet laminate is included. The method of manufacturing a semiconductor device according to claim 8.

12. After forming a source / drain diffusion layer in the planar region, a step of patterning the nano-sheet laminate in the planar region is included. The method of manufacturing a semiconductor device according to claim 11.

13. After forming the source / drain diffusion layer in the planar region, The step of removing the gate pattern in the plenary region; The step of forming an insulating layer on the exposed surface of the nanosheet laminate in the plenary region; And a step of forming a channel diffusion layer on the surface layer of the nanosheet laminate in the plenary region The method of manufacturing a semiconductor device according to claim 8.

14. After forming the channel diffusion layer, Removing the first semiconductor layer selectively with respect to the second semiconductor layer in the entire peripheral gate region Forming a gate insulating film surrounding the entire periphery of the second semiconductor layer in the entire peripheral gate region and in contact with the insulating layer in the plenary region; And a step of forming an electrode material layer for filling between the second semiconductor layers in the entire peripheral gate region on the gate insulating film in the entire peripheral gate region and the plenary region The method of manufacturing a semiconductor device according to claim 13.

15. The first semiconductor layer is a silicon germanium layer, The second semiconductor layer is a silicon layer, After removing the gate pattern in the plenary region, further removing the silicon layer constituting the surface layer of the nanosheet laminate to expose the silicon germanium layer, In the step of forming the channel diffusion layer in the plenary region, a p-type channel diffusion layer is formed on the silicon germanium layer The method of manufacturing a semiconductor device according to claim 13.

16. After forming the source / drain diffusion layer in the plenary region, Removing the gate pattern in the entire peripheral gate region and the plenary region, and further removing the first semiconductor layer selectively with respect to the second semiconductor layer; And a step of forming a nanosheet laminate composed of a second semiconductor layer integrated by epitaxially growing the second semiconductor layer in the plenary region The method of manufacturing a semiconductor device according to claim 8.

17. The laminate of the second semiconductor layers is a laminate of single crystal silicon layers The method of manufacturing a semiconductor device according to claim 16.

18. The step of forming an insulating layer on the exposed surface of the nanosheet laminate composed of the second semiconductor layer in the plenary region; And a step of forming a channel diffusion layer on the nanosheet laminate composed of the second semiconductor layer exposed in the plenary region The method of manufacturing a semiconductor device according to claim 16.

19. After forming the channel diffusion layer, A step of forming a gate insulating film surrounding the entire circumference of the second semiconductor layer in the all-around gate region and in contact with the insulating layer in the planar region; A step of forming an electrode material layer filling between the second semiconductor layers in the all-around gate region on the gate insulating film in the all-around gate region and the planar region. The method of manufacturing a semiconductor device according to claim 18.

Images