Semiconductor device

Abstract

To provide a semiconductor device capable of maintaining connection relationship between logic circuit sections or a circuit configuration in each logic circuit section even if supply of power source voltage is stopped, and capable of changing the connection relationship between the logic circuit sections or the circuit configuration in each logic circuit section at high speed.SOLUTION: In a circuit which is reconfigurable, an oxide semiconductor is used as a semiconductor element for storing data such as circuit configuration and connection relationship. The oxide semiconductor is especially used in a channel formation region of the semiconductor element.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The technical field relates to a semiconductor device, a method for driving a semiconductor device, and a method for manufacturing a semiconductor device. In particular, the semiconductor device relates to a semiconductor integrated circuit having semiconductor elements such as transistors. .

Background Art

[0002] As one type of semiconductor integrated circuit, there is a Programmable Logic Device (PLD). A PLD is an integrated circuit in which the internal circuit configuration and the like can be determined and changed (reconfigurable) after manufacturing (see Patent Document 1). ).

[0003] Compared with conventional ASICs (Application Specific Integrated Circuits) and the like, PLDs have advantages such as the ability to shorten the development period and the ability to flexibly respond to changes in design specifications, and their use in various devices is progressing.

[0004] For example, a PLD has a plurality of logic circuit units and wirings between the logic circuit units. By changing the circuit configuration within each logic circuit unit or the connection relationship between the logic circuit units, the function of the PLD can be changed.

[0005] Furthermore, the PLD may have a memory circuit, and the memory circuit can store information on the circuit configuration within the logic circuit unit and information on the connection relationship between the logic circuit units.

[0006] Note that, for example, an Arithmetic Logic Unit (ALU) is used as the logic circuit unit. An ALU generally includes an adder, a subtractor, and the like. ​ An arithmetic operation unit combined with a shift operation unit having a shift circuit, and a selection circuit such as a multiplexer that selects and outputs them, is composed of a logical operation unit combined with an AND circuit, an OR circuit, etc.,

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] When using SRAM or DRAM as the above storage circuit, changes in the connection relationship between ALUs, or changes in the circuit configuration within each ALU can be performed at high speed. However, since SRAM and D RAM are volatile, when the supply of the power voltage is stopped, the stored information is lost and ends up.

[0009] Also, when using flash memory as the above storage circuit, since it is non-volatile, information can be maintained even when the supply of the power voltage is stopped. However, since the driving voltage is high, it is difficult to perform high-speed operation and reduce power consumption.

[0010] In view of the above, in one aspect of the present invention, a semiconductor device that can maintain the connection relationship between logic circuit units or the circuit configuration within each logic circuit unit for a long time even when the supply of the power voltage is stopped is provided. This is one of the problems.

[0011] Also, in one aspect of the present invention, changes in the connection relationship between logic circuit units, or within each logic circuit unit An object of the present invention is to provide a semiconductor device that can change a circuit configuration at high speed. [Means for solving the problem]

[0012] One embodiment of the present invention includes a memory circuit that stores information such as a circuit configuration, Specifically, the semiconductor device is a P LD (Programmable Logic Device), which consists of a logic circuit section and A memory circuit is provided. The memory circuit is provided with a logic circuit section. The circuit configuration is maintained.

[0013] It is also preferable that the semiconductor device has a plurality of the logic circuit units. The memory circuit maintains the circuit configuration of each logic circuit unit or the connection relationship between the logic circuit units. The circuit section can use ALU (Arithmetic Logic Unit). , an arithmetic circuit, a selection circuit, etc.

[0014] In this specification, a PLD is also called a reconfigurable circuit.

[0015] In this specification, a semiconductor device is a device that functions by using a semiconductor (an element). Semiconductor devices generally refer to semiconductor elements (transistors, diodes, etc.), Electrical devices incorporating such semiconductor elements (electronic circuits, display devices, light-emitting devices, etc.) and their electrical This category includes electronic devices equipped with electromagnetic devices.

[0016] Another embodiment of the present invention is a semiconductor memory device including a plurality of arithmetic circuits, a selection circuit, and a memory circuit. The path includes a transistor and a capacitor, and the memory circuit is connected to the capacitor through the transistor. Input data to a child and a selection circuit, and the selection circuit selects one or more of the operation results of a plurality of arithmetic circuits according to the data. In the channel formation region of the transistor, an oxide semiconductor is used in the semiconductor device. One or more of the operation results of a plurality of arithmetic circuits are selected according to the data, and an oxide semiconductor is used in the channel formation region of the transistor in the semiconductor device. is a semiconductor device.

[0017] Another aspect of the present invention has a plurality of logic circuit portions and a connection portion. The connection portion has a memory circuit and a first transistor. One of the source or drain of the first transistor is electrically connected to one of the plurality of logic circuit portions, and the other of the source or drain of the first transistor is electrically connected to another one of the plurality of logic circuit portions. The memory circuit has a second transistor and a capacitor element. The memory circuit inputs data to the capacitor element and the gate of the first transistor via the second transistor. The first transistor controls the electrical connection between one and another of the plurality of logic circuit portions according to the data. In the channel formation region of the second transistor, an oxide semiconductor is used in the semiconductor device is. is.

[0018] Another aspect of the present invention has a plurality of logic circuit portions, a first memory circuit, and a connection portion. The plurality of logic circuit portions have a plurality of arithmetic circuits and a selection circuit. The first memory circuit has a first transistor and a first capacitor element. The first memory circuit inputs first data to the first capacitor element and the selection circuit via the first transistor. The selection circuit selects one or more of the operation results of the plurality of arithmetic circuits according to the first data. The connection portion has a second memory circuit and a second transistor. One of the source or drain of the second transistor is electrically connected to one of the plurality of logic circuit portions. The source of the second transistor or the other of the drains is electrically connected to one of the plurality of logic circuit portions. The source of the second transistor The other of the source or drain is electrically connected to another one of the plurality of logic circuit units, and the memory circuit of No. 2 has a third transistor and a second capacitor element, and the second memory circuit inputs data to the second capacitor element and the gate of the second transistor via the third transistor, and the second transistor controls the electrical connection between one of the plurality of logic circuit units and another one according to the data, and the first transistor and the third transistor are in a semiconductor device in which an oxide semiconductor is used in a channel formation region.

Advantages of the Invention

[0019] According to one aspect of the present invention, there is provided a semiconductor device capable of retaining information on the connection relationship between logic circuit units, or information on the circuit configuration within each logic circuit unit for a long time even when the supply of the power voltage is stopped. It is possible.

[0020] In addition, according to one aspect of the present invention, there is provided a semiconductor device capable of changing the connection relationship between logic circuit units or changing the circuit configuration of each logic circuit unit at high speed or with low power consumption. It is possible. It can be done.

Brief Description of the Drawings

[0021]

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Best Mode for Carrying Out the Invention

[0022] Hereinafter, embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details thereof can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not interpreted as being limited to the description of the embodiments shown below.

[0023] Note that the functions of the "source" and "drain" may be interchanged when transistors with different polarities are employed or when the direction of the current changes in the circuit operation. Therefore, in this specification, the terms "source" and "drain" are assumed to be interchangeable.

[0024] "Electrically connected" includes cases where connection is made through "something having some electrical action". Here, "something having some electrical action" is not particularly limited as long as it enables the exchange of electrical signals between the connection targets. For example, "something having some electrical action" includes electrodes, wiring, switching elements such as transistors, resistance elements, inductors, capacitors, and other elements having various functions.

[0025] Even when components that are independent on the circuit diagram are shown to be electrically connected, actually, for example, when a part of the wiring also functions as an electrode, or when a single conductive film has the functions of a plurality of components. In this specification, electrically connected includes such cases where a single conductive film has the functions of a plurality of components. ​​​Include it in that scope.

[0026] The terms "upper" and "lower" do not necessarily define that the positional relationship of the components is "directly above" or "directly below". For example, in the expression "gate electrode on the gate insulating layer", components other than the gate insulating layer and the gate electrode are not excluded if they are included between the gate insulating layer and the gate electrode.

[0027] Regarding the position, size, range, etc. of each component shown in the drawings, etc., for the sake of easy understanding, they may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings, etc.

[0028] Ordinal numbers such as "first", "second", "third", etc. are attached to avoid confusion of components and so on.

[0029] (Embodiment 1) In this embodiment, an example of a semiconductor device will be described.

[0030] Fig. 1(A) shows an example of a block diagram of a semiconductor device.

[0031] The semiconductor device in Fig. 1(A) has a logic circuit section 101 and a memory circuit 103. The logic circuit section 101 has a plurality of logic circuits 105. And in the semiconductor device, according to the data (also referred to as a signal) stored in the memory circuit 1 03, one or a plurality of the plurality of logic circuits 105 are selected, and the circuit configuration within the logic circuit section 101 is determined.

[0032] As an example of the logic circuit section 101, an ALU or the like can be mentioned. As the plurality of logic circuits 105 are concerned, an adder, a subtractor, a multiplier, an AND circuit, an OR circuit, a NOT circuit, an XOR circuit, or Examples include arithmetic circuits such as shift circuits and selection circuits such as multiplexers. Also, the logic circuit 105 may be composed of one element such as one transistor. The logic circuit 10 5 can also be said to be a circuit having one or more elements (such as transistors) having a function as a switch.

[0033] Then, the logic circuit section 101 can appropriately change the circuit configuration according to the data stored in the memory circuit 103, for example, be used as an adder or an AND circuit.

[0034] Furthermore, by holding data in the memory circuit 103, the circuit configuration of the logic circuit section 101 can be maintained. Note that the memory circuit 103 may be provided inside the logic circuit section 101. Hereinafter, the specific circuit configuration and driving method of the semiconductor device will be described.

[0035] (Circuit configuration of memory circuit 103 and logic circuit 105) FIG. 1(B) shows an example of a specific circuit configuration of the memory circuit 103 and the logic circuit 105.

[0036] The memory circuit 103 includes a transistor 107 and a capacitive element 109. Note that a plurality of memory circuits 103 may be provided, and the number thereof may be determined according to the configuration of the logic circuit section 101. When a plurality are provided, the set may be simply called a memory circuit or a memory circuit section. Also, it may have elements such as resistors and diodes.

[0037] An oxide semiconductor is used for the transistor 107. In particular, an oxide semiconductor is used for the channel formation region of the transistor 107. In FIG. 1(B), the transistor ​​​​​​​​ To indicate that an oxide semiconductor is used for the transistor 107, a symbol "OS" is attached.

[0038] The gate of the transistor 107 is electrically connected to the terminal W, one of the source or drain of the transistor 107 is electrically connected to the terminal D, and the other of the source or drain of the transistor 107 is electrically connected to one of the pair of electrodes of the terminal F and the capacitor element 109. The other of the pair of electrodes of the capacitor element 109 is electrically connected to the terminal C. Here, each terminal can be configured to be electrically connected to a wiring or an electrode. Note that a constant potential, for example, a low power supply potential, can be input to the terminal C.

[0039] On the other hand, the logic circuit 105 includes a transistor 111. Here, for simplicity, a case where there is one transistor will be described, but other configurations may be used.

[0040] The gate of the transistor 111 is electrically connected to the terminal F of the memory circuit 103. That is, the gate is electrically connected to the other of the source or drain of the transistor 107 and one of the pair of electrodes of the capacitor element 109. One of the source or drain of the transistor 111 is electrically connected to the terminal I, and the other of the source or drain of the transistor 111 is electrically connected to the terminal O.

[0041] For the transistor 111, various semiconductors such as a semiconductor containing a Group 14 semiconductor (such as silicon) in the periodic table of elements, an organic semiconductor, a compound semiconductor, or an oxide semiconductor can be used. Also, an amorphous semiconductor, a microcrystalline semiconductor, a polycrystalline semiconductor, or a single crystal semiconductor, etc. can be used. In particular, these semiconductors are used in the channel formation region of the transistor 111. are used.

[0042] Note that examples of transistors using single-crystalline semiconductors include bulk transistors using single-crystalline semiconductor substrates, thin-film transistors using SOI substrates, and the like. Examples of the base substrates of SOI substrates include glass substrates and semiconductor substrates. Examples of transistors using amorphous semiconductors, microcrystalline semiconductors, or polycrystalline semiconductors include thin-film transistors provided on substrates such as glass substrates or semiconductor substrates. transistors, thin-film transistors using SOI substrates, and the like. Examples of the base substrates of SOI substrates include glass substrates and semiconductor substrates. Examples of transistors using amorphous semiconductors, microcrystalline semiconductors, or polycrystalline semiconductors include thin-film transistors provided on substrates such as glass substrates or semiconductor substrates. substrates include glass substrates and semiconductor substrates. Examples of transistors using amorphous semiconductors, microcrystalline semiconductors, or polycrystalline semiconductors include thin-film transistors provided on substrates such as glass substrates or semiconductor substrates. substrates such as glass substrates or semiconductor substrates. Examples of thin-film transistors provided thereon include thin-film transistors.

[0043] (Drive methods for the memory circuit 103 and the logic circuit 105) The drive methods for the memory circuit 103 and the logic circuit 105 shown in FIG. 1(B) will be described.

[0044] Storing data (also referred to as storing) in the memory circuit 103 is performed by the following method. First, the transistor 107 is selected to be in an on state by a control signal Write (control signal input to terminal W) input to the gate. Then, the signal potential corresponding to the data Data (signal potential input to terminal D) is input to one of the pair of electrodes of the capacitive element 109 through the on-state transistor 107. That is, the memory circuit 103 has a function of inputting the data Data to the capacitive element 109 through the transistor 107. transistor 107 is selected to be in an on state by a control signal Write (control signal input to terminal W) input to the gate. Then, the signal potential corresponding to the data Data (signal potential input to terminal D) is input to one of the pair of electrodes of the capacitive element 109 through the on-state transistor 107. That is, the memory circuit 103 has a function of inputting the data Data to the capacitive element 109 through the transistor 107. through the on-state transistor 107. is input to one of the pair of electrodes of the capacitive element 109. That is, the memory circuit 103 has a function of inputting the data Data to the capacitive element 109 through the transistor 107. That is, the memory circuit 103 has a function of inputting the data Data to the capacitive element 109 through the transistor 107. 107.

[0045] Thereafter, the transistor 107 is selected to be in an off state by a control signal Write (control signal input to terminal W) input to the gate, so that the signal potential is held at one of the pair of electrodes of the capacitive element 109. At that time, the signal potential is also held at the terminal F. input to terminal W) input to the gate, so that the signal potential is held at one of the pair of electrodes of the capacitive element 109. At that time, the signal potential is also held at the terminal F. At that time, the signal potential is also held at the terminal F. Thus, the data Data can be stored in the memory circuit 103.

[0046] Here, an oxide semiconductor is used for the transistor 107. For example, compared with a silicon-based transistor, the off-current (also referred to as leakage current) is extremely small. Therefore, when the transistor 107 is in the off state, the memory circuit 103 can hold the signal potential at one of the pair of electrodes of the capacitive element 109 and at the terminal F for a long period of time. Therefore, the memory circuit 103 can hold the data Data for a long time even after, for example, the supply of the power supply voltage to the semiconductor device is stopped.

[0047] In addition, the memory circuit 103 having the transistor 107 using an oxide semiconductor has a lower drive voltage than, for example, a flash memory using a silicon-based transistor. Therefore, it is possible to operate at a higher speed and reduce power consumption compared with such a flash memory.

[0048] On the other hand, in the logic circuit 105 of FIG. 1(B), the signal potential is input to the gate of the transistor 111, and the on / off of the transistor 111 is controlled. That is, the conduction between the terminal I and the terminal O is controlled. Since the memory circuit 103 can hold the data Data for a long time, the circuit configuration of the logic circuit 105 can be maintained even after the supply of the power supply voltage to the semiconductor device is stopped. Maintaining the circuit configuration of the logic circuit 105 in FIG. 1(B) means maintaining the on state or off state (conduction or non-conduction between the terminal I and the terminal O) of the transistor 111.

[0049] Here, since it is desirable for the transistor 111 to operate at high speed, a junction with high mobility It is preferable to use a crystalline semiconductor. In particular, it is preferable to use a single-crystalline semiconductor, and it is also preferable to use a semiconductor containing silicon whose crystallinity is easily improved. That is, it is preferable to use single-crystalline silicon for the transistor 111.

[0050] Also, by laminating the transistor 107 and the transistor 111, the circuit area can be reduced. For example, the transistor 107 may be provided on the transistor 111 as shown in FIG. 7(C). In that case, a structure in which the transistor 107 using an oxide semiconductor is provided on the transistor 111 using single-crystalline silicon is preferable. FIG. 7(D) shows a specific example of the cross-sectional structure when they are laminated.

[0051] The cross-sectional structure of FIG. 7(D) corresponds to the circuit configuration of FIG. 1(B), and shows a structure in which the transistor 107 using an oxide semiconductor and the capacitor element 109 are provided on the transistor 111 using single-crystalline silicon.

[0052] The transistor 111 has a single-crystalline silicon layer 131, a gate insulating layer 133, and a gate electrode 135. The transistor 107 has an oxide semiconductor layer 137, a gate insulating layer 139, and a gate electrode 141. The capacitor element 109 has one of a pair of electrodes, i.e., an electrode 143 and the other electrode 145, and an insulating layer 147 serving as a dielectric layer. The gate electrode 135 of the transistor 111 is electrically connected to one electrode 143 of the capacitor element 109 and one electrode 149 of the source electrode or drain electrode of the transistor 107.

[0053] In the example of FIG. 7(D), one electrode 143 of the capacitive element 109 is an extension of one electrode 149 of the source electrode or the drain electrode of the transistor 107. Also, the insulating layer 147 serving as the dielectric layer of the capacitive element 109 is an extension of the gate insulating layer 139 of the transistor 107. Further, the other electrode 145 of the capacitive element 109 is provided on the same layer as the layer on which the gate electrode 141 of the transistor 107 is provided. By using a part or all of such a structure, films, electrodes, etc. of each element can be formed in the same process using the same material, and costs and the number of processes can be reduced. A semiconductor device having a structure as shown in FIG. 7(D) can achieve all of high-speed operation, data retention, reduction of circuit area, and reduction of costs and the number of processes. Note that the cross-sectional structure of the semiconductor device is not limited to FIGS. 7(C) and (D), and a transistor 111 may be provided on the transistor 107. Also, in FIG. 7(D), a part of the transistor 107 overlaps with the transistor 111, but all of the transistor 107 may overlap with the transistor 111. Further, the transistor 111 and the transistor 107 do not have to be stacked, and a structure in which the transistor 107 and the capacitive element 109 are stacked, a structure in which the transistor 111 and the capacitive element 109 are stacked, etc. may be used. As described above, the logic circuit 105 can be controlled according to the data Data stored in the memory circuit 103. Note that in FIG. 1(B), a case where there is one transistor as the logic circuit 105 is shown, but the logic circuit 105 may include a plurality of transistors.

[0054] As described above, the logic circuit 105 can be controlled according to the data Data stored in the memory circuit 103. A semiconductor device having a structure as shown in FIG. 7(D) can achieve all of high-speed operation, data retention, reduction of circuit area, and reduction of costs and the number of processes. Note that the cross-sectional structure of the semiconductor device is not limited to FIGS. 7(C) and (D), and a transistor 111 may be provided on the transistor 107. Also, in FIG. 7(D), a part of the transistor 107 overlaps with the transistor 111, but all of the transistor 107 may overlap with the transistor 111. Further, the transistor 111 and the transistor 107 do not have to be stacked, and a structure in which the transistor 107 and the capacitive element 109 are stacked, a structure in which the transistor 111 and the capacitive element 109 are stacked, etc. may be used. Note that in FIG. 1(B), a case where there is one transistor as the logic circuit 105 is shown, but the logic circuit 105 may include a plurality of transistors. As described above, the logic circuit 105 can be controlled according to the data Data stored in the memory circuit 103. A semiconductor device having a structure as shown in FIG. 7(D) can achieve all of high-speed operation, data retention, reduction of circuit area, and reduction of costs and the number of processes. Note that the cross-sectional structure of the semiconductor device is not limited to FIGS. 7(C) and (D), and a transistor 111 may be provided on the transistor 107. Also, in FIG. 7(D), a part of the transistor 107 overlaps with the transistor 111, but all of the transistor 107 may overlap with the transistor 111. Further, the transistor 111 and the transistor 107 do not have to be stacked, and a structure in which the transistor 107 and the capacitive element 109 are stacked, a structure in which the transistor 111 and the capacitive element 109 are stacked, etc. may be used.

[0055] As described above, the logic circuit 105 can be controlled according to the data Data stored in the memory circuit 103.

[0056] Note that in FIG. 1(B), a case where there is one transistor as the logic circuit 105 is shown, ​​​Other circuit configurations are also possible. For example, as shown in Fig. 1(C), the logic circuit 105 may have a CMOS circuit such as an inverter. The operation of Fig. 1(C) is also the same as that of Fig. 1(B). Depending on the data Data stored in the memory circuit 103, the on / off states of the transistor 121 and the transistor 123 are controlled. That is, the conduction between the terminal I1 and the terminal O, or the conduction between the terminal I2 and the terminal O is selected. Note that a high power supply potential may be input to the terminal I1, and a low power supply potential may be input to the terminal I2.

[0057] (Circuit configurations and driving methods of the memory circuit 103 and the logic circuit unit 101) Fig. 2(A) shows an example of the circuit configurations of the memory circuit 103 and the logic circuit unit 101.

[0058] The logic circuit unit 101 includes an adder 201, an AND circuit 203, and a selection circuit 205, corresponding to the logic circuit 105 in Fig. 1(A). That is, the logic circuit unit 101 includes arithmetic circuits such as an adder 201 and an AND circuit 203, and a selection circuit 205. Other logic circuits described above may be used. Also, it may have elements such as resistors and diodes.

[0059] As the adder 201 and the AND circuit 203, known circuits may be used. The adder 201 and the AND circuit 203 perform operations based on the inputs from the terminals A and B, and have a function of inputting the operation results to the selection circuit 205.

[0060] An example of the selection circuit 205 is a multiplexer or the like. The selection circuit 205 is electrically connected to the terminal F of the memory circuit 103, and uses the data D of the memory circuit 103 as the selection signal S. ​​​​​​​​​​Data is input. Then, the selection circuit 205 selects one of the inputs from the adder 201 or the AND circuit 203 according to the data Data and outputs it to the terminal O. That is, the selection circuit 205 has a function of selecting one of the operation results of arithmetic circuits such as the adder 201 and the AND circuit 203 according to the data Data. Depending on the configuration of the logic circuit unit 101, it is also possible to select a plurality of arithmetic circuits.

[0061] Fig. 2(B) shows a specific circuit configuration of the memory circuit 103 and the selection circuit 205.

[0062] The selection circuit 205 is an example of a multiplexer having two inputs (input from the AND circuit and input from the adder), and includes a transistor 207, a transistor 209, and an inverter 211. Here, the transistor 207 and the transistor 209 have the same polarity. Note that the circuit configuration of the selection circuit 205 only needs to be able to control the electrical connection between the arithmetic circuit and the terminal O, and is not limited to Fig. 2(B).

[0063] The gate of the transistor 207 is electrically connected to the terminal F via the inverter 211, one of the source or drain of the transistor 207 is electrically connected to the AND circuit 203, the gate of the transistor 209 is electrically connected to the terminal F, one of the source or drain of the transistor 209 is electrically connected to the adder 201, and the other of the source or drain of the transistor 207 and the other of the source or drain of the transistor 209 are electrically connected to the terminal O. Note that the inputs of the multiplexer can be arbitrarily set according to It may be appropriately changed to any desired number m (where m is a positive integer). Also, the number of selection signals S may be determined according to the number of inputs. Further, the number of memory circuits 103 may be determined according to the number of selection signals S. For example, when having four inputs (m = 4: I0, I1, I2, I3), since there are four outputs from terminal O, two selection signals S0, S1 (the four cases of "S0S1" being "00", "01", "10", "11") may be used, and two memory circuits 103 corresponding to each of the two selection signals S0, S1 may be provided (see FIGS. 27(A) and (B)). The circuit in FIG. 2(B) may be driven in the same manner as the circuits in FIGS. 1(B) and (C). First, the memory circuit 103 inputs the data Data that becomes the selection signal S to the selection circuit 205 via the transistor 107. Next, the selection circuit 205 controls the on / off of the transistor 209 according to the data Data, and controls the on / off of the transistor 207 according to the inverted data of the data Data. Then, when the transistor 207 is in the on state and the transistor 209 is in the off state, the input from the AND circuit 203 is selected and output to the terminal O. Also, when the transistor 209 is in the on state and the transistor 207 is in the off state, the input from the adder 201 is selected and output to the terminal O. In this way, according to the data Data of the memory circuit 103, the selection circuit 205 is controlled, and one of the operation results of the adder 201 or the AND circuit 203 is selected. Note that in FIG. 2, for simplicity, only the adder 201, the AND circuit 203, and the selection circuit 205 are shown as the logic circuit 105 of the logic circuit section 101, but other configurations may also be used. FIG. 3 shows a more practical configuration.

[0064] The circuit in FIG. 2(B) may be driven in the same manner as the circuits in FIGS. 1(B) and (C). First, the memory circuit 103 inputs the data Data that becomes the selection signal S to the selection circuit 205 via the transistor 107. Next, the selection circuit 205 controls the on / off of the transistor 209 according to the data Data, and controls the on / off of the transistor 207 according to the inverted data of the data Data. Then, when the transistor 207 is in the on state and the transistor 209 is in the off state, the input from the AND circuit 203 is selected and output to the terminal O. The memory circuit 103 inputs the data Data that becomes the selection signal S to the selection circuit 205 via the transistor 107. Next, the selection circuit 205 controls the on / off of the transistor 209 according to the data Data, and controls the on / off of the transistor 207 according to the inverted data of the data Data. Then, when the transistor 207 is in the on state and the transistor 209 is in the off state, the input from the AND circuit 203 is selected and output to the terminal O. Also, when the transistor 209 is in the on state and the transistor 207 is in the off state, the input from the adder 201 is selected and output to the terminal O. Thus, according to the data Data of the memory circuit 103, the selection circuit 205 is controlled, and one of the operation results of the adder 201 or the AND circuit 203 is selected. Note that in FIG. 2, for simplicity, only the adder 201, the AND circuit 203, and the selection circuit 205 are shown as the logic circuit 105 of the logic circuit section 101, but other configurations may also be used. FIG. 3 shows a more practical configuration. The circuit in FIG. 2(B) may be driven in the same manner as the circuits in FIGS. 1(B) and (C). First, the memory circuit 103 inputs the data Data that becomes the selection signal S to the selection circuit 205 via the transistor 107. Next, the selection circuit 205 controls the on / off of the transistor 209 according to the data Data, and controls the on / off of the transistor 207 according to the inverted data of the data Data. Then, when the transistor 207 is in the on state and the transistor 209 is in the off state, the input from the AND circuit 203 is selected and output to the terminal O. Also, when the transistor 209 is in the on state and the transistor 207 is in the off state, the input from the adder 201 is selected and output to the terminal O.

[0065] Thus, according to the data Data of the memory circuit 103, the selection circuit 205 is controlled, and one of the operation results of the adder 201 or the AND circuit 203 is selected. Note that in FIG. 2, for simplicity, only the adder 201, the AND circuit 203, and the selection circuit 205 are shown as the logic circuit 105 of the logic circuit section 101, but other configurations may also be used. FIG. 3 shows a more practical configuration. In FIG. 2, for simplicity, only the adder 201, the AND circuit 203, and the selection circuit 205 are shown as the logic circuit 105 of the logic circuit section 101, but other configurations may also be used. FIG. 3 shows a more practical configuration. In FIG. 2, for simplicity, only the adder 201, the AND circuit 203, and the selection circuit 205 are shown as the logic circuit 105 of the logic circuit section 101, but other configurations may also be used. FIG. 3 shows a more practical configuration. FIG. 3 shows a more practical configuration.

[0066] FIG. 3 is a block diagram when a general ALU is used as the logic circuit unit 101. The logic circuit unit 101 includes an arithmetic operation unit 301 that combines an adder, a subtractor, etc., an logical operation unit 303 that combines an AND circuit, an OR circuit, etc., a shift operation unit 305 having a shift circuit, and a selection circuit 205 such as a multiplexer that selects and outputs them. Further, each of the operation units 301, 303, 305 has a selection circuit 307, 309, 31 1, and the combination of the circuit configurations of the logic circuits within each operation unit can be changed. .

[0067] The selection circuits 307, 309, 311 within each operation unit are controlled in accordance with the data Data of the storage circuit 103 that becomes the selection signal S, similar to the selection circuit 205. In the case of FIG. 3, the storage circuit 103 may be a storage circuit unit provided with a plurality of sets of a transistor 107 and a capacitor element 109 as shown in FIG. 1(B), and the data Data may be output from the terminals F1 to F4. Fur ther, the number of the sets may be determined by the number of inputs of the selection circuits 205, 307, 309, 311. Also, when the same data Data is output from the terminals F1 to F4, the storage circuit 103 as shown in FIG. 1( B) may be shared by the selection circuits 205, 307, 309, 311, and the semiconductor device can be miniaturized. Moreover, since the storage circuit 103 can hold the data Data for a long time, the circuit configuration of the logic circuit unit 101 can be maintained even after the supply of the power supply voltage to the semiconductor device is stopped. Also, as the circuit configuration becomes complex as shown in FIG. 3, the effect of reducing the high-speed operation and power consumption of the storage circuit 103 becomes more remarkable.

[0068] And, since the storage circuit 103 can hold the data Data for a long time, the circuit configuration of the logic circuit unit 101 can be maintained even after the supply of the power supply voltage to the semiconductor device is stopped. Also, as the circuit configuration becomes complex as shown in FIG. 3, the effect of reducing the high-speed operation and power consumption of the storage circuit 103 becomes more remarkable. And, since the storage circuit 103 can hold the data Data for a long time, the circuit configuration of the logic circuit unit 101 can be maintained even after the supply of the power supply voltage to the semiconductor

[0069] Note that by providing a plurality of circuits such as those in FIG. 2 and FIG. 3, the number of bits of the signal input from terminal A and terminal B can be increased. That is, an arbitrary n (n is a positive integer)-bit logic circuit unit 101 can be configured. Note that by providing a plurality of circuits such as those in FIG. 2 and FIG. 3, the number of bits of the signal input from terminal A and terminal B can be increased. That is, an arbitrary n (n is a positive integer)-bit logic circuit unit 101 can be configured. Note that by providing a plurality of circuits such as those in FIG. 2 and FIG. 3, the number of bits of the signal input from terminal A and terminal B can be increased. That is, an arbitrary n (n is a positive integer)-bit logic circuit unit 101 can be configured.

[0070] This embodiment can be implemented in appropriate combination with other embodiments.

[0071] (Embodiment 2) In this embodiment, an example of a semiconductor device different from that in Embodiment 1 will be described.

[0072] FIGS. 4(A) and (B) show a modified example of FIG. 1(B).

[0073] First, the example of FIG. 4(A) will be described. The memory circuit 103 is the same as that in FIG. 1(B) and the like. Same as that in FIG. 1(B) and the like.

[0074] The logic circuit 105 in FIG. 4(A) includes a transistor 111, a transistor 401, and an inverter 403. The transistor 111 and the transistor 401 are electrically connected in parallel between a terminal I and a terminal O. That is, one of the source or drain of the transistor 111 and one of the source or drain of the transistor 401 are electrically connected to the terminal I, and the other of the source or drain of the transistor 111 and the other of the source or drain of the transistor 401 are electrically connected to the terminal O. The transistor 111 and the transistor 401 are electrically connected in parallel between a terminal I and a terminal O. That is, one of the source or drain of the transistor 111 and one of the source or drain of the transistor 401 are electrically connected to the terminal I, and the other of the source or drain of the transistor 111 and the other of the source or drain of the transistor 401 are electrically connected to the terminal O. The transistor 111 and the transistor 401 are electrically connected in parallel between a terminal I and a terminal O. That is, one of the source or drain of the transistor 111 and one of the source or drain of the transistor 401 are electrically connected to the terminal I, and the other of the source or drain of the transistor 111 and the other of the source or drain of the transistor 401 are electrically connected to the terminal O. The transistor 111 and the transistor 401 are electrically connected in parallel between a terminal I and a terminal O. That is, one of the source or drain of the transistor 111 and one of the source or drain of the transistor 401 are electrically connected to the terminal I, and the other of the source or drain of the transistor 111 and the other of the source or drain of the transistor 401 are electrically connected to the terminal O. The transistor 111 and the transistor 401 are electrically connected in parallel between a terminal I and a terminal O. That is, one of the source or drain of the transistor 111 and one of the source or drain of the transistor 401 are electrically connected to the terminal I, and the other of the source or drain of the transistor 111 and the other of the source or drain of the transistor 401 are electrically connected to the terminal O. The transistor 111 and the transistor 401 are electrically connected in parallel between a terminal I and a terminal O. That is, one of the source or drain of the transistor 111 and one of the source or drain of the transistor 401 are electrically connected to the terminal I, and the other of the source or drain of the transistor 111 and the other of the source or drain of the transistor 401 are electrically connected to the terminal O.

[0075] One of the transistor 111 and the transistor 401 is of N-channel type and the other is of P-channel type, and those with different polarities are used. The data Data of the memory circuit 103 is input to the gate of the transistor 111, and the complement of the data is input to the gate of the transistor 401. One of the transistor 111 and the transistor 401 is of N-channel type and the other is of P-channel type, and those with different polarities are used. The data Data of the memory circuit 103 is input to the gate of the transistor 111, and the complement of the data is input to the gate of the transistor 401. One of the transistor 111 and the transistor 401 is of N-channel type and the other is of P-channel type, and those with different polarities are used. The data Data of the memory circuit 103 is input to the gate of the transistor 111, and the complement of the data is input to the gate of the transistor 401. The inverted data of Data is input. Transistors 11 with different polarities as shown in Fig. 4(A) By using 1 and 401, voltage fluctuations corresponding to the threshold voltages of transistors 111 and 401 can be suppressed to be able to.

[0076] Next, the example in Fig. 4(B) will be described.

[0077] The memory circuit 103 in Fig. 4(B) includes a transistor 107, a capacitive element 109, a trans istor 405, a capacitive element 407, and an inverter 409. The transistor 107 and the capacitive element 109 are the same as those in Fig. 1(B) and the like. And, the gate of the transistor 40 5 is electrically connected to the terminal W, and one of the source or drain of the transistor 405 is electrically connected to the terminal D via the inverter 409, and the other of the source or drain of the transistor 405 is electrically connected to one of the pair of electrodes of the capacitive element 407 and the terminal F2 to be connected.

[0078] The logic circuit 105 in Fig. 4(B), similar to Fig. 4(A), has transistors 11 with different polarities 1 and transistor 401 electrically connected in parallel between the terminal I and the terminal O. And Data of the memory circuit 103 is input to the gate of the transistor 111, and the inverted data of the said data Data is input to the gate of the transistor 401. By using transistors 111 and 401 with different polarities in the same way as in Fig. 4(A ) voltage fluctuations corresponding to the threshold voltages of transistors 11 1 and 401 can be suppressed. to be able to.

[0079] This embodiment can be implemented in appropriate combination with other embodiments.

[0080] (Embodiment 3) In this embodiment mode, an example of a semiconductor device different from that in the above embodiment mode will be described.

[0081] The semiconductor device in FIG. 5A includes a plurality of logic circuit portions 101 and a connection portion 501 . The logic circuit unit 101 is the same as that shown in FIG. 1 to FIG. 3, and can use an ALU, etc. .

[0082] The connection portion 501 controls the conduction of wiring 503 that electrically connects a plurality of logic circuit portions 101 together. The details are shown in Figure 5(B).

[0083] The circuit configuration and driving method of the connection portion 501 in FIG. 5B are the same as those in FIG. 1B. The on / off state of the transistor 111 is controlled in response to data from the circuit 103 . That is, the conduction between the terminal I and the terminal O is controlled. The terminal I and the terminal O are different The logic circuit unit 101 is electrically connected to the logic circuit unit 101, and the logic circuit unit 101 is connected to the logic circuit unit 102 by controlling the electrical continuity between the terminals I and O. The logic circuit 105 controls electrical connections between the logic circuit units 101. The present invention is not limited to a circuit having one 111, but includes any element (transistor) that functions as a switch. The circuit may have one or more input / output terminals (e.g., a resistor, a power supply, etc.).

[0084] In this way, the transistor 111 of the connection unit 501 performs multiple The function of controlling the electrical connection between one of the logic circuit units 101 and the other one of the logic circuit units 101 is In addition, the terminal I and the terminal O are respectively connected to the terminal A and the terminal O of one logic circuit unit 101 (FIG. 3). In other words, one logic circuit unit 101 may be electrically connected to the other logic circuit unit 102. The output of the memory circuit 103 may be fed back to the input.

[0043]

[0085] FIG. 5(C) is a diagram showing an example of the electrical connection between a plurality of logic circuit units 101. FIG. 5 (C) The semiconductor device includes a memory 505 and a selection circuit 507. In the memory 505 information a to information n such as a control signal Write and data Data are stored. The selection circuit 507 is a multiplexer or the like, and selects the information and outputs it to the storage circuit 1 03 of the connection part 501.

[0086] In FIG. 5(C), information a is selected, and the wiring 503 between the logic circuit units 101 is shown as being connected as indicated by the arrow. Also, when information b to information n are selected, the connection relationship may be changed. Note that FIG. 5(C) shows only the connected wiring 503 . . .

[0087] And, since the semiconductor device of FIG. 5(C) can hold the data Data for a long time in the storage circuit 103 included in the connection part 501, the connection relationship between the plurality of logic circuit units 101 can be maintained even after the supply of the power supply voltage to the semiconductor device is stopped. Also, the transistor 107 using the oxide semiconductor included in the connection part 501 has a low drive voltage. Therefore, when changing the connection relationship, for example, compared with a flash memory or the like, high-speed operation and low power consumption are possible . . . . .

[0088] Note that a storage circuit 103 may be used for the memory 505. In that case, the memory 505 can also operate at high speed and with low power consumption. Also, as the circuit configuration of the connection part 501, FIGS. 4 (A) and (B) may be used.

[0089] This embodiment can be implemented in appropriate combination with other embodiments.

[0090] (Embodiment 4) This embodiment describes an example of a semiconductor device that combines Embodiment 1 and Embodiment 3.

[0091] The semiconductor device in Fig. 6(A) includes a plurality of logic circuit sections 101 (the parts marked with “+” or “AND”), a connection section 501, a memory circuit 103, a memory 505, and a selection circuit 507. The memory 505 and the selection circuit 507 may be provided outside the semiconductor device.

[0092] As described in Embodiment 1 and the like, the memory circuit 103 has a function of maintaining the circuit configuration of the plurality of logic circuit sections 101.

[0093] As described in Embodiment 3 and the like, the connection section 501 has a function of maintaining the connection relationship between the plurality of logic circuit sections 101.

[0094] Each of the information a to information n stored in the memory 505 has information on both the circuit configuration and the connection relationship. By having the memory circuit 103 and the connection section 501 maintain this information, the semiconductor device can maintain both the circuit configuration and the connection relationship even after the supply of the power voltage is stopped. Also, the transistors using the oxide semiconductor included in the memory circuit 103 have a low drive voltage. Therefore, changes in the circuit configuration and the connection relationship can be performed at high speed and with low power consumption.

[0095] This embodiment can be implemented in appropriate combination with other embodiments.

[0096] (Embodiment 5) This embodiment shows an example of a configuration for reducing the power consumption of a semiconductor device. ​

[0097] Fig. 6(B) shows a configuration for stopping the supply of the power supply voltage to a circuit not used in the semiconductor device. Note that the configurations of the logic circuit unit 101 (logic circuit units 101a and 101b), the connection unit 501, the memory circuit 103, etc. are the same as those in other embodiments.

[0098] Among the logic circuit unit 101a and the memory circuit 103 to be used, the part that supplies data Da ta to the logic circuit unit 101a, and the memory circuit that controls the connection relationship of the logic circuit unit 101a among the connection unit 501 are supplied with the power supply voltage.

[0099] On the other hand, among the logic circuit unit 101b and the memory circuit 103 that are not used, the part that supplies data Data to the logic circuit unit 101b, and the memory circuit that controls the connection relationship of the logic circuit unit 101b among the connection unit 501 have the supply of the power supply voltage stopped. Also, the supply of the power supply voltage to any of them may be stopped. That is, the supply of the power supply voltage may be stopped only for the logic circuit unit 101b that is not used.

[0100] As an example of stopping the supply of the power supply voltage, in the inverter shown as the logic circuit 105 in Fig. 1(C), the electrical connection between the terminals I1 and I2 and the power supply line is cut off by a switch or the like so that the supply of the high power supply potential and the supply of the low power supply potential can be stopped. Similarly, for the adder 201, the AND circuit 203, and the selection circuit 205 in Fig. 2(A) etc., the supply of the high power supply potential and the supply of the low power supply potential can be stopped by using a switch or the like.

[0101] In this way, by stopping the supply of the power supply voltage to the unused circuit, the power consumption of the semiconductor device can be reduced.

[0102] This embodiment can be implemented in appropriate combination with other embodiments.

[0103] (Embodiment 6) In this embodiment, an example of a field-effect transistor including an oxide semiconductor layer applicable to the transistors of the memory circuit shown in the above embodiment will be described.

[0104] An example of the transistor in this embodiment will be described with reference to FIGS. 7(A) and 7(B).

[0105] The transistor shown in FIG. 7(A) includes a conductive layer 601_a, an insulating layer 602_a, a semiconductor layer 603_a, a conductive layer 605a_a, and a conductive layer 605b_a.

[0106] The semiconductor layer 603_a includes a region 604a_a and a region 604b_a. The regions 604a _a and 604b_a are separated from each other and are regions doped with dopants. Note that the region between the regions 604a_a and 604b_a becomes a channel formation region. The semiconductor layer 603_a is provided on the device formation layer 600_a. Note that the regions 604a _a and 604b_a do not necessarily have to be provided.

[0107] The conductive layer 605a_a and the conductive layer 605b_a are provided on the semiconductor layer 603_a and are electrically connected to the semiconductor layer 603_a. In addition, the side surfaces of the conductive layer 605a_a and the conductive layer 605 b_a are tapered.

[0108] In addition, the conductive layer 605a_a overlaps a part of the region 604a_a, but is not necessarily limited to this. By overlapping the conductive layer 605a_a with a part of the region 604a_a, ​​​The resistance value between the conductive layer 605a_a and the region 604a_a can be reduced. Also , all of the region of the semiconductor layer 603_a that overlaps the conductive layer 605a_a may be in the region 604a_a .

[0109] Also, the conductive layer 605b_a overlaps a part of the region 604b_a, but is not necessarily limited to this . By overlapping the conductive layer 605b_a with a part of the region 604b_a, the resistance between the conductive layer 605b_a and the region 604b_a can be reduced. Also, all of the region of the semiconductor layer 603_a that overlaps the conductive layer 605b_a may be in the region 604b_a .

[0110] The insulating layer 602_a is provided on the semiconductor layer 603_a, the conductive layer 605a_a, and the conductive layer 605b _a.

[0111] The conductive layer 601_a is provided on a part of the insulating layer 602_a and overlaps the semiconductor layer 603_a through the insulating layer 602_a. The region of the semiconductor layer 603_a that overlaps the conductive layer 601_a through the insulating layer 602_a becomes the channel formation region .

[0112] Also, the transistor shown in FIG. 7(B) includes a conductive layer 601_b, an insulating layer 602_b, a semiconductor layer 603_b, a conductive layer 605a_b, a conductive layer 605b_b, an insulating layer 606a , an insulating layer 606b, and an insulating layer 607

[0113] The semiconductor layer 603_b includes a region 604a_b and a region 604b_b. The region 604a _b and the region 604b_b are separated from each other and are regions doped with dopants respectively. The semiconductor layer 603_b is, for example, the conductive layer 605a_b, the conductive layer 605b_b, and the substrate​ It is provided above the sub-formation layer 600_b and is electrically connected to the conductive layer 605a_b and the conductive layer 605b_b. Note that the regions 604a_b and 604b_b do not necessarily have to be provided. It is okay.

[0114] The insulating layer 602_b is provided on a part of the semiconductor layer 603_b.

[0115] The conductive layer 601_b is provided on a part of the insulating layer 602_b and overlaps the semiconductor layer 603_b with the insulating layer 602_b in between. Note that the region of the semiconductor layer 603_b that overlaps with the conductive layer 601_b through the insulating layer 602_b becomes the channel formation region of the transistor. Note that an insulating layer may be provided on the conductive layer 601_b. through the insulating layer 602_b The region of the semiconductor layer 603_b that overlaps with the conductive layer 601_b becomes the channel formation region of the transistor. Note that An insulating layer may be provided on the conductive layer 601_b.

[0116] The insulating layer 606a is provided on the insulating layer 602_b and contacts one of the pair of side surfaces of the conductive layer 601_b. contacts one of the pair of side surfaces of the conductive layer 601_b.

[0117] The insulating layer 606b is provided on the insulating layer 602_b and contacts the other of the pair of side surfaces of the conductive layer 601_b. contacts the other of the pair of side surfaces of the conductive layer 601_b.

[0118] Note that the concentration of the dopant in the regions 604a_b and 604b_b that overlap with the insulating layer 606a and the insulating layer 606b through the insulating layer 602_b may be lower than the concentration of the dopant in the regions 604a_b and 604b_b that do not overlap with the insulating layer 606a and the insulating layer 606b. 04a_b and the part of the dopant in the region 604b_b The concentration of the dopant in the regions 604a_b and 604b_b that do not overlap with the insulating layer 606a and the insulating layer 606b may be lower.

[0119] The conductive layer 605a_b and the conductive layer 605b_b are provided on the semiconductor layer 603_b. .

[0120] The conductive layer 605a_b is electrically connected to the region 604a_b. Also, the conductive layer 605 a_b is in contact with the insulating layer 606a.

[0121] The conductive layer 605b_b is electrically connected to the region 604b_b. Also, the conductive layer 605 b_b is in contact with the insulating layer 606b.

[0122] The insulating layer 607 is provided over the conductive layer 601_b, the conductive layer 605a_b, the conductive layer 605b_b, the insulating layer 606a, and the insulating layer 606b.

[0123] Furthermore, each component shown in FIGS. 7(A) and 7(B) will be described.

[0124] As the device-forming layers 600_a and 600_b, for example, an insulating layer or a substrate having an insulating surface can be used. Also, a layer on which elements are previously formed can be used as the device-forming layers 600_a and 600_b.

[0125] Each of the conductive layers 601_a and 601_b has a function as a gate of a transistor. Note that a layer having a function as a gate of a transistor is also referred to as a gate electrode or a gate wiring.

[0126] As the conductive layers 601_a and 601_b, for example, a metal material such as molybdenum, magnesium, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or a layer of an alloy material having these as main components can be used.

[0127] Each of the insulating layer 602_a and the insulating layer 602_b functions as a gate insulating layer of a transistor and has the function as such.

[0128] As the insulating layer 602_a and the insulating layer 602_b, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer, an aluminum nitride oxide layer, a hafnium oxide layer, or a lanthanum oxide layer can be used. Further, the insulating layer 602_a and the insulating layer 602_b can also be formed by laminating materials applicable to the insulating layer 602_a and the insulating layer 602_b. .

[0129] In addition, as the insulating layer 602_a and the insulating layer 602_b, for example, an insulating layer made of a material containing a Group 13 element and an oxygen element in the periodic table can also be used. For example, when the semiconductor layer 6 03_a and the semiconductor layer 603_b contain a Group 13 element, by using an insulating layer containing a Group 13 element as the insulating layer in contact with the semiconductor layer 603_a and the semiconductor layer 603_b, the state of the interface between the insulating layer and the oxide semiconductor layer can be improved.

[0130] Examples of the material containing a Group 13 element and an oxygen element include gallium oxide, aluminum oxide, aluminum gallium oxide, gallium aluminum oxide, etc. Note that aluminum gallium oxide refers to a substance in which the content of aluminum (atomic%) is more than the content of gallium (atomic%), and gallium aluminum oxide refers to a substance in which the content of gallium (atomic%) is equal to or more than the content of aluminum (atomic%). For example, Al2O (x = 3 + α, α is a value greater than 0 and less than 1), Ga2O x (x = 3 + α, α is a value greater than 0 and less than 1), Ga2Ox (x = 3 + α, where α is a value greater than 0 and less than 1), or Ga x Al 2-x O 3+α (x is a value greater than 0 and less than 2, and α is a value greater than 0 and less than 1) can also be used.

[0131] Also, the insulating layers 602_a and 602_b can be formed by laminating layers of materials applicable thereto. For example, the insulating layers 602_a and 602_b can be formed by laminating a plurality of layers containing gallium oxide represented as Ga2O x . Also, the insulating layers 602_a and 602_b can be formed by laminating an insulating layer containing gallium oxide represented as Ga2O x and an insulating layer containing aluminum oxide represented as Al2 O x .

[0132] Each of the semiconductor layers 603_a and 603_b functions as a layer in which a channel of a transistor is formed. As oxide semiconductors applicable to the semiconductor layers 603_a and 603_b, for example, In-based oxides (such as indium oxide), Sn -based oxides (such as tin oxide), or Zn-based oxides (such as zinc oxide) can be used .

[0133] Also, as the above metal oxides, for example, metal oxides such as quaternary metal oxides, ternary metal oxides, and binary -based metal oxides can be used. Note that the metal oxides applicable as the above oxide semiconductors include gallium as a stabilizer for reducing variations in characteristics . It may contain one or more of tin, hafnium, and aluminum. Also, the above The metal oxide applicable as the oxide semiconductor may contain, as the above stabilizer, one or more of lanthanoid such as lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium. Also, the above oxide semiconductor The applicable metal oxide may contain silicon oxide.

[0134] For example, as the quaternary metal oxide, for example, In-Sn-Ga-Zn oxide, In- Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide, etc. can be used.

[0135] Also, as the ternary metal oxide, for example, In-Ga-Zn oxide (also referred to as IGZO), In-Sn-Zn oxide, In-Al-Zn oxide, Sn-Ga-Zn oxide oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide oxide, In-La-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, I n-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In -Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In- Yb-Zn oxide, or In-Lu-Zn oxide, etc. can be used.

[0136] In addition, as the binary metal oxide, for example, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Sn oxide, or In-Ga oxide, etc. can be used.

[0137] Note that, for example, In-Ga-Zn oxide means an oxide containing In, Ga, and Zn, and the ratio of In, Ga, and Zn is not limited. Also, other metal elements may be contained.

[0138] In addition, as the oxide semiconductor, InLO3(ZnO) m (where m is a number greater than 0) can also be used. InLO3(ZnO) The L in represents one or more metal elements selected from Ga, Al, Mn, m and Co.

[0139] For example, as the oxide semiconductor, In:Ga:Zn = 1:1:1 (= 1 / 3:1 / 3: 1 / 3) or In:Ga:Zn = 2:2:1 (= 2 / 5:2 / 5:1 / 5) atomic ratio of In-Ga-Zn oxide and oxides in the vicinity of its composition can be used. Also, as the oxide semiconductor, In:Sn:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3), In: Sn:Zn = 2:1:3 (= 1 / 3:1 / 6:1 / 2) or In:Sn:Zn = 2:1: 5 (= 1 / 4:1 / 8:5 / 8) atomic ratio of In-Sn-Zn oxide and oxides in the vicinity of its composition can be used.

[0140] However, it is not limited to these, and those with an appropriate composition may be used according to the required semiconductor characteristics (mobility, threshold voltage, variation, etc.). Also, in order to obtain the required semiconductor characteristics, ​​​It is preferable to make the carrier concentration, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic bond distance, density, etc. appropriate. It is preferable that they are appropriate.

[0141] The oxide semiconductor may be single crystal or non-single crystal. In the latter case, it may be amorphous or polycrystalline. Also, it may have a structure including a crystalline part in the amorphous, or may be non-amorphous. Further, as the semiconductor layers 603_a and 603_b, an oxide semiconductor (also referred to as CAAC-OS: C Axis Aligned Crystalline Oxide Semiconductor) having an atomic arrangement that is triangular or hexagonal when viewed from the direction of the ab plane, surface or interface, is oriented along the c axis, and in which metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers along the c axis, and including a crystal in which the direction of the a axis or the b axis is different (rotated about the c axis) in the ab plane can be used.

[0142] In general, CAAC refers to a non-single crystal that has an atomic arrangement of a triangle, hexagon, equilateral triangle or regular hexagon when viewed from a direction perpendicular to its ab plane, and includes a phase in which metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers when viewed from a direction perpendicular to the c-axis direction.

[0143]

[0144] CAAC is not a single crystal nor a material formed only from amorphous. Also, CAAC includes a crystallized part (crystalline part), but sometimes the boundary between one crystalline part and another crystalline part cannot be clearly distinguished.

[0145] When oxygen is included in CAAC, a part of the oxygen may be substituted with nitrogen. Also, CAA The c-axes of the individual crystal parts constituting C may be aligned in a certain direction (for example, a direction perpendicular to the substrate surface on which CAAC is formed, the surface of CAAC, etc.). Or, the normal vectors of the ab-planes of the individual crystal parts constituting CAAC may face a certain direction (for example, a direction perpendicular to the substrate surface on which CAAC is formed, the surface of CAAC, etc.). Or, the normal vectors of the ab-planes of the individual crystal parts constituting CAAC may face a certain direction (for example, a direction perpendicular to the substrate surface on which CAAC is formed, the surface of CAAC, etc.). Or, the normal vectors of the ab-planes of the individual crystal parts constituting CAAC may face a certain direction (for example, a direction perpendicular to the substrate surface on which CAAC is formed, the surface of CAAC, etc.). AAC may be a conductor, a semiconductor, or an insulator depending on its composition and the like. Also, it may be transparent or opaque to visible light depending on its composition and the like.

[0146] AAC may be a conductor, a semiconductor, or an insulator depending on its composition and the like. Also, it may be transparent or opaque to visible light depending on its composition and the like. AAC may be a conductor, a semiconductor, or an insulator depending on its composition and the like. Also, it may be transparent or opaque to visible light depending on its composition and the like. AAC may be a conductor, a semiconductor, or an insulator depending on its composition and the like. Also, it may be transparent or opaque to visible light depending on its composition and the like.

[0147] Examples of such CAAC include, for example, a crystal that is formed in a film shape, and when observed from a direction perpendicular to the film surface or the substrate surface, a triangular or hexagonal atomic arrangement is observed, and when its film cross-section is observed, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is observed. Examples of such CAAC include, for example, a crystal that is formed in a film shape, and when observed from a direction perpendicular to the film surface or the substrate surface, a triangular or hexagonal atomic arrangement is observed, and when its film cross-section is observed, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is observed. Examples of such CAAC include, for example, a crystal that is formed in a film shape, and when observed from a direction perpendicular to the film surface or the substrate surface, a triangular or hexagonal atomic arrangement is observed, and when its film cross-section is observed, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is observed. Examples of such CAAC include, for example, a crystal that is formed in a film shape, and when observed from a direction perpendicular to the film surface or the substrate surface, a triangular or hexagonal atomic arrangement is observed, and when its film cross-section is observed, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is observed.

[0148] 1+σ Ga1 -σ O3(ZnO) M (where 0 < σ < 1, M is a number from 1 to 3), and the composition of the entire semiconductor layer including the crystal region oriented in the c-axis direction is In (where 0 < σ < 1, M is a number from 1 to 3), and the composition of the entire semiconductor layer including the crystal region oriented in the c-axis direction is In P Ga Q O R (ZnO) M (where 0 < P < 2, 0 < Q < 2, M is a number from 1 to 3), such a material can also be used. 0 < P < 2, 0 < Q < 2, M is a number from 1 to 3), such a material can also be used.

[0149] Also, for example, semiconductor layer 603_a and semiconductor layer 603_b are CAAC oxide semiconductors In the case of the layer, when the channel length of the transistor is 30 nm, even if the thicknesses of the semiconductor layer 603_ a and the semiconductor layer 603_b are, for example, about 5 nm, the short-channel effect in the transistor can be suppressed.

[0150] Here, an example of the crystal structure included in CAAC will be further described with reference to FIGS. 8 to 10. Unless otherwise specified, in FIGS. 8 to 10, the upward direction is the c-axis direction, and the plane perpendicular to the c-axis direction is the ab plane. In addition, when simply referring to the upper half and the lower half, it means the upper half and the lower half with the ab plane as the boundary. Further, in FIG. 8, O surrounded by a circle indicates O with 4-fold coordination and O surrounded by a double circle indicates O with 3-fold coordination.

[0151] In FIG. 8(A), a structure having one 6-fold coordinated indium atom (also referred to as 6-fold coordinated In) and six 4-fold coordinated oxygen atoms (also referred to as 4-fold coordinated O) adjacent to the 6-fold coordinated In is shown. A part composed of one metal atom such as In and oxygen atoms adjacent to the metal atom is referred to as a small group. Further, in FIG. 8(A), for the sake of convenience, the octahedral structure is shown as a planar structure In addition, in the upper half and the lower half of FIG. 8(A), there are three 4-fold coordinated O atoms each. Further, the charge of the small group shown in FIG. 8(A) is 0.

[0152] In FIG. 8(B), a structure having one 5-fold coordinated Ga, three 3-fold coordinated oxygen atoms (also referred to as 3-fold coordinated O) adjacent to the 5-fold coordinated Ga, and two 4-fold coordinated O atoms adjacent to the 5-fold coordinated Ga is shown. Each of the three 3-fold coordinated O atoms is present on the ab plane. Further, in FIG. 8( B), there is one 4-fold coordinated O atom each in the upper half and the lower half. Further, indium In addition to 6 - coordinate atoms, there are also 5 - coordinate indium atoms (5 - coordinate In) in the atom. Therefore, a structure shown in Fig. 8(B) can be formed by 5 - coordinate In, three 3 - coordinate O, and two 4 - coordinate O. Also, the charge of the small group shown in Fig. 8(B) is 0.

[0153] Fig. 8(C) shows a structure having one 4 - coordinate zinc atom (also referred to as 4 - coordinate Zn) and four 4 - coordinate O adjacent to the 4 - coordinate Zn. There is one 4 - coordinate O in the upper half of Fig. 8(C) and three 4 - coordinate O in the lower half. Note that the charge of the small group shown in Fig. 8(C) is 0.

[0154] Fig. 8(D) shows a structure having one 6 - coordinate tin atom (also referred to as 6 - coordinate Sn) and six 4 - coordinate O adjacent to the 6 - coordinate Sn. There are three 4 - coordinate O in the upper half of Fig. 8(D) and three 4 - coordinate O in the lower half. Note that the charge of the small group shown in Fig. 8(D) is + 1.

[0155] Fig. 8(E) shows a small group containing two zinc atoms. There is one 4 - coordinate O in the upper half of Fig. 8(E) and one 4 - coordinate O in the lower half. The charge of the small group shown in Fig. 8(E) is - 1.

[0156] Note that an aggregate of a plurality of small groups is called a medium group, and an aggregate of a plurality of medium groups is called a large group (also referred to as a unit cell).

[0157] Here, the rule for the bonding between the above - mentioned small groups will be described. For example, the three 4 - coordinate O in the upper half of 6 - coordinate In are bonded to three 6 - coordinate In adjacent in the downward direction. The three four-coordinated O atoms in the lower half bond to the three six-coordinated In atoms that are close above them. Also, one three-coordinated O atom in the upper half of the five-coordinated Ga bonds to one five-coordinated Ga atom that is close below it, and one three-coordinated O atom in the lower half bonds to one five-coordinated Ga atom that is close above it. Further, one four-coordinated O atom in the upper half of the four-coordinated Zn bonds to one four-coordinated Zn atom that is close below it, and the three four-coordinated O atoms in the lower half bond to the three four-coordinated Zn atoms that are close above them. In this way, the number of four-coordinated O atoms above the metal atom is equal to the number of metal atoms that are close below that O, and similarly, the number of four-coordinated O atoms below the metal atom is equal to the number of metal atoms that are close above that O. At this time, since O is four-coordinated, the sum of the number of metal atoms that are close below and the number of metal atoms that are close above is 4. Therefore, when the sum of the number of four-coordinated O atoms above one metal atom and the number of four-coordinated O atoms below another metal atom is 4, two small groups having metal atoms can bond to each other. For example, when a six-coordinated metal atom (In or Sn) bonds through the four-coordinated O atoms in the lower half, since there are three four-coordinated O atoms, it will bond to a five-coordinated metal atom or a four-coordinated metal atom. The metal atoms having these coordination numbers bond through four-coordinated O atoms in the c-axis direction. In addition to this, a plurality of small groups bond to form a medium group so that the total charge of the layer structure becomes 0. Furthermore, Fig. 9(A) shows a model diagram of a medium group that constitutes the layer structure of the In-Sn-Zn system. Also, Fig. 9(B) shows a large group composed of three medium groups. Also, one three-coordinated O atom in the upper half of the five-coordinated Ga bonds to one five-coordinated Ga atom that is close below it, and one three-coordinated O atom in the lower half bonds to one five-coordinated Ga atom that is close above it. Further, one four-coordinated O atom in the upper half of the four-coordinated Zn bonds to one four-coordinated Zn atom that is close below it, and the three four-coordinated O atoms in the lower half bond to the three four-coordinated Zn atoms that are close above them. In this way, the number of four-coordinated O atoms above the metal atom is equal to the number of metal atoms that are close below that O, and similarly, the number of four-coordinated O atoms below the metal atom is equal to the number of metal atoms that are close above that O. At this time, since O is four-coordinated, the sum of the number of metal atoms that are close below and the number of metal atoms that are close above is 4. Therefore, when the sum of the number of four-coordinated O atoms above one metal atom and the number of four-coordinated O atoms below another metal atom is 4, two small groups having metal atoms can bond to each other.

[0158] For example, when a six-coordinated metal atom (In or Sn) bonds through the four-coordinated O atoms in the lower half, since there are three four-coordinated O atoms, it will bond to a five-coordinated metal atom or a four-coordinated metal atom. The metal atoms having these coordination numbers bond through four-coordinated O atoms in the c-axis direction. In addition to this, a plurality of small groups bond to form a medium group so that the total charge of the layer structure becomes 0.

[0159] Furthermore, Fig. 9(A) shows a model diagram of a medium group that constitutes the layer structure of the In-Sn-Zn system. Also, Fig. 9(B) shows a large group composed of three medium groups. In Fig. 9(C), the atomic arrangement when observing the layer structure shown in Fig. 9(B) from the c-axis direction is shown.

[0160] In Fig. 9(A), for the sake of convenience, the 3-coordinated O is omitted, and only the number of 4-coordinated O is shown , for example, that there are three 4-coordinated O atoms each in the upper and lower halves of Sn is indicated by the circled 3. Similarly, in Fig. 9(A), that there is one 4-coordinated O each in the upper and lower halves of In is indicated by the circled 1. Also, similarly, in Fig. 9(A), the Zn with one 4-coordinated O in the lower half and three 4-coordinated O in the upper half, and the Zn with one 4-coordinated O in the upper half and three 4-coordinated O in the lower half are shown. In Fig. 9(A), in the middle group constituting the In-Sn-Zn layer structure, from top to bottom in order, it has the following structure. Sn with three 4-coordinated O atoms each in the upper and lower halves is bonded to In with one 4-coordinated O atom each in the upper and lower halves. The In is bonded to Zn with three 4-coordinated O atoms in the upper half. The Zn is bonded to In with three 4-coordinated O atoms each in the upper and lower halves through one 4-coordinated O in the lower half of the Zn. The In is bonded to a small group consisting of two Zn with one 4-coordinated O in the upper half. The small group is bonded to Sn with three 4-coordinated O atoms each in the upper and lower halves through one 4-coordinated O in the lower half of the small group. The bonding of a plurality of the above middle groups forms a large group.

[0161] In Fig. 9(A), in the middle group constituting the In-Sn-Zn layer structure, from top to bottom in order, it has the following structure. Sn with three 4-coordinated O atoms each in the upper and lower halves is bonded to In with one 4-coordinated O atom each in the upper and lower halves. The In is bonded to Zn with three 4-coordinated O atoms in the upper half. The Zn is bonded to In with three 4-coordinated O atoms each in the upper and lower halves through one 4-coordinated O in the lower half of the Zn. The In is bonded to a small group consisting of two Zn with one 4-coordinated O in the upper half. The small group is bonded to Sn with three 4-coordinated O atoms each in the upper and lower halves through one 4-coordinated O in the lower half of the small group. The bonding of a plurality of the above middle groups forms a large group. O to In with three 4-coordinated O atoms each in the upper and lower halves. The In is bonded to a small group consisting of two Zn with one 4-coordinated O in the upper half. The small group is bonded to Sn with three 4-coordinated O atoms each in the upper and lower halves through one 4-coordinated O in the lower half of the small group. The bonding of a plurality of the above middle groups forms a large group.

[0162] Here, for 3-coordinated O and 4-coordinated O, the charge per bond is -0. It can be considered as 667, -0.5. For example, the charges of In (6 - coordinate or 5 - coordinate), Zn (4 - coordinate), and Sn (5 - coordinate or 6 - coordinate) are +3, +2, and +4 respectively. Therefore , the charge of the small group containing Sn is +1. Thus , to form a layer structure containing Sn, a charge of -1 is required to cancel out the +1 charge. As a structure with a charge of -1, as shown in Fig. 8(E), a small group containing 2 Zn atoms can be cited. For example , if there is 1 small group containing Sn and 1 small group containing 2 Zn atoms, the charges will be cancelled out, so that the total charge of the layer structure can be made 0. Furthermore, by forming a structure in which the large group shown in Fig. 9(B) is repeated, a crystal of the In - Sn - Zn system (In2SnZn3O8) can be obtained. Note that the obtained layer structure of the In - Sn - Zn system can be represented by a composition formula of In2SnZn2O7(ZnO) (m is 0 or a natural number).

[0163] n - Zn system can be represented by a composition formula of In2SnZn2O7(ZnO) (m is 0 or a natural number). m The same applies when using other quaternary metal oxides, ternary metal oxides, binary metal oxides, and other metal oxides shown in this embodiment. For example, a model diagram of the middle group constituting the layer structure of the In - Ga - Zn system is shown in Fig. 10(A).

[0164] In Fig. 10(A), the middle group constituting the layer structure of the In - Ga - Zn system has the following structure in order from the top. Three 4 - coordinate O atoms are in the upper half and the lower half respectively, and In is bonded to Zn with 1 4 - coordinate O atom in the upper half. The Zn is bonded to 3 4 - coordinate O atoms in the lower half of the Zn

[0165] is shown in Fig. 10(A).

[0166] In Fig. 10(A), the middle group constituting the layer structure of the In - Ga - Zn system has the following structure in order from the top. In the upper half and the lower half, there are three 4 - coordinate O atoms each, and In is bonded to Zn with 1 4 - coordinate O atom in the upper half. The Zn is bonded to 3 4 - coordinate O atoms in the lower half of the Zn is bonded to 3 4 - coordinate O atoms in the lower half of the Zn is bonded to Zn with 1 4 - coordinate O atom in the upper half. The Zn is bonded to 3 4 - coordinate O atoms in the lower half of the Zn Four-coordinate O atoms are each bonded to Ga atoms through coordinated O atoms, with one in the upper half and one in the lower half. The Ga atom is bonded to In atoms through one four-coordinate O atom in the lower half of the Ga atom, with three four-coordinate O atoms in the upper half and three in the lower half. By bonding multiple middle groups as described above, a large loop is formed.

[0167] Figure 10(B) shows a large group composed of three middle groups. Also, Figure 10(C) shows the atomic arrangement when observing the layer structure shown in Figure 10(B) from the c-axis direction.

[0168] Here, since the charges of In (6-coordinate or 5-coordinate), Zn (4-coordinate), and Ga (5-coordinate) are +3, +2, and +3 respectively, the charge of a small group containing any of In, Zn, and Ga is 0. Therefore, for any combination of these small groups, the total charge of the middle group is always 0.

[0169] Note that the middle groups constituting the In-Ga-Zn-based layer structure are not limited to the middle groups shown in Figure 10(A), and large loops can also be formed by combining middle groups with different arrangements of In, Ga, and Zn.

[0170] Specifically, by repeating the large group shown in Figure 10(B), a crystal of the In-Ga-Zn system can be obtained. The obtained In-Ga-Zn-based layer structure can be represented by a composition formula of InGaO3(ZnO) n (where n is a natural number). n

[0171] In the case of n = 1 (InGaZnO4), for example, it can have the crystal structure shown in Figure 26(A). In the crystal structure shown in Figure 26(A), as described in Figure 8(B), Ga and ​​​​​​​​​​Since In takes a 5 - coordinate structure, a structure in which Ga replaces In is also possible.

[0172] Also, in the case of n = 2 (InGaZn2O5), for example, the crystal structure shown in Fig. 26(B) is possible. In the crystal structure shown in Fig. 26(B), as explained in Fig. 8(B) , since Ga and In take a 5 - coordinate structure, a structure in which Ga replaces In is also possible.

[0173] The above is an explanation of an example of the CAAC structure. An oxide semiconductor having crystallinity like CAAC has few defects in the bulk.

[0174] Furthermore, the regions 604a_a, 604b_a, regions 604a_b, and 604b_b shown in Figs. 7(A) and 7(B) have the function of a source or drain of a transistor. As the dopant, for example, elements in Group 1 to 3 of the periodic table (such as boron, etc.), elements in Group 15 of the periodic table (such as nitrogen, phosphorus, and one or more of arsenic), and one or more of noble gas elements (such as helium, argon, and xenon ) can be used. A region having the function of a source of a transistor is also referred to as a source region, and a region having the function of a drain of a transistor is also referred to as a drain region. By adding a dopant to the regions 604a_a, 604b_a, regions 604 a_b, and 604b_b, the resistance between the conductive layer can be reduced, so that the transistor can be miniaturized. Since the conductive layers 605a_a, 605b_a, 605a_b, and 605b

[0175] _b each have the function of a source or drain of a transistor. Note that the t A layer having a function as a source of a transistor is also referred to as a source electrode or a source wiring, and a layer having a function as a drain of a transistor is also referred to as a drain electrode or a drain wiring.

[0176] As the conductive layers 605a_a, 605b_a, 605a_b, and 605b _b, for example, a metal material such as aluminum, magnesium, chromium, copper, tantalum, titanium, mol ybdenum, or tungsten, or a layer of an alloy material mainly composed of these metal materials can be used. For example, a layer of an alloy material containing copper, magnesium, and aluminum can be used to form the conductive layers 605a_a, 605b_a, 605a_b , and 605b_b. Further, the conductive layers 605a_a, 605b_a, 605a_b, and 605b_b can also be formed by laminating materials applicable to them. For example, a layer of an alloy material containing copper, magnesium, and aluminum and a layer containing copper can be laminated to form the conductive layers 605a_a, 605b_a, 605a_b , and 605b_b. Moreover, as the conductive layers 605a_a, 605b_a, 605a_b, and 605b_b, a layer containing a conductive metal oxide can also be used. As the conductive metal oxide, for example, indium oxide, tin oxide, zinc oxide, indium tin oxide , or indium zinc oxide can be used. Note that the conductive metal applicable to the conductive layers 605a_a, 605b_a, 605a_b, and 605b_b oxide can also be used to form the conductive layers 605a_a, 605b_a, 605a_b, and 605b_b.

[0177] In addition, as the conductive layers 605a_a, 605b_a, 605a_b, and 6 05b_b, a layer containing a conductive metal oxide can also be used. As the conductive metal oxide, for example, indium oxide, tin oxide, zinc oxide, indium tin oxide , or indium zinc oxide can be used. Note that the conductive metal applicable to the conductive layers 605a_a, 605b_a, 605a_b, and 605b_b oxide can also be used to form the conductive layers 605a_a, 605b_a, 605a_b, and 605b_b. The metal oxide may contain silicon oxide.

[0178] As the insulating layers 606a and 606b, for example, layers of materials applicable to the insulating layers 602_a and 60 2_b can be used. Also, the insulating layers 606a and 6 06b may be formed by laminating materials applicable to the insulating layers 606a and 606b. That is acceptable.

[0179] The insulating layer 607 functions as a protective insulating layer that suppresses the intrusion of impurities into the transistor. It has this function.

[0180] As the insulating layer 607, for example, layers of materials applicable to the insulating layers 602_a and 602_b can be used. Also, the insulating layer 607 may be formed by laminating materials applicable to the insulating layer 607. For example, the insulating layer 607 may be formed by a silicon oxide layer, an aluminum oxide layer, or the like. For example, by using an aluminum oxide layer, the effect of suppressing the intrusion of impurities into the semiconductor layer 603_b can be enhanced, and the effect of suppressing the desorption of oxygen in the semiconductor layer 60 3_b can be enhanced.

[0181] Note that the transistor of this embodiment may have a structure including an insulating layer on a part of an oxide semiconductor layer having a function as a channel formation layer, and a conductive layer having a function as a source or a drain, which is superimposed on the oxide semiconductor layer with the insulating layer interposed therebetween. In the case of the above structure, the insulating layer functions as a layer (also referred to as a channel protection layer) that protects the channel formation layer of the transistor. As the insulating layer having a function as a channel protection layer, for example, layers of materials applicable to the insulating layers 602_a and 602_b can be used. In this case, the insulating layer has a function as a layer (also referred to as a channel protection layer) that protects the channel formation layer of the transistor. As the insulating layer having a function as a channel protection layer, for example, layers of materials applicable to the insulating layers 602_a and 602_b can be used. That is acceptable. Further, an insulating layer having a function as a channel protection layer may be formed by laminating materials applicable to the insulating layer 602_a and the insulating layer 602_b.

[0182] Also, a base layer may be formed on the device formation layer 600_a and the device formation layer 600_b, and a transistor may be formed on the base layer. At this time, as the base layer, for example, a layer of a material applicable to the insulating layer 602_a and the insulating layer 602_b can be used. Further, the base layer may be constituted by laminating materials applicable to the insulating layer 602_a and the insulating layer 602_b. For example, the base layer may be constituted by laminating an aluminum oxide layer and a silicon oxide layer. By doing so, it is possible to suppress the oxygen contained in the base layer from desorbing through the semiconductor layer 603_a and the semiconductor layer 603_b.

[0183] Furthermore, as an example of a method for manufacturing a transistor in the present embodiment, an example of a method for manufacturing a transistor shown in FIG. 7(A) will be described with reference to FIG. 11. FIG. 11 is a cross-sectional schematic view for explaining the method for manufacturing the transistor shown in FIG. 7(A).

[0184] First, as shown in FIG. 11(A), a device formation layer 600_a is prepared, and a semiconductor layer 603_a is formed on the device formation layer 600_a.

[0185] For example, a semiconductor layer 603_a can be formed by forming a film of an oxide semiconductor material applicable to the semiconductor layer 603_a (also referred to as an oxide semiconductor film) using a sputtering method. After forming the oxide semiconductor film, a part of the oxide semiconductor film may be etched. Further, in a rare gas atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas and oxygen An oxide semiconductor film may be formed in an atmosphere.

[0186] Also, as a sputtering target, an oxide target having a composition ratio of In2O3:Ga2O3:ZnO = 1:1: 1 [molar ratio] can be used to form an oxide semiconductor film. For example, In2O3:Ga2O3:ZnO = 1:1:2 [molar ratio , 4:2:3 [molar ratio], 3:1:2 [molar ratio], 2:1:3 [molar ratio] , an oxide semiconductor film may be formed using an oxide target having a composition ratio of 3:1:4 [molar ratio]. It may be formed.

[0187] Also, as a sputtering target, In:Sn:Zn = 1:2:2 [atomic ratio] , 2:1:3 [atomic ratio], 1:1:1 [atomic ratio], or 20:45:35 [atomic ratio can be used to form an oxide semiconductor film. By using an oxide target having such a composition ratio, an oxide semiconductor film with high crystallinity can be formed. In particular, by using an oxide target having a composition ratio of In:Sn:Zn = 2:1:3, an oxide semiconductor film with higher crystallinity can be formed.

[0188] Also, as a sputtering target, In:Zn = 50:1 to In:Zn = 1: 2 (converted to molar ratio, In2O3:ZnO = 25:1 to In2O3:ZnO = 1: 4), preferably In:Zn = 20:1 to In:Zn = 1:1 (converted to molar ratio In2O3:ZnO = 10:1 to In2O3:ZnO = 1:2), more preferably I n:Zn = 15:1 to In:Zn = 1.5:1 (converted to molar ratio, In2O3:Z The composition ratio of the oxide target was In2O3:ZnO=15:2 or In2O3:ZnO=3:4. For example, an In-Zn oxide semiconductor film may be formed. The target used for film formation has an atomic ratio of In:Zn:O=S:U:R, where R>1.5. By increasing the amount of In, the field effect mobility (simply called the mobility This can improve the mobility.

[0189] In addition, when a sputtering method is used, for example, a rare gas (typically argon) atmosphere is used. The semiconductor layer 603_a is formed under an oxygen atmosphere or a mixed atmosphere of a rare gas and oxygen. At this time, when the semiconductor layer 603_a is formed under a mixed atmosphere of rare gas and oxygen, the rare gas It is preferable that the amount of oxygen is large relative to the amount of gas.

[0190] In addition, when a film is formed using a sputtering method, hydrogen, water, and hydroxyl groups are present in the deposited film. In order to prevent impurities such as hydrides (also called hydrogen compounds) from being included, It is preferable to sufficiently suppress leakage from the gas supply and degassing from the inner walls of the film formation chamber.

[0191] For example, before forming a film by sputtering, the sputtering device is preheated. By carrying out the preheating treatment, the above impurities can be removed. You can detach things.

[0192] In addition, before forming a film by sputtering, for example, argon, nitrogen, helium, or In the present study, no voltage was applied to the target side in an oxygen atmosphere, and a voltage was applied to the substrate side using an RF power source. Even if a treatment is performed to modify the surface by applying a voltage to generate plasma (also called reverse sputtering), Good. By performing reverse sputtering, the powdery substances (particles, also called dust) adhering to the surface to be formed can be removed.

[0193] In addition, when forming a film using the sputtering method, the residual moisture in the film formation chamber can be removed using an adsorption type vacuum pump or the like. As the adsorption type vacuum pump, for example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Alternatively, a turbo molecular pump equipped with a cold trap can be used to remove the residual moisture in the film formation chamber. By using the above vacuum pump, the backflow of the exhaust gas containing the above impurities can be reduced.

[0194] In addition, as the sputtering gas, for example, a high-purity gas from which the above impurities have been removed is used, so that the concentration of the above impurities in the formed film can be reduced. For example, as the sputtering gas, it is preferable to use a gas with a dew point of -70°C or lower.

[0195] In addition, in an example of the method for manufacturing a transistor in this embodiment, when forming a layer by etching a part of the film, for example, a resist mask is formed on a part of the film by a photolithography process, and the layer is formed by etching the film using the resist mask. In this case, the resist mask is removed after the formation of the layer.

[0196] In addition, when forming an oxide semiconductor layer that is CAAC as the semiconductor layer 603_a, using the sputtering method, the temperature of the element formation layer on which the oxide semiconductor film is to be formed is set to 100°C or higher and 5 00°C or lower, preferably 200°C or higher and 350°C or lower, to form the oxide semiconductor film. ​​In addition, the temperature of the element formation layer is increased to form an oxide semiconductor film. Improved field effect mobility of transistors and improved stability against gate bias stress It can be done.

[0197] In this case, it is preferable that the element formation layer 600_a is flat. The average surface roughness of the formation layer 600_a is 1 nm or less, and further 0.3 nm or less. It is preferable that the flatness of the element formation layer 600_a is improved, so that the amorphous state For example, chemical mechanical polishing (CMP) can improve the mobility of the oxide semiconductor. P) The element formation layer 600_a is planarized by one or more of a process and a plasma process. In this case, the plasma treatment involves sputtering the surface with rare gas ions. This also includes a process of etching a surface using a treatment or etching gas.

[0198] Next, as shown in FIG. 11B, a conductive layer 605a_a and A conductive layer 605b_a is formed.

[0199] For example, a sputtering method or the like is used to form the conductive layer 605a_a and the conductive layer 605b_a. A film of an applicable material is formed as a first conductive film, and a part of the first conductive film is etched. In this way, the conductive layers 605a_a and 605b_a can be formed.

[0200] Next, as shown in FIG. 11(C), an insulating layer 602_ is formed so as to be in contact with the semiconductor layer 603_a. Form a.

[0201] For example, the reaction may be carried out under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixture of a rare gas and oxygen. In a mixed atmosphere, a film applicable to the insulating layer 602_a is formed using a sputtering method. As a result, the insulating layer 602_a can be formed. By forming the insulating layer 602_a using a sputtering method, it is possible to suppress a decrease in resistance in a portion of the semiconductor layer 603_a that functions as a back channel of the transistor. Also, the temperature of the device-forming layer 600_a when forming the insulating layer 602_a is preferably room temperature or higher and 300°C or lower.

[0202] Also, before forming the insulating layer 602_a, plasma treatment may be performed using a gas such as N2O, N2, or Ar to remove adsorbed water or the like attached to the surface of the exposed semiconductor layer 603_a. When plasma treatment is performed, it is preferable to form the insulating layer 602_a without exposing it to the atmosphere thereafter.

[0203] Next, a conductive layer 601_a is formed on the insulating layer 602_a.

[0204] For example, a film of a material applicable to the conductive layer 601_a is formed as a second conductive film using a sputtering method or the like, and a part of the second conductive film is etched to form the conductive layer 601_a.

[0205] Also, in an example of a method for manufacturing a transistor shown in FIG. 7(A), for example, heat treatment is performed at a temperature of 600°C or higher and 750°C or lower, or at a temperature of 600°C or higher and lower than the distortion point of the substrate. For example, after forming an oxide semiconductor film, after etching a part of the oxide semiconductor film, after forming a first conductive film, after etching a part of the first conductive film, after forming the insulating layer 602_a, after forming a second conductive film, or after etching a part of the second conductive film, the above heat treatment is performed. ​​​​​​​​​​​​ By performing the above heat treatment, impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed from the semiconductor layer 603_a by half. The conductor layer 603_a is removed.

[0206] As the heat treatment apparatus for performing the above heat treatment, an apparatus that heats the object to be treated by heat conduction or heat radiation from a heating element such as an electric furnace or a resistance heating element can be used. For example, a G RTA (Gas Rapid Thermal Anneal) apparatus or an RTA (Rapid T hermal Anneal) apparatus such as an LRTA (La mp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is, for example, a halogen gen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high-pressure mercury lamp, etc. It is an apparatus that heats the object to be treated by the radiation of light (electromagnetic waves) emitted from a lamp. Also, the GRTA apparatus is an apparatus that performs a heat treatment using a high-temperature gas. As the high-temperature gas, for example, a noble gas or an inert gas (such as nitrogen) that does not react with the object to be treated by heat treatment can be used. pressure sodium lamp, or a high-pressure mercury lamp, etc. It is an apparatus that heats the object to be treated by the radiation of light (electromagnetic waves) emitted from a lamp. Also, the GRTA apparatus is an apparatus that performs a heat treatment using a high-temperature gas. As the high-temperature gas, for example, a noble gas or an inert gas (such as nitrogen) that does not react with the object to be treated by heat treatment can be used. Furthermore, after performing the above heat treatment, while maintaining the heating temperature or during the process of cooling from the heating temperature, high-purity oxygen gas, high-purity N2O gas, or ultra-dry air (atmosphere with a dew point of -40°C or lower, preferably -60°C or lower) can be introduced into the same furnace as the furnace in which the heat treatment was performed. At this time, it is preferable that the oxygen gas or N2O gas does not contain water, hydrogen, etc. Furthermore, after performing the above heat treatment, while maintaining the heating temperature or during the process of cooling from the heating temperature, high-purity oxygen gas, high-purity N2O gas,

[0207] Also, after performing the above heat treatment, while maintaining the heating temperature or during the process of cooling from the heating temperature, high-purity oxygen gas, high-purity N2O gas, or ultra-dry air (atmosphere with a dew point of -40°C or lower, preferably -60°C or lower) can be introduced into the same furnace as the furnace in which the heat treatment was performed. At this time, it is preferable that the oxygen gas or N2O gas does not contain water, hydrogen, etc. or ultra-dry air (atmosphere with a dew point of -40°C or lower, preferably -60°C or lower) can be introduced into the same furnace as the furnace in which the heat treatment was performed. At this time, it is preferable that the oxygen gas or N2O gas does not contain water, hydrogen, etc. Also, it is preferable that the oxygen gas or N2O gas does not contain water, hydrogen, etc. In addition, the purity of the oxygen gas or N2O gas introduced into the heat treatment apparatus is 6N or higher, preferably 7N or higher, that is, the impurity concentration in the oxygen gas or N2O gas is 1 ppm or lower, preferably It is preferably 0.1 ppm or less. Due to the action of oxygen gas or N2O gas, oxygen is supplied to the semiconductor layer 603_a, and defects caused by oxygen deficiency in the semiconductor layer 603_a can be reduced. Note that the introduction of the high-purity oxygen gas, high-purity N2O gas, or ultra-dry air may be performed during the above heat treatment. Oxygen is supplied to the semiconductor layer 603_a, and defects caused by oxygen deficiency in the semiconductor layer 603_a can be reduced. Note that the introduction of the high-purity oxygen gas, high-purity N2O gas, or ultra-dry air may be performed during the above heat treatment.

[0208] In addition, in an example of a method for manufacturing a transistor shown in FIG. 7(A), after forming the semiconductor layer 603_a, after forming the conductive layer 605a_a and the conductive layer 605b_a, after forming the insulating layer 602_a, after forming the conductive layer 601_a, or after the above heat treatment, oxygen may be implanted into the oxide semiconductor film by a method such as oxygen doping treatment using oxygen plasma or a method of accelerating oxygen ions by an electric field. For example, oxygen doping treatment may be performed using high-density plasma of 2.45 GHz. Also, oxygen doping treatment may be performed using the ion implantation method. By performing oxygen doping treatment, variations in the electrical characteristics of the manufactured transistor can be reduced. For example, oxygen doping treatment is performed to make the insulating layer 602_a in a state where oxygen is more than the stoichiometric composition ratio. By making the oxygen in the insulating layer in contact with the semiconductor layer 603_a excessive, oxygen is easily supplied to the semiconductor layer 603_a. Therefore, oxygen defects in the semiconductor layer 603_a or at the interface between the insulating layer 602_a and the semiconductor layer 603_a can be reduced, so that the carrier concentration of the semiconductor layer 603_a can be further reduced. Also, not limited to this, even when the oxygen contained in the semiconductor layer 603_a is made excessive during the manufacturing process, the above insulating layer in contact with the semiconductor layer 603_a suppresses the desorption of oxygen from the semiconductor layer 603_a.

[0209] By making the oxygen in the insulating layer in contact with the semiconductor layer 603_a excessive, oxygen is easily supplied to the semiconductor layer 603_a. Therefore, oxygen defects in the semiconductor layer 603_a or at the interface between the insulating layer 602_a and the semiconductor layer 603_a can be reduced, so that the carrier concentration of the semiconductor layer 603_a can be further reduced. Also, not limited to this, even when the oxygen contained in the semiconductor layer 603_a is made excessive during the manufacturing process, the above insulating layer in contact with the semiconductor layer 603_a suppresses the desorption of oxygen from the semiconductor layer 603_a. ​​​​​​​​​​​ can be achieved.

[0210] For example, when forming an insulating layer containing gallium oxide as the insulating layer 602_a, oxygen is supplied to the insulating layer to make the composition of gallium oxide Ga2O x can be achieved.

[0211] Also, when forming an insulating layer containing aluminum oxide as the insulating layer 602_a, oxygen is supplied to the insulating layer to make the composition of aluminum oxide Al2O x can be achieved.

[0212] Also, when forming an insulating layer containing gallium aluminum oxide or aluminum gallium oxide as the insulating layer 602_a, oxygen is supplied to the insulating layer to make the composition of gallium aluminum oxide or aluminum gallium oxide Ga x Al 2-x O 3+α can be achieved.

[0213] Through the above steps, impurities such as hydrogen, water, hydroxyl groups, or hydrides (also referred to as hydrogen compounds) are removed from the semiconductor layer 603_a, and oxygen is supplied to the semiconductor layer 603_a, so that the oxide semiconductor layer can be purified to a high purity.

[0214] Furthermore, separately from the above heat treatment, after forming the insulating layer 602_a, heat treatment is performed in an inert gas atmosphere or an oxygen gas atmosphere (preferably at 200°C or higher and 600°C or lower, for example, 2 50°C or higher and 350°C or lower) may be performed.

[0215] The intended heating temperature of the device formation layer 600_a shown above or the temperature of the heat treatment after forming the oxide semiconductor film is 150°C or higher, preferably 200°C or higher, more preferably 400°C or higher ​as described above. In the heat treatment after the formation of the oxide semiconductor film, if the temperature is 300 °C or higher, impurities such as hydrogen contained in the film can be released and removed (dehydration, dehydrogenation).

[0216] The above heat treatment can be carried out in an oxygen atmosphere, but it may also be carried out in two steps, first in a nitrogen atmosphere or under reduced pressure for dehydration and dehydrogenation, and then in an oxygen atmosphere for heat treatment. By performing heat treatment in an atmosphere containing oxygen after dehydration and dehydrogenation, it becomes possible to add oxygen to the oxide semiconductor, further enhancing the effect of the above heat treatment. Also, the above heat treatment for oxidation may be carried out with an insulating layer provided in contact with the oxide semiconductor layer. For example, defects due to oxygen deficiency are likely to be generated at the interface between the oxide semiconductor layer and the layer laminated on the oxide semiconductor layer. By making the oxide semiconductor contain an excessive amount of oxygen through the above heat treatment, the constantly generated oxygen deficiency can be compensated for by the excessive oxygen. The above excessive oxygen mainly exists between the lattices. By setting the oxygen concentration to 1×10 or more and 2×10 or less, it is possible to make the oxide semiconductor layer contain oxygen without causing strain or the like in the crystal even when the crystal is crystallized, for example. In addition, by performing heat treatment after the formation of the oxide semiconductor film, the stability of the manufactured transistor against gate bias stress can be enhanced. Also, the field-effect mobility of the transistor can be improved. 16 / cm 3 20 / cm 3

[0217]

[0218] ​​​​​​​​​​​​​​Further, as shown in FIG. 11(E), the semiconductor layer 6 By adding a dopant to the insulating layer 603_a, the region is self-aligned through the insulating layer 602_a. 604a_a and region 604b_a are formed.

[0219] For example, dopants can be added using an ion doping device or an ion implantation device. can be done.

[0220] Note that although an example of a method for manufacturing the transistor illustrated in FIG. 7A has been described, the present invention is not limited to this. For example, in each component shown in FIG. 7(B), the names of the components are the same as those of the components shown in FIG. 7(A). 7A and at least a part of the functions are the same as those of the components shown in FIG. The description of the example of the manufacturing method of the transistor illustrated in (A) can be used as appropriate.

[0221] As described with reference to FIGS. 7 to 11, an example of the transistor in this embodiment is The gate insulating layer is a conductive layer having a function as a gate. a conductive layer having a function as a gate through an insulating layer having a function as a gate insulating layer; an oxide semiconductor layer which overlaps with the oxide semiconductor layer and in which a channel is formed; A conductive layer having a function as one of a source and a drain and an oxide semiconductor layer and a conductive layer having a function as the other of the source and drain. In this way, a transistor can be formed.

[0222] In addition, in the example of the transistor of this embodiment, the carrier concentration of the oxide semiconductor layer 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3Less than, more preferably 1×10 11 / cm 3 can be made less than.

[0223] To apply an oxide semiconductor to a transistor, the carrier density should be 1×10 18 / cm 3 or less is preferred. Oxide semiconductors containing In or Zn not only include Ga or Sn as one element constituting the oxide semiconductor, but also purify the oxide semiconductor film to a high purity (removing hydrogen, etc.) as described above, or by performing heat treatment after film formation, the carrier density can be made 1×10 / cm 18 / cm 3 or less.

[0224] In addition, by performing one or more of the heat treatment during film formation of the oxide semiconductor film and the heat treatment after film formation, the threshold voltage of the transistor can be positively shifted to achieve normally-off operation, and the off-current per 1-μm channel width can be made 10 aA (1×10 A -17 A ) or less, more preferably 1 aA (1×10 -18 A) or less, more preferably 10 zA (1×10 -20 A) or less, more preferably 1 zA (1×10 -21 A) or less, more preferably 100 yA (1×10 - 22 A) or less. The lower the off-current of the transistor, the better, but the lower limit of the off-current of the transistor in this embodiment is estimated to be about 10 -30 A / μm is.

[0225] The transistor including the oxide semiconductor layer of this embodiment, for example, in the above embodiment By using it for the transistors of the memory circuit, the data retention time in the memory circuit can be lengthened. This can be achieved.

[0226] Also, an example of the transistor in this embodiment can be stacked with other transistors (for example, transistors including a semiconductor layer containing a Group 14 semiconductor (such as silicon) in the periodic table). Therefore, while forming the transistor including the oxide semiconductor layer and the other transistors on the same substrate, the circuit area can be reduced. As described in Embodiment 1, a structure in which a transistor using an oxide semiconductor (corresponding to the transistor 107 in FIG. 1(B) etc.) is provided on a transistor using single crystal silicon (corresponding to the transistor 111 in FIG. 1(B) etc.) is preferable. This structure can achieve all of high-speed operation, data retention, and reduction of the circuit area. Also, the transistor using the oxide semiconductor can obtain a relatively high field-effect mobility in either the amorphous or crystalline state. This improvement in field-effect mobility is presumably due to not only the removal of impurities by dehydration and dehydrogenation but also the shortening of the interatomic distance due to densification. Also, crystallization can be achieved by removing impurities from the oxide semiconductor film to increase its purity. For example, in an In-Sn-Zn-based oxide semiconductor, it is possible to obtain a field-effect mobility exceeding 31 cm / Vsec, preferably exceeding 39 cm / Vsec, more preferably exceeding 60 cm / Vsec. Also, the highly purified non-single crystal oxide semiconductor ideally has a field-effect mobility of 100 cm / Vsec.

[0227] As described in Embodiment 1, a structure in which a transistor using an oxide semiconductor (corresponding to the transistor 107 in FIG. 1(B) etc.) is provided on a transistor using single crystal silicon (corresponding to the transistor 111 in FIG. 1(B) etc.) is preferable. This structure can achieve all of high-speed operation, data retention, and reduction of the circuit area. Also, the transistor using the oxide semiconductor can obtain a relatively high field-effect mobility in either the amorphous or crystalline state. This improvement in field-effect mobility is presumably due to not only the removal of impurities by dehydration and dehydrogenation but also the shortening of the interatomic distance due to densification. Also, crystallization can be achieved by removing impurities from the oxide semiconductor film to increase its purity. For example, in an In-Sn-Zn-based oxide semiconductor, it is possible to obtain a field-effect mobility exceeding 31 cm / Vsec, preferably exceeding 39 cm / Vsec, more preferably exceeding 60 cm / Vsec. Also, the highly purified non-single crystal oxide semiconductor ideally has a field-effect mobility of 100 cm / Vsec. Also, the transistor using the oxide semiconductor can obtain a relatively high field-effect mobility in either the amorphous or crystalline state. This improvement in field-effect mobility is presumably due to not only the removal of impurities by dehydration and dehydrogenation but also the shortening of the interatomic distance due to densification. Also, crystallization can be achieved by removing impurities from the oxide semiconductor film to increase its purity. For example, in an In-Sn-Zn-based oxide semiconductor, it is possible to obtain a field-effect mobility exceeding 31 cm / Vsec, preferably exceeding 39 cm / Vsec, more preferably exceeding 60 cm / Vsec. Also, the highly purified non-single crystal oxide semiconductor ideally has a field-effect mobility of 100 cm / Vsec. This structure can achieve all of high-speed operation, data retention, and reduction of the circuit area.

[0228] Also, the transistor using the oxide semiconductor can obtain a relatively high field-effect mobility in either the amorphous or crystalline state. This improvement in field-effect mobility is presumably due to not only the removal of impurities by dehydration and dehydrogenation but also the shortening of the interatomic distance due to densification. Also, crystallization can be achieved by removing impurities from the oxide semiconductor film to increase its purity. For example, in an In-Sn-Zn-based oxide semiconductor, it is possible to obtain a field-effect mobility exceeding 31 cm / Vsec, preferably exceeding 39 cm / Vsec, more preferably exceeding 60 cm / Vsec. Also, the highly purified non-single crystal oxide semiconductor ideally has a field-effect mobility of 100 cm / Vsec. cm 2 / Vsec, preferably exceeding 39 cm 2 / Vsec, more preferably exceeding 60 cm 2 / Vsec. Also, the highly purified non-single crystal oxide semiconductor ideally has a field-effect mobility of 100 cm 2It is also suggested that it becomes possible to achieve a field-effect mobility exceeding / Vsec. Also, in an example of the transistor in the present embodiment, it is suggested that the lower the defect density of the oxide semiconductor layer, the higher the field-effect mobility of the transistor. The reason for this will be described below. This also suggests that it becomes possible. Further, in an example of the transistor in this embodiment, it is suggested that the lower the defect density of the oxide semiconductor layer, the higher the field-effect mobility of the transistor. This is suggested. The reason will be explained below. The reason will be explained below.

[0229] Not limited to the field-effect transistor including an oxide semiconductor layer, the actually measured field-effect mobility of the field-effect transistor becomes lower than the original field-effect mobility for various reasons. The factors that reduce the field-effect mobility include defects inside the semiconductor layer and defects at the interface between the semiconductor layer and the insulating layer. For example, using the Levinson model, the field-effect mobility of the transistor can be theoretically derived when it is assumed that there are no defects in the oxide semiconductor layer. The factors that reduce the field-effect mobility include defects inside the semiconductor layer and defects at the interface between the semiconductor layer and the insulating layer. For example, using the Levinson model, when it is assumed that there are no defects in the oxide semiconductor layer, the field-effect mobility of the transistor can be theoretically derived. For example, using the Levinson model, the field-effect mobility of the transistor can be theoretically derived when it is assumed that there are no defects in the oxide semiconductor layer. For example, using the Levinson model, the field-effect mobility of the transistor can be theoretically derived when it is assumed that there are no defects in the oxide semiconductor layer.

[0230] Assuming that the original field-effect mobility of the semiconductor layer is μ0, the measured field-effect mobility is μ, and there is some potential barrier (grain boundary, etc.) in the semiconductor layer, the measured field-effect mobility μ is expressed by the following formula (1). Assuming that there is some potential barrier (grain boundary, etc.) in the semiconductor layer, the measured field-effect mobility μ is expressed by the following formula (1). In the above formula (1), E is the height of the potential barrier, k is the Boltzmann constant, and T is the absolute temperature. Also, assuming that the potential barrier is due to defects, in the Levinson model, the height of the potential barrier E is expressed by the following formula (2).

[0231]

Equation

[0232] In the above formula (1), E is the height of the potential barrier, k is the Boltzmann constant, and T is the absolute temperature. In the above formula (1), E is the height of the potential barrier, k is the Boltzmann constant, and T is the absolute temperature. Also, assuming that the potential barrier is due to defects, in the Levinson model, the height of the potential barrier E is expressed by the following formula (2). In the Levinson model, when it is assumed that the potential barrier is due to defects, the height of the potential barrier E is expressed by the following formula (2). In the Levinson model, when it is assumed that the potential barrier is due to defects, the height of the potential barrier E is expressed by the following formula (2).

[0233]

Equation

[0234] In the above formula (2), e is the elementary charge, and N is the average defect density per unit area in the channel. is the dielectric constant of the semiconductor, n is the carrier areal density of the channel, and C ox is the volume per unit area quantity, V g is the gate voltage, and t is the channel thickness. In this case, the thickness of the channel may be the same as the thickness of the semiconductor layer. Drain current I d is expressed by the following equation (3).

[0235]

number

[0236] In the above formula (3), L is the channel length and W is the channel width, where L=W= 10μm. Also, V d is the drain voltage. Furthermore, change both sides of the above equation to V g Divide by Furthermore, by taking the logarithm of both sides, equation (3) can be transformed into the following equation (4).

[0237]

number

[0238] In the above formula (4), the right side is V g As can be seen from equation (4), the vertical axis is ln(I d / V g ), the horizontal axis is 1 / V g The straight line on the graph obtained by plotting the actual measured values as The defect density N can be calculated from the slope of the I d -V g Due to its characteristics, The defect density can be evaluated. For example, the ratio of indium (In), gallium (Ga), and zinc (Zn) in an oxide semiconductor film with In:Ga:Zn = 1:1:1 [atomic ratio] The defect density N of the oxide semiconductor film is about 1×10 12 / cm 2 .

[0239] Based on the defect density obtained by the above method, etc., using the above formulas (1) and (2), when obtaining μ0 which is the field-effect mobility of the original semiconductor layer, μ0 = 120 cm 2 / Vs. Usually, the field-effect mobility measured in an In-Ga-Zn-based oxide with defects is about 40 c m / Vs. However, the mobility μ0 of an oxide semiconductor without defects inside the semiconductor and at the interface between the semiconductor and the insulating film can be expected to be 120 cm 2 . From this, it can be understood that the less the defects, the higher the mobility of the oxide semiconductor and further the field-effect mobility of the transistor. For example, an oxide semiconductor layer such as CAAC has a low defect density. 2 / Vs. That is, the higher the defect density, the higher the mobility of the oxide semiconductor and further the field-effect mobility of the transistor. For example, an oxide semiconductor layer such as CAAC has a low defect density. For example, an oxide semiconductor layer such as CAAC has a low defect density.

[0240] However, even if there are no defects inside the semiconductor layer, the transport characteristics of the transistor are affected by scattering at the interface between the channel and the gate insulating layer. That is, the mobility μ1 at a location x away from the gate insulator interface is represented by the following formula (5). That is, the mobility μ1 at a location x away from the gate insulator interface is represented by the following formula (5). In the above formula (5), D is the electric field in the gate direction, and B and l are constants. B and l can be obtained from actual measurement results. In the above measurement results, B = 2.38×10

[0241]

Equation

[0242] In the above formula (5), D is the electric field in the gate direction, and B and l are constants. B and l can be obtained from actual measurement results. In the above measurement results, B = 2.38×10 cm / 7 cm / s and l = 10 nm (depth affected by interface scattering). In Equation (5), as D increases (that is, as the gate voltage increases), the second term of Equation (5) increases, so it can be seen that mobility μ1 decreases as D increases. Specifically, as the gate voltage increases, the second term of Equation (5) increases, so it can be seen that mobility μ1 decreases as D increases. μ1 decreases.

[0243] Figure 12 shows the calculation results of the mobility μ2 of a transistor using an ideal oxide semiconductor without defects inside the semiconductor layer as the channel. For the above calculation, device simulation software Sentaurus Device manufactured by Synopsys is used. In the oxide semiconductor layer, the bandgap is 2.8 electron volts, the electron affinity is 4.7 electron volts, the relative permittivity is 15, and the thickness is 15 nm. Further, in the transistor, the work functions of the gate, source, and drain are 5.5 electron volts, 4.6 electron volts, and 4.6 electron volts, respectively. In the gate insulating layer, the thickness is 100 nm and the relative permittivity is 4.1. Further, in the transistor, both the channel length and the channel width are 10 μm, and the drain voltage V is 0.1 V. is used. Also, in the oxide semiconductor layer, the bandgap is set to 2.8 electron volts, the electron affinity is set to 4.7 electron volts, the relative permittivity is set to 15, and the thickness is set to 15 nm. Furthermore, in the transistor, the work functions of the gate, source, and drain are set to 5.5 electron volts, 4.6 electron volts, and 4.6 electron volts, respectively. In the gate insulating layer, the thickness is set to 100 nm and the relative permittivity is set to 4.1. Moreover, in the transistor, both the channel length and the channel width are set to 10 μm, and the drain voltage V is 0.1 V. is 0.1 V. is 0.1 V. is 0.1 V. is 0.1 V. is 0.1 V. d is 0.1 V.

[0244] As shown in Figure 12, when the gate voltage V G is around 1 V, the field-effect mobility is as high as 100 cm / Vs or more. However, when the gate voltage V 2 becomes even higher, the interface scattering becomes larger and the mobility decreases. In order to reduce the interface scattering, it is desirable to make the surface of the semiconductor layer flat at the atomic level (also referred to as Atomic Layer Flatness). G becomes even higher, the interface scattering becomes larger and the mobility decreases. In order to reduce the interface scattering, it is desirable to make the surface of the semiconductor layer flat at the atomic level (also referred to as Atomic Layer Flatness). becomes even higher, the interface scattering becomes larger and the mobility decreases. In order to reduce the interface scattering, it is desirable to make the surface of the semiconductor layer flat at the atomic level (also referred to as Atomic Layer Flatness). becomes even higher, the interface scattering becomes larger and the mobility decreases. In order to reduce the interface scattering, it is desirable to make the surface of the semiconductor layer flat at the atomic level (also referred to as Atomic Layer Flatness).

[0245] Furthermore, a fine transistor using the oxide semiconductor with the above high field-effect mobility is The calculation results of the electrical characteristics in the [object] are shown below.

[0246] First, the cross-sectional structure of the transistor used in the calculation is shown in FIG. 13. The transistor shown in FIG. 13 has N-type semiconductor regions 653a and 653b and a semiconductor region 653 c in the oxide semiconductor layer. The resistivity of the semiconductor regions 653a and 653b is 2×10 -3 Ωcm shall be.

[0247] The transistor shown in FIG. 13(A) is provided on the underlying insulator 651 and the buried insulator 652. The buried insulator 652 is provided so as to be buried in the underlying insulator 651 using aluminum oxide. shall be provided so as to be buried.

[0248] Also, the transistor shown in FIG. 13(A) includes a semiconductor region 653a, a semiconductor region 653 b, a semiconductor region 653c, a gate insulating layer 654, a gate electrode 655, sidewall insulators 656a, sidewall insulators 656b, an insulating layer 657, a source electrode 658a, and a drain electrode 658b.

[0249] The semiconductor region 653c is sandwiched between the semiconductor regions 653a and 653b and provided therein. The semiconductor region 653c is an intrinsic semiconductor region that becomes a channel formation region.

[0250] The gate electrode 655 is provided on the gate insulating layer 654. Note that the width of the gate electrode 655 is 33 nm.

[0251] The sidewall insulators 656a and 656b are provided so as to be in contact with the side surfaces of the gate electrode 655. In the transistor shown in FIG. 13(A), the semiconductor under the sidewall insulator 656a The region is included in the N-type semiconductor region 653a, and the semiconductor region under the sidewall insulator 656b is included in the N-type semiconductor region 653b. Note that the width of each of the sidewall insulator 656a and the sidewall insulator 656 b is 5 nm.

[0252] The insulating layer 657 is provided on the gate electrode 655. The insulating layer 657 has a function of preventing a short circuit between the gate electrode 6 55 and other wirings.

[0253] The source electrode 658a is in contact with the semiconductor region 653a.

[0254] The drain electrode 658b is in contact with the semiconductor region 653b.

[0255] Note that the channel width in the transistor shown in Fig. 13(A) is 40 nm.

[0256] Also, the transistor shown in Fig. 13(B) has a different conductivity type of the semiconductor region under the sidewall insulator 656a and the sidewall insulator 656b compared with the transistor shown in Fig. 13(A). In the transistor shown in Fig. 13(B), the semiconductor region under the sidewall insulator 656a and the sidewall insulator 656b is included in the intrinsic semiconductor region 653c. That is, the transistor shown in Fig. 13(B) includes a region where the semiconductor region 653a and the gate electrode 655 do not overlap and a region where the semiconductor region 653c and the gate electrode 655 do not overlap. Each of these regions is called an offset region, and its width is called an offset length (also referred to as Loff). In Fig. 13(B), the offset length is the same as the width of each of the sidewall insulator 656a and the sidewall insulator 656b. is. region, and its width is called an offset length (also referred to as Loff). In Fig. 13(B), the offset length is the same as the width of each of the sidewall insulator 656a and the sidewall insulator 656b. is.

[0257] Note that other parameters used in the calculation are as described above. Also, for the calculation, the The device calculation software Sentaurus Device, manufactured by Synopsys, was used.

[0258] Figure 14 shows the drain current (Id, solid line) of the transistor with the structure shown in Fig. 13(A) and the figure showing the gate voltage (Vg, potential difference between the gate and the source) dependence of the mobility (μ, dotted line). The drain current Id was calculated with the drain voltage (potential difference between the drain and the source) set to +1V and the field-effect mobility μ was calculated with the drain voltage set to +0.1V.

[0259] Figure 14(A) is the figure for the case of a transistor with the thickness of the gate insulating layer 654 being 15nm and Fig. 14(B) is the figure for the case of a transistor with the thickness of the gate insulating layer 654 being 10nm and Fig. 14(C) is the figure for the case of a transistor with the thickness of the gate insulating layer 654 being 5nm As shown in Figs. 14(A) to 14(C), the thinner the gate insulating layer 654 is, especially the drain current Id (off-current) in the off state decreases significantly. On the other hand there is no noticeable change in the peak value of the field-effect mobility μ and the drain current Id (on-current) in the on state. Also, around the gate voltage of 1V, the value of the drain current exceeds 10 μA, which is required for a memory circuit etc.

[0260] Figure 15 shows the gate voltage Vg dependence of the drain current Id (solid line) and the mobility μ (dotted line) of a transistor with an offset length (Loff) of 5nm and the structure shown in Fig. 13(B). Here, the drain current Id was calculated with the drain voltage set to +1V, and the field-effect mobility μ was calculated with the drain voltage set to +0.1V. Further, Fig. 15(A) is the figure for the case where the thickness of the gate insulating layer 654 is 15nm, and Fig. 15(B) is the figure for the case where the gate insulating layer is... ... 654 is 15nm, and Fig. 15(B) is the figure for the case where the gate insulating layer It is a diagram when the thickness of 654 is 10 nm, and FIG. 15(C) shows the diagram when the thickness of the gate insulating layer 654 is 5 nm.

[0261] Also, FIG. 16 shows a transistor having the structure shown in FIG. 13(B), with an offset length Lof f of 15 nm, showing the gate voltage dependence of the drain current Id (solid line) and the mobility μ (dotted line). Here, the drain current Id is calculated with the drain voltage set to +1 V, and the mobility μ is calculated with the drain voltage set to +0.1 V. FIG. 16(A) is a diagram when the thickness of the gate insulating layer 65 4 is 15 nm, FIG. 16(B) is a diagram when the thickness of the gate insulating layer 654 is 10 nm, and FIG. 16(C) is a diagram when the thickness of the gate insulating layer 654 is 5 nm .

[0262] As can be seen from FIGS. 14 to 16, as the gate insulating layer 654 becomes thinner, the off-current of the transistor significantly decreases, while there is no significant change in the peak value of the mobility μ or the on-current of the transistor.

[0263] Note that the peak of the field-effect mobility μ is about 80 cm 2 / Vs in FIG. 14, but about 60 cm / Vs in FIG. 1 2 5 and about 40 cm 2 / Vs in FIG. 16. Therefore, it decreases as the offset length (Loff) increases. Also, the off-current of the transistor shows a similar tendency. On the other hand, the on-current of the transistor decreases as the offset length (Loff) increases, but is much gentler compared to the decrease in the off-current of the transistor. Also, in any transistor, around a gate voltage of 1 V, the drain current, for example, in a memory circuit ​​​​​exceeds 10 μA required in etc.

[0264] As described above, in a transistor including an oxide semiconductor, the field-effect mobility can be increased so that the memory circuit in the above embodiment can operate without problems .

[0265] Furthermore, as an example of the above transistor, an example of a transistor including an oxide semiconductor layer containing In, Sn, and Zn as a channel formation layer will be described.

[0266] For example, a transistor including an oxide semiconductor layer mainly composed of In, Sn, and Zn and a gate insulating layer with a thickness of 100 nm, having a channel length L of 3 μm and a channel width W of 10 μm is shown in FIGS. 17(A) to 17(C). Note that V is set to 10 V. d

[0267] FIG. 17(A) shows the characteristics of a transistor when an oxide semiconductor layer is formed by forming an oxide semiconductor film mainly composed of In, Sn, and Zn using a sputtering method without intentionally heating the element formation layer. In FIG. 17(A), the field-effect mobility is 18 .8 cm / Vsec. On the other hand, FIG. 17(B) shows the characteristics of a transistor when an oxide semiconductor layer is formed by forming an oxide semiconductor film mainly composed of In, 2 Sn, and Zn by heating the substrate to 200°C. In FIG. 17(B), the field-effect mobility is 32.2 c m / Vsec. Therefore, it can be seen that the field-effect mobility of the transistor is improved by intentionally heating. m 2

[0268] Also, FIG. 17(C) shows an oxide semiconductor film mainly composed of In, Sn, and Zn at 200 After forming an oxide semiconductor layer by film formation using a sputtering method at a temperature of ℃, the characteristics of the transistor when heat treatment is performed at 650℃ are shown in the figure. In Fig. 17(C), the field-effect mobility is 34.5 cm 2 / Vsec. Therefore, it can be seen that by performing heat treatment after forming the oxide semiconductor film, the above-mentioned field-effect mobility is increased.

[0269] In addition, oxygen ions may be implanted into an oxide semiconductor layer mainly composed of In, Sn, and Zn, and impurities such as hydrogen, water, hydroxyl groups, or hydrides contained in the oxide semiconductor are released by heat treatment, and the oxide semiconductor layer is crystallized by heat treatment simultaneously with or after the heat treatment. A non-single crystal oxide semiconductor layer with good crystallinity can be obtained by the above crystallization or recrystallization treatment.

[0270] In addition, a transistor including an oxide semiconductor layer mainly composed of In, Sn, and Zn formed without intentionally heating the device formation layer has a tendency for the threshold voltage to shift negatively, as shown in, for example, Fig. 17(A). However, when an oxide semiconductor layer formed by intentionally heating the device formation layer is used, the threshold voltage shifts in the direction in which the transistor becomes normally off, as shown in, for example, Fig. 17(B). Therefore, it can be seen that one or more of the heating during film formation of the oxide semiconductor film and the heat treatment after film formation make the transistor more likely to be normally off.

[0271] In addition, the threshold voltage of the transistor can also be controlled by changing the ratio of In, Sn, and Zn. For example, the composition ratio of the oxide semiconductor film is In:Sn:Zn = 2:1:3 By doing so, it becomes easier to make the transistor a normally-off type.

[0272] Furthermore, for example, under the conditions of applying 2 MV / cm, 150 °C, for 1 hour, when a gate bias stress test (also called BT test) is performed, the drift is less than ±1.5 V, preferably less than ±1.0 V. Therefore, by performing one or more of the heating during the formation of the oxide semiconductor film and the heating treatment after film formation, it can be seen that the stability against gate bias stress is high. Here, the results of the BT test in the transistors of sample 1 which has not been subjected to heat treatment after the formation of the oxide semiconductor film and sample 2 which has been subjected to heat treatment at 650 °C are shown in FIGS. 18 and 19. Note that as the BT test, a positive BT test and a negative BT test were performed. For the positive BT test, first, the temperature of the device formation layer (substrate) is set to 25 °C, and V

[0273] is set to 1 ds 0 V, and the V -I gs characteristics of the transistor are measured. Next, the temperature of the device formation layer (substrate) is set to 150 °C, and V ds is set to 0.1 V. Next, 20 V is applied to V so that the electric field strength applied to the gate insulating layer becomes 2 MV / cm, and it is held for 1 hour as it is. ds Next, V is set to 0 V. Next, the temperature of the device formation layer (substrate) is set to 25 °C, and V gs is set to 10 V, and the V gs -I ds characteristics of the transistor are measured.

[0274] gs ds

[0274] Also, for the negative BT test, first, the temperature of the device formation layer (substrate) is set to 25 °C, and V ds is set to 10 V, and the V gs -Ids The characteristics were measured. Next, the device formation (substrate) temperature was set to 150 °C, and V ds was set to 0.1 V. Next, an electric field strength applied to the gate insulating layer was set to -2 MV / cm by applying -20 V to V and held for 1 gs hour. Next, V was set to 0 V. Next, the device formation layer (substrate) temperature was set to 25 °C gs and V was set to 10 V, and the V ds -I gs of the transistor was measured. ds The results of the plus BT test of Sample 1 are shown in Fig. 18(A), and the results of the minus BT test of Sample 1 are shown in Fig. 18(B). Also, the results of the plus BT test of Sample 2 are shown in Fig. 19(A),

[0275] and the results of the minus BT test of Sample 2 are shown in Fig. 19(B). As shown in Fig. 18(A) and Fig. 18(B), the variations in the threshold voltage of the transistor due to the plus BT test and the minus BT test of Sample 1 were 1.80 V and -0.42 V, respectively. Also, as shown in Fig. 19(A) and Fig. 19(B), the variations in the threshold voltage of the transistor due to the plus BT test and the minus BT test of Sample 2 were 0.79 V and 0 .76 V, respectively. Therefore, it can be seen that in both Sample 1 and Sample 2, the variations in the threshold voltage of the transistor before and after the BT test were small, indicating high reliability.

[0276] As shown in Fig. 18(A) and Fig. 18(B), the variations in the threshold voltage of the transistor due to the plus BT test and the minus BT test of Sample 1 were 1.80 V and -0.42 V, respectively. Also, as shown in Fig. 19(A) and Fig. 19(B), the variations in the threshold voltage of the transistor due to the plus BT test and the minus BT test of Sample 2 were 0.79 V and 0 .76 V, respectively. Therefore, it can be seen that in both Sample 1 and Sample 2, the variations in the threshold voltage of the transistor before and after the BT test were small, indicating high reliability. Furthermore, an oxide semiconductor film formed by sputtering using a metal oxide target with a composition ratio of In:Sn:Zn = 1:1:1 without intentionally heating the device formation layer had a halo pattern observed by X-ray diffraction (XRD: X-Ray Diffraction). As shown in Fig. 19(A) and Fig. 19(B), the variations in the threshold voltage of the transistor due to the plus BT test and the minus BT test of Sample 2 were 0.79 V and 0 .76 V, respectively. Therefore, it can be seen that in both Sample 1 and Sample 2, the variations in the threshold voltage of the transistor before and after the BT test were small, indicating high reliability. Therefore, it can be seen that in both Sample 1 and Sample 2, the variations in the threshold voltage of the transistor before and after the BT test were small, indicating high reliability.

[0277] Furthermore, an oxide semiconductor film formed by sputtering using a metal oxide target with a composition ratio of In:Sn:Zn = 1:1:1 without intentionally heating the device formation layer had a halo pattern observed by X-ray diffraction (XRD: X-Ray Diffraction). Furthermore, an oxide semiconductor film formed by sputtering using a metal oxide target with a composition ratio of In:Sn:Zn = 1:1:1 without intentionally heating the device formation layer had a halo pattern observed by X-ray diffraction (XRD: X-Ray Diffraction). film had a halo pattern observed by X-ray diffraction (XRD: X-Ray Diffraction). It is measured. However, it can be crystallized by heat-treating the oxide semiconductor film. The heat-treatment temperature at this time is arbitrary. For example, by performing heat-treatment at 650 °C, clear diffraction peaks can be observed by X-ray diffraction.

[0278] Here, the results of the XRD analysis of the In-Sn-Zn-O film are shown below. In the XRD analysis, measurement was performed by the Out-of-Plane method using an X-ray diffractometer D8 ADVANCE manufactured by Bruker AXS.

[0279] As samples for which XRD analysis was performed, Sample A and Sample B were prepared. The manufacturing methods of Sample A and Sample B are described below.

[0280] An In-Sn-Zn-O film was formed with a thickness of 100 nm on a dehydrogenated quartz substrate.

[0281] The In-Sn-Zn-O film was formed using a sputtering apparatus with a power of 100 W (DC) in an oxygen atmosphere. As the target at this time, an In-Sn-Zn-O target with an atomic ratio of In:Sn:Zn = 1:1:1 was used. The heating temperature during film formation was 200 °C. The sample prepared by the above process is designated as Sample A.

[0282] Next, the sample prepared in the same manner as Sample A was heat-treated at a temperature of 650 °C. Here, heat-treatment was performed in a nitrogen atmosphere for 1 hour, and then further heat-treatment was performed in an oxygen atmosphere for 1 hour without lowering the temperature. The sample prepared by the above process is designated as Sample B.

[0283] The XRD spectra of Sample A and Sample B are shown in Fig. 20. In Sample A, peaks derived from crystals was not observed, but in Sample B, peaks derived from crystals were observed at around 2θ = 35 deg and 37 deg to 38 deg. Therefore, by performing one or more of heating during the formation of an oxide semiconductor film mainly composed of In, Sn, and Zn, and heat treatment after film formation, it can be seen that the crystallinity of the oxide semiconductor layer is improved.

[0284] By performing one or more of heating during the formation of the oxide semiconductor film and heat treatment after film formation, the off-current per 1 μm channel width of the fabricated transistor is, for example, as shown in FIG. 21, 1 aA (1 × 10 A) or less when the temperature of the element formation layer (substrate) is 125 °C, 100 zA (1 × 10 -1 8 A) or less when the temperature is 85 °C, and 1 zA (1 × 10 -19 A) or less at room temperature (27 °C). Also, the off-current per 1 μm channel width of the above transistor is preferably 0.1 aA (1 × 10 -21 A) or less at 125 °C, 10 zA (1 × 10 A) or less at 85 °C, and 0.1 zA -19 (1 × 10 -20 A) or less at room temperature. (1 × 10 -22 A) or less can also be achieved.

[0285] Note that although the oxide semiconductor film mainly composed of In, Sn, and Zn can remove hydrogen in the film by heat treatment, since the water release temperature is higher than that of the oxide semiconductor film mainly composed of In, Ga, and Zn, it is preferable to form a film that is preferably free of impurities from the beginning.

[0286] Furthermore, for the transistor of Sample B that was heat-treated at 650 °C after the formation of the oxide semiconductor film, The relationship between the temperature of the element formation layer (substrate) and the electrical characteristics was evaluated.

[0287] The transistor used for measurement had a channel length L of 3 μm, a channel width W of 10 μm, and Lo v of 3 μm on one side (total 6 μm) and dW of 0 μm. Note that V ds was set to 1 0 V. Also, the evaluation was performed under six conditions where the temperature of the element formation layer (substrate) was -40°C, -25°C, 25°C, 75 °C, 125°C, and 150°C. Note that Lov refers to the overlapping width between the gate electrode and the pair of electrodes, and dW refers to the overhang of the pair of electrodes with respect to the oxide semiconductor film.

[0288] Fig. 22 shows the V ds (solid line) and the field-effect mobility (dotted line) dependencies. Also, gs Fig. 23(A) shows the relationship between the temperature of the element formation layer (substrate) and the threshold voltage, and Fig. 23(B) shows the relationship between the temperature of the element formation layer (substrate) and the field-effect mobility.

[0289] From Fig. 22 and Fig. 23(A), it can be seen that the higher the temperature of the element formation layer (substrate), the lower the threshold voltage. The range was 1.09 V to -0.23 V at -40°C to 150°C.

[0290] Also, from Fig. 22 and Fig. 23(B), it can be seen that the higher the temperature of the element formation layer (substrate), the lower the field-effect mobility. The range was 36 cm 2 / V s to 32 cm 2 / Vs at -40°C to 150°C. Therefore, it can be seen that the variation in electrical characteristics is small within the above temperature range.

[0291] The above is the description of a transistor including an oxide semiconductor layer containing In, Sn, and Zn.

[0292] In the transistor including the oxide semiconductor layer containing In, Sn, and Zn as main components, while keeping the off-current at 1 aA / μm or less, the field-effect mobility is 30 cm / Vsec or more, preferably 2 40 cm / Vsec or more, more preferably 60 cm 2 / Vsec or more, and it can satisfy the value of the on-current required by L 2 SI. For example, in a transistor with L / W = 33 nm / 40 nm, when the gate voltage is 2.7 V and the drain voltage is 1.0 V, an on-current of 12 μA or more can flow. Also, sufficient electrical characteristics can be ensured even in the temperature range required for the operation of the transistor. With such characteristics, even if a transistor including the oxide semiconductor layer is mixed in a circuit using a transistor including a semiconductor layer containing a Group 14 semiconductor (such as silicon), a circuit having a new function can be provided without sacrificing the operation speed. This embodiment can be implemented in appropriate combination with other embodiments.

[0293]

[0294] This embodiment can be implemented in appropriate combination with other embodiments.

[0294] (Embodiment 7) In this embodiment, as an example of a semiconductor device, an arithmetic processing device such as a CPU will be described.

[0295] FIG. 24 shows an example of an arithmetic processing device.

[0296] The arithmetic processing device in FIG. 24 includes a bus interface (also referred to as IF) 801, a control device (also referred to as CTL) 802, a cache memory (also referred to as CACHE) 803, and instructions​ It has a decoder (also referred to as IDecoder) 805 and a processing circuit 806.

[0297] The bus interface 801 has a function of performing signal exchanges with the outside and with each circuit within the arithmetic processing unit. etc.

[0298] The control device 802 has a function of controlling the operations of each circuit within the arithmetic processing unit.

[0299] The cache memory 803 is controlled by the control device 802 and has a function of temporarily holding data during the operation of the arithmetic processing unit. Note that, for example, multiple cache memories 803 may be provided in the arithmetic processing unit as a primary cache and a secondary cache. etc. The instruction decoder 805 has a function of translating the read instruction signal. The translated instruction signal is input to the control device 802, and the control device 802 outputs a control signal corresponding to the instruction signal to the processing circuit 806.

[0300] The processing circuit 806 is controlled by the control device 802 and has a function of performing arithmetic processing according to the input instruction signal. The processing circuit 806 is a part having an ALU etc., and the logic circuit unit 101 and the storage circuit 103 in FIGS. 1 to 6 can be provided. etc. The processing circuit 806 is controlled by the control device 802 and has a function of performing arithmetic processing according to the input instruction signal. The processing circuit 806 is a part having an ALU etc., and the logic circuit unit 101 and the storage circuit 103 in FIGS. 1 to 6 can be provided.

[0301] The processing circuit 806 is controlled by the control device 802 and has a function of performing arithmetic processing according to the input instruction signal. The processing circuit 806 is a part having an ALU etc., and the logic circuit unit 101 and the storage circuit 103 in FIGS. 1 to 6 can be provided. etc. Note that registers etc. may be provided as memories in the arithmetic processing unit. At this time, the memory is controlled by the control device 802. For example, multiple memories may be provided in the arithmetic processing unit, with one memory being used as the memory for the processing circuit 806 and another memory being used as the register for the instruction decoder 805.

[0302] Note that registers etc. may be provided as memories in the arithmetic processing unit. At this time, the memory is controlled by the control device 802. For example, multiple memories may be provided in the arithmetic processing unit, with one memory being used as the memory for the processing circuit 806 and another memory being used as the register for the instruction decoder 805. etc. Note that registers etc. may be provided as memories in the arithmetic processing unit. At this time, the memory is controlled by the control device 802. For example, multiple memories may be provided in the arithmetic processing unit, with one memory being used as the memory for the processing circuit 806 and another memory being used as the register for the instruction decoder 805. etc.

[0303] Further, a storage circuit 103 shown in FIGS. 1 to 6 may be provided in the control device 802 and the instruction decoder 805. By doing so, in the control device 802 and the instruction decoder 805, data input to the transistors of the integrated circuit can be stored in the storage circuit, and data retention, high-speed operation, and power consumption reduction can be achieved.

[0304] This embodiment can be implemented in appropriate combination with other embodiments.

[0305] (Embodiment 8) In this embodiment, an example of an electronic device including the arithmetic processing device in Embodiment 7 above will be described.

[0306] An example of the electronic device in this embodiment will be described with reference to FIGS. 25(A) to 25(D).

[0307] The electronic device shown in FIG. 25(A) is an example of a portable information terminal. The information terminal shown in FIG. 25(A) includes a housing 1001a and a display unit 1002a provided on the housing 1001a.

[0308] Note that connection terminals for connecting to an external device may be provided on the side surface 1003a of the housing 1001a, and one or more buttons for operating the portable information terminal shown in FIG. 25(A) may be provided.

[0309] The portable information terminal shown in FIG. 25(A) includes a CPU, a memory, an interface for transmitting and receiving signals between the external device and the CPU and the memory, and an antenna for transmitting and receiving signals to and from the external device inside the housing 1001a.

[0310] The portable information terminal shown in Fig. 25(A) has functions as, for example, one or more of a telephone, an e-book, a personal computer, and a gaming machine.

[0311] The electronic device shown in Fig. 25(B) is an example of a foldable portable information terminal. The portable information terminal shown in Fig. 25(B) includes a housing 1001b, a display unit 1002b provided on the housing 1001b, a housing 1004, a display unit 1005 provided on the housing 1004, and a shaft portion 1006 that connects the housing 1001 b and the housing 1004.

[0312] Further, in the portable information terminal shown in Fig. 25(B), by moving the housing 1001b or the housing 1004 by the shaft portion 1006, the housing 1001b can be superimposed on the housing 1004.

[0313] Note that connection terminals for connecting to an external device may be provided on the side surface 1003b of the housing 1001b or the side surface 1007 of the housing 1004, and one or more buttons for operating the portable information terminal shown in Fig. 25(B) may be provided.

[0314] Further, different images or a continuous image may be displayed on the display unit 1002b and the display unit 1005. Note that the display unit 1005 is not necessarily provided, and a keyboard, which is an input device, may be provided instead of the display unit 1005.

[0315] The portable information terminal shown in Fig. 25(B) includes a CPU, a memory, and an interface that transmits and receives signals between an external device and the CPU and the memory inside the housing 1001b or the housing 1004. Note that an antenna for transmitting and receiving signals to and from the outside may be provided in the portable information terminal shown in Fig. 25(B). ​

[0316] The portable information terminal shown in Fig. 25(B) has functions as, for example, one or more of a telephone, an e-book, a personal computer, and a gaming machine. and a gaming machine.

[0317] The electronic device shown in Fig. 25(C) is an example of an installation-type information terminal. The installation-type information terminal shown in Fig. 25(C) includes a housing 1001c and a display unit 1002c provided on the housing 1001c. The installation-type information terminal shown in Fig. 25(C) includes a housing 1001c and a display unit 1002c provided on the housing 1001c. comprises.

[0318] Note that the display unit 1002c can also be provided on the deck portion 1008 of the housing 1001c. be possible.

[0319] Also, the installation-type information terminal shown in Fig. 25(C) includes a CPU, a memory, and an interface for transmitting and receiving signals between an external device and the CPU and the memory inside the housing 1001c. Note that an antenna for transmitting and receiving signals to and from the outside may be provided on the installation-type information terminal shown in Fig. 25(C). and an interface for transmitting and receiving signals between an external device and the CPU and the memory, inside the housing 1001c. Note that an antenna for transmitting and receiving signals to and from the outside may be provided on the installation-type information terminal shown in Fig. 25(C). may be provided.

[0320] Furthermore, one or more of a ticket output unit for outputting tickets, a coin insertion unit, and a bill insertion unit may be provided on the side surface 1003c of the housing 1001c of the installation-type information terminal shown in Fig. 25(C). for outputting tickets, a coin insertion unit, and a bill insertion unit may be provided on the side surface 1003c of the housing 1001c of the installation-type information terminal shown in Fig. 25(C). may be provided.

[0321] The installation-type information terminal shown in Fig. 25(C) has functions as, for example, a cash dispenser, an information communication terminal (also referred to as a multimedia station) for ordering tickets, etc., or a gaming machine. or a gaming machine. functions.

[0322] Fig. 25(D) is an example of an installation-type information terminal. The installation-type information terminal shown in Fig. 25(D) includes a housing 1001d and a display unit 1002d provided on the housing 1001d. Note The installation-type information terminal shown in Fig. 25(D) includes a housing 1001d and a display unit 1002d provided on the housing 1001d. , a support base for supporting the housing 1001d may be provided.

[0323] In addition, connection terminals for connecting to external devices may be provided on the side surface 1003d of the housing 1001d, and one or more buttons for operating the installation-type information terminal shown in FIG. 25(D) may be provided. Yes.

[0324] Also, the installation-type information terminal shown in FIG. 25(D) may include, inside the housing 1001d, a CPU, a memory, and an interface for transmitting and receiving signals between the external device and the CPU and the memory. In addition, an antenna for transmitting and receiving signals to and from the outside may be provided on the installation-type information terminal shown in FIG. 25(D). It may be provided.

[0325] The installation-type information terminal shown in FIG. 25(D) has functions as, for example, a digital photo frame, a monitor, or a television device. It has functions as, for example, a digital photo frame, a monitor, or a television device.

[0326] The arithmetic processing unit of the above embodiment is used as the CPU of the electronic devices shown in FIGS. 25(A) to 25(D). It is used as the CPU of the electronic devices shown in FIGS. 25(A) to 25(D).

[0327] As described with reference to FIG. 25, an example of the electronic device in the present embodiment has a configuration including the arithmetic processing unit in the above embodiment as the CPU. It has a configuration including the arithmetic processing unit in the above embodiment as the CPU.

[0328] In addition, in an example of the electronic device in the present embodiment, by using the storage circuit and the logic circuit in the above embodiment, it is possible to suppress the power consumption of the arithmetic processing unit while holding data for a long time. Also, by using the storage circuit and the logic circuit in the above embodiment, the area of the arithmetic processing unit can be reduced. By using the storage circuit and the logic circuit in the above embodiment, it is possible to suppress the power consumption of the arithmetic processing unit while holding data for a long time. Also, by using the storage circuit and the logic circuit in the above embodiment, the area of the arithmetic processing unit can be reduced. By using the storage circuit and the logic circuit in the above embodiment, the area of the arithmetic processing unit can be reduced.

[0329] This embodiment can be implemented in appropriate combination with other embodiments.

Explanation of Signs

[0330] 101 Logic circuit section 101a Logic circuit section 101b Logic circuit section 103 Memory circuit 105 Logic circuit 107 Transistor 109 Capacitive element 111 Transistor 121 Transistor 123 Transistor 131 Single-crystalline silicon layer 133 Gate insulating layer 135 Gate electrode 137 Oxide semiconductor layer 139 Gate insulating layer 141 Gate electrode 143 Electrode 145 Electrode 147 Insulating layer 149 Electrode 201 Adder 203 AND circuit 205 Selection circuit 207 Transistor 209 Transistor 211 Inverter 301 Arithmetic operation section 303 Logic operation section 305 Shift operation section 307 Selection circuit 309 Selection circuit 311 Selection circuit 401 Transistor 403 Inverter 405 Transistor 407 Capacitive element 409 Inverter 501 Connection section 503 Wiring 505 Memory 507 Selection circuit 600 Base element formation layer 601 Conductive layer 602 Insulating layer 603 Semiconductor layer 604a Region 604b Region 605a Conductive layer 605b Conductive layer 606a Insulating layer 606b Insulating layer 607 Insulating layer 651 Underlying insulator 652 Embedded insulator 653a Semiconductor region 653b Semiconductor region 653c Semiconductor region 654 Gate insulating layer 655 Gate electrode 656a Sidewall insulator 656b Sidewall insulator 657 Insulating layer 658a Source electrode 658b Drain electrode 801 Bus interface 802 Control device 803 Cache memory 805 Instruction decoder 806 Processing circuit 1001a Housing 1001b Housing 1001c Housing 1001d Housing 1002a Display unit 1002b Display unit 1002c Display unit 1002d Display unit 1003a Side surface 1003b Side surface 1003c Side surface 1003d Side surface 1004 Housing 1005 Display unit 1006 Shaft part 1007 Side surface 1008 Deck part

Claims

【Claim 1】 A semiconductor device having a plurality of arithmetic circuits, a selection circuit, and a memory circuit, wherein the memory circuit includes a transistor and a capacitive element, the memory circuit inputs data to the capacitive element and the selection circuit via the transistor, the selection circuit selects one or more of the arithmetic results of the plurality of arithmetic circuits according to the data, and an oxide semiconductor is used for a channel formation region of the transistor.

Images