Glitch elimination circuit

Abstract

To accurately remove glitches even when glitches are input consecutively.SOLUTION: A glitch elimination circuit includes: a first glitch elimination circuit that includes a first delay element, delays an input signal using the first delay element to generate a first delay signal, and outputs a logical OR signal of the input signal and the first delay signal; a clock generation circuit that generates a clock signal having a period sufficiently long relative to the glitch width of a glitch; a multi-stage flip-flop circuit that latches an output signal of the first glitch elimination circuit at the timing of the clock signal to output a first latch signal, and further latches the first latch signal at the timing of the clock signal to output a second latch signal; and a second glitch elimination circuit that includes a second delay element, delays the second latch signal using the second delay element to generate a second delay signal, and outputs a logical OR signal of the second latch signal and the second delay signal.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a glitch removal circuit. relates to.

Background Art

[0002] There is known an illegal act (FI attack (Fault Injection)) of applying glitch noise from the outside to an LSI holding secret information to extract the information. When a continuous minute pulse is injected from an ESD gun or the like to the reset terminal of the LSI, due to the delay difference to the reset terminals of flip-flop circuits arranged in large numbers inside the LSI, there may occur an event that a certain flip-flop circuit is reset while another flip-flop circuit is not reset. Such an event is a reset abnormal state, and when software control is executed, there is a possibility that secret information may leak to the outside, for example, by skipping a security check program. For this reason, a glitch removal circuit for removing glitches related to such FI attacks has been proposed.

[0003] However, the conventional glitch removal circuit has a problem that there is still a high possibility of causing a reset abnormal state of the flip-flop circuit when glitches are continuously input.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In view of the above problems, the present invention provides a glitch removal circuit that can accurately remove glitches even when glitches are continuously input.

Means for Solving the Problem

[0006] The grid removal circuit according to the present invention includes a first delay element that delays an input signal by the first delay element to generate a first delayed signal, and outputs a logical sum signal of the input signal and the first delayed signal; a clock generation circuit that generates a clock signal having a period sufficiently long with respect to the grid width of the grid; a multi-stage flip-flop circuit that latches the output signal of the first grid removal circuit at the timing of the clock signal to output a first latch signal, and further latches the first latch signal at the timing of the clock signal to output a second latch signal; and a second grid removal circuit that includes a second delay element, delays the second latch signal by the second delay element to generate a second delayed signal, and outputs a logical sum signal of the second latch signal and the second delayed signal.

Advantages of the Invention

[0007] According to the present invention, it is possible to provide a grid removal circuit that can accurately remove grids even when grids are continuously input.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Embodiments for Carrying Out the Invention

[0009] Hereinafter, this embodiment will be described with reference to the accompanying drawings. In the accompanying drawings, elements having the same function may sometimes be denoted by the same reference numeral. Although the accompanying drawings show embodiments and implementation examples in accordance with the principles of the present disclosure, these are for the purpose of understanding the present disclosure and are in no way used for limiting the interpretation of the present disclosure. The description in this specification is merely a typical example and does not limit the claims or application examples of the present disclosure in any sense.

[0010] In this embodiment, although the description is made in sufficient detail for those skilled in the art to implement the present disclosure, other implementations and forms are also possible, and it is necessary to understand that changes in configuration and structure and replacement of various elements can be made without departing from the scope and spirit of the technical idea of the present disclosure. Therefore, the following description should not be construed as being limited thereto.

[0011] First, referring to FIG. 4, a conventional grid removal circuit 1' as a comparative example will be described. This grid removal circuit 1' is composed of a first delay element 11 and an OR circuit 12. The delay element 11 delays the input signal IN and outputs a delayed signal A. The OR circuit 12 outputs an output signal OUT which is the logical sum signal of the input signal IN and the delayed signal A.

[0012] Next, the operation of the grid removal circuit in FIG. 4 will be described. As shown by reference symbol T1, when a single grid (single-grid input pattern) is input as the input signal IN, in the delayed signal A, a single grid appears with a predetermined delay amount. Due to this delay, in the logical sum signal OUT of the input signal IN and the delayed signal A, this grid is removed.

[0013] However, as shown by reference symbol T2, when continuous grids (continuous-grid input pattern) are input as the input signal IN, the grids cannot be completely removed by delay and logical sum operations, and grids remain in the output signal OUT. The grid removal circuit 1 of the present embodiment can effectively remove such continuous grids.

[0014] Referring to FIG. 1, the grid removal circuit 1 according to an embodiment of the present invention will be described. As shown in FIG. 1, this grid removal circuit 1 includes a first delay element 11, an OR circuit 12, a first flip-flop circuit 13 (D flip-flop circuit), a second flip-flop circuit 14 (D flip-flop circuit), a second delay element 15, an OR circuit 16, and an oscillator (oscillation circuit) 17.

[0015] The first delay element 11 delays the input signal IN and outputs a delayed signal A. The OR circuit 12 outputs a logical sum signal B of the input signal IN and the delayed signal A. The first delay element 11 and the OR circuit 12 constitute a first grid removal circuit.

[0016] The first flip-flop circuit 13 and the second flip-flop circuit 14 are connected in series. The first flip-flop circuit 13 receives the logical sum signal B and latches the input signal at the rising timing of the clock signal CLK to output a signal Q1. The second flip-flop circuit 14 receives the signal Q1 and latches the input signal at the rising timing of the clock signal CLK to output a signal Q2. The first flip-flop circuit 13 and the second flip-flop circuit 14 are provided as a metastability countermeasure to synchronize the asynchronous signal input from the logical sum signal B. The period of the clock signal CLK generated by the oscillator 17 is set to be sufficiently long (for example, 10 times or more) with respect to the grid width of the assumed grid. For example, when the grid width is assumed to be several nS, it can be set to several tens of nS, which is 10 times that. Note that the initial values of the flip-flop circuits 13 and 14 are initialized to Low by the logical sum signal B. In the illustrated example, two-stage flip-flop circuits 13 and 14 are provided, but it is also possible to provide three or more stages of flip-flop circuits.

[0017] Further downstream of the second flip-flop circuit 14, a second delay element 15 and an OR circuit 16 are provided. The second delay element 15 and the OR circuit 16 constitute a second grid removal circuit. The second delay element 15 delays the signal Q2 and outputs a delayed signal C. The OR circuit 16 outputs an output signal OUT as the logical sum signal of the delayed signal C and the signal Q2. The output signal OUT is input to the reset terminal of a flip-flop circuit in an electronic circuit (not shown).

[0018] Next, with reference to the timing chart of FIG. 2, the operation of the grid removal circuit 1 of FIG. 1 will be described. Similar to what was described in FIG. 5, when a continuous grid (grid continuous input pattern) is input as the input signal IN, the grid may not be completely removed by the delay and logical sum operations, and the grid may remain in the logical sum signal B.

[0019] The logical sum signal B with the grid remaining is input to the first flip-flop circuit 13. However, since the first flip-flop circuit 13 latches the input signal at the timing of the rising edge of the clock signal CLK, if the clock edge does not occur during the Low period of the logical sum signal B, the first flip-flop circuit 13 does not capture the Low signal. (α in FIG. 2). If the Low period of the logical sum signal B happens to occur at the rising edge of the clock signal CLK with good timing, the first flip-flop circuit 13 may capture the Low signal. (β in FIG. 2).

[0020] Since the clock signal CLK has a period that is sufficiently long compared to the pulse width of the grid, the output signal Q1 of the first flip-flop circuit 13 becomes a signal with an extended Low period compared to the logical sum signal B. The output signal Q1 is captured by the second flip-flop circuit 14 at the rising edge of the next clock signal CLK. This is a measure in case a metastable state occurs.

[0021] Since the output signal B of the OR circuit 12 is input to the asynchronous reset terminals of the first flip-flop circuit 13 and the second flip-flop circuit 14, if the first flip-flop circuit 13 misses a Low glitch, a metastable state may occur in the flip-flop circuits 13 and 14 depending on the rising edge of the clock signal CLK and the timing of the asynchronous reset (see Fig. 3).

[0022] To avoid this metastable state, a glitch removal circuit composed of the subsequent second delay element 15 and OR circuit 16 can remove the glitch of the metastable state. Although the metastable state depends on the process, it recovers in several ns to several tens of ns. Therefore, by adjusting the delay amount of the second delay element 15 to a value with sufficient margin, such as several times the expected length of the metastable state, the glitch can be removed.

[0023] As described above, according to the present embodiment, even when a continuous glitch is input and cannot be removed, a normal reset signal can be generated, thus preventing the reset abnormal state of the flip-flop circuit.

[0024] The present invention is not limited to the above-described embodiments and includes various modifications. For example, the above-described embodiments have been described in detail for easy understanding of the present invention and are not necessarily limited to those having all the configurations described. Also, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. Further, for a part of the configuration of each embodiment, addition, deletion, or replacement with other configurations is possible.

Description of Reference Numerals

[0025] 1, 1´... Glitch removal circuit 11... First delay element 12, 16... OR circuit 13... First flip-flop circuit 14... Second flip-flop circuit 15…Second delay element 17…Oscillator (oscillation circuit)

Claims

1. A first grid removal circuit that includes a first delay element, delays an input signal by the first delay element to generate a first delayed signal, and outputs a logical sum signal of the input signal and the first delayed signal; A clock generation circuit that generates a clock signal having a period sufficiently long with respect to the grid width of the grid; A multi-stage flip-flop circuit that latches the output signal of the first grid removal circuit at the timing of the clock signal to output a first latch signal, and further latches the first latch signal at the timing of the clock signal to output a second latch signal; A second grid removal circuit that includes a second delay element, delays the second latch signal by the second delay element to generate a second delayed signal, and outputs a logical sum signal of the second latch signal and the second delayed signal A grid removal circuit characterized by comprising the above.

2. The grid removal circuit according to claim 1, wherein the delay amount by the second delay element is a time sufficiently longer than the duration of the metastable state generated in the flip-flop circuit.

3. The grid removal circuit according to claim 1, wherein the output signal of the first grid removal circuit is input to the asynchronous reset terminal of the flip-flop circuit.

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