Memory structure of memory device and control method

Abstract

To provide a memory structure capable of reducing a circuit area without arranging a capacitance in order to store data.SOLUTION: A memory structure 100 contains a plurality of first transistors T1 and a plurality of second transistors T2 that are arranged onto a substrate SUB. The first transistors are arranged to a first array, and first ends of the first transistors are respectively coupled to a plurality of first bit lines WBL, and gates of the first transistors are respectively coupled to a plurality of first word lines WWL. The second transistors are arranged to a second array, and gates of the second transistors are respectively coupled to second ends of the first transistors. Second ends and first ends of the second transistors are respectively coupled to second bit lines RBL and second word lines RWL. The first word lines or the first bit lines are extended along a normal direction of a flat surface of the substrate, and the second word lines or the bit lines are extended along the normal direction.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a memory structure and a control method of a memory device, and particularly to a memory structure of a dynamic random access memory and a control method of a memory device.

Background Art

[0002] In the conventional technical field, the memory cells of a dynamic random access memory are often configured by using a 1T1C architecture. In this technology, when adjusting the circuit scale of the memory cell, the complexity of the process for forming the capacitance causes a major obstacle. When the size of the memory decreases, the ratio of the area of the capacitance increases significantly.

[0003] By configuring a dynamic random access memory by three-dimensional stacking, the memory capacity of the dynamic random access memory can be effectively increased. However, in the conventional 1T1C architecture, since the capacitance occupies a large circuit area in the three-dimensional stacked structure, the manufacturing cost of the memory increases.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present disclosure provides a memory structure that does not require arranging a capacitance for storing data and can effectively reduce the circuit area.

Means for Solving the Problems

[0005] The memory structure according to the present disclosure includes a plurality of first transistors and a plurality of second transistors. The first transistors are arranged in a first array. A first end of the first transistor is respectively coupled to a plurality of first bit lines, and a gate of the first transistor is respectively coupled to a plurality of first word lines. The second transistors are arranged in a second array. A gate of the second transistor is respectively coupled to a second end of the first transistor, a second end of the second transistor is respectively coupled to a second bit line, and a first end of the second transistor is respectively coupled to a second word line. The first transistors and the second transistors are arranged on a substrate. One of each of the first word lines and each of the first bit lines extends along a normal direction of the plane of the substrate, and one of each of the second word lines and each of the second bit lines extends along the normal direction.

[0006] A method for controlling a memory device includes arranging a plurality of first transistors arranged in a first array, wherein a first end of the first transistor is respectively coupled to a plurality of first bit lines, and a gate of the first transistor is respectively coupled to a plurality of first word lines; arranging a plurality of second transistors arranged in a second array, wherein a gate of the second transistor is respectively coupled to a second end of the first transistor, a second end of the second transistor is respectively coupled to a plurality of second bit lines, and a first end of the second transistor is respectively coupled to a plurality of second word lines; extending one of each of the first word lines and each of the first bit lines along a normal direction of the plane of the substrate to provide a first signal; and extending one of each of the second word lines and each of the second bit lines along a normal direction of the plane of the substrate to provide a second signal.

Advantages of the Invention

[0007] Based on the above, in the memory structure according to the present disclosure, a memory cell includes a first transistor and a second transistor. The combined end portions of the first transistor and the second transistor can be used as a data storage node. In this way, the memory cell can be used to perform dynamic random access to the memory cell, and the memory cell can effectively reduce the layout area of the circuit without providing a storage capacitance.

Brief Description of the Drawings

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Figure 1

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Mode for Carrying Out the Invention

[0017] Please refer to FIG. 1. FIG. 1 is a schematic three-dimensional structure diagram of a memory structure according to an embodiment of the present invention. The memory structure 100 is arranged on the plane of the substrate SUB. The plane of the substrate SUB is formed on the X-Y axis plane and has the same normal direction as the Z axis. The memory structure 100 includes a plurality of first transistors T1 and a plurality of second transistors T2. The first transistor T1 is arranged in a first array in the form of N×M, and the second transistor T2 is arranged in a second array in the form of N×M. In this embodiment, both N and M can be equal to 4. In other embodiments of the present disclosure, N and M may be any other positive integers.

[0018] In this embodiment, the first array has a plurality of channel pillars 110 and a plurality of conductive structures WWL1 to WWL4. The channel pillars 110 are arranged in a 4×4 form. Taking the case where the X-axis direction is the row direction and the Z-axis direction is the column direction as an example, each of the conductive structures WWL1 to WWL4 can extend along the row direction, and the conductive structures WWL1 to WWL4 can be arranged vertically along the column direction. The conductive structures WWL1 to WWL4 respectively surround the channel pillars 110 arranged in the same row. In this embodiment, each of the conductive structures WWL1 to WWL4 surrounds four channel pillars 110 and can form a common gate line and word line of four first transistors T1 corresponding to the four surrounded channel pillars 110. Taking the conductive structure WWL1 as an example, a gate oxide layer GOX can be provided between the conductive structure WWL1 and the surrounded channel pillar 110.

[0019] Also, in the present embodiment, the first end of the channel pillar 110 can be coupled to the second transistor T2, and the second end of the channel pillar 110 can be coupled to the bit lines WBL1 to WBL4 respectively formed by the conductive structure. In the present embodiment, each of the bit lines WBL1 to WBL4 extends along the Z-axis and can be coupled to the second ends of a plurality of channel pillars 110 arranged in the same column. The bit lines WBL1 to WBL4 can be arranged continuously along the X-axis direction. In the present embodiment, the extending direction of each of the bit lines WBL1 to WBL4 can be substantially orthogonal to the extending direction of each of the conductive structures WWL1 to WWL4 forming the word lines. It is worth noting that the extending directions of each of the bit lines WBL1 to WBL4 and each of the conductive structures WWL1 to WWL4 may not be exactly orthogonal to each other due to tolerances resulting from the manufacturing process, and thus form a substantially orthogonal state.

[0020] On the other hand, the second array has a plurality of gate structures, a plurality of conductive structures 120, and RWL1 to RWL4. In the present embodiment, the channel pillar 110 extends into the second array along the Y-axis and can form a corresponding gate structure. That is, each channel pillar 110 and each corresponding gate structure can be of the same structure. In the present embodiment, based on the fact that the channel pillars 110 are arranged in a 4×4 form, the gate structures are also arranged in a 4×4 form. The plurality of conductive structures 120 respectively correspond to the gate structures and extend along the Y-axis direction so as to surround the corresponding gate structures respectively, forming the gates of the plurality of second transistors T2. Similarly, a gate oxide layer (not shown) can be provided between each of the conductive structures 120 and each of the surrounded gate structures.

[0021] Also, each of the conductive structures RWL1 to RWL4 extends along the X-axis direction. The conductive structures RWL1 to RWL4 are vertically arranged along the Z-axis direction. Each of the conductive structures RWL1 to RWL4 covers four conductive structures 120 arranged in the same row and forms a common word line for a plurality of second transistors T2 arranged in the same row. Each of the bit lines RBL1 to RBL4 extends along the Z-axis direction and can be coupled to one end of a plurality of conductive structures 120 arranged in the same column. The bit lines RBL1 to RBL4 are arranged along the Z-axis direction.

[0022] It is worth mentioning that in this embodiment, on the conductive structure 120, a channel (for example, the channel CH between the conductive structure RWL4 and the bit line RBL1) can be formed between each of the conductive structures RWL1 to RWL4 and each of the bit lines RBL1 to RBL4.

[0023] In this embodiment, the extending direction of each of the bit lines RBL1 to RBL4 can be substantially orthogonal to the extending direction of each of the conductive structures RWL1 to RWL4 that form the word line. It is worth noting that the extending directions of each of the bit lines RBL1 to RBL4 and each of the conductive structures RWL1 to RWL4 may not be exactly orthogonal to each other due to tolerances resulting from the manufacturing process, and thus form a substantially orthogonal state.

[0024] Also, in this embodiment, based on manufacturing tolerances, the extending directions of the conductive structures WWL1 to WWL4 and the conductive structures RWL1 to RWL4 are substantially the same. Also, the extending directions of the bit lines WBL1 to WBL4 and the bit lines RBL1 to RBL4 are substantially the same.

[0025] It is worth mentioning that in this embodiment, the material of the channel pillar 110 can be silicon, gallium arsenide, silicon carbide, or other suitable semiconductor channel materials, and the conductive structures 120, WWL1 to WWL4, and RWL1 to RWL4 can be any conductive structures in the semiconductor manufacturing process, and the present disclosure is not limited thereto. The first transistor T1 of this embodiment can be a gate-all-around (GAA) transistor, and the second transistor T2 can be a channel-all-around (CAA) transistor.

[0026] In the following description, please refer to FIG. 2. FIG. 2 is an equivalent circuit diagram of a memory cell in a memory structure according to an embodiment of the present invention. The memory cell 200 includes a first transistor T1 and a second transistor T2. The first end of the first transistor T1 is coupled to the bit line WBL, the second end of the first transistor T1 is coupled to the data storage node SN, and the gate of the first transistor T1 is coupled to the word line formed by the conductive structure WWL. The first end of the second transistor T2 is coupled to the bit line RBL, the second end of the second transistor T2 is coupled to the word line formed by the conductive structure RWL, and the gate of the second transistor T2 is coupled to the data storage node SN.

[0027] In the data writing mode, the first transistor T1 can be turned on according to the control signal transmitted by the conductive structure WWL. The first end of the first transistor T1 receives the write data through the bit line WBL, and the write data can be written into the data storage node SN through the turned-on first transistor T1.

[0028] In the data read mode, the first transistor T1 can be turned off. The second end of the second transistor T2 can receive a selected voltage for starting a read operation via the conductive structure RWL. At the same time, based on the data stored in the data storage node SN, the second transistor T2 can be turned on or off. For example, if the data stored in the data storage node SN is a high logic value, the second transistor T2 can be turned on. In this way, the second transistor T2 can supply a corresponding read current to the bit line RBL. By arranging a sense amplifier to sense the read current, it can be known that the data stored in the data storage node SN is a high logic value. Conversely, taking the case where the data stored in the data storage node SN is a low logic value as an example, the second transistor T2 can be turned off. As a result, the corresponding read current supplied onto the bit line RBL by the second transistor T2 is substantially equal to 0. The sense amplifier can know that the data stored in the data storage node SN is a low logic value by sensing a read current that is substantially equal to 0.

[0029] Please refer to FIG. 3. FIG. 3 is a schematic circuit diagram of a memory cell array formed by the memory structure of FIG. 1 according to an embodiment of the present invention. The memory cell array 300 has a plurality of memory cell slices 301 to 30n. Each of the memory cell slices 301 to 30n includes a memory cell array including a plurality of memory cells MC (only one is typically shown in the figure), and each memory cell MC includes a first transistor T1 and a second transistor T2. The memory cell slice 301 has a plurality of bit lines WBL_00 to WBL_0n extending along the Z axis and a plurality of bit lines RBL_00 to RBL_0n extending along the Z axis. The bit lines WBL_00 to WBL_0n are connected to the first transistor T1, and the bit lines RBL_00 to RBL_0n are connected to the second transistor T2. Similarly, the memory cell slice 30n has a plurality of bit lines WBL_n0 to WBL_nn extending along the Z axis and a plurality of bit lines RBL_n0 to RBL_nn extending along the Z axis. The bit lines WBL_n0 to WBL_nn are connected to the first transistor T1, and the bit lines RBL_n0 to RBL_nn are connected to the second transistor T2.

[0030] Conductive structures WWL_00 to WWL_nn and RWL_00 to RWL_nn for forming word lines extend along the X axis and are cross-connected between the plurality of memory cell slices 301 to 30n. The conductive structures WWL_00 to WWL_nn are connected to the first transistor T1, and the conductive structures RWL_00 to RWL_nn are connected to the second transistor T2.

[0031] During the data writing mode, for the selected memory cell, the selected write word line (at least one of the conductive structures WWL_00 to WWL_nn) can supply a word line signal equal to the voltage V1, and the write bit line corresponding to the selected memory cell (at least one of the bit lines WBL_00 to WBL_nn) can provide a bit line signal equal to the voltage V1 or the voltage V2 according to the logical value 0 or 1 of the written data. The voltage V1 can be 3V, and the voltage V2 can be 0V. Relatively, in the case of unselected memory cells, the unselected word lines and bit lines can provide a signal of 0V. During the hold mode, all voltages of the bit lines and word lines are 0V. In the data readout mode, the read word line (at least one of the conductive structures RWL_00 to RWL_nn) supplies a word line signal equal to the voltage V3, and the voltage RV of the read bit line (at least one of the bit lines RBL_00 to RBL_nn) can be determined by the stored logical value of the corresponding selected memory cell. Here, the voltage V3 may be smaller than the voltage V1. For example, the voltage V3 may be 1V. The details of the operation can be confirmed as the following truth table.

Table 1

[0032] Please refer to FIG. 4. FIG. 4 is a schematic three-dimensional structure diagram of a memory structure according to another embodiment of the present invention. The memory structure 400 is arranged on the plane of the substrate SUB. The plane of the substrate SUB is formed on the X-Y axis plane and has the same normal direction as the Z axis. The memory structure 400 includes a plurality of first transistors T1 and a plurality of second transistors T2. The first transistors T1 are arranged in a first array in the form of N×M, and the second transistors T2 are arranged in a second array in the form of N×M. In this embodiment, both N and M can be equal to 4. In other embodiments of the present disclosure, N and M may be any other positive integers.

[0033] In the following description, the X-axis direction is described as the row direction and the Z-axis direction is described as the column direction. The structures of the first transistor T1 and the second transistor T2 of this embodiment are the same as those of the embodiment in FIG. 1. Notably, in this embodiment, each of the plurality of bit lines WBL1 to WBL4 coupled to the first transistor T1 extends along the X-axis and is coupled to a plurality of channel pillars 410 arranged in the same row. The bit lines WBL1 to WBL4 are vertically arranged along the Z-axis direction. Each of the conductive structures WWL1 to WWL4 extends along the Z-axis direction, surrounds a plurality of channel pillars 410 arranged in the same column, and forms a common gate for the plurality of first transistors T1 arranged in the same column. The conductive structures WWL1 to WWL4 are arranged along the X-axis direction.

[0034] Also, each of the plurality of bit lines RBL1 to RBL4 coupled to the second transistor T2 extends along the Z-axis direction. The bit lines RBL1 to RBL4 are arranged along the X-axis direction. Each of the bit lines RBL1 to RBL4 is coupled to one end of a plurality of conductive structures 420 arranged in the same column. Each of the conductive structures RWL1 to RWL4 extends along the X-axis direction, covers a plurality of conductive structures 420 arranged in the same row, and forms a word line for the plurality of second transistors T2 arranged in the same row. The conductive structures RWL1 to RWL4 are vertically arranged along the Z-axis direction.

[0035] In this embodiment, the plurality of word lines formed by each of the conductive structures WWL1 to WWL4 and the bit lines RBL1 to RBL4 extend along the normal direction of the plane of the substrate SUB (i.e., the Z-axis direction).

[0036] Please refer to FIG. 5. FIG. 5 is a schematic circuit diagram of a memory cell array formed by the memory structure of FIG. 4 according to an embodiment of the present disclosure. The memory cell array 500 has a plurality of memory cell slices 501 to 50n. Each of the memory cell slices 501 to 50n includes a memory cell array including a plurality of memory cells MC, and each memory cell MC includes a first transistor T1 and a second transistor T2. The memory cell slice 501 has a plurality of conductive structures WWL_00 to WWL_0n extending along the Z axis to form word lines, and a plurality of bit lines RBL_00 to RBL_0n extending along the Z axis. The conductive structures WWL_00 to WWL_0n are coupled to the control terminals of the first transistors T1, and the bit lines RBL_00 to RBL_0n are coupled to the second transistors T2. Similarly, the memory cell slice 50n has a plurality of conductive structures WWL_n0 to WWL_nn extending along the Z axis to form word lines, and a plurality of bit lines RBL_n0 to RBL_nn extending along the Z axis. The conductive structures WWL_n0 to WWL_nn are coupled to the control terminals of the first transistors T1, and the bit lines RBL_n0 to RBL_nn are coupled to the second transistors T2.

[0037] The bit lines WBL_00 to WBL_nn and the conductive structures RWL_00 to RWL_nn for forming word lines may extend along the X-axis direction and be cross-connected between the plurality of memory cell slices 501 to 50n. The bit lines WBL_00 to WBL_nn are coupled to the first transistors T1, and the conductive structures RWL_00 to RWL_nn are coupled to the second transistors T2.

[0038] Please refer to FIG. 6. FIG. 6 is a schematic three-dimensional structure diagram of a memory structure according to another embodiment of the present invention. The memory structure 600 is arranged on the plane of the substrate SUB. The plane of the substrate SUB is formed on the X-Y axis plane and has the same normal direction as the Z axis. The memory structure 600 includes a plurality of first transistors T1 and a plurality of second transistors T2. The first transistor T1 is arranged in a first array in the form of N×M, and the second transistor T2 is arranged in a second array in the form of N×M. In this embodiment, both N and M can be equal to 4. In other embodiments of the present disclosure, N and M may be any other positive integers.

[0039] In the following description, the X-axis direction will be described as the row direction and the Z-axis direction will be described as the column direction. The structures of the first transistor T1 and the second transistor T2 in this embodiment are the same as those in the embodiments of FIGS. 1 and 4. It is worth noting that in this embodiment, each of the plurality of bit lines WBL1~WBL4 coupled to the first transistor T1 extends along the X axis and is coupled to a plurality of channel pillars 610 arranged in the same row. The bit lines WBL1~WBL4 are vertically arranged along the Z-axis direction. Each of the conductive structures WWL1~WWL4 extends along the Z-axis direction, surrounds a plurality of channel pillars 610 arranged in the same column, and forms a common gate for the plurality of first transistors T1 arranged in the same column. The conductive structures WWL1~WWL4 are continuously arranged along the X-axis direction.

[0040] Also, each of the plurality of bit lines RBL1~RBL4 coupled to the second transistor T2 extends along the X-axis direction. The bit lines RBL1~RBL4 are vertically arranged along the Z-axis direction. Each of the bit lines RBL1~RBL4 is coupled to one end of a plurality of conductive structures 620 arranged in the same row. Each of the conductive structures RWL1~RWL4 extends along the Z-axis direction, covers and surrounds a plurality of conductive structures 620 arranged in the same row, and forms a word line for the plurality of second transistors T2 arranged in the same column. The conductive structures RWL1~RWL4 are continuously arranged along the X-axis direction.

[0041] In this embodiment, each of the plurality of word lines formed by the conductive structures WWL1 to WWL4 and RWL1 to RWL4 extends along the normal direction of the plane of the substrate SUB (i.e., the Z-axis direction).

[0042] Refer to FIG. 7. FIG. 7 is a schematic circuit diagram of a memory cell array formed by the memory structure of FIG. 6 according to an embodiment of the present disclosure. The memory cell array 700 has a plurality of memory cell slices 701 to 70n. Each of the memory cell slices 701 to 70n includes a memory cell array including a plurality of memory cells MC, and each memory cell MC includes a first transistor T1 and a second transistor T2. The memory cell slice 701 has a plurality of conductive structures WWL_00 to WWL_0n that extend along the Z-axis to form word lines, and a plurality of conductive structures RWL_00 to RWL_0n that extend along the Z-axis to form word lines. The conductive structures WWL_00 to WWL_0n are coupled to the control terminal of the first transistor T1, and the conductive structures RWL_00 to RWL_0n are coupled to the control terminal of the second transistor T2. Similarly, the memory cell slice 70n has a plurality of conductive structures WWL_n0 to WWL_nn that extend along the Z-axis to form word lines, and a plurality of conductive structures RWL_n0 to RWL_nn that extend along the Z-axis to form word lines. The conductive structures WWL_n0 to WWL_nn are coupled to the control terminal of the first transistor T1, and the conductive structures RWL_n0 to RWL_nn are coupled to the control terminal of the second transistor T2.

[0043] The bit lines WBL_00 to WBL_nn and the conductive structures RWL_00 to RWL_nn for forming word lines extend along the X-axis direction and can be cross-connected between the plurality of memory cell slices 701 to 70n. The bit lines WBL_00 to WBL_nn are coupled to the first transistor T1, and the conductive structures RWL_00 to RWL_nn are coupled to the second transistor T2.

[0044] Please refer to FIG. 8. FIG. 8 is a schematic three-dimensional structure diagram of a memory structure according to another embodiment of the present invention. The memory structure 800 is disposed on the plane of the substrate SUB. The plane of the substrate SUB is formed on the X-Y axis plane and has the same normal direction as the Z axis. The memory structure 800 includes a plurality of first transistors T1 and a plurality of second transistors T2. The first transistor T1 is arranged in a first array in the form of N×M, and the second transistor T2 is arranged in a second array in the form of N×M. In this embodiment, both N and M can be equal to 4. In other embodiments of the present disclosure, N and M may be any other positive integers.

[0045] In the following description, the X-axis direction will be described as the row direction and the Z-axis direction as the column direction. The structures of the first transistor T1 and the second transistor T2 in this embodiment are the same as those in the embodiments of FIGS. 1, 4, and 6. It is worth noting that in this embodiment, each of the plurality of bit lines WBL1~WBL4 coupled to the first transistor T1 extends along the Z axis and is coupled to a plurality of channel pillars 810 arranged in the same row. The bit lines WBL1~WBL4 are arranged continuously along the X-axis direction. Each of the conductive structures WWL1~WWL4 extends along the X-axis direction, surrounds a plurality of channel pillars 810 in the same column, and forms a common gate for the plurality of first transistors T1 arranged in the same row. The conductive structures WWL1~WWL4 are arranged vertically along the Z-axis direction.

[0046] Also, each of the plurality of bit lines RBL1~RBL4 coupled to the second transistor T2 extends along the X-axis direction. The bit lines RBL1~RBL4 are arranged vertically along the Z-axis direction. Each of the bit lines RBL1~RBL4 is coupled to one end of a plurality of conductive structures 820 arranged in the same row. Each of the conductive structures RWL1~RWL4 extends along the Z-axis direction, covers and surrounds a plurality of conductive structures 820 arranged in the same row, and forms a word line for the plurality of second transistors T2 arranged in the same column. The conductive structures RWL1~RWL4 are arranged continuously along the X-axis direction.

[0047] In this embodiment, each of the plurality of word lines formed by bit lines WBL1 to WBL4 and conductive structures RWL1 to RWL4 extends along the normal direction of the plane of the substrate SUB (i.e., the Z-axis direction).

[0048] Refer to FIG. 9. FIG. 9 is a schematic circuit diagram of a memory cell array formed by the memory structure of FIG. 8 according to an embodiment of the disclosure. The memory cell array 900 has a plurality of memory cell slices 901 to 90n. Each of the memory cell slices 901 to 90n includes a memory cell array including a plurality of memory cells MC, and each memory cell MC includes a first transistor T1 and a second transistor T2. The memory cell slice 901 has a plurality of bit lines WBL1_00 to WBL_0n extending along the Z-axis and a plurality of conductive structures RWL_00 to RWL_0n extending along the Z-axis to form word lines. The bit lines WBL1_00 to WBL_0n are coupled to the first transistor T1, and the conductive structures RWL_00 to RWL_0n are coupled to the control terminal of the second transistor T2. Similarly, the memory cell slice 90n has a plurality of bit lines WBL1_n0 to WBL_nn extending along the Z-axis and a plurality of conductive structures RWL_n0 to RWL_nn extending along the Z-axis to form word lines. The bit lines WBL1_n0 to WBL_nn are coupled to the control terminal of the first transistor T1, and the conductive structures RWL_n0 to RWL_nn are coupled to the control terminal of the second transistor T2.

[0049] The bit lines RBL_00 to RBL_nn and the conductive structures WWL_00 to WWL_nn for forming word lines extend along the X-axis direction and can be cross-connected between the plurality of memory cell slices 901 to 90n. The bit lines RBL_00 to RBL_nn are coupled to the second transistor T2, and the conductive structures WWL_00 to WWL_nn are coupled to the first transistor T1.

[0050] In summary, the memory structure according to the present disclosure forms a memory cell with two transistors. In this way, it is not necessary to provide a storage capacitance for each memory cell, and the circuit area can be effectively saved. Further, the memory structure according to the present disclosure is arranged vertically with respect to a word line or a bit line. In the manufacturing process, it is not necessary to define the vertically arranged word line or bit line for each layer, and the process of the vertically arranged word line or bit line can be completed by a single etching. Therefore, the complexity of the process can be effectively reduced, and the manufacturing cost can be effectively reduced.

Industrial Applicability

[0051] The memory structure and its control method of the present invention can be applied to a DRAM device without arranging a storage capacitance, and can save the circuit area.

Explanation of Reference Numerals

[0052] 100: Memory structure 110, 410, 610, 810: Channel pillar 120, 420, 620, 820, RWL1~RWL4, WWL1~WWL4, RWL, WWL, WWL_00~WWL_nn, RWL_00~RWL_nn: Conductive structure CH: Channel RBL1~RBL4, WBL1~WBL4, WBL, RBL, WBL_00~WBL_nn, RBL_00~RBL_nn: Bit line SUB: Subtraction SN: Data storage node T1: First transistor T2: Second transistor 300, 500, 700, 900: Memory cell array 301~30n, 501~50n, 701~70n, 901~90n: Memory cell slice MC: Memory cell X, Y, Z: Axes

Claims

1. A plurality of first transistors disposed in a first array, wherein a first end of each of the first transistors is respectively coupled to a plurality of first bit lines, and a gate of each of the first transistors is respectively coupled to a plurality of first word lines; a plurality of first transistors, A plurality of second transistors disposed in a second array, wherein a gate of each of the second transistors is respectively coupled to a second end of each of the first transistors, a second end of each of the second transistors is respectively coupled to a plurality of second bit lines, and a first end of each of the second transistors is respectively coupled to a plurality of second word lines; a second transistor, Comprising: The first transistor and the second transistor are disposed on a substrate, and one of each of the first word lines and each of the first bit lines extends along a normal direction of a plane of the substrate, and one of each of the second word lines and each of the second bit lines extends along the normal direction; a memory structure.

2. The extending directions of each of the first word lines and each of the first bit lines are substantially perpendicular to each other, and the extending directions of each of the second word lines and each of the second bit lines are substantially perpendicular to each other; the memory structure according to Claim 1.

3. The first array includes: N×M (N, M: positive integers) channel pillars; M first conductive structures; Each of the first conductive structures surrounds N channel pillars, and each of the first conductive structures forms a common gate and each of the first word lines of the first transistors corresponding to the N channel pillars; the memory structure according to Claim 1.

4. The second array includes: N×M gate structures each having a plurality of first ends respectively coupled to first ends of the corresponding N×M channel pillars; N×M second conductive structures respectively surrounding the gate structures; M third conductive structures; Each of the third conductive structures covers N of the second conductive structures, and the third conductive structures respectively form the second word lines; the memory structure according to Claim 3.

5. Each of the first bit lines is coupled to a second end of a corresponding one of the channel pillars, the memory structure of claim 4. **Claim 6** Each of the second bit lines is coupled to a second end of a corresponding one of the gate structures, the memory structure of claim 4. **Claim 7** Over each of the second conductive structures, a channel of each of the second transistors is formed between each of the third conductive structures and each of the second bit lines, the memory structure of claim 6. **Claim 8** Each of the gate structures and a corresponding one of the channel pillars are of the same structure, the memory structure of claim 4. **Claim 9** The extending directions of each of the first word lines and each of the second word lines are substantially the same, and the extending directions of each of the first bit lines and each of the second bit lines are substantially the same, the memory structure of claim 4. **Claim 10** The second array includes N×M gate structures each having a plurality of first ends respectively coupled to first ends of corresponding ones of the N×M channel pillars, N×M second conductive structures each surrounding a corresponding one of the gate structures, N third conductive structures, wherein each of the third conductive structures surrounds M of the second conductive structures, and the third conductive structures respectively form the second word lines, the memory structure of claim 3. **Claim 11** The extending directions of each of the first word lines and each of the second word lines are substantially orthogonal to each other, and the extending directions of each of the first bit lines and each of the second bit lines are substantially orthogonal to each other, the memory structure of claim 10. **Claim 12** The connection ends of each of the first transistors and each of the second transistors are data storage nodes, the memory structure of claim 1. **Claim 13** In a write mode, each of the first transistors is turned on, and write data received by the first ends of each of the transistors is written to corresponding ones of the data storage nodes, the memory structure of claim 12. **Claim 14** In the read mode, each of the second transistors is turned on or off according to the data stored in the corresponding data storage node, and the second ends of each of the transistors are configured to provide read data. The memory structure according to claim 12.

15. Each of the first transistors is a gate all-around (GAA) transistor, and each of the second transistors is a channel all-around (CAA) transistor. The memory structure according to claim 1.

16. Arranging a plurality of first transistors disposed in a first array, wherein a first end of the first transistor is respectively coupled to a plurality of first bit lines, and a gate of the first transistor is respectively coupled to a plurality of first word lines; Arranging a plurality of second transistors disposed in a second array, wherein a gate of the second transistor is respectively coupled to a second end of the first transistor, a second end of the second transistor is respectively coupled to a plurality of second bit lines, and a first end of the second transistor is respectively coupled to a plurality of second word lines; Extending one of each of the first word lines and each of the first bit lines along a normal direction of the plane of the substrate to provide a first signal; Extending one of each of the second word lines and each of the second bit lines along a normal direction of the plane of the substrate to provide a second signal; A control method for a memory device, comprising:

17. Each of the first word lines provides a first word line signal that becomes the first signal; Each of the second word lines provides a second word line signal that becomes the second signal; Each of the first bit lines provides a first bit line signal that becomes the first signal; Each of the second bit lines provides a second bit line signal that becomes the second signal. The control method according to claim 16.

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