Semiconductor device and equipment

Abstract

To provide a technology that is advantageous in improving effectiveness of redundancy relief.SOLUTION: A semiconductor device comprises: a memory cell array including a plurality of memories, each of which is a volatile memory, arranged across a plurality of rows and a plurality of columns; a plurality of relief circuits for relieving the memory cell array; a selection circuit for selecting a relief circuit from the plurality of relief circuits that is connected to a memory included in the plurality of memories; and a holding circuit for holding selection information for the selection circuit to select a specified relief circuit from the plurality of relief circuits, and controlling the selection circuit based on the selection information.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to semiconductor devices and equipment.

Background Art

[0002] In a semiconductor device equipped with a memory such as a volatile memory, a technique called redundant relief for remedying defective portions of the memory is used. Patent Document 1 shows that a redundant circuit including a spare memory is provided to remedy defective bits included in the memory and improve the yield.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] There is a possibility that the memory to be redundant cannot be remedied when there is a defective portion in the spare memory or when there is a defect in the wiring pattern between the memory to be redundant and the spare memory.

[0005] An object of the present invention is to provide a technique advantageous for improving the effect of redundant relief.

Means for Solving the Problems

[0006] In view of the above problems, a semiconductor device according to an embodiment of the present invention includes a memory cell array including a plurality of memories each of which is a volatile memory and arranged over a plurality of rows and a plurality of columns, a plurality of repair circuits for repairing the memory cell array, a selection circuit for selecting a repair circuit connected to a memory included in the plurality of memories among the plurality of repair circuits, and a holding circuit that holds selection information for the selection circuit to select a specified repair circuit among the plurality of repair circuits and controls the selection circuit based on the selection information.

Effect of the Invention

[0007] According to the present invention, it is possible to provide a technique advantageous for improving the effect of redundant repair.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the invention according to the claims. Although a plurality of features are described in the embodiments, not all of these plurality of features are essential to the invention, and the plurality of features may be arbitrarily combined. Further, in the accompanying drawings, the same or similar configurations are denoted by the same reference numerals, and redundant explanations are omitted.

[0010] With reference to FIGS. 1 to 15, a semiconductor device according to an embodiment of the present disclosure will be described. FIG. 1 is a block diagram showing a configuration example of a semiconductor device 11 in the present disclosure. In the configuration shown in FIG. 1, four blocks 101 to 104 including four memories 201 to 204 that are targets of redundancy relief, in other words, four memories that can be redundantly relieved, are arranged in the semiconductor device 11. Each of the blocks 101 to 104 is a memory cell array including a plurality of memories arranged over a plurality of rows and a plurality of columns. Each memory arranged in each of the blocks 101 to 104 can be a volatile memory. Here, the number of blocks arranged in the semiconductor device 11 is not limited to four, and may be three or less or five or more. Similarly, the number of memories arranged in each block may be three or less or five or more. Also, in FIG. 1, the description of the memories 201 to 204 arranged in the blocks 102 to 104 is omitted.

[0011] FIG. 2 shows a configuration example of a circuit when four redundantly relievable memories 201 to 204 are arranged in the block 101. The memories 201 to 204 are, for example, volatile memories. Typically, each of the memories 201 to 204 is a Static Random Access Memory (SRAM). In addition to the memories 201 to 204, the block 101 of the semiconductor device 11 includes a plurality of relief circuits 401 to 404 for relieving the memories (for example, the memories 201 to 204) arranged in the memory cell array, selection circuits 301 to 304, and a holding circuit 501. The selection circuits 301 to 304 are respectively arranged between the corresponding memories 201 to 204 and two or more of the plurality of relief circuits 401 to 404, and select the relief circuits 401 to 404 connected to the memories 201 to 204 among the plurality of relief circuits 401 to 404. The holding circuit 501 holds selection information for the selection circuits 301 to 304 to select a specified relief circuit among the plurality of relief circuits 401 to 404, and controls the selection circuits 301 to 304 based on the selection information.

[0012] The recovery circuits 401 to 404 may be non-volatile memories or volatile memories. Examples of non-volatile memories include Read Only Memory (ROM), flash memory, Magnetoresistive Random Access Memory (MRAM), and Ferroelectric Random Access Memory (FeRAM). Examples of volatile memories include the aforementioned SRAM and Dynamic Random Access Memory (DRAM). As shown in FIG. 2, the recovery circuits 401 to 404 may be arranged for each row and each column with respect to the memories 201 to 204 arranged in the row direction and the column direction. Further, for example, even if the recovery circuits 401 to 404 are arranged within the semiconductor device 11, they do not necessarily have to be arranged within the block 101. For example, the recovery circuits 401 to 404 may be non-volatile memories arranged within the semiconductor device 11 and shared by two or more of the blocks 101 to 104. Further, for example, the recovery circuits 401 to 404 may be volatile memories such as flip-flops to which information to be recovered from the memories 201 to 204 is transferred.

[0013] In the configuration shown in FIG. 2, the holding circuit 501 holds 4-bit information as selection information. The 0-bit selection signal of the holding circuit 501 is supplied to the selection circuit 301. Similarly, the 1-bit, 2-bit, and 3-bit selection signals of the holding circuit 501 are supplied to the selection circuits 302, 303, and 304, respectively.

[0014] The selection circuit 301 is connected to a signal line from which a redundant recovery signal is output from the memory 201. Similarly, the selection circuits 302, 303, and 304 are respectively connected to signal lines from which redundant recovery signals are output from the memories 202, 203, and 204.

[0015] The memory 201 is configured to be connectable to the salvage circuits 401 and 403 among the plurality of salvage circuits 401 to 404 via the selection circuit 301. The memory 202 is configured to be connectable to the salvage circuits 401 and 404 among the plurality of salvage circuits 401 to 404 via the selection circuit 302. The memory 203 is configured to be connectable to the salvage circuits 402 and 403 among the plurality of salvage circuits 401 to 404 via the selection circuit 303. The memory 204 is configured to be connectable to the salvage circuits 402 and 404 among the plurality of salvage circuits 401 to 404 via the selection circuit 304.

[0016] When the 0th bit of the selection information held in the holding circuit 501 is "0", the salvage circuit 401 is selected as the salvage circuit connected to the memory 201 via the selection circuit 301, and when it is "1", the salvage circuit 403 is selected. When the 1st bit of the selection information held in the holding circuit 501 is "0", the salvage circuit 401 is selected as the salvage circuit connected to the memory 202 via the selection circuit 302, and when it is "1", the salvage circuit 404 is selected. When the 2nd bit of the selection information held in the holding circuit 501 is "0", the salvage circuit 402 is selected as the salvage circuit connected to the memory 203 via the selection circuit 303, and when it is "1", the salvage circuit 403 is selected. When the 3rd bit of the selection information held in the holding circuit 501 is "0", the salvage circuit 402 is selected as the salvage circuit connected to the memory 204 via the selection circuit 304, and when it is "1", the salvage circuit 404 is selected.

[0017] Next, with reference to FIGS. 3(a) and 3(b), an example of circuit switching when saving the memory 201 is shown. When saving the memory 201, there are two circuit configurations. In the example shown in FIG. 3(a), the holding circuit 501 holds [N0N1] as 4-bit selection information Sel[3:0] (described as Sel[3:0]=N0N1 in FIG. 3(a); the same applies hereinafter). Here, "N" may be either a selection signal of "0" or "1". When the selection signal "1" is supplied from the holding circuit 501 to the selection circuit 301, the information to be saved in the memory 201 is written into the saving circuit 403. On the other hand, in the example shown in FIG. 3(b), the holding circuit 501 holds [NN10] as 4-bit selection information Sel[3:0]. When the selection signal "0" is supplied from the holding circuit 501 to the selection circuit 301, the information to be saved in the memory 201 is written into the saving circuit 401. Thus, it is possible to save the memory 201 using either of the saving circuits 401 and 403.

[0018] FIG. 4 shows an example of circuit switching when saving memories 201 to 204. In this case, the holding circuit 501 holds

[0110] as 4-bit selection information Sel[3:0]. Thereby, the memory 201 uses the saving circuit 401, the memory 202 uses the saving circuit 404, the memory 203 uses the saving circuit 403, and the memory 204 uses the saving circuit 402, and all the memories 201 to 204 are saved. Although not shown, when the holding circuit 501 holds

[1001] as the selection information Sel[3:0], all the memories 201 to 204 are also saved using the corresponding saving circuits 401 to 404 respectively.

[0019] FIG. 5 shows an example in which a plurality of recovery circuits 401 and 403 can be used when recovering the memory 201. For example, if the recovery circuit 401 is a non-volatile memory and a defect occurs in the storage area for recovering the memory 201 and a write failure occurs, there is a possibility that the memory 201 to be redundant cannot be recovered. Also, for example, if there is a defect in the wiring pattern between the selection circuit 301 and the recovery circuit 401, etc., there is also a possibility that the memory 201 cannot be recovered. An example of improving redundancy in such a case will be described with reference to FIG. 5.

[0020] As shown in FIG. 5, the holding circuit 501 holds [N01M] as the selection information Sel[3:0]. That is, depending on the value of "M" of the 0th bit of the selection information Sel of the holding circuit 501, the selection circuit 301 can select the recovery circuit 401 and the recovery circuit 403. For example, even if a write failure occurs in the recovery circuit 401 and cannot be recovered when M = 0, the 0th bit of the selection information Sel is set to M = 1. Thereby, the recovery circuit 403 can be used to recover the memory 201.

[0021] In the semiconductor device 11, not all of the memories 201 to 204 arranged in the block 101 fail. Therefore, as in the case shown in FIG. 5, one of the recovery circuit 401 and the recovery circuit 403 can be used as a spare recovery circuit for the memory 201 that requires recovery. In that case, the information for recovering the memory 201 may need to be written to both the recovery circuit 401 and the recovery circuit 403.

[0022] As described above, in the circuit configuration of this embodiment, since the relief circuits 401 to 404 are arranged corresponding to the memories 201 to 204 respectively, when there is a problem in the memories 201 to 204, a high redundant relief effect can be expected. Furthermore, the possibility that problems occur in all of the memories 201 to 204 is low. In that case, a plurality of relief circuits are arranged for one memory. Therefore, even when a problem occurs in the relief circuit or when a problem occurs in the wiring pattern between the memory and the relief circuit, the possibility of rescuing the failed memory is increased. As a result, the redundant relief effect can be further improved.

[0023] FIG. 6 shows an example of a flow when rescuing the memories 201 to 204. Hereinafter, the flow when rescuing the memories 201 to 204 arranged in the block 101 will be described. Similar inspections can be performed in other blocks (for example, blocks 102 to 104). The flow shown in FIG. 6 is a relief flow when the relief circuits 401 to 404 are non-volatile memories.

[0024] First, the states of the memories 201 to 204 are inspected at S601. For the inspection of the memories 201 to 204, for example, a method such as Built-In Self Test (BIST) is used. However, it is not limited thereto, and any appropriate method capable of inspecting the memories 201 to 204 may be used. The inspection circuit for inspecting the memories 201 to 204 may be arranged, for example, inside the block 101, outside the block 101 and inside the semiconductor device 11, or outside the semiconductor device 11.

[0025] At S601, if the inspection of the memories 201 to 204 is passed, there is no need to rescue the memories 201 to 204. Therefore, the block 101 is determined to be passed (S613), and the flow ends. On the other hand, if the inspection of the memories 201 to 204 is failed, the failure information of the memories 201 to 204 is output to the analysis device arranged outside the semiconductor device 11 (S602).

[0026] When failure information is output from the semiconductor device 11, in S603, an analysis device external to the semiconductor device 11 analyzes the failure information indicating the states of the memories 201 to 204. The analysis device determines whether the memories 201 to 204 can be recovered (S604). If it is determined that the memories 201 to 204 cannot be recovered, block 101 becomes non-conforming (S612), and the flow ends.

[0027] On the other hand, if it is determined that the memories 201 to 204 can be recovered, the flow transitions to S605, and the analysis device determines whether there is one failed memory. Here, the failed memory may include a memory with a part thereof failed and a memory with the whole thereof failed. If there is one failed memory (for example, the memory 201 will be described below), the flow transitions to S606. In S606, the analysis device generates selection information Sel[N01M] based on the states of the memories 201 to 204 and supplies it to the holding circuit 501. The holding circuit 501 controls the selection circuit 301 based on the selection information. The recovery circuits 401 and 403 can be connected to the memory 201. Therefore, an inspection circuit for inspecting the memories 201 to 204 writes information to the memory 201 and the recovery circuits 401 and 403 including the reserve to which the memory 201 is connected. Next, in S607, the states of the memory 201 and the recovery circuit (for example, the recovery circuit 401) connected to the memory 201 among the plurality of recovery circuits 401 to 404 are further inspected. If the inspection is passed, block 101 is determined to be conforming (S613), and the flow ends.

[0028] If the inspection at S607 is failed, the flow transitions to S608. At S608, the 0th bit (“M”) of the holding information switches from “0” to “1”, and the relief circuit connected to the memory 201 switches from the relief circuit 401 to the relief circuit 403. Next, at S609, the states of the memory 201 and the relief circuit 403 connected to the memory 201 are further inspected. If the inspection is passed, the block 101 is determined to be passed (S613), and the flow ends. Also, if the inspection is failed, the block 101 fails (S612), and the flow ends.

[0029] At S605, if it is determined that a plurality of memories among the memories 201 to 204 are faulty, the flow transitions to S610. At S610, the analysis device generates selection information Sel

[0110] or

[1001] based on the states of the memories 201 to 204 and supplies it to the holding circuit 501. The holding circuit 501 controls the selection circuit 301 based on the selection information. Thereby, the memories 201 to 204 are respectively connected to the corresponding relief circuits 401 to 404. The inspection circuit for inspecting the memories 201 to 204 writes information to the memories 201 to 204 and the relief circuits 401 to 404 to which the memories 201 to 204 are respectively connected. Next, at S611, the states of the memories 201 to 204 and the relief circuits 401 to 404 to which the memories 201 to 204 are respectively connected are further inspected. If the inspection is passed, the block 101 is determined to be passed (S613), and the flow ends. Also, if the inspection is failed, the block 101 fails (S612), and the flow ends.

[0030] Next, with reference to FIG. 7, the recovery flow when the recovery circuits 401 to 404 are volatile memories will be described. First, the states of the memories 201 to 204 are inspected at S621. S621 may be the same as the above-described S601. In S621, if the inspections for the memories 201 to 204 are passed, there is no need to recover the memories 201 to 204. Therefore, block 101 is determined to be passed (S628), and the flow ends. On the other hand, if the inspections for the memories 201 to 204 are failed, the failure information of the memories 201 to 204 is output to an analysis device arranged outside the semiconductor device 11 (S622).

[0031] When the failure information is output from the semiconductor device 11, in S623, an analysis device outside the semiconductor device 11 analyzes the failure information indicating the states of the memories 201 to 204. The analysis device determines whether the memories 201 to 204 can be recovered (S624). When it is determined that the memories 201 to 204 cannot be recovered, block 101 becomes failed (S627), and the flow ends.

[0032] On the other hand, when it is determined that the memories 201 to 204 can be recovered, the flow transitions to S625, and the analysis device generates selection information based on the states of the memories 201 to 204 and supplies it to the holding circuit 501. The holding circuit 501 controls the selection circuit 301 based on the selection information, and the memories 201 to 204 are connected to the designated recovery circuits 401 to 404, respectively. An inspection circuit for inspecting the memories 201 to 204 writes information to the memories 201 to 204 and the recovery circuits 401 to 404 to which the memories 201 to 204 are respectively connected.

[0033] Next, in S626, the states of the memories 201 to 204 and the recovery circuits 401 to 404 to which the memories 201 to 204 are respectively connected are further inspected. If the inspection is passed, block 101 is determined to be passed (S628), and the flow ends. Also, if the inspection is failed, block 101 becomes failed (S627), and the flow ends.

[0034] In the flow shown in FIGS. 6 and 7, it was explained that the states of memories 201 to 204 and recovery circuits 401 to 401 are analyzed by an analysis device arranged outside the semiconductor device 11, and selection information is supplied from the analysis device to the holding circuit 501 based on the analyzed results. However, it is not limited to this. An analysis circuit for analyzing the states of memories 201 to 204 and recovery circuits 401 to 401 may be arranged in the semiconductor device 11. For example, as shown in FIG. 2, an analysis circuit 551 may be arranged in the block 101. Also, for example, the analysis circuit 551 may be arranged outside the block 101 and inside the semiconductor device 11. In that case, the analysis circuit 551 may be shared by a plurality of blocks among the blocks 101 to 104. FIG. 8 is a diagram showing an example of a flow when the analysis circuit 551 is arranged in the semiconductor device 11.

[0035] First, in S631, the states of memories 201 to 204 are inspected by an inspection circuit for inspecting memories 201 to 204. S631 may be the same as the above-described S601 and S621. If the inspection of memories 201 to 204 is passed in S631, there is no need to recover memories 201 to 204. Therefore, the block 101 is determined to be qualified (S637), and the flow ends.

[0036] On the other hand, if the inspection of memories 201 to 204 fails, the failure information of memories 201 to 204 is supplied to the analysis circuit 551, and analysis is performed (S632). Next, the analysis circuit 551 determines whether memories 201 to 204 can be recovered (S633). If it is determined that memories 201 to 204 cannot be recovered, the block 101 becomes unqualified (S627), and the flow ends.

[0037] On the other hand, when it is determined that the memories 201 to 204 can be salvaged, the flow transitions to S634, and the analysis circuit 551 generates selection information based on the states of the memories 201 to 204 and supplies it to the holding circuit 501. The holding circuit 501 controls the selection circuit 301 based on the selection information supplied from the analysis circuit 551, and the memories 201 to 204 are connected to the designated salvage circuits 401 to 404, respectively. The inspection circuit for inspecting the memories 201 to 204 writes information to the memories 201 to 204 and the salvage circuits 401 to 404 to which the memories 201 to 204 are respectively connected.

[0038] Next, in S635, the states of the memories 201 to 204 and the salvage circuits 401 to 404 to which the memories 201 to 204 are respectively connected are further inspected. If the inspection is passed, block 101 is determined to be passed (S637), and the flow ends. Also, if the inspection fails, block 101 fails (S636), and the flow ends.

[0039] Here, after the analysis circuit 551 generates selection information based on the states of the memories 201 to 204 in S634, the analysis circuit 551 may further analyze the states of the memories 201 to 204 and the relief circuits 401 to 404 respectively connected to the memories 201 to 204. As described above, only the memory 201 among the plurality of memories 201 to 204 arranged in the block 101 may be faulty. In such a case, the analysis circuit 551 generates [N010] as selection information in S634 and supplies it to the holding circuit 501. Then, when the inspection in S635 is unqualified, the analysis circuit 551 generates [N011] as selection information and supplies it to the holding circuit 501. That is, the analysis circuit 551 may change the selection information when it is necessary to change the selection information according to the respective states of the memory 201 and the relief circuit 401 connected to the memory 201, and supply the changed selection information to the holding circuit 501. Also, in the above description, it has been described that the inspection circuit for inspecting the memories 201 to 204 and the analysis circuit 551 are arranged independently of each other, but the inspection circuit and the analysis circuit 551 may be arranged at least partially integrally and may operate at least partially in cooperation.

[0040] FIGS. 9(a) and 9(b) show information including selection information supplied to the holding circuit 501 when a predetermined address area of a non-volatile memory is designated as the relief circuits 401 to 404. For example, it can be information sent from outside the semiconductor device 11 to the semiconductor device 11.

[0041] FIG. 9(a) shows the information 701 sent to the semiconductor device 11 when only one block (for example, block 101) is arranged in the semiconductor device 11. In this case, it is only necessary to supply selection information (for example, the above-mentioned 4-bit information) to only one holding circuit 501 arranged in the semiconductor device 11. The information 701 can be supplied to the semiconductor device 11 using an appropriate communication method such as serial communication or parallel communication.

[0042] FIG. 9(b) shows information 702 including selection information when a plurality of blocks 101 to 104 are arranged in the semiconductor device 11 as shown in FIG. 1. In this case, the information 702 includes block information indicating which block among the blocks 101 to 104 is to be supplied to the holding circuit 501 in addition to the selection information.

[0043] FIGS. 10(a) and 10(b) show information including selection information supplied to the holding circuit 501 when volatile memories are used as the recovery circuits 401 to 404. For example, it can be information sent from outside the semiconductor device 11 to the semiconductor device 11.

[0044] FIG. 10(a) shows information 801 sent to the semiconductor device 11 when only one block (for example, block 101) is arranged in the semiconductor device 11. In this case, in addition to the information 701 shown in FIG. 9(a), setting information of the recovery circuits 401 to 404, such as areas of the recovery circuits 401 to 404 for writing the recovery information of the memories 201 to 204, is supplied to the semiconductor device 11. The information 801 can be supplied to the semiconductor device 11 using an appropriate communication method such as serial communication or parallel communication.

[0045] FIG. 10(b) shows information 802 including selection information when a plurality of blocks 101 to 104 are arranged in the semiconductor device 11 as shown in FIG. 1. In this case, similar to the relationship between the information 701 and the information 702, the information 802 includes block information indicating which block among the blocks 101 to 104 is to be supplied to the holding circuit 501.

[0046] When transferring the location information of the failure points of memories 201 to 204, discrimination signals of the relief circuits 401 to 404, etc. when relieving memories 201 to 204, the amount of signals may increase. Therefore, the communication time may become long. Also, the circuit used for decoding the signals becomes complex, and the circuit design may become complicated. On the other hand, in the present embodiment, the information 701, 702, 801, 802 supplied to the semiconductor device 11 when relieving memories 201 to 204 require less information volume as described above. For example, in the case of the above-described configuration, the information 701 only requires 4-bit information. Therefore, the communication time is short, and it is possible to minimize the circuit scale such as the decoding circuit. As a result, it becomes possible to realize a semiconductor device 11 that is easy to use while ensuring high redundancy.

[0047] In FIGS. 2 to 5, a configuration in which each of the memories 201 to 204 can be connected one-to-one to any one of the relief circuits 401 to 404 is shown. However, when the same number of relief circuits are arranged for the memories to be redundant, the circuit scale may become large. FIGS. 11 to 14 show circuit configuration examples when a plurality of memories to be redundantly relieved are connected to one relief circuit. In this case, the relief probability is low, but the number of relief circuits can be reduced. Also, it is unlikely that all of the memories to be redundant will fail. Therefore, depending on the circuit scale, two or more memories to be redundantly relieved may be connected to one relief circuit.

[0048] FIG. 11 shows a configuration example of a circuit when 16 redundant - recoverable memories 201a to 204d are arranged in block 101. In block 101 of semiconductor device 11, a plurality of recovery circuits 401 to 404 for recovering memories 201a to 204d, selection circuits 301a to 304d, and a holding circuit 501 are further arranged. Here, an example in which 16 memories 201a to 204d are arranged will be described. However, the number of selection circuits 301a to 304d respectively corresponding to memories 201a to 201d or memories 201a to 201d may be appropriately determined according to the specifications required for semiconductor device 11 and the like. Also, the number of arranged recovery circuits and the number of memories that can be connected to one recovery circuit, etc. may be appropriately determined according to the specifications required for semiconductor device 11 and the like. Hereinafter, differences from the above - described configuration will be explained, and explanations of configurations that may be the same will be omitted.

[0049] Memories 201a to 201d are configured to be connectable to recovery circuit 401 and recovery circuit 403 among a plurality of recovery circuits 401 to 404 via corresponding selection circuits 301a to 301d. Memories 202a to 202d are configured to be connectable to recovery circuit 401 and recovery circuit 404 among a plurality of recovery circuits 401 to 404 via corresponding selection circuits 302a to 302d. Memories 203a to 203d are configured to be connectable to recovery circuit 402 and recovery circuit 403 among a plurality of recovery circuits 401 to 404 via corresponding selection circuits 303a to 303d. Memories 204a to 204d are configured to be connectable to recovery circuit 402 and recovery circuit 404 among a plurality of recovery circuits 401 to 404 via corresponding selection circuits 304a to 304d.

[0050] The holding circuit 501 holds 4-bit information as selection information, similar to the above-described configuration. When the 0th bit of the selection information held in the holding circuit 501 is "0", the relief circuit 401 is selected as the relief circuit connected to the memories 201a to 201d via the selection circuits 301a to 301d, and when it is "1", the relief circuit 403 is selected. When the 1st bit of the selection information held in the holding circuit 501 is "0", the relief circuit 401 is selected as the relief circuit connected to the memories 202a to 202d via the selection circuits 302a to 302d, and when it is "1", the relief circuit 404 is selected. When the 2nd bit of the selection information held in the holding circuit 501 is "0", the relief circuit 402 is selected as the relief circuit connected to the memories 203a to 203d via the selection circuits 303a to 303d, and when it is "1", the relief circuit 403 is selected. When the 3rd bit of the selection information held in the holding circuit 501 is "0", the relief circuit 402 is selected as the relief circuit connected to the memories 204a to 204d via the selection circuits 304a to 304d, and when it is "1", the relief circuit 404 is selected. In this way, the relief circuit 401 is connected to, for example, a plurality of memories 201a to 201d. The same applies to the relief circuits 402 to 404. However, although it also depends on the failure rates of the memories 201a to 204d, there are few problems even when the relief circuits 401 to 404 are shared among a plurality of memories to be redundant.

[0051] FIG. 12 shows an example of circuit switching when rescuing the faulty memory 201a. As shown in FIG. 12, the holding circuit 501 holds [N0N1] as 4-bit selection information Sel[3:0]. When a "1" is supplied from the holding circuit 501 to the selection circuit 301a as a selection signal, the information to be rescued from the memory 201a is written into the rescue circuit 403. In this case, the selection circuits 301b to 301d are controlled to select the same rescue circuit 403 as the selection circuit 301a among the plurality of rescue circuits 401 to 404. In this case, the rescue circuit 403 is used for each of the memories 201a to 201d. However, for example, the rescue circuit 403 can be designed so that it is no problem even if the non-faulty memories 201b to 201d use the rescue circuit 403. The same applies to the other rescue circuits 401, 402, and 404. Also, for example, each of the memories 201a to 204d may have a function of selecting whether to use the rescue circuits 401 to 404. Further, for example, information for selecting whether to use the rescue circuits 401 to 404 may be supplied together with the selection information.

[0052] FIG. 13 shows an example of circuit switching when rescuing any one of the memories 201a to 201d, any one of the memories 202a to 202d, any one of the memories 203a to 203d, and any one of the memories 204a to 204d. In this case, the holding circuit 501 holds

[0110] as 4-bit selection information Sel[3:0]. Thereby, the memories 201a to 201d use the rescue circuit 401, the memories 202a to 202d use the rescue circuit 404, the memories 203a to 203d use the rescue circuit 403, and the memories 204a to 204d use the rescue circuit 402, and all the memories 201a to 204d can be rescued. Although not shown, all the memories 201a to 204d can also be rescued by using the corresponding rescue circuits 401 to 404 when the holding circuit 501 holds

[1001] as the selection information Sel[3:0].

[0053] As described in the description of FIG. 12, the redundancy circuits 401 to 404 can be designed such that the non-failed memories among the memories 201a to 204d can be used without problems using the redundancy circuits 401 to 404 respectively. Also, for example, each of the memories 201a to 204d may have a function of selecting whether to use the redundancy circuits 401 to 404. Further, for example, information for selecting whether to use the redundancy circuits 401 to 404 may be supplied together with the selection information, separately from the selection information.

[0054] FIG. 14 shows an example in which a plurality of redundancy circuits 401 and 403 can be used when saving the memory 201a. For example, when the redundancy circuit 401 is a non-volatile memory and a problem occurs in the storage area for saving the memory 201 and a write failure occurs, there is a possibility that the memory 201a to be made redundant cannot be saved. Also, for example, there is a possibility that the memory 201a cannot be saved even if there is a problem in the wiring pattern or the like between the selection circuit 301a and the redundancy circuit 401. An example of improving the redundancy in such a case will be described with reference to FIG. 14.

[0055] As shown in FIG. 14, the holding circuit 501 holds [N01M] as the selection information Sel[3:0]. That is, depending on the value of "M" of the 0th bit of the selection information Sel of the holding circuit 501, the selection circuit 301a can select the redundancy circuit 401 and the redundancy circuit 403. For example, even if a write failure occurs in the redundancy circuit 401 and it cannot be saved when M = 0, the 0th bit of the selection information Sel is set to M = 1. Thereby, the redundancy circuit 403 can be used to save the memory 201a.

[0056] Even when having the circuit configurations shown in FIGS. 11 to 14, memories 201a to 204d are rescued according to the flow shown in FIGS. 6 to 8 described above. Also, regarding information 701, 702, 801, 802 including selection information supplied to semiconductor device 11 from outside the semiconductor device 11, similar information is supplied. Also in the configurations shown in FIGS. 11 to 14, while improving the effect of redundant rescue, the number of rescue circuits that may not be used when no failure occurs in memories 201a to 204d can be suppressed.

[0057] FIG. 15 shows a layout example in the circuit configuration shown in FIG. 11. As shown in FIG. 15, since it is sufficient to supply a 1-bit selection signal to selection circuits 301a to 304d respectively connected to memories 201a to 204d, only one wiring pattern is arranged from holding circuit 501 for each. Furthermore, systems can be supplied collectively for every four selection circuits. Therefore, the wiring efficiency is good. Also, eight wiring patterns from rescue circuit 401 are arranged as wiring patterns common to selection circuits 301a, 301b, 302a, 302b. Therefore, the number of wirings becomes 1 / 4 compared to the case where wiring patterns are arranged separately from rescue circuit 401 to each of selection circuits 301a, 301b, 302a, 302b. The same applies to combinations of other rescue circuits and selection circuits.

[0058] As described above, each of memories 201 to 204 subject to redundant rescue is configured to be connectable to two or more of rescue circuits 401 to 404 via corresponding selection circuits 301 to 304. On the other hand, selection circuits 301 to 304 are controlled based on selection information by one holding circuit 501. Therefore, the wiring patterns between holding circuit 501 and selection circuits 301a to 304d and the wiring patterns between selection circuits 301a to 304d and corresponding rescue circuits 401 to 404 can be reduced. That is, the complexity of the wiring patterns in block 101 is alleviated, and the layout design of block 101 may become easier. Also, the reduction of the wiring patterns can reduce the possibility of problems such as disconnection of the wiring patterns, and can realize an improvement in the yield of semiconductor device 11.

[0059] Here, with reference to FIG. 16, an application example of the semiconductor device 11 of the present embodiment will be described. FIG. 16 is a schematic diagram of a device 9191 including the semiconductor device 11. Here, it will be described on the assumption that the semiconductor device 11 includes a pixel region 200 in which pixels 201 are arranged. Also, a case where a photoelectric conversion element is arranged in each of the pixels 201 will be described. That is, the semiconductor device 11 is a so-called photoelectric conversion device. In that case, the semiconductor device 11 can also be called an imaging device. The semiconductor device 11 is housed in a package 920 in the device 9191. The device 9191 may include at least any one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. However, the semiconductor device 11 arranged in the device 9191 is not limited to a photoelectric conversion device, and may function as a light emitting device, a processing device, a storage device, etc. as long as it includes a memory that is a target of redundancy relief as described above. The device 9191 may include, for example, the semiconductor device 11 and a processing device that processes a signal output from the semiconductor device 11.

[0060] Hereinafter, the device 9191 including the semiconductor device 11 that functions as a photoelectric conversion device shown in FIG. 16 will be described in detail. The package 920 can include a base on which the semiconductor device 11 is fixed and a lid such as glass facing the semiconductor device 11. The package 920 can further include a bonding member such as a bonding wire or a bump that connects a terminal provided on the base and a pad provided on the semiconductor device 11.

[0061] The device 9191 can include at least any one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 is, for example, a lens, a shutter, or a mirror. The control device 950 controls the semiconductor device 11. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0062] The processing device 960 processes the signals output from the semiconductor device 11. The processing device 960 is a semiconductor device such as a CPU or an ASIC for constituting an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays the information (image) obtained by the semiconductor device 11 functioning as a photoelectric conversion device. The storage device 980 is a magnetic device or a semiconductor device that stores the information (image) obtained by the semiconductor device 11. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0063] The mechanical device 990 has a movable part or a propulsion part such as a motor or an engine. In the device 9191, the signals output from the semiconductor device 11 are displayed on the display device 970 or transmitted to the outside by a communication device (not shown) provided in the device 9191. For this purpose, the device 9191 may further include a storage device 980 and a processing device 960 separately from the storage circuit and the arithmetic circuit of the semiconductor device 11. The mechanical device 990 may be controlled based on the signals output from the semiconductor device 11.

[0064] Also, the device 9191 is suitable for electronic devices such as an information terminal having a photographing function (for example, a smartphone or a wearable terminal) or a camera (for example, a single-lens reflex camera, a compact camera, a video camera, a surveillance camera). The mechanical device 990 in the camera can drive the components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 11 for anti-vibration operation.

[0065] Also, the device 9191 can be a transportation device such as a vehicle, a ship, or an airplane. The mechanical device 990 in the transportation device can be used as a moving device. The device 9191 as a transportation device is suitable for transporting the semiconductor device 11 or for assisting and / or automating driving (operation) by means of a photographing function. The processing device 960 for assisting and / or automating driving (operation) can perform processing for operating the mechanical device 990 as a moving device based on the information obtained by the semiconductor device 11. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analysis device such as an electron microscope, or an office device such as a copying machine.

[0066] The disclosure of this specification includes the following semiconductor device and device.

[0067] (Item 1) A memory cell array including a plurality of memories each of which is a volatile memory and arranged over a plurality of rows and columns, A plurality of repair circuits for repairing the memory cell array, A selection circuit for selecting a repair circuit connected to a memory included in the plurality of memories among the plurality of repair circuits, A holding circuit that holds selection information for the selection circuit to select a specified repair circuit among the plurality of repair circuits and controls the selection circuit based on the selection information, A semiconductor device characterized by comprising:

[0068] (Item 2) The semiconductor device according to Item 1, wherein the holding circuit controls the selection circuit based on the selection information supplied from the outside of the semiconductor device.

[0069] (Item 3) Further including an analysis circuit for analyzing the state of the memory, The semiconductor device according to Item 1, wherein the analysis circuit generates the selection information based on the state of the memory and supplies it to the holding circuit.

[0070] (Item 4) The semiconductor device according to item 3, wherein after generating the selection information based on the state of the memory, the analysis circuit further analyzes the state of each of the memory and the redundancy circuits connected to the memory among the plurality of redundancy circuits.

[0071] (Item 5) The semiconductor device according to item 4, wherein the analysis circuit changes the selection information when it is necessary to change the selection information according to the state of each of the memory and the redundancy circuits connected to the memory among the plurality of redundancy circuits, and supplies the changed selection information to the holding circuit.

[0072] (Item 6) The selection circuit is used as a first selection circuit, and further includes a second selection circuit, The memory is used as a first memory, and the plurality of memories include a second memory, The first memory is configured to be connectable to a first redundancy circuit and a second redundancy circuit among the plurality of redundancy circuits via the first selection circuit, The semiconductor device according to any one of items 1 to 5, wherein the second memory is configured to be connectable to the first redundancy circuit and a third redundancy circuit among the plurality of redundancy circuits via the second selection circuit.

[0073] (Item 7) Further includes a third selection circuit and a fourth selection circuit, The plurality of memories include a third memory and a fourth memory, The third memory is configured to be connectable to the second redundancy circuit and a fourth redundancy circuit among the plurality of redundancy circuits via the third selection circuit, The semiconductor device according to item 6, wherein the fourth memory is configured to be connectable to the third redundancy circuit and the fourth redundancy circuit among the plurality of redundancy circuits via the fourth selection circuit.

[0074] (Item 8) Further includes a fifth selection circuit, The plurality of memories includes a fifth memory, and the fifth memory is configured to be connectable to the first and second of the plurality of recovery circuits via the fifth selection circuit. The semiconductor device according to item 6 or 7, wherein the first selection circuit and the fifth selection circuit are controlled to select the same recovery circuit among the plurality of recovery circuits.

[0075] (Item 9) further includes a sixth selection circuit, the plurality of memories includes a sixth memory, and the sixth memory is configured to be connectable to the first and third of the plurality of recovery circuits via the sixth selection circuit. The semiconductor device according to item 8, wherein the second selection circuit and the sixth selection circuit are controlled to select the same recovery circuit among the plurality of recovery circuits.

[0076] (Item 10) The semiconductor device according to any one of items 1 to 9, wherein each of the plurality of memories is an SRAM.

[0077] (Item 11) A semiconductor device according to any one of items 1 to 10, a processing device that processes a signal output from the semiconductor device, and a device comprising the same.

[0078] The invention is not limited to the above embodiments, and various changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, the claims are appended to disclose the scope of the invention.

Explanation of Reference Numerals

[0079] 11: Semiconductor device, 201 - 204: Memories, 301 - 304: Selection circuits, 401 - 404: Recovery circuits, 501: Holding circuit

Claims

1. A memory cell array including a plurality of memories each being a volatile memory and arranged over a plurality of rows and a plurality of columns, a plurality of repair circuits for repairing the memory cell array, a selection circuit for selecting a repair circuit connected to a memory included in the plurality of memories among the plurality of repair circuits, a holding circuit for holding selection information for the selection circuit to select a specified repair circuit among the plurality of repair circuits and controlling the selection circuit based on the selection information; A semiconductor device characterized by comprising the above.

2. The semiconductor device according to claim 1, wherein the holding circuit controls the selection circuit based on the selection information supplied from outside the semiconductor device.

3. Further including an analysis circuit for analyzing the state of the memory, wherein the analysis circuit generates the selection information based on the state of the memory and supplies the selection information to the holding circuit.

4. The semiconductor device according to claim 3, wherein after generating the selection information based on the state of the memory, the analysis circuit further analyzes the state of each of the memory and the repair circuit connected to the memory among the memory and the plurality of repair circuits.

5. The semiconductor device according to claim 4, wherein the analysis circuit changes the selection information when it is necessary to change the selection information according to the state of each of the memory and the repair circuit connected to the memory among the memory and the plurality of repair circuits, and supplies the changed selection information to the holding circuit.

6. The selection circuit is used as a first selection circuit, and further includes a second selection circuit, the memory is used as a first memory, and the plurality of memories include a second memory, the first memory is configured to be connectable to a first repair circuit and a second repair circuit among the plurality of repair circuits via the first selection circuit, the semiconductor device according to claim 1, wherein the second memory is configured to be connectable to the first repair circuit and a third repair circuit among the plurality of repair circuits via the second selection circuit.

7. Further including a third selection circuit and a fourth selection circuit, the plurality of memories include a third memory and a fourth memory, the third memory is configured to be connectable to the second repair circuit and a fourth repair circuit among the plurality of repair circuits via the third selection circuit, The semiconductor device according to claim 6, wherein the fourth memory is configured to be connectable to the third and fourth of the plurality of recovery circuits via the fourth selection circuit.

8. further comprising a fifth selection circuit, wherein the plurality of memories includes a fifth memory, the fifth memory is configured to be connectable to the first and second of the plurality of recovery circuits via the fifth selection circuit, The semiconductor device according to claim 6, wherein the first selection circuit and the fifth selection circuit are controlled to select the same recovery circuit among the plurality of recovery circuits.

9. further comprising a sixth selection circuit, wherein the plurality of memories includes a sixth memory, the sixth memory is configured to be connectable to the first and third of the plurality of recovery circuits via the sixth selection circuit, The semiconductor device according to claim 8, wherein the second selection circuit and the sixth selection circuit are controlled to select the same recovery circuit among the plurality of recovery circuits.

10. The semiconductor device according to claim 1, wherein each of the plurality of memories is a SRAM.

11. A semiconductor device according to any one of claims 1 to 10, a processing device that processes a signal output from the semiconductor device, and a device characterized by comprising the same.

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