Automated transistor-level placement for design of integrated circuit

Abstract

To provide a computer-implemented method for designing an integrated circuit using transistor placement optimization.SOLUTION: A computing system receives a specification for an integrated circuit. The specification includes a netlist describing a plurality of transistors and connections between terminals of the plurality of transistors. The computing system determines an initial location and an orientation on a canvas for each transistor in the plurality of transistors. The computing system uses an objective function based at least in part on the initial locations and the orientations of the plurality of transistors to generate a rough placement having globally optimized locations and orientations for the plurality of transistors. The computing system uses a local refinement technique to optimize the rough placement to generate a fine placement, and uses a routing technique to generate a routing for the fine placement to generate a completed design.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] Cross - reference to Related Applications This application claims the benefit of U.S. patent application Ser. No. 17 / 957,621, filed Sep. 30, 2022, and U.S. Provisional Application No. 63 / 310,675, filed Feb. 16, 2022, the contents of both of which are incorporated herein by reference.

[0002] The present disclosure generally relates to techniques for integrated circuit design, and more particularly, but not limited to, iterative optimization of transistor placement in an integrated circuit layout.

Background Art

[0003] Conventional approaches to integrated circuit design include rule - based placement engines that refer to one or more software applications that determine the optimal or nearly optimal placement of standard cells or hard macros, rather than individual transistors. In the context of integrated circuit design, a standard cell represents a group of transistors that provide a Boolean logic function (such as AND, OR, XOR, XNOR, inverter, etc.) or a memory function (such as flip - flop or latch) and an interconnection structure. Similarly, a “hard macro” refers to a block - level placement of transistors that has been pre - verified for a given semiconductor manufacturing process (e.g., from the perspective of design rules). Thus, conventional transistor placement operates at a higher hierarchical level than individual transistors, and each object to be placed is either a standard cell or a hard macro, and each net represents a logical connection between objects (cells or macros) or various input / output pins associated with the inputs / outputs of the design, rather than individual transistors. Therefore, individual transistors are placed based on the placement of their respective standard cells or macros. Further, for transistors that do not host connections outside of a standard cell or macro, the net routing has already been determined.

[0004] Analytical formulations such as quadratic programming and nonlinear programming have become the mainstream solutions within commercial toolchains for handling standard cell-based designs. By focusing on placement at the standard cell or hard macro level, the need for formulations that directly and automatically facilitate design at the transistor level is not met. Transistor-level placement has been considered for the layout of standard cells and hard macros, and standard cells are typically relatively small in terms of the number of transistors, objects, and / or nets (<100). Nevertheless, conventional techniques for rule-based placement engines mostly ignore analytical formulations in favor of graph-based search or combinatorial solvers. Therefore, there is still a need for a transistor-level placement engine for integrated circuit design that is configured to optimize individual transistor placement for one or more analytical objectives and can operate automatically (e.g., without human intervention). SUMMARY OF THE INVENTION MEANS FOR SOLVING THE PROBLEM

[0005] In some embodiments, a computer-implemented method for designing an integrated circuit using transistor placement optimization is provided. A computing system receives a specification of the integrated circuit. The specification includes a netlist describing a plurality of transistors and connections between terminals of the plurality of transistors. The computing system determines an initial position and orientation on a canvas of each transistor within the plurality of transistors. The computing system uses an objective function that is at least partially based on the initial positions and orientations of the plurality of transistors to generate a rough placement having a globally optimized position and orientation of the plurality of transistors. The computing system uses a local refinement technique to optimize the rough placement to generate a detailed placement. The computing system uses a routing technique to generate a routing for the detailed placement to generate a completed design. The computing system stores the completed design in a layout data store.

[0006] In some embodiments, a non-transitory computer-readable medium storing computer-executable instructions is provided. The instructions, in response to execution by one or more processors of a computing system, cause the computing system to perform operations for designing an integrated circuit using transistor placement optimization, the operations including: receiving, by the computing system, a specification of the integrated circuit, the specification including a netlist describing a plurality of transistors and connections between terminals of the plurality of transistors; determining, by the computing system, an initial position and orientation on a canvas of each transistor within the plurality of transistors; using, by the computing system, an objective function based at least in part on the initial positions and orientations of the plurality of transistors to generate a rough placement having a globally optimized position and orientation of the plurality of transistors; using, by the computing system, a local refinement technique to optimize the rough placement to generate a detailed placement; using, by the computing system, a routing technique to generate routing for the detailed placement to generate a completed design; and storing, by the computing system, the completed design in a layout data store.

[0007] Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, in which like reference numerals refer to like parts throughout the various figures unless otherwise specified. Not all instances of elements are necessarily labeled, where appropriate, to avoid obscuring the drawings. The drawings are not necessarily to scale; rather, emphasis is placed on illustrating the principles being described.

Brief Description of the Drawings

[0008]

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DETAILED DESCRIPTION OF THE INVENTION

[0009] Embodiments of a computer-implemented method for transistor-level object placement described herein improve flexibility and control over transistor placement in an integrated circuit layout compared to standard cell and hard macro-based approaches, and as a result, improve the optimization of custom integrated circuits at the level of individual or arbitrarily grouped transistors.

[0010] Figure 1 is a schematic diagram of NMOS and PMOS transistors according to an embodiment of the present disclosure. Techniques for transistor placement can be implemented automatically and can include techniques for large-scale transistor-level placement to achieve a globally optimized solution. In such a formulation, it can be assumed that each object can be a transistor or any group of transistors (not limited to functional or manufacturable grouping), and each net represents a logical connection between transistors or grouped transistors or various input / output pins associated with the input / output of the design.

[0011] As shown in FIG. 1, the transistors are multi-terminal devices such as the illustrated three-terminal NMOS and PMOS transistors. As part of the design, each terminal of a transistor is connected to a respective net such as n1, n2,... n5. In some embodiments, as indicated by n2, individual nets can be connected to multiple transistors. In this way, a group of n transistors can be associated with a number of nets from n to 3n. A group of transistors, as opposed to standard cells or hard macros, can describe a hierarchical optimization strategy for segmenting a transistor placement matrix (e.g., the transistor placement matrix of FIG. 2) into smaller groups for parallelization or optimization of computing resources (e.g., in the context of a distributed computing system, a graphics processing unit (GPU), or other parallel computing resources).

[0012] As illustrated, the material characteristics of individual transistors can also provide information for the placement decisions described with reference to FIG. 2. For example, the transistors can be of N-type or P-type (e.g., NMOS or PMOS), and these two types of transistors can be used in a single integrated circuit to create a CMOS integrated circuit. As shown in FIG. 2, a given type of transistor can be limited to one or more specific regions of the transistor placement matrix.

[0013] Figure 2 is a schematic diagram of a transistor placement matrix according to an embodiment of the present disclosure. The transistor placement matrix is an example of a discretized data structure that arranges a set of transistors according to the coordinates of one or more dimensions and / or sub-dimensions (sub-dimensions refer to encoded dimensions that constrain the placement of a given transistor to a subset of coordinates) of a coordinate space. The coordinate space can then be mapped to the physical space on a CMOS substrate as part of the manufacture of a semiconductor integrated circuit. Thus, by optimizing the placement of transistors within this discretized coordinate space, the layout of transistors and nets in the integrated circuit can be improved with respect to one or more objectives.

[0014] As shown, the transistor placement matrix can correspond to a discretized Cartesian coordinate space (e.g., a quantized x-y space). In this scheme, any i-th transistor is placed at (x i , y i ). As shown, a set of transistors can include an NMOS 202 at the coordinates (0,0) shown by the solid line and a PMOS 204 at the coordinates (3,2) shown by the dashed line.

[0015] Optimizing the positions of a set of transistors in the transistor placement matrix can help improve the performance, reliability, cost, and manufacturability of the resulting integrated circuit. However, typical transistor-level optimization techniques use combinatorial methods that do not scale when the total number of transistors is small (e.g., on the order of 100 transistors), and this is perhaps one of the reasons why optimization techniques have not been widely applied at the transistor level in the past, rather than at the cell level with a small number. The optimization techniques can still be used in small partitions of the transistor placement matrix, but without considering the entire transistor placement matrix at once, it is unlikely to find a globally optimal solution.

[0016] In embodiments of the present disclosure, an optimization technique is provided that can be efficiently applied to all components specified in a netlist to generate an optimal rough layout in a discretized placement matrix (instead of requiring operations on smaller partitions). Then, to create an optimal layout for providing to a fabrication system, the rough layout can be partitioned and processed using conventional methods. By creating a rough layout using a technique that first considers an optimal solution for the entire layout before optimizing the partitions, a better overall layout is achieved.

[0017] FIG. 3 is a block diagram showing aspects of a non-limiting exemplary embodiment of a layout computing system according to various aspects of the present disclosure. The illustrated layout computing system 310 can be implemented by any computing device or collection of computing devices including, but not limited to, a desktop computing device, a laptop computing device, a mobile computing device, a server computing device, a computing device of a cloud computing system, and / or combinations thereof. The layout computing system 310 is configured to receive a netlist specifying a plurality of components and to optimize the layout of the components within the netlist. In some embodiments, the layout computing system 310 can provide a user interface that enables manual modification of the optimized layout. In some embodiments, the layout computing system 310 can provide an optimized layout to a fabrication system for fabricating the represented integrated circuit.

[0018] As shown, the layout computing system 310 includes one or more processors 302, one or more communication interfaces 304, a layout data store 308, and a computer-readable medium 306.

[0019] In some embodiments, the processor 302 may include any suitable type of general-purpose computer processor. In some embodiments, the processor 302 may include one or more dedicated computer processors or AI accelerators optimized for specific computing tasks, including but not limited to a graphics processing unit (GPU), a vision processing unit (VPT), and a tensor processing unit (TPU).

[0020] In some embodiments, the communication interface 304 includes one or more hardware and / or software interfaces suitable for providing communication links between components. The communication interface 304 may support one or more wired communication technologies (including but not limited to Ethernet, FireWire, and USB), one or more wireless communication technologies (including but not limited to Wi-Fi, WiMAX, Bluetooth, 2G, 3G, 4G, 5G, and LTE), and / or combinations thereof.

[0021] As shown, the computer-readable medium 306 stores logic that, in response to execution by one or more processors 302, causes the layout computing system 310 to provide a layout management engine 312, an analysis layout engine 314, a simulated annealing layout engine 316, and a user interface engine 318.

[0022] As used herein, "computer-readable medium" refers to any removable or non-removable device that implements any technology capable of storing information in a volatile or non-volatile manner so as to be readable by a processor of a computing device, including, but not limited to, hard drives, flash memories, solid state drives, random access memories (RAMs), read-only memories (ROMs), CD-ROMs, DVDs, or other disk storage devices, magnetic cassettes, magnetic tapes, and magnetic disk storage devices.

[0023] In some embodiments, the layout management engine 312 is configured to manage a layout optimization process executed by other components of the layout computing system 310 before receiving a netlist and storing the optimized layout in the layout data store 308. In some embodiments, the user interface engine 318 is configured to generate a visual presentation of the optimized layout stored in the layout data store 308 and receive and process manual adjustments to the optimized layout.

[0024] In some embodiments, the analytical layout engine 314 is configured to generate a rough layout using analytical techniques. In some embodiments, the simulated annealing layout engine 316 is configured to generate a rough layout using simulated annealing techniques. Since the analytical techniques and the simulated annealing techniques are alternatives, in some embodiments, only one or the other of the analytical layout engine 314 and the simulated annealing layout engine 316 may be present.

[0025] The configurations of each of these components will be further described below.

[0026] As used herein, "engine" refers to logic embodied in hardware instructions or software instructions that can be written in one or more programming languages including, but not limited to, C, C++, C#, COBOL, JAVA®, PHP, Perl, HTML, CSS, JavaScript, VBScript, ASPX, Go, and Python. The engine may be compiled into an executable program or may be written in an interpreted type programming language. The software engine may be called from other engines or from itself. In general, the engines described herein refer to logical modules that can be merged with other engines or divided into sub-engines. The engine is implemented by logic stored in any type of computer-readable medium or computer storage device, stored and executable on one or more general-purpose computers, and thus creates a dedicated computer configured to provide the engine or its functionality. The engine may be implemented by logic programmed in an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or another hardware device.

[0027] As used herein, "data store" refers to any suitable device configured to store data for access by a computing device. An example of a data store is a highly reliable, high-speed relational database management system (DBMS) that runs on one or more computing devices and is accessible via a high-speed network. Another example of a data store is a key-value store. However, any other suitable storage technique and / or device that can quickly and reliably provide the stored data in response to a query may be used, and the computing device may be accessible locally rather than via a network, or may be provided as a cloud-based service. A data store may also include data stored in an organized manner on a computer-readable storage medium, such as a hard disk drive, flash memory, RAM, ROM, or any other type of computer-readable storage medium. One of ordinary skill in the art will recognize that the separate data stores described herein can be combined into a single data store and / or the single data store described herein can be separated into multiple data stores without departing from the scope of the present disclosure.

[0028] Figure 4 is a flowchart showing a non-limiting, exemplary embodiment of a method of laying out a plurality of transistors for fabricating an integrated circuit, according to various aspects of the present disclosure. In method 400, an analysis technique or a simulated annealing technique is used to optimize the overall transistor layout to generate a gross placement. This gross placement is more globally optimized than what was possible using previous techniques and is then partitioned to generate a finished design suitable for fabrication.

[0029] From the start block, method 400 proceeds to block 402 where the layout management engine 312 of the layout computing system 310 receives a specification of an integrated circuit that includes a netlist. In some embodiments, the entries of the netlist include, but are not limited to, information regarding transistors within the integrated circuit, including the type of each transistor (e.g., NMOS or PMOS) and the identification of the nets connected to each terminal of each transistor. In some embodiments, the specification can also identify additional characteristics of the integrated circuit, including, but not limited to, the footprint of the integrated circuit and physical restrictions on various portions of the footprint (e.g., regions where only NMOS transistors can be placed and regions where only PMOS transistors can be placed). In some embodiments, the specification includes a transistor list and the nets are included as metadata within the list. In some embodiments, the specification can be, include, or be included within a data structure such as an integrated circuit configuration file.

[0030] At block 404, the layout management engine 312 determines an initial position on the canvas for the transistors within the netlist. In some embodiments, the size and / or dimensions of the canvas can be determined by information provided by the specification. The initial position on the canvas can be specified in a continuous coordinate system (e.g., the horizontal and vertical coordinates of each transistor can be specified with real values instead of, or in addition to, integer values). In some embodiments, the initial position can be randomly distributed across the entire canvas, randomly distributed with weights applied to transistors connected to matching nets, made the output of another type of optimization, or distributed using other suitable techniques.

[0031] FIG. 5 is a schematic diagram of a non-limiting exemplary embodiment of a canvas after the initial positions of transistors have been determined according to various aspects of the present disclosure. As shown, NMOS transistors (shown in solid lines) and PMOS transistors (shown in dashed lines) are randomly arranged throughout canvas 502. Also, as shown, the transistors are arranged using a continuous coordinate system, which is evident by the horizontal and vertical directions of the positions overlapping. The initial positions may or may not be valid positions from a manufacturability perspective, but function as an initial state for subsequent optimization.

[0032] Returning to FIG. 4, method 400 then proceeds to subroutine block 406, where layout management engine 312 provides the canvas to either the analytical layout engine 314 of layout computing system 310 or the simulated annealing layout engine 316 of layout computing system 310 to perform procedures for generating a rough placement that includes optimization of the orientation of the transistors. One aspect of the layout of transistors compared to the layout of other types of components (e.g., cells) is that a three-terminal transistor can be arranged in at least one of two orientations. For example, in FIG. 1, the left terminal of the NMOS transistor coupled to net N1 can be the source terminal, and the right terminal of the NMOS transistor coupled to net N3 can be the drain terminal. However, when laying out this transistor, it may be inverted so that the drain terminal coupled to N3 is on the left and the source terminal coupled to N1 is on the right. In embodiments of the present disclosure, in addition to considering the positions, the optimization for generating a rough placement can consider inverting one or more transistors to improve the overall layout.

[0033] In some embodiments, the rough placement is in a discretized coordinate system (e.g., the horizontal and vertical coordinates of each transistor are specified as integer values) rather than the continuous coordinate system used for the initial placement. Since the discretized coordinate system can be used as an input in future steps of method 400 (including, but not limited to, fabrication systems), the procedure executed in subroutine block 406 can convert from the continuous coordinate system to the discretized coordinate system to generate a rough placement to enable subsequent operations of method 400.

[0034] Non-limiting exemplary embodiments of suitable procedures performed by the analytical layout engine 314 to generate a rough placement using analytical techniques are shown in FIG. 6. Non-limiting exemplary embodiments of suitable procedures performed by the simulated annealing layout engine 316 to generate a rough placement using simulated annealing techniques are shown in FIG. 8. Both exemplary procedures are described in more detail below.

[0035] In block 408, the layout management engine 312 partitions and optimizes the rough placement to generate a detailed placement. In some embodiments, one or more conventional techniques applicable to transistor-level optimization, including, but not limited to, general combinatorial search schemes, including, but not limited to, satisfiability modulo theory (SMT), mixed integer programming (MIP), graph search, branch and bound, and dynamic programming, can be used to optimize the partitions. Optimization factors for power, performance, and area can be approximated by other objectives, including, but not limited to, interconnect length and diffusion sharing.

[0036] In block 410, the layout management engine 312 routes the detailed placement to generate a completed design. Any suitable router can be used, including but not limited to maze routers, line probe routers, pattern routers, channel routers, or gridless routers, and any suitable routing technique can be used, including but not limited to rip-up and reroute techniques or iterative improvement routing methods. Techniques for routing the detailed placement to generate a completed design are known to those of ordinary skill in the art and are not described in further detail herein for the sake of brevity.

[0037] Since determining the positions of the transistors and the paths of the connections between the transistors are two objectives of method 400, placement and routing are described as separate tasks in blocks 406-410 for clarity. However, placement and routing are considered separate aspects of a single problem in integrated circuit design that can affect each other. Thus, in some embodiments, a routing step may follow the placement step, and then one or more additional iterations of the placement step may follow (e.g., if it is determined that the initial placement is not routable in the routing step). Further, in some embodiments, the placement and routing problems are considered simultaneously by a combinatorial optimization device, and at least some blocks of the integrated circuit are placed and routed simultaneously.

[0038] In block 412, the layout management engine 312 stores the completed design in the layout data store 308 of the layout computing system 310. In some embodiments, the layout management engine 312 may not store the completed design in the layout data store 308 but instead immediately pass it to other components of the layout computing system 310. However, by storing the completed design in the layout data store 308, the layout computing system 310 may be able to update or reuse the completed design without having to repeat the optimization steps described above.

[0039] In block 414, the user interface engine 318 of the layout computing system 310 presents the completed design, receives one or more manual updates to the completed design, and stores the updated design in the layout data store 308. Often, it may be desirable to make manual adjustments to the completed design. For example, the user may wish to add one or more components to the completed design, remove one or more components from the completed design, add input ports or output ports or vias to the completed design so that the resulting integrated circuit can communicate with other devices, adjust the position of one or more components to enhance interoperability with other devices, and / or make various other types of changes. In some embodiments, the user interface engine 318 receives instructions for such changes and responds by adjusting the completed design while ensuring that any design rules are satisfied.

[0040] In some embodiments, the user interface can include an interactive and / or searchable transistor map that can be used to identify connected transistors that would conventionally be replaced with cell representations in mapping or otherwise grouped (e.g., into Boolean logic functions). Thus, the user interface can include a search tool configured to query the completed design and return a subset of transistors and / or nets according to the query terms. The user interface can update the presentation of the transistor map to visually highlight the subset of transistors and / or nets that match the query terms. Additionally or alternatively, the user interface can include data or information useful to the user of the environment, such as the value of an objective / loss function as a function of the number of iterations to determine convergence, a qualitative or quantitative determination of convergence, etc. Similarly, the layout management engine 312 can interact with the user interface to facilitate at least partial manual input regarding one or more transistors. For example, during the iteration of auto-correction, the user can insert additional transistors, delete transistors, modify the netlist, manually reset the coordinates and / or orientation of the transistors, and / or add soft or hard area fences around transistor groups.

[0041] In block 416, the layout management engine 312 provides the design from the layout data store 308 to the fabrication system to fabricate the integrated circuit. Any type of fabrication system capable of fabricating an integrated circuit can be used, including but not limited to a photolithography system.

[0042] The method 400 then proceeds to the end block and ends.

[0043] Figure 6 shows a non-limiting, exemplary embodiment of a procedure for generating a rough layout using analysis techniques, according to various aspects of the present disclosure. In procedure 600, the analysis technique utilizes the differentiability of operations in a continuous coordinate space to optimize the positions of transistors, and then converts the positions in the continuous coordinate space to positions in a discrete coordinate space for use in further operations of calling method 400.

[0044] Starting from the start block, procedure 600 proceeds to block 602, where analysis layout engine 314 optimizes the transistor positions in the continuous coordinate space using a loss function that may include terms related to the orientation of the transistors.

[0045] In some embodiments, the optimization minimizes the value of a loss function (also referred to as an objective function) by perturbing a design point (e.g., the position of a transistor in the continuous coordinate space) until a minimum value of the value is found (or until a predetermined number of iterations are performed). In some embodiments, perturbing the design point includes inverting the orientation of one or more transistors. In some embodiments, the loss function may include terms representing the orientation of one or more transistors. Subsequent design points can be found using any suitable optimization technique, including but not limited to gradient descent methods, genetic algorithms, and combinations thereof. By using the continuous coordinate space at this point in procedure 600, iterative techniques such as gradient descent can be effectively used even if the positions in the continuous coordinate space cannot be used for fabrication.

[0046] The loss function may include one or more terms for convergence purposes. An example of a convergence objective for optimization is the weighted sum of the half-perimeter wire length (HPWL). Regarding the weighting coefficient, w ij is defined as the weight of the net, and the weighted sum of HPWL is Σw ij *(|x i -x j | + |y i -y jFormulated as (), which can be approximated using quadratic equations or other non - linear objectives (e.g., distances can be constrained to straight - line routing rules, shortest straight - line paths can be used, curve rules incorporating manufacturability limitations of the radius of curvature can also be included, etc.). Additional or alternative convergence objectives include, but are not limited to, interconnect length, transistor density, routability, timing, power, manufacturability, etc.

[0047] The objective can be used to estimate the optimization factors of power, performance, and area. The weighting factor w ij can be net - specific for a given net connecting transistors “i” and “j”. In some embodiments, a given net can connect more than two transistors. Thus, the weighting factor w ijk can be defined for a net connected to three transistors and logically extended to nets connecting more than three transistors. In some embodiments, transistor - specific weighting is applied, and a weight can be assigned to a given transistor “i” to make its influence on the overall layout of the set of transistors relatively large or small. For example, if transistor density is used as an objective function, individual weights w i can be given to each transistor.

[0048] In some embodiments, the weight w i can be defined in terms of a density function d i that defines the numerical probability that a transistor is placed in a given matrix space. The density function d i can also depend at least in part on the number of transistors within a given interval of transistor t i (e.g., as the density of transistors within a given region of the placement matrix increases, the probability of placing transistor t i decreases).

[0049] In some embodiments, one or more constraints can be applied to prevent the transistor placement matrix from converging to a non - physical solution (e.g., two different transistors occupying the same physical space). For example, a size within a coordinate space and / or an exclusion radius within the coordinate space (e.g., a zero - dimensional size with an exclusion radius of (1,1)) can be assigned to a transistor, and the term "exclusion radius" refers to the spacing around a given transistor "i" that other transistors "j" are not allowed in. The spacing can be defined in spatial dimensions (e.g., physical terms in a two - dimensional plane) or in coordinate space (e.g., indexical terms relative to the coordinates of the transistor). In an example, transistor t i can be given an exclusion radius of two grid spacings in the x - y space, and for a second transistor t j coordinates up to two units away from the position of the transistor are not assigned. In some embodiments, the same size can be assigned to each transistor within a set of transistors, corresponding to the physical state of the transistors in the fabricated integrated circuit. In some embodiments, different sizes and / or exclusion distances are assigned to the transistors.

[0050] As an approach to reduce the complexity of the calculations for applying the constraints, the objective function (e.g., the HPWL described above) can be modified to include penalty terms. For example, constraints regarding physical space (e.g., non - overlapping transistor rules) can be relaxed into the objective function using penalty terms. Similarly, local refinement steps can be included to optimize the placement of the transistors, for example, as part of optimizing power, performance, and / or area. In an example, as part of reducing the overall area of an integrated circuit containing thousands of transistors, a subset of the transistors can be moved or otherwise shifted.

[0051] Once the optimal position and orientation are determined by the optimization technique in block 602, procedure 600 then converts the position from the continuous coordinate space to the discrete coordinate space. Thus, procedure 600 proceeds to block 604 where the analytical layout engine 314 sorts the transistors in the continuous coordinate space in the horizontal and vertical directions. To do so, the analytical layout engine 314 can compare the positions of the transistors to each other and create two lists: a first list sorted in order based on the horizontal axis position of the transistors, and a second list sorted in order based on the vertical axis position of the transistors. Additional lists can be used if there are more or fewer dimensions present at that location.

[0052] In block 606, the analytical layout engine 314 places the transistors into multiple rows of the discrete coordinate space according to the vertical sort and into multiple columns of the discrete coordinate space according to the horizontal sort to generate a preliminary discrete layout. In some embodiments, the analytical layout engine 314 can determine the number of available rows in the discrete coordinate space and the number of transistors to be placed in each row to evenly distribute the transistors across the rows, and the number of transistors to be placed in each column to evenly distribute the transistors across the columns. The analytical layout engine 314 then processes the list of transistors sorted by vertical position to place the transistors into rows (e.g., if three transistors are placed in each row, the first three transistors in the list are assigned to the first row, the next three transistors in the list are assigned to the second row, and so on), and then, similarly, processes the list of transistors sorted by horizontal position to place the transistors into columns (e.g., if five transistors are placed in each column, the first five transistors in the list are placed in the first column, the next five transistors in the list are placed in the second column, and so on). In some embodiments, the placement at this point may take into account these constraints (and / or other fabrication constraints) if a particular location is restricted to a particular type of transistor (e.g., PMOS vs. NMOS).

[0053] FIG. 7 is a schematic diagram of a non-limiting exemplary embodiment of a layout in a discrete coordinate space according to various aspects of the present disclosure. In layout 702, the canvas is divided into individual rows and columns. The rows include pairs of rows where only PMOS transistors (shown by dashed lines) can be placed, and pairs of rows where only NMOS transistors (shown by solid lines) can be placed. The operation of block 606 spreads the transistors to discrete positions defined by the rows and columns.

[0054] Returning to FIG. 6, in block 608, the analysis layout engine 314 uses a combinatorial optimizer that can take into account the orientation of the transistors to convert the preliminary discrete layout into a rough layout. To complete the combinatorial optimization in a reasonable amount of time, similar to conventional techniques, the discrete coordinate space can be partitioned into smaller areas. To reduce the problem to a reasonable size, even if combinatorial optimization techniques are applied to smaller partitions of a large layout problem, in previous techniques, the global optimization described above is not applied first, and therefore the partitioned optimization is not effective for the overall design and cannot be used for the layout of a large number of individual transistors in an integrated circuit design. Those skilled in the art are proficient in applying combinatorial techniques to small partitions of integrated circuit design, and for the sake of brevity, further details of these operations are not described herein.

[0055] Next, procedure 600 proceeds to an end block and returns control to the caller.

[0056] FIG. 8 is a flowchart showing a non-limiting exemplary embodiment of a procedure for generating a rough layout using a simulated annealing technique according to various aspects of the present disclosure. In procedure 800, a simulated annealing technique that can operate efficiently on a discrete coordinate space is used to optimize the positions of the transistors.

[0057] From the start block, procedure 800 proceeds to block 802 where the simulated annealing layout engine 316 converts the initial positions of the transistors into a discrete coordinate space. In some embodiments, sorting techniques as described in blocks 604 - 606 of FIG. 6 can be used to convert from the continuous coordinate space of the initial positions to the discrete coordinate space. In some embodiments, the initial positions may be provided directly in the discrete coordinate space.

[0058] At block 804, the simulated annealing layout engine 316 uses simulated annealing techniques to optimize the positions of the transistors within the discrete coordinate space to create a preliminary discrete layout, and the moves of the simulated annealing techniques can include changing the orientation of the transistors. In the simulated annealing techniques, a loss function similar to that described in block 602 can be optimized, but instead of using gradient techniques to perturb the design points, iterations are performed where the loss function is used to evaluate one or more neighborhoods of the current state, and probabilistic decisions are made to determine whether to move to a neighboring state or stay in the current state. The neighborhood is determined by changing the positions of one or more transistors and can also include changing the orientation of one or more transistors.

[0059] At block 806, the simulated annealing layout engine 316 uses a combinatorial optimizer to convert the preliminary discrete layout into a rough layout. As in block 608, conventional partitioning and combinatorial optimization techniques can be used to convert the preliminary discrete layout into a rough layout.

[0060] Procedure 800 then proceeds to the end block and returns control to the caller.

[0061] As part of the techniques described herein, analytical formulations for standard cell-based placement can be adapted to transistor-level placement. For example, orientation, grouping, routingability constraints, and / or per-group weighting can be implemented to give flexibility to transistor placement. In contrast to the standard cell hierarchies conventionally applied in the industry, transistor-level placement improves the optimization process by decoupling transistor positions from the grouping of Boolean logic functions. In this way, a balance can be struck between local deviations from the optimal placement and the overall improvement to the overall placement of the transistors. In contrast, conventional tools are limited to the placement of standard cells rather than transistors, and the flexibility regarding the placement of individual transistors at the integrated circuit scale is limited, such that cell-scale optimization is prioritized over IC-scale optimization. Therefore, directly placing transistors at a scale of over 1000 transistors was previously rare and was done manually.

[0062] In the foregoing description, numerous specific details are set forth in order to provide a thorough understanding of various embodiments of the present disclosure. However, one of ordinary skill in the art will recognize that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0063] Throughout this specification, the mention of "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0064] In each of the method flowcharts, the order in which some or all of the blocks appear is not to be considered limiting. Rather, those skilled in the art having the benefit of this disclosure will understand that the operations associated with some of the blocks may be performed in various orders not illustrated, or in parallel.

[0065] The processes described above have been described from the perspective of computer software and hardware. The described techniques can comprise machine-executable instructions embodied within a tangible or non-transitory machine (e.g., a computer) readable storage medium, which instructions, when executed by a machine, cause the machine to perform the described operations. Additionally, the processes can be embodied within hardware such as an application specific integrated circuit (ASIC).

[0066] The foregoing description of the illustrated embodiments of the invention, including what is set forth in the summary, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Specific embodiments and examples of the invention are described herein for illustrative purposes, but various modifications are possible within the scope of the invention as will be recognized by those of ordinary skill in the art.

[0067] In light of the above detailed description, these modifications can be made to the present invention. The terms used in the following claims are not to be construed as limiting the invention to the specific embodiments disclosed herein. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with the established principles of claim interpretation.

Description of Reference Numerals

[0068] 202 NMOS 204 PMOS 302 Processor 304 Communication Interface 306 Computer Readable Medium 308 Layout Data Store 310 Layout Computing System 312 Layout Management Engine 314 Analytical Layout Engine 316 Simulated Annealing Layout Engine 318 User Interface Engine 400 Method 502 Canvas 600 Procedure 702 Layout 800 Procedure

Claims

1. A computer-implemented method for designing an integrated circuit using transistor placement optimization, comprising: receiving, by a computing system, a specification of the integrated circuit, the specification including a netlist describing a plurality of transistors and connections between terminals of the plurality of transistors; determining, by the computing system, an initial position and orientation on a canvas for each transistor within the plurality of transistors; generating, by the computing system, a rough placement having globally optimized positions and orientations for the plurality of transistors using an objective function based at least in part on the initial positions and the orientations of the plurality of transistors; optimizing, by the computing system, the rough placement using a local refinement technique to generate a detailed placement; generating, by the computing system, routing for the detailed placement using a routing technique to generate a completed design; storing, by the computing system, the completed design in a layout data store A computer-implemented method comprising the steps above.

2. The computer-implemented method of claim 1, further comprising providing the completed design to a fabrication system for fabrication of the integrated circuit.

3. generating a user interface based on at least one of the rough placement, the detailed placement, and the completed design; receiving, via the user interface, a query including one or more query terms; updating the user interface to visually highlight at least one of a subset of transistors or a subset of nets that match the query terms The computer-implemented method of claim 1, further comprising the steps above.

4. receiving, via the user interface, instructions for adding a transistor, deleting a transistor, modifying the netlist, modifying the position of a transistor, modifying the orientation of a transistor, or adding a region fence around a group of transistors Updating at least one of the rough layout, the detailed layout, and the completed design based on the command The computer-implemented method according to claim 3, further comprising

5. The step of generating the rough layout having the globally optimized positions and orientations of the plurality of transistors using the objective function Optimizing the positions of the plurality of transistors in a continuous coordinate space using an analysis technique Creating a preliminary discrete layout by converting the optimized positions of the plurality of transistors in the continuous coordinate space into positions in a discrete coordinate space The computer-implemented method according to claim 1, comprising

6. Converting the optimized positions of the plurality of transistors in the continuous coordinate space into positions in the discrete coordinate space Creating a sorted list of the plurality of transistors for each dimension of the canvas, the sorted list being arranged by the positions of the optimized positions of each transistor in the corresponding dimension Arranging the plurality of transistors in the discrete coordinate space according to the sorted list The computer-implemented method according to claim 5, comprising

7. The computer-implemented method according to claim 5, wherein the analysis technique includes a gradient descent technique

8. The step of generating the rough layout having the globally optimized positions and orientations of the plurality of transistors using the objective function Optimizing the positions of the plurality of transistors in a discrete coordinate space using a simulated annealing technique The computer-implemented method according to claim 1, comprising

9. The computer-implemented method according to claim 8, wherein at least one movement of the simulated annealing technique includes modifying the orientation of at least one transistor

10. The computer-implemented method according to claim 1, wherein the objective function includes a weighted half-perimeter wire length (HPWL) function

11. A computer-readable storage medium storing computer-executable instructions that, in response to execution by one or more processors of a computing system, cause the computing system to perform operations for designing an integrated circuit using transistor placement optimization, the operations comprising: receiving, by the computing system, a specification of the integrated circuit, the specification including a netlist describing a plurality of transistors and connections between terminals of the plurality of transistors; determining, by the computing system, an initial position and orientation on a canvas of each transistor within the plurality of transistors; generating, by the computing system, a rough placement having globally optimized positions and orientations of the plurality of transistors using an objective function based at least in part on the initial positions and the orientations of the plurality of transistors; optimizing, by the computing system, the rough placement using a local refinement technique to generate a detailed placement; generating, by the computing system, routing for the detailed placement using a routing technique to generate a completed design; storing, by the computing system, the completed design in a layout data store A computer-readable storage medium including the above. **Claim 12** The computer-readable storage medium of claim 11, wherein the operations further include providing the completed design to a fabrication system for fabrication of the integrated circuit. **Claim 13** The operations include: generating, based on at least one of the rough placement, the detailed placement, and the completed design, a user interface; receiving, via the user interface, a query including one or more query terms; updating the user interface to visually highlight at least one of a subset of transistors or a subset of nets that match the query terms The computer-readable storage medium of claim 11, further including the above. **Claim 14** The operations include: Receiving instructions via the user interface to add a transistor, delete a transistor, modify the netlist, modify the position of a transistor, modify the orientation of a transistor, or add an area fence around a group of transistors; Updating at least one of the rough layout, the detailed layout, and the completed design based on the instructions; The computer-readable storage medium according to claim 13, further comprising.

15. Generating the rough layout having the globally optimized positions and orientations of the plurality of transistors using the objective function; Optimizing the positions of the plurality of transistors in the continuous coordinate space using an analysis technique; Creating a preliminary discrete layout by converting the optimized positions of the plurality of transistors in the continuous coordinate space into positions in the discrete coordinate space; The computer-readable storage medium according to claim 11, comprising.

16. Converting the optimized positions of the plurality of transistors in the continuous coordinate space into positions in the discrete coordinate space; Creating a sorted list of the plurality of transistors for each dimension of the canvas, the sorted list being arranged by the positions of the optimized positions of each transistor in the corresponding dimension; the creating; Arranging the plurality of transistors in the discrete coordinate space according to the sorted list; The computer-readable storage medium according to claim 15, comprising.

17. The computer-readable storage medium according to claim 15, wherein the analysis technique includes a gradient descent technique.

18. Generating a rough layout having the globally optimized positions and orientations of the plurality of transistors using the objective function; Optimizing the positions of the plurality of transistors in the discrete coordinate space using a simulated annealing technique; The computer-readable storage medium according to claim 11, comprising.

19. The computer-readable storage medium according to claim 18, wherein at least one movement of the simulated annealing technique includes modifying the orientation of at least one transistor.

20. The computer-readable storage medium according to claim 11, wherein the objective function includes a weighted half-perimeter wire length (HPWL) function.

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