Multilayer ceramic capacitor

Abstract

To provide a multilayer ceramic capacitor that can increase the bonding strength between a laminate and an external electrode while suppressing the occurrence of delamination in a coating.SOLUTION: A multilayer ceramic capacitor includes a substantially rectangular parallelepiped laminate 2 including an active portion 3 formed by alternately stacking dielectric layers 4 and internal electrode layers 5, and a first covering portion 61 and a second covering portion 62 located at both ends of the active portion 3 in the stacking direction. The laminate has a first surface 7a and a second surface 7b facing each other in the stacking direction, a first end surface 8a and a second end surface 8b facing each other, and a first side surface and a second side surface facing each other. The first covering portion includes a first dielectric portion 61c and dummy electrodes 61a and 61b located at ends of the first dielectric portion in the X direction perpendicular to the first end surface. The dummy electrodes include multiple dummy electrode layers stacked directly on top of each other, are thicker than the internal electrode layers, are embedded in the first covering portion, and are exposed on the first surface.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a multilayer ceramic capacitor.

Background Art

[0002] The prior art of multilayer ceramic capacitors is described in, for example, Patent Document 1.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] The multilayer ceramic capacitor of the present disclosure is a substantially rectangular parallelepiped laminate including an active portion in which dielectric layers and internal electrode layers are alternately laminated, and a first covering portion and a second covering portion respectively located at both ends of the active portion in the lamination direction of the dielectric layers and the internal electrode layers, the laminate having a first surface and a second surface facing each other in the lamination direction, a first end surface and a second end surface facing each other, and a first side surface and a second side surface facing each other, a first external electrode located from the first end surface over the first surface and the second surface, and a second external electrode located from the second end surface over the first surface and the second surface, wherein the first external electrode and the second external electrode are connected to different internal electrode layers of the internal electrode layers, the first covering portion has a first dielectric portion, and a dummy electrode located at an end of the first dielectric portion in a first direction orthogonal to the first end surface, the dummy electrode including a plurality of dummy electrode layers directly laminated on each other, being thicker than the internal electrode layer, being embedded in the first covering portion, and being exposed on the first surface.

Brief Description of the Drawings

[0005] The objects, features, and advantages of the present disclosure will become more apparent from the following detailed description and the drawings.

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MODE FOR CARRYING OUT THE INVENTION

[0006] A multilayer ceramic capacitor includes a laminate in which dielectric layers and internal electrode layers are alternately laminated, and external electrodes formed on the surface of the laminate and connected to the internal electrode layers. By using a plating film as the external electrode, the multilayer ceramic capacitor can be miniaturized. However, since the bonding strength between the laminate and the plating film is weak, the plating film may peel off. Patent Document 1 described above discloses providing a plurality of dummy electrode layers joined to the plating film on the laminate in order to increase the bonding strength between the laminate and the plating film.

[0007] In the manufacturing process of a conventional multilayer ceramic capacitor, after firing an unfired laminate, a step of barrel-polishing the laminate is included in order to sufficiently expose the internal electrode layer on the surface of the laminate. In the multilayer ceramic capacitor described in Patent Document 1, since there are many interfaces of different materials between the dielectric layer and the dummy electrode layer at the corners of the laminate, when the collision force between the polishing medium applied to the corners of the laminate and other laminates becomes excessive, delamination between the dielectric layer and the dummy electrode layer may occur. As a result, the reliability of the multilayer ceramic capacitor may deteriorate.

[0008] Hereinafter, embodiments of the multilayer ceramic capacitor of the present disclosure will be described with reference to the drawings. The drawings used in the following description are schematic, and the dimensional ratios and the like on the drawings do not necessarily match the actual ones. Regarding the multilayer ceramic electronic component according to the embodiment, any direction may be regarded as upward or downward, but in this specification, in some of the drawings, for convenience, a rectangular coordinate system xyz is defined. In the following description, the positive side in the z-axis direction is regarded as upward, and terms such as the upper surface or the lower surface may be used. The x-axis direction is also referred to as the first direction or the length direction. The y-axis direction is also referred to as the second direction or the width direction. The z-axis direction is also referred to as the third direction, the height direction, or the lamination direction.

[0009] FIG. 1 is a perspective view showing a multilayer ceramic capacitor according to the present embodiment, and FIG. 2 is a perspective view showing a laminate of the multilayer ceramic capacitor of FIG. 1. FIG. 3 is a cross-sectional view taken along the cutting plane line III-III of FIG. 1, and FIG. 4 is a cross-sectional view taken along the cutting plane line IV-IV of FIG. 3. In FIG. 2, for ease of illustration, hatching is applied to the portions exposed on the surface of the laminate in the internal electrode layer and the first to fourth dummy electrodes.

[0010] As shown in FIG. 1, the multilayer ceramic capacitor 1 according to the present embodiment includes a laminate 2, a first external electrode 10a, and a second external electrode 10b. Hereinafter, the first external electrode 10a and the second external electrode 10b may be collectively referred to as external electrodes 10a, 10b.

[0011] As shown in FIG. 2, the laminate 2 has a substantially rectangular parallelepiped shape. The laminate 2 has a first surface 7a and a second surface 7b that face each other, a first end surface 8a and a second end surface 8b that face each other, and a first side surface 9a and a second side surface 9b that face each other. The first end surface 8a and the second end surface 8b may be perpendicular to the first direction (x-axis direction). The first side surface 9a and the second side surface 9b may be perpendicular to the second direction (y-axis direction). The first surface 7a and the second surface 7b may be perpendicular to the third direction (z-axis direction). Hereinafter, the first surface 7a and the second surface 7b may be collectively referred to as main surfaces 7a, 7b, the first end surface 8a and the second end surface 8b may be collectively referred to as end surfaces 8a, 8b, and the first side surface 9a and the second side surface 9b may be collectively referred to as side surfaces 9a, 9b.

[0012] The laminate 2 includes an active portion 3, a first covering portion 61, and a second covering portion 62. As shown in FIG. 3, the active portion 3 is formed by alternately laminating a dielectric layer 4 and an internal electrode layer 5. The dielectric layer 4 and the internal electrode layer 5 are laminated in the third direction (z-axis direction). The active portion 3 forms a capacitance. In FIG. 3, the boundaries between the active portion 3 and the first covering portion 61 and the second covering portion 62 are indicated by a two-dot chain line, but the actual boundaries are not clearly visible.

[0013] The dielectric layer 4 is made of a dielectric material. The dielectric layer 4 may be made of a ceramic material mainly composed of, for example, barium titanate (BaTiO3), calcium titanate (CaTiO3), strontium titanate (SrTiO3), barium zirconate (BaZrO3), etc. The dielectric layer 4 may have a thickness of, for example, 0.1 μm or more and 10 μm or less. In this specification, the "main component" refers to the component with the highest content ratio in the material or member, etc. being focused on.

[0014] The internal electrode layer 5 is made of a conductive material. The internal electrode layer 5 may be made of a metal material mainly composed of, for example, metals such as Ni (nickel), Cu (copper), Sn (tin), Pt (platinum), Pd (palladium), Ag (silver), Au (gold), or alloys thereof. The internal electrode layer 5 may have a thickness of, for example, 1.5 μm or less. In this case, internal defects caused by internal stress during firing or voltage application of the laminate 2 can be suppressed, and the reliability of the multilayer ceramic capacitor 1 can be improved.

[0015] The internal electrode layer 5 includes a first internal electrode layer 5a and a second internal electrode layer 5b having different polarities. The active part 3 is configured by alternately laminating the first internal electrode layer 5a and the second internal electrode layer 5b with the dielectric layer 4 interposed therebetween.

[0016] As shown in FIG. 4, the first internal electrode layer 5a has a capacitance forming part 5aa and a lead-out part 5ab. The lead-out part 5ab is exposed on the first end face 8a and the side faces 9a, 9b. It can also be said that the lead-out part 5ab constitutes a part of the first end face 8a and the side faces 9a, 9b. As shown in FIG. 4, the second internal electrode layer 5b has a capacitance forming part 5ba and a lead-out part 5bb. The lead-out part 5bb is exposed on the second end face 8b and the side faces 9a, 9b. It can also be said that the lead-out part 5bb constitutes a part of the second end face 8b and the side faces 9a, 9b. The capacitance forming part 5aa and the capacitance forming part 5ba overlap each other in a plan view (that is, when viewed from the third direction).

[0017] As shown in FIG. 3, the first covering portion 61 and the second covering portion 62 are respectively located at both ends of the active portion 3 in the third direction (z-axis direction). Hereinafter, the first covering portion 61 and the second covering portion 62 may be collectively referred to as the covering portions 61, 62.

[0018] The first covering portion 61 includes a first dummy electrode 61a, a second dummy electrode 61b, and a first dielectric portion 61c. The first dummy electrode 61a and the second dummy electrode 61b are respectively located at both ends of the first dielectric portion 61c in the first direction (x-axis direction).

[0019] As shown in FIG. 3, the first dummy electrode 61a is exposed on the first end face 8a. It can be said that the first dummy electrode 61a constitutes a part of the first end face 8a. In plan view, the first dummy electrode 61a may have the same shape as the lead-out portion 5ab of the first internal electrode layer 5a, or may have a different shape from the lead-out portion 5ab. In the first direction (x-axis direction), the first dummy electrode 61a may be longer than the lead-out portion 5ab or shorter than the lead-out portion 5ab. As shown in FIG. 3, the second dummy electrode 61b is exposed on the second end face 8b. It can be said that the second dummy electrode 61b constitutes a part of the second end face 8b. In plan view, the second dummy electrode 61b may have the same shape as the lead-out portion 5bb of the second internal electrode layer 5b, or may have a different shape from the lead-out portion 5bb. In the first direction, the second dummy electrode 61b may be longer than the lead-out portion 5bb or shorter than the lead-out portion 5bb.

[0020] The first dielectric portion 61c is made of a dielectric material and electrically insulates the first dummy electrode 61a and the second dummy electrode 61b. The first dielectric portion 61c may be made of the ceramic material that constitutes the dielectric layer 4.

[0021] The second covering portion 62 includes a third dummy electrode 62a, a fourth dummy electrode 62b, and a second dielectric portion 62c. The third dummy electrode 62a and the fourth dummy electrode 62b are respectively positioned at both ends of the second dielectric portion 62c in the first direction (X-axis direction). Hereinafter, the first dielectric portion 61c and the second dielectric portion 62c may be collectively referred to as the dielectric portions 61c, 62c.

[0022] As shown in FIGS. 2 and 3, the third dummy electrode 62a is exposed on the first end face 8a. It can be said that the third dummy electrode 62a constitutes a part of the first end face 8a. The third dummy electrode 62a may have the same shape as the lead-out portion 5ab of the first internal electrode layer 5a in a plan view, or may have a shape different from that of the lead-out portion 5ab. In the first direction (x-axis direction), the third dummy electrode 62a may be longer than the lead-out portion 5ab or may be shorter than the lead-out portion 5ab. As shown in FIG. 3, the fourth dummy electrode 62b is exposed on the second end face 8b. It can be said that the fourth dummy electrode 62b constitutes a part of the second end face 8b. The fourth dummy electrode 62b may have the same shape as the lead-out portion 5bb of the second internal electrode layer 5b in a plan view, or may have a shape different from that of the lead-out portion 5bb. In the first direction, the fourth dummy electrode 62b may be longer than the lead-out portion 5bb or may be shorter than the lead-out portion 5bb.

[0023] The second dielectric portion 62c is made of a dielectric material and electrically insulates the third dummy electrode 62a and the fourth dummy electrode 62b. The second dielectric portion 62c may be made of the ceramic material constituting the dielectric layer 4.

[0024] Hereinafter, the first dummy electrode 61a, the second dummy electrode 61b, the third dummy electrode 62a, and the fourth dummy electrode 62b may be collectively referred to as the dummy electrodes 61a to 62b.

[0025] At least one of the dummy electrodes 61a to 62b has a thickness in the third direction (z-axis direction) greater than that of one layer of the internal electrode layer 5, as shown in FIGS. 2 and 3. The thickness of the dummy electrodes 61a to 62b may be 3 times or more, 5 times or more, or 10 times or more the thickness of one layer of the internal electrode layer 5. The dummy electrodes 61a to 62b may have substantially the same dimensions as each other. Hereinafter, unless otherwise specified, as shown in FIGS. 2 and 3, it is assumed that all of the dummy electrodes 61a to 62b have a greater thickness in the third direction than the internal electrode layer 5.

[0026] The first external electrode 10a is located from the first end face 8a over the first surface 7a, the second surface 7b, the first side surface 9a, and the second side surface 9b. The first external electrode 10a is connected to the exposed portion of the laminated body 2 surface at the lead-out portion 5ab. The first external electrode 10a may completely cover the exposed portion of the lead-out portion 5ab. In this case, the first internal electrode layer 5a and the first external electrode 10a can be electrically connected well, and the active portion 3 can be protected from the external environment (for example, moisture, etc.). The first external electrode 10a is connected to the exposed portions of the laminated body 2 surface at the first dummy electrode 61a and the third dummy electrode 62a. The first external electrode 10a may completely cover the exposed portions of the first dummy electrode 61a and the third dummy electrode 62a. In this case, the contact area between the laminated body 2 and the first external electrode 10a can be increased, and the bonding strength between the laminated body 2 and the first external electrode 10a can be improved.

[0027] The second external electrode 10b is located from the second end face 8b over the first face 7a, the second face 7b, the first side face 9a, and the second side face 9b. The second external electrode 10b is connected to a portion exposed on the surface of the laminate 2 in the lead-out portion 5bb. The second external electrode 10b may completely cover the exposed portion of the lead-out portion 5bb. In this case, the second internal electrode layer 5b and the second external electrode 10b can be electrically connected well, and the active portion 3 can be protected from the external environment (for example, moisture, etc.). The second external electrode 10b is connected to portions exposed on the surface of the laminate 2 in the second dummy electrode 61b and the fourth dummy electrode 62b. The second external electrode 10b may completely cover the exposed portions of the second dummy electrode 61b and the fourth dummy electrode 62b. In this case, the contact area between the laminate 2 and the second external electrode 10b can be increased, and the bonding strength between the laminate 2 and the second external electrode 10b can be improved.

[0028] As shown in FIGS. 3 and 4, the external electrodes 10a and 10b may be configured to include a first layer 11 in contact with the surface of the laminate 2 and a second layer 12 covering the first layer 11. The first layer 11 is also referred to as an underlayer. The second layer 12 is also referred to as an outer layer. By forming the external electrodes 10a and 10b into a multilayer structure, it becomes possible to increase the bonding strength between the underlayer 11 and the laminate 2 while improving the wettability of the conductive bonding material (for example, solder, etc.) to the outer layer 12. As a result, it becomes possible to improve the reliability of the multilayer ceramic capacitor 1 and the reliability of the mounting structure including the multilayer ceramic capacitor 1.

[0029] The underlying layer 11 may be made of a metal material mainly composed of a metal such as Ni, Cu, Sn, Pt, Pd, Ag, Au or an alloy thereof. The underlying layer 11 may be formed using a thin film forming technique such as electroplating, sputtering, or vapor deposition. In this case, since the volume of the underlying layer 11 can be reduced, the multilayer ceramic capacitor 1 can be miniaturized or the effective volume contributing to the capacitance can be increased. The technique for forming the underlying layer 11 is not limited to thin film forming techniques. The underlying layer 11 may be formed using a thick film forming technique such as dipping, screen printing, or gravure printing. As shown in FIGS. 3 and 4, the underlying layer 11 may completely cover the exposed portions of the lead portions 5ab, 5bb and the dummy electrodes 61a to 62b.

[0030] The outer layer 12 may be made of a metal material mainly composed of a metal such as Ni, Cu, Sn, Pt, Pd, Ag, Au or an alloy thereof. The outer layer 12 may be formed using a thin film forming technique such as electroless plating or electroplating. As shown in FIGS. 3 and 4, the outer layer 12 may completely cover the underlying layer 11 (the surface thereof). The outer layer 12 may extend to the central side of the laminate 2 beyond the end portion on the central side of the laminate 2 in the underlying layer 11. In other words, the inner end portions 10t on the central side of the laminate 2 in the external electrodes 10a, 10b may be composed only of the outer layer 12.

[0031] In the multilayer ceramic capacitor 1 of the present embodiment, dummy electrodes 61a to 62b thicker than the internal electrode layer 5 are exposed at the end faces 8a, 8b, and the external electrodes 10a, 10b are connected to the exposed portions of the dummy electrodes 61a to 62b. Thereby, the bonding strength between the laminate 2 and the external electrodes 10a, 10b can be increased, and as a result, the reliability of the multilayer ceramic capacitor 1 can be improved.

[0032] In a conventional multilayer ceramic capacitor, a coating portion (corresponding to coating portions 61 and 62) includes a dummy electrode portion in which a plurality of dielectric layers and a plurality of dummy electrode layers are alternately laminated. Compared with the conventional multilayer ceramic capacitor, the multilayer ceramic capacitor 1 of the present embodiment has fewer dissimilar material interfaces in the coating portions 61 and 62, so that the occurrence of delamination between layers in the coating portions 61 and 62 during (barrel) polishing of the laminate 2 can be reduced. Therefore, the reliability of the multilayer ceramic capacitor 1 can be improved.

[0033] Further, according to the multilayer ceramic capacitor 1, the area of the exposed portions of the dummy electrodes 61a to 62b at the end faces 8a and 8b can be increased without increasing the number of dissimilar material interfaces in the coating portions 61 and 62. Therefore, the reliability of the multilayer ceramic capacitor 1 can be effectively improved.

[0034] The first dummy electrode 61a and the second dummy electrode 61b may be further exposed on the first surface 7a, and the third dummy electrode 62a and the fourth dummy electrode 62b may be further exposed on the second surface 7b. In other words, the first dummy electrode 61a and the second dummy electrode 61b may constitute a part of the first surface 7a, and the third dummy electrode 62a and the fourth dummy electrode 62b may constitute a part of the second surface 7b. Since the first external electrode 10a is located from the first end face 8a to the main surfaces 7a and 7b, and the second external electrode 10b is located from the second end face 8b to the main surfaces 7a and 7b, when the dummy electrodes 61a to 62b are exposed on the main surfaces 7a and 7b, the contact area between the dummy electrodes 61a to 62b and the external electrodes 10a and 10b can be increased. As a result, the bonding strength between the laminate 2 and the external electrodes 10a and 10b can be further increased, and the reliability of the multilayer ceramic capacitor 1 can be further improved.

[0035] The upper surfaces of the first dummy electrodes 61a and the second dummy electrodes 61b may be flush with the upper surface of the first dielectric part 61c, and the lower surfaces of the third dummy electrodes 62a and the fourth dummy electrodes 62b may be flush with the lower surface of the second dielectric part 62c. In this case, in the manufacturing process of the multilayer ceramic capacitor 1, since the thicknesses of the external electrodes 10a and 10b on the main surfaces 7a and 7b can be easily and accurately controlled, it becomes easier to manufacture the multilayer ceramic capacitor 1 with dimensions as designed.

[0036] The upper surfaces of the first dummy electrodes 61a and the second dummy electrodes 61b may slightly protrude upward from the upper surface of the first dielectric part 61c, and the lower surfaces of the third dummy electrodes 62a and the fourth dummy electrodes 62b may slightly protrude downward from the lower surface of the second dielectric part 62c. In this case, by forming the external electrodes 10a and 10b so as to wrap around the end portions on the central side of the laminate 2 in the dummy electrodes 61a to 62b, the contact area between the laminate 2 and the external electrodes 10a and 10b increases, and it becomes difficult for the laminate 2 and the external electrodes 10a and 10b to peel off. As a result, the reliability of the multilayer ceramic capacitor 1 can be improved.

[0037] The dummy electrodes 61a to 62b may be further exposed on the first side surface 9a and the second side surface 9b. In other words, the dummy electrodes 61a to 62b may constitute a part of the first side surface 9a and the second side surface 9b. Since the first external electrode 10a is located from the first end surface 8a to the side surfaces 9a and 9b, and the second external electrode 10b is located from the second end surface 8b to the side surfaces 9a and 9b, by exposing the dummy electrodes 61a to 62b on the side surfaces 9a and 9b, the contact area between the dummy electrodes 61a to 62b and the external electrodes 10a and 10b can be increased. As a result, the bonding strength between the laminate 2 and the external electrodes 10a and 10b can be further increased, and the reliability of the multilayer ceramic capacitor 1 can be further improved.

[0038] The sides of the first dummy electrode 61a and the second dummy electrode 61b may be flush with the side of the first dielectric part 61c, and the sides of the third dummy electrode 62a and the fourth dummy electrode 62b may be flush with the side of the second dielectric part 62c. In this case, in the manufacturing process of the multilayer ceramic capacitor 1, since the thicknesses of the external electrodes 10a and 10b on the sides 9a and 9b can be easily and accurately controlled, it becomes easier to manufacture the multilayer ceramic capacitor 1 with the dimensions as designed.

[0039] The sides of the first dummy electrode 61a and the second dummy electrode 61b may slightly protrude from the side of the first dielectric part 61c in the second direction (y-axis direction), and the sides of the third dummy electrode 62a and the fourth dummy electrode 62b may slightly protrude from the side of the second dielectric part 62c in the second direction. In other words, the side of the first dielectric part 61c may be recessed from the sides of the first dummy electrode 61a and the second dummy electrode 61b, and the side of the second dielectric part 62c may be recessed from the sides of the third dummy electrode 62a and the fourth dummy electrode 62b. In this case, by forming the external electrodes 10a and 10b so as to wrap around the ends on the central side of the laminate 2 in the dummy electrodes 61a to 62b, the contact area between the laminate 2 and the external electrodes 10a and 10b increases, and it becomes difficult for the laminate 2 and the external electrodes 10a and 10b to peel off. As a result, the reliability of the multilayer ceramic capacitor 1 can be improved.

[0040] The multilayer ceramic capacitor 1 of the present embodiment only needs to have a configuration in which at least one of the dummy electrodes 61a to 62b is thicker than the internal electrode layer 5. As shown in FIG. 5, in the multilayer ceramic capacitor 1, the first dummy electrode 61a may be thicker than the internal electrode layer 5, and the second dummy electrode 61b, the third dummy electrode 62a, and the fourth dummy electrode 62b may have the same thickness as the internal electrode layer 5 or may be thinner than the internal electrode layer 5. Compared with the conventional multilayer ceramic capacitor, the multilayer ceramic capacitor 1 can reduce the number of heterogeneous material interfaces in the coating parts 61 and 62, so that the occurrence of interlayer peeling in the coating parts 61 and 62 when the laminate 2 is barrel-polished can be reduced. Therefore, the reliability of the multilayer ceramic capacitor 1 can be improved.

[0041] The laminate 2 may have an auxiliary electrode portion 61ba located inside (below) the second dummy electrode 61b in the third direction (z-axis direction), in which a dielectric layer 65 and an electrode layer 66 are alternately laminated. In this case, it is possible to provide the first dummy electrode 61a and the second dummy electrode 61b without forming a step on the first surface 7a of the laminate 2. The electrode layer 66 may be exposed on the second end face 8b and the side faces 9a, 9b. In this case, the bonding strength between the laminate 2 and the second external electrode 10b can be increased. The electrode layer 66 may have the same shape as the second dummy electrode 61b or a different shape from the second dummy electrode 61b in plan view.

[0042] The laminate 2 may have an auxiliary electrode portion 62aa located inside (above) the third dummy electrode 62a in the third direction (z-axis direction) and an auxiliary electrode portion 62ba located inside (above) the fourth dummy electrode 62b in the third direction. Similar to the auxiliary electrode portion 61ba, the auxiliary electrode portions 62aa, 62ba may be configured by alternately laminating a dielectric layer 65 and an electrode layer 66. The electrode layer 66 of the auxiliary electrode portion 62aa may be exposed on the first end face 8a and the side faces 9a, 9b, and the electrode layer 66 of the auxiliary electrode portion 62ba may be exposed on the second end face 8b and the side faces 9a, 9b. In this case, the bonding strength between the laminate 2 and the external electrodes 10a, 10b can be increased. The electrode layer 66 of the auxiliary electrode portion 62aa may have the same shape as the third dummy electrode 62a or a different shape from the third dummy electrode 62a in plan view. The electrode layer 66 of the auxiliary electrode portion 62ba may have the same shape as the fourth dummy electrode 62b or a different shape from the fourth dummy electrode 62b in plan view.

[0043] The multilayer ceramic capacitor 1 may be configured such that two of the dummy electrodes 61a to 62b are thicker than the internal electrode layer 5, or three of the dummy electrodes 61a to 62b may be thicker than the internal electrode layer 5.

[0044] Next, another example of the multilayer ceramic capacitor of the present embodiment will be described. FIGS. 6 to 8 are cross-sectional views showing another example of the multilayer ceramic capacitor of the present embodiment. The cross-sectional views shown in FIGS. 6 to 8 correspond to the cross-sectional view shown in FIG. 3.

[0045] As shown in FIG. 6, the dummy electrodes 61a to 62b may be configured by laminating a plurality of dummy electrode layers 63. The plurality of dummy electrode layers 63 may be laminated in the third direction (z-axis direction). In this case, by laminating the dummy electrode layers 63 having a small thickness, the dummy electrodes 61a to 62b having a large thickness can be formed. Since the thickness of the dummy electrode layer 63 is small, the dimensions of the dummy electrode layer 63 can be accurately controlled. For this reason, the dimensions of the dummy electrodes 61a to 62b can be more accurately controlled than in the case of forming the single-piece dummy electrodes 61a to 62b. As a result, even when the multilayer ceramic capacitor 1 is small, the dummy electrodes 61a to 62b having the designed dimensions can be formed, and the reliability of the multilayer ceramic capacitor 1 can be improved. In FIG. 6, the boundaries between the dummy electrode layers 63 are indicated by a two-dot chain line, but the actual boundaries do not appear clearly. The same applies to FIGS. 7 and 8.

[0046] The thickness of the dummy electrode layer 63 may be substantially the same as the thickness of the internal electrode layer 5. Although details will be described later, in the manufacturing process of the multilayer ceramic capacitor 1, the active portion 3 of the unfired laminate 2 is formed by a printing method such as a screen printing method or a gravure printing method using a ceramic slurry and a conductive paste. Therefore, when the thickness of the dummy electrode layer 63 is substantially the same as the thickness of the internal electrode layer 5, the dummy electrode layer 63 can be printed using the same printing method as the printing method used for printing the internal electrode layer 5. As a result, it becomes possible to efficiently form the dummy electrodes 61a to 62b having the designed dimensions.

[0047] When the dummy electrodes 61a to 62b are configured such that a plurality of dummy electrode layers 63 are stacked, the first dielectric part 61c and the second dielectric part 62c may be configured such that a plurality of dielectric layers 64 are stacked. The thickness of the dielectric layer 64 may be substantially the same as the thickness of the dummy electrode layer 63. In this case, the dielectric layer 64 can be printed using the same printing method as the printing method used for printing the dummy electrode layer 63. As a result, it becomes possible to efficiently form the covering parts 61 and 62 having the designed dimensions. In FIG. 6, the boundaries between the dielectric layers 64 are shown by a two-dot chain line, but the actual boundaries do not clearly appear. This also applies to FIGS. 7 and 8.

[0048] The dummy electrode layer 63 may include a common material 63a made of a dielectric material. In this case, since the bonding strength between the dummy electrode layers 63 can be increased, the occurrence of delamination between the dummy electrodes 61a to 62b can be suppressed. The dummy electrode layer 63 may include a common material made of the ceramic material constituting the dielectric layer 4 and the dielectric layer 64. In this case, while increasing the bonding strength between the dummy electrode layers 63, the bonding strength between the dummy electrodes 61a to 62b and the active part 3 can be increased. Further, the bonding strength between the first dummy electrode 61a and the second dummy electrode 61b and the first dielectric part 61c can be increased, and the bonding strength between the third dummy electrode 62a and the fourth dummy electrode 62b and the first dielectric part 61c can be increased. As a result, the occurrence of peeling in the laminate 2 can be suppressed, and the reliability of the multilayer ceramic capacitor 1 can be improved.

[0049] At least one of the first dummy electrode 61a and the second dummy electrode 61b and the interface 61d with the first dielectric part 61c may have an uneven structure. The multilayer ceramic capacitor 1 is, for example, surface-mounted (reflow soldered) on an external substrate and used. When mounting the multilayer ceramic capacitor 1 on the external substrate, due to the shrinkage of the external electrodes 10a and 10b during the cooling after heating, cracks are likely to occur in the region near the inner ends 10t of the external electrodes 10a and 10b on the first surface 7a of the laminate 2 (hereinafter also referred to as the "opposing region") 2f. By having the interface 61d of the first covering part 61 have an uneven structure, even if a crack occurs in the opposing region 2f in the first covering part 61, it is possible to suppress the crack from extending to the active part 3. As a result, the moisture resistance of the multilayer ceramic capacitor 1 can be enhanced and the reliability can be improved.

[0050] When the first dummy electrode 61a and the second dummy electrode 61b are composed of a plurality of dummy electrode layers 63, the uneven structure of the interface 61d may be formed by the positions of the ends of the plurality of dummy electrode layers 63 on the first dielectric part 61c side changing regularly or irregularly in the first direction (x-axis direction), as shown in FIG. 7. When the first dummy electrode 61a and the second dummy electrode 61b are single-layer structures, the uneven structure of the interface 61d may be formed, for example, by providing unevenness at the interface between the electrode pattern that becomes the first dummy electrode 61a and the second dummy electrode 61b and the dielectric pattern that becomes the first dielectric part 61c in the manufacturing process of the mother laminate (see FIGS. 9 and 12).

[0051] At least one of the third dummy electrode 62a and the fourth dummy electrode 62b and the interface 62d with the second dielectric part 62c may have an uneven structure. The effect of the uneven structure of the interface 62d is the same as the effect of the uneven structure of the interface 61d, and the method of making the interface 62d have an uneven structure is the same as the method of making the interface 61d have an uneven structure, so detailed description is omitted.

[0052] As shown in FIGS. 3, 6 to 8, the lower surfaces of the first dummy electrode 61a and the second dummy electrode 61b may be in contact with the upper surface of the active portion 3. The laminate 2 may be configured such that the interfaces 61e between the active portion 3 and the first dummy electrode 61a and the second dummy electrode 61b respectively have an uneven structure. In this case, it becomes difficult for the active portion 3 and the first dummy electrode 61a and the second dummy electrode 61b to peel off, and as a result, the reliability of the multilayer ceramic capacitor 1 can be improved.

[0053] The lower surfaces of the first dummy electrode 61a and the second dummy electrode 61b do not have to be in contact with the upper surface of the active portion 3. The first covering portion 61 may include an intervening layer (not shown) located between the active portion 3 and the first dummy electrode 61a and between the active portion 3 and the second dummy electrode 61b. The intervening layer may be made of a dielectric material that constitutes the first dielectric portion 61c. The first covering portion 61 may be configured such that the interfaces between the first dummy electrode 61a and the second dummy electrode 61b and the intervening layer respectively have an uneven structure. In this case, the occurrence of peeling in the first covering portion 61 can be suppressed, and the reliability of the multilayer ceramic capacitor 1 can be improved.

[0054] The upper surfaces of the third dummy electrode 62a and the fourth dummy electrode 62b may be in contact with the lower surface of the active portion 3. The laminate 2 may be configured such that the interfaces 62e between the active portion 3 and the third dummy electrode 62a and the fourth dummy electrode 62b respectively have an uneven structure. In this case, it becomes difficult for the active portion 3 and the third dummy electrode 62a and the fourth dummy electrode 62b to peel off, and as a result, the reliability of the multilayer ceramic capacitor 1 can be improved.

[0055] The upper surfaces of the third dummy electrode 62a and the fourth dummy electrode 62b do not necessarily have to be in contact with the lower surface of the active part 3. The second covering part 62 may include a second intervening layer (not shown) located between the active part 3 and the third dummy electrode 62a and between the active part 3 and the fourth dummy electrode 62b. The intervening layer may be made of a dielectric material that constitutes the second dielectric part 62c. The second covering part 62 may be configured such that the interfaces between each of the third dummy electrode 62a and the fourth dummy electrode 62b and the second intervening layer have an uneven structure. In this case, the occurrence of peeling in the second covering part 62 can be suppressed, and the reliability of the multilayer ceramic capacitor 1 can be improved.

[0056] Next, an example of a manufacturing method of the multilayer ceramic capacitor 1 (hereinafter, also referred to as the "first manufacturing method") will be described. FIG. 9 is a perspective view for explaining an example of a manufacturing process of a mother laminate, FIG. 10 is a perspective view showing an example of the mother laminate, and FIG. 11 is a perspective view showing an example of a laminate obtained by cutting the mother laminate.

[0057] First, as a material for the dielectric layer 4, raw material powder mainly composed of a dielectric material such as BaTiO3, CaTiO3, SrTiO3, BaZrO3 or a mixture thereof is prepared. Subsequently, an organic vehicle is mixed with the prepared raw material powder to prepare a ceramic slurry. The organic vehicle used for the preparation of the ceramic slurry may be, for example, a resin such as a butyral resin dissolved in a solvent obtained by mixing ethyl alcohol and toluene. Subsequently, using the prepared ceramic slurry, a ceramic green sheet (hereinafter, also referred to as a "green sheet") 13 that becomes the dielectric layer 4 is formed by a sheet forming method such as a doctor blade method or a die coater method. The average thickness of the green sheet 13 may be, for example, about 0.5 to 10 μm. The above-mentioned ceramic slurry may be used for the dielectric parts 61c and 62c.

[0058] Next, as the material of the internal electrode layer 5, a powder mainly composed of a metal such as Ni, Cu, Sn, Pt, Pd, Ag, Au or an alloy thereof is mixed with an organic vehicle to prepare a conductive paste. The organic vehicle used for preparing the conductive paste may be, for example, a resin such as ethyl cellulose dissolved in a solvent obtained by mixing a dihydroterpineol-based solvent and butyl cellosolve. The dispersant may be, for example, oleic acid, polyethylene glycol, or the like. The above-described conductive paste may be used for the dummy electrodes 61a to 62b.

[0059] Next, using the conductive paste, a pattern sheet 15 is formed in which an electrode pattern 14 that becomes the internal electrode layer 5 is printed on the main surface of the green sheet 13 (see FIG. 9). The printing of the electrode pattern 14 can be performed using a printing method such as a screen printing method or a gravure printing method.

[0060] Next, a temporary laminate that is a precursor of the mother laminate is produced. First, using a ceramic slurry and a conductive paste, a first cover sheet 17 that becomes the covering portions 61 and 62 is formed on the support sheet 16 by a printing method such as a screen printing method or a gravure printing method. The first cover sheet 17 is composed of an electrode pattern 18 that becomes the dummy electrodes 61a to 62b and a dielectric pattern 19 that becomes the dielectric portions 61c and 62c. The first cover sheet 17 may be formed by printing a plurality of times or may be formed by printing once. FIG. 9 shows a case where the first cover sheet 17 is formed by printing a plurality of times, that is, a case where the dummy electrodes 61a to 62b are formed by laminating a plurality of dummy electrode layers 63 and the dielectric portions 61c and 62c are formed by laminating a plurality of dielectric layers 64. In FIG. 9, the electrode pattern 14 and the electrode pattern 18 are shown with hatching.

[0061] Next, as shown in FIG. 9, a predetermined number of pattern sheets 15 are laminated on the first cover sheet 17, and the second cover sheet 20 is formed thereon to produce a temporary laminate. The second cover sheet 20 can be formed in the same manner as the first cover sheet 17. Subsequently, by pressing the temporary laminate in the lamination direction, a mother laminate 21 as shown in FIG. 10 is obtained. In FIG. 10, hatching is applied to the portions exposed on the surface of the mother laminate 21 in the electrode pattern 14 and the electrode pattern 18. Pressurization of the temporary laminate can be performed using, for example, a hydrostatic press device. Subsequently, a plurality of unfired laminates 2 as shown in FIG. 11 are produced by cutting the mother laminate 21 along the virtual division line 22. Cutting of the mother laminate 21 can be performed using, for example, a guillotine cutter, a dicing saw device, or the like. Since the unfired laminate 2 has the same structure as the fired laminate 2, hereinafter, for the unfired laminate 2 as well, terms and reference numerals such as the internal electrode layer 5, the main surfaces 7a, 7b, the end surfaces 8a, 8b, and the side surfaces 9a, 9b are used. In FIG. 11, hatching is applied to the portions exposed on the surface of the laminate 2 in the internal electrode layer 5 and the dummy electrodes 61a to 62b.

[0062] Next, the unfired laminate 2 is subjected to a debinding treatment in an air atmosphere, an inert gas atmosphere, or a reducing atmosphere. The debinding treatment may be performed under atmospheric pressure or under reduced pressure.

[0063] Next, the debound laminate 2 is fired in a reducing atmosphere. The atmosphere gas may be, for example, a mixed gas of hydrogen (H2) and nitrogen (N2). The firing temperature may be, for example, about 1100 to 1300°C. The fired laminate 2 may be subjected to a reoxidation treatment in an oxidizing atmosphere.

[0064] Next, the fired laminate 2 is subjected to barrel polishing treatment to sufficiently expose the internal electrode layers 5 on the end faces 8a, 8b and the side faces 9a, 9b, and to remove burrs on the surface of the laminate 2, thereby obtaining a laminate 2 as shown in FIG. 2. By forming external electrodes 10a, 10b on the obtained laminate 2, the multilayer ceramic capacitor 1 can be manufactured. The external electrodes 10a, 10b may be formed by applying a conductive paste that will become the external electrodes 10a, 10b to the unfired laminate 2 and co-firing the laminate 2 and the external electrodes 10a, 10b.

[0065] Next, another example of the manufacturing method of the multilayer ceramic capacitor 1 (hereinafter, also referred to as "the second manufacturing method") will be described. The second manufacturing method is different from the first manufacturing method in that green sheets 13 are disposed on the uppermost layer and the lowermost layer of the mother laminate, and the other aspects are the same. Therefore, for the same steps as the first manufacturing method, detailed descriptions will be omitted. FIG. 12 is a perspective view for explaining another example of the manufacturing process of the mother laminate, FIG. 13 is a perspective view showing another example of the mother laminate, and FIG. 14 is a perspective view showing another example of the laminate obtained by cutting the mother laminate. In FIG. 12, the electrode patterns 14 and 18 are shown with hatching. In FIG. 13, the hatched portions are the parts exposed on the surface of the mother laminate in the electrode patterns 14 and 18. In FIG. 14, the hatched portions are the parts exposed on the surface of the laminate in the internal electrode layer 5 and the dummy electrodes 61a to 62b.

[0066] In the second manufacturing method, as shown in FIG. 12, one green sheet 13 is placed on the support sheet 16, and a first cover sheet 17 is formed thereon. Further, a predetermined number of pattern sheets 15 are laminated on the first cover sheet 17, a second cover sheet 20 is formed thereon, and one green sheet 13 is placed thereon to produce a temporary laminate. The second cover sheet 20 can be formed in the same manner as the first cover sheet 17. By pressing the temporary laminate in the lamination direction, a mother laminate 23 as shown in FIG. 13 is obtained. The mother laminate 23 has the same configuration as the mother laminate 21 except that the green sheets 13 are located in the uppermost and lowermost layers in the lamination direction with respect to the mother laminate 21 described above. Subsequently, by cutting the mother laminate 23 along the virtual division line 24, a plurality of unfired laminates 2A as shown in FIG. 14 are produced. The laminate 2A has the same configuration as the laminate 2 except that a part of the green sheet 13 (reference numeral 13' in FIG. 14) is located in the uppermost and lowermost layers in the lamination direction with respect to the laminate 2 described above. It can also be said that the laminate 2A is composed of the laminate 2 and a part of the green sheet 13.

[0067] Next, the unfired laminate 2A is subjected to a debinding process. The debinding process may be the same as the debinding process in the first manufacturing method. Subsequently, the debound laminate 2A is fired. Also, the firing atmosphere and firing temperature may be the same as the firing atmosphere and firing temperature in the first manufacturing method.

[0068] Next, the fired laminate 2A is subjected to barrel polishing to remove the dielectric layer formed by firing a part of the green sheet 13, sufficiently expose the internal electrode layers 5 and the dummy electrodes 61a to 62b on the surface of the laminate 2, and remove the burrs on the surface of the laminate 2, thereby obtaining the laminate 2 as shown in FIG. 2. By forming external electrodes 10a and 10b on the obtained laminate 2, the multilayer ceramic capacitor 1 can be manufactured.

[0069] In the second manufacturing method, the electrode patterns 18 that become the dummy electrodes 61a to 62b are in contact with the support sheet 16 via the green sheet 13 and do not directly contact the support sheet 16. Therefore, when peeling the laminate 2A obtained by cutting the mother laminate 23 from the support sheet 16, it is possible to suppress a part of the electrode pattern 18 from remaining on the support sheet 16 (hereinafter also referred to as "electrode eaten"). As a result, it is possible to suppress the formation defect of the dummy electrodes 61a to 62b due to electrode eaten, and thus improve the reliability of the multilayer ceramic capacitor 1.

[0070] In addition, in order to suppress the electrode eaten by the support sheet 16, it is not necessary to dispose the green sheet 13 on the second cover sheet 20. However, by disposing the green sheet 13 on the second cover sheet 20, the unfired laminate 2A has a substantially vertically symmetric configuration. Therefore, when the fired laminate 2A is barrel-polished, the upper and lower portions of the laminate 2A are polished uniformly, and the laminate 2A after barrel polishing (that is, the laminate 2 shown in FIG. 2) has a substantially vertically symmetric configuration. As a result, it is possible to suppress the deviation of the bonding strength between the laminate 2 and the external electrodes 10a and 10b, and thus improve the reliability of the multilayer ceramic capacitor 1.

[0071] Hereinafter, a multilayer ceramic capacitor according to another embodiment of the present disclosure will be described.

[0072] FIGS. 15, 16, 17, 18A, and 18B relate to a multilayer ceramic capacitor of another embodiment. FIG. 15 is a perspective view showing a multilayer ceramic capacitor of another embodiment, FIG. 16 is a perspective view showing a laminate of the multilayer ceramic capacitor of FIG. 15, FIG. 17 is a cross-sectional view taken along the cutting line XVII-XVII of FIG. 15, FIG. 18A is a cross-sectional view taken along the cutting line XVIIIA-XVIIIA of FIG. 17, and FIG. 18B is a cross-sectional view taken along the cutting line XVIIIB-XVIIIB of FIG. 17. Note that FIG. 18A shows an end face cut along the cutting line XVIIIA-XVIIIA of FIG. 17.

[0073] The multilayer ceramic capacitor 1A of this embodiment has different configurations of the internal electrode layer 5 and the external electrodes 10a and 10b compared to the multilayer ceramic capacitor 1, and the other configurations are the same. Therefore, for the same configurations, detailed descriptions will be omitted.

[0074] In the multilayer ceramic capacitor 1A, as shown in FIGS. 16, 17, and 18A, the lead-out portion 5ab of the first internal electrode layer 5a is exposed on the first end face 8a and the side faces 9a and 9b, and the lead-out portion 5bb of the second internal electrode layer 5b is exposed on the second end face 8b and the side faces 9a and 9b. As shown in FIGS. 16, 17, and 18B, the first dummy electrode 61a is exposed on the first surface 7a, the first end face 8a, and the side faces 9a and 9b, and the second dummy electrode 61b is exposed on the first surface 7a, the second end face 8b, and the side faces 9a and 9b. Also, the third dummy electrode 62a is exposed on the second surface 7b, the first end face 8a, and the side faces 9a and 9b, and the fourth dummy electrode 62b is exposed on the second surface 7b, the second end face 8b, and the side faces 9a and 9b.

[0075] As shown in FIGS. 15, 17, 18A, and 18B, the first external electrode 10a is located from the first end face 8a over the main surfaces 7a and 7b and the side faces 9a and 9b, and the second external electrode 10b is located from the second end face 8b over the main surfaces 7a and 7b and the side faces 9a and 9b. The first external electrode 10a covers the portion exposed on the first surface 7a of the first dummy electrode 61a and also covers the portion exposed on the second surface 7b of the third dummy electrode 62a. The first external electrode 10a covers the portion exposed on the first end face 8a and the side faces 9a and 9b of the first dummy electrode 61a, the third dummy electrode 62a, and the lead-out portion 5ab of the first internal electrode layer 5a. The second external electrode 10b covers the portion exposed on the first surface 7a of the second dummy electrode 61b and also covers the portion exposed on the second surface 7b of the fourth dummy electrode 62b. The second external electrode 10b covers the portion exposed on the second end face 8b and the side faces 9a and 9b of the second dummy electrode 61b, the fourth dummy electrode 62b, and the lead-out portion 5bb of the second internal electrode layer 5b.

[0076] As shown in FIGS. 16, 18A, and 18B, the portions exposed on the side surfaces 9a and 9b in the lead-out portions 5ab are shorter in length in the first direction (x-axis direction) than the portions exposed on the side surfaces 9a and 9b in the first dummy electrodes 61a and the third dummy electrodes 62a. The end portions on the second end surface 8b side of the portions exposed on the side surfaces 9a and 9b in the lead-out portions 5ab are located closer to the first end surface 8a side than the end portions on the second end surface 8b side of the portions exposed on the side surfaces 9a and 9b in the first dummy electrodes 61a and the third dummy electrodes 62a. The portions exposed on the side surfaces 9a and 9b in the lead-out portions 5bb are shorter in length in the first direction (x-axis direction) than the portions exposed on the side surfaces 9a and 9b in the second dummy electrodes 61b and the fourth dummy electrodes 62b. The end portions on the first end surface 8a side of the portions exposed on the side surfaces 9a and 9b in the lead-out portions 5bb are located closer to the second end surface 8b side than the end portions on the first end surface 8a side of the portions exposed on the side surfaces 9a and 9b in the second dummy electrodes 61b and the fourth dummy electrodes 62b. As shown in FIG. 15, the external electrodes 10a and 10b have a U-shaped configuration when viewed from the second direction (y-axis direction).

[0077] Since the multilayer ceramic capacitor 1A has the dummy electrodes 61a to 62b thicker than the internal electrode layer 5, the number of heterogeneous material interfaces in the coating portions 61 and 62 can be reduced as compared with the conventional multilayer ceramic capacitor. As a result, the occurrence of delamination between layers in the coating portions 61 and 62 during barrel polishing of the laminate 2 can be reduced, and the reliability of the multilayer ceramic capacitor 1A can be improved.

[0078] The portions of the external electrodes 10a and 10b located on the main surfaces 7a and 7b may be composed of only the outer layer 12. In this case, the portions of the external electrodes 10a and 10b located on the main surfaces 7a and 7b can be made thinner, and as a result, the multilayer ceramic capacitor 1A can be made lower in height.

[0079] Since the side surfaces 9a and 9b of the multilayer ceramic capacitor 1A, which have lower solder wettability compared to the surfaces of the external electrodes 10a and 10b, are largely exposed, it is difficult for solder to adhere to the side surfaces 9a and 9b when solder-mounting on an external substrate. As a result, even when the multilayer ceramic capacitor 1A is made thinner, the risk of short circuit between the first external electrode 10a and the second external electrode 10b due to the solder adhering to the side surfaces 9a and 9b can be reduced.

[0080] As shown in FIGS. 16 and 17, the multilayer ceramic capacitor 1A may have a configuration in which all of the dummy electrodes 61a to 62b are thicker than the internal electrode layer 5, or as in the multilayer ceramic capacitor 1 shown in FIG. 5, at least one of the dummy electrodes 61a to 62b may be thicker than the internal electrode layer 5.

[0081] FIGS. 19, 20, 21, 22A, and 22B relate to multilayer ceramic capacitors of still other embodiments. FIG. 19 is a perspective view showing a multilayer ceramic capacitor of still other embodiments, FIG. 20 is a perspective view showing the laminate of the multilayer ceramic capacitor of FIG. 19, FIG. 21 is a cross-sectional view taken along the cutting plane line XIX-XIX of FIG. 19, FIG. 22A is a cross-sectional view taken along the cutting plane line XXIIA-XXIIA of FIG. 21, and FIG. 22B is a cross-sectional view taken along the cutting plane line XXIIB-XXIIB of FIG. 21. Note that FIG. 22A shows the end face cut along the cutting plane line XXIIA-XXIIA of FIG. 21.

[0082] The multilayer ceramic capacitor 1B of the present embodiment has a different configuration of the internal electrode layer 5, the dummy electrodes 61a to 62b, and the external electrodes 10a and 10b from the multilayer ceramic capacitor 1, and the other configurations are the same. Therefore, detailed descriptions of the same configurations are omitted.

[0083] In the multilayer ceramic capacitor 1B, as shown in FIGS. 20 and 22A, the lead-out portion 5ab of the first internal electrode layer 5a is exposed only on the first end face 8a and not on the side faces 9a and 9b. The lead-out portion 5bb of the second internal electrode layer 5b is exposed only on the second end face 8b and not on the side faces 9a and 9b. As shown in FIGS. 20 and 21, the first dummy electrode 61a is exposed on the first surface 7a, the first end face 8a, and the side faces 9a and 9b, and the second dummy electrode 61b is exposed on the first surface 7a, the second end face 8b, and the side faces 9a and 9b. The third dummy electrode 62a is exposed on the second surface 7b, the first end face 8a, and the side faces 9a and 9b, and the fourth dummy electrode 62b is exposed on the second surface 7b, the second end face 8b, and the side faces 9a and 9b.

[0084] As shown in FIGS. 19, 21, and 22B, the first external electrode 10a is located from the first end face 8a over the main surfaces 7a and 7b and the side faces 9a and 9b, and the second external electrode 10b is located from the second end face 8b over the main surfaces 7a and 7b and the side faces 9a and 9b. As shown in FIGS. 21 and 22B, the first external electrode 10a covers the portions of the first dummy electrode 61a exposed on the first surface 7a and the side faces 9a and 9b, and also covers the portions of the third dummy electrode 62a exposed on the second surface 7b and the side faces 9a and 9b. The second external electrode 10b covers the portions of the second dummy electrode 61b exposed on the first surface 7a and the side faces 9a and 9b, and also covers the portions of the fourth dummy electrode 62b exposed on the second surface 7b and the side faces 9a and 9b. The external electrodes 10a and 10b have a U-shaped configuration when viewed from the second direction (y-axis direction) as shown in FIG. 19.

[0085] Since the multilayer ceramic capacitor 1B has dummy electrodes 61a to 62b that are thicker than the internal electrode layer 5, the number of dissimilar material interfaces in the coating portions 61 and 62 can be reduced compared to conventional multilayer ceramic capacitors. As a result, the occurrence of delamination between layers in the coating portions 61 and 62 during barrel polishing of the laminate 2 can be reduced, and the reliability of the multilayer ceramic capacitor 1B can be improved.

[0086] The portions of the external electrodes 10a and 10b located on the main surfaces 7a and 7b may be composed of only the outer layer 12. In this case, the portions of the external electrodes 10a and 10b located on the main surfaces 7a and 7b can be made thinner, and as a result, the multilayer ceramic capacitor 1B can be made lower-profile.

[0087] In the multilayer ceramic capacitor 1B, since the side surfaces 9a and 9b with lower solder wettability are largely exposed compared to the surfaces of the external electrodes 10a and 10b, it is difficult for solder to adhere to the side surfaces 9a and 9b when solder-mounting on an external substrate. As a result, even when the multilayer ceramic capacitor 1B is made lower-profile, the risk of short-circuit between the first external electrode 10a and the second external electrode 10b due to solder adhering to the side surfaces 9a and 9b can be reduced.

[0088] As shown in FIGS. 20 and 21, the multilayer ceramic capacitor 1B may have a configuration in which all of the dummy electrodes 61a to 62b are thicker than the internal electrode layer 5, or as in the multilayer ceramic capacitor 1 shown in FIG. 5, a configuration in which at least one of the dummy electrodes 61a to 62b is thicker than the internal electrode layer 5 may also be acceptable.

[0089] FIGS. 23, 24, 25, 26A, 26B, 26C, and 26D relate to multilayer ceramic capacitors of still other embodiments. FIG. 23 is a perspective view showing a multilayer ceramic capacitor of still other embodiments, FIG. 24 is a perspective view showing the laminate of the multilayer ceramic capacitor of FIG. 23, and FIG. 25 is a cross-sectional view taken along the cutting plane line XXV-XXV of FIG. 23. FIG. 26A is a cross-sectional view taken along the cutting plane line XXVIA-XXVIA of FIG. 25, FIG. 26B is a cross-sectional view taken along the cutting plane line XXVIB-XXVIB of FIG. 25, FIG. 26C is a cross-sectional view taken along the cutting plane line XXVIC-XXVIC of FIG. 25, and FIG. 26D is a cross-sectional view taken along the cutting plane line XXVID-XXVID of FIG. 25. In FIG. 24, hatching is added to the portions of the internal electrode layer and the dummy electrodes that are exposed on the surface of the laminate.

[0090] As shown in FIG. 23, the multilayer ceramic capacitor 1C of the present embodiment includes a laminate 25, a first external electrode 26a, a second external electrode 26b, a third external electrode 26c, and a fourth external electrode 26d. Hereinafter, the first external electrode 26a, the second external electrode 26b, the third external electrode 26c, and the fourth external electrode 26d may be collectively referred to as external electrodes 26a to 26d.

[0091] As shown in FIG. 24, the laminate 25 has a substantially rectangular parallelepiped shape. The laminate 25 has a first surface 27a and a second surface 27b that face each other, a first end surface 28a and a second end surface 28b that face each other, and a first side surface 29a and a second side surface 29b that face each other. The first end surface 28a and the second end surface 28b may be perpendicular to the first direction (x-axis direction). The first side surface 29a and the second side surface 29b may be perpendicular to the second direction (y-axis direction). The first surface 27a and the second surface 27b may be perpendicular to the third direction (z-axis direction). The first surface 27a and the second surface 27b may be substantially square in plan view.

[0092] As shown in FIG. 25, the laminate 25 includes an active portion 30, a first covering portion 33, and a second covering portion 34. The active portion 30 is configured by alternately laminating a dielectric layer 31 and an internal electrode layer 32. The dielectric layer 31 and the internal electrode layer 32 are laminated in the third direction (z-axis direction). The active portion 30 forms a capacitance. In FIG. 25, the boundaries between the active portion 30 and the first covering portion and the second covering portion are indicated by two-dot chain lines, but the actual boundaries are not clearly shown. Hereinafter, the first covering portion 33 and the second covering portion 34 may be collectively referred to as covering portions 33, 34.

[0093] The dielectric layer 31 may be made of a ceramic material mainly composed of, for example, BaTiO3, CaTiO3, SrTiO3, BaZrO3, or the like. The internal electrode layer 32 may be made of a metal material mainly composed of a metal such as Ni, Cu, Sn, Pt, Pd, Ag, Au, or an alloy thereof.

[0094] The internal electrode layer 32 includes a first internal electrode layer 32a and a second internal electrode layer 32b with different polarities. The active part 30 is configured by alternately laminating the first internal electrode layer 32a and the second internal electrode layer 32b with the dielectric layer 31 interposed therebetween. In FIGS. 24 and 25, an example in which the active part 30 has two internal electrode layers 32 is shown, but the active part 30 may have more than two internal electrode layers 32.

[0095] As shown in FIG. 26B, the first internal electrode layer 32a has a capacitance forming part 32aa, a first lead-out part 32ab, and a second lead-out part 32ac. The first lead-out part 32ab is exposed on the first end face 28a and the second side face 29b. The second lead-out part 32ac is exposed on the second end face 28b and the first side face 29a. As shown in FIG. 26B, the first lead-out part 32ab and the second lead-out part 32ac are respectively located at two corner parts positioned on the diagonal line of the laminate 25 in plan view.

[0096] As shown in FIG. 26C, the second internal electrode layer 32b has a capacitance forming part 32ba, a third lead-out part 32bb, and a fourth lead-out part 32bc. The third lead-out part 32bb is exposed on the first end face 28a and the first side face 29a. The fourth lead-out part 32bc is exposed on the second end face 28b and the second side face 29b. The third lead-out part 32bb and the fourth lead-out part 32bc are respectively located at two corner parts positioned on the diagonal line of the laminate 25 in plan view.

[0097] The capacitance forming part 32aa and the capacitance forming part 32ba overlap each other in plan view. The first lead-out part 32ab does not overlap the third lead-out part 32bb and the fourth lead-out part 32bc in plan view. The second lead-out part 32ac does not overlap the third lead-out part 32bb and the fourth lead-out part 32bc in plan view.

[0098] As shown in FIG. 25, the first covering part 33 and the second covering part 34 are respectively located at both ends of the active part 30 in the third direction (z-axis direction).

[0099] As shown in FIG. 26A, the first covering portion 33 includes four dummy electrodes 33a, 33b, 33c, 33d and a first dielectric portion 33e. The four dummy electrodes 33a, 33b, 33c, 33d are respectively located at four corner portions of the laminate 25 in a plan view. The dummy electrodes 33a, 33b, 33c, 33d are exposed on the first surface 27a. The dummy electrode 33a is further exposed on the first end surface 28a and the second side surface 29b. The dummy electrode 33b is further exposed on the second end surface 28b and the first side surface 29a. The dummy electrode 33c is further exposed on the first end surface 28a and the first side surface 29a. The dummy electrode 33d is further exposed on the second end surface 28b and the second side surface 29b. The dummy electrodes 33a, 33b, 33c, 33d may be, for example, rectangular parallelepiped-shaped, cubic-shaped, triangular prism-shaped, quarter-cylindrical-shaped, etc. The dummy electrodes 33a, 33b, 33c, 33d may be made of the metal material constituting the internal electrode layer 32. The first dielectric portion 33e is made of a dielectric material and electrically insulates the dummy electrodes 33a, 33b, 33c, 33d from each other. The first dielectric portion 33e may be made of the ceramic material constituting the dielectric layer 31.

[0100] As shown in FIG. 26D, the second covering portion 34 includes four dummy electrodes 34a, 34b, 34c, 34d and a second dielectric portion 34e. The four dummy electrodes 34a, 34b, 34c, 34d are respectively located at the four corners of the laminate 25 in a plan view. The dummy electrodes 34a, 34b, 34c, 34d are exposed on the second surface 27b. The dummy electrode 34a is further exposed on the first end surface 28a and the first side surface 29a. The dummy electrode 34b is further exposed on the second end surface 28b and the second side surface 29b. The dummy electrode 34c is further exposed on the first end surface 28a and the second side surface 29b. The dummy electrode 34d is further exposed on the second end surface 28b and the first side surface 29a. The dummy electrodes 34a, 34b, 34c, 34d may be, for example, rectangular parallelepiped, cubic, triangular prism, quarter-cylindrical, etc. The dummy electrodes 34a, 34b, 34c, 34d may be made of the metal material constituting the internal electrode layer 32. The second dielectric portion 34e is made of a dielectric material and electrically insulates the dummy electrodes 34a, 34b, 34c, 34d from each other. The second dielectric portion 34e may be made of the ceramic material constituting the dielectric layer 31. Hereinafter, the dummy electrodes 33a, 33b, 33c, 33d and the dummy electrodes 34a, 34b, 34c, 34d may be collectively referred to as dummy electrodes 33a to 34d.

[0101] The first external electrode 26a is located on the first surface 27a, the first end surface 28a, the second side surface 29b and the second surface 27b. The first external electrode 26a is connected to the portion exposed on the surface of the laminate 25 in the first lead-out portion 32ab, and the portions exposed on the surface of the laminate 25 in the dummy electrode 33a and the dummy electrode 34c. The first external electrode 26a may completely cover the portion exposed on the surface of the laminate 25 in the first lead-out portion 32ab, and the portions exposed on the surface of the laminate 25 in the dummy electrode 33a and the dummy electrode 34c.

[0102] The second external electrode 26b is located on the first surface 27a, the second end surface 28b, the first side surface 29a, and the second surface 27b. The second external electrode 26b is connected to the portion exposed on the surface of the laminate 25 in the second lead-out portion 32ac, and the portions exposed on the surface of the laminate 25 in the dummy electrode 33b and the dummy electrode 34d. The second external electrode 26b may completely cover the portion exposed on the surface of the laminate 25 in the second lead-out portion 32ac, and the portions exposed on the surface of the laminate 25 in the dummy electrode 33b and the dummy electrode 34d.

[0103] The third external electrode 26c is located on the first surface 27a, the first end surface 28a, the first side surface 29a, and the second surface 27b. The third external electrode 26c is connected to the portion exposed on the surface of the laminate 25 in the third lead-out portion 32bb, and the portions exposed on the surface of the laminate 25 in the dummy electrode 33c and the dummy electrode 34a. The third external electrode 26c may completely cover the portion exposed on the surface of the laminate 25 in the third lead-out portion 32bb, and the portions exposed on the surface of the laminate 25 in the dummy electrode 33c and the dummy electrode 34a.

[0104] The fourth external electrode 26d is located on the first surface 27a, the second end surface 28b, the second side surface 29b, and the second surface 27b. The fourth external electrode 26d is connected to the portion exposed on the surface of the laminate 25 in the fourth lead-out portion 32bc, and the portions exposed on the surface of the laminate 25 in the dummy electrode 33d and the dummy electrode 34b. The fourth external electrode 26d may completely cover the portion exposed on the surface of the laminate 25 in the fourth lead-out portion 32bc, and the portions exposed on the surface of the laminate 25 in the dummy electrode 33d and the dummy electrode 34b.

[0105] The external electrodes 26a to 26d may be made of a metal material mainly composed of a metal such as Ni, Cu, Sn, Pt, Pd, Ag, Au or an alloy thereof. The external electrodes 26a to 26d may be formed using a thick film forming technique such as a dipping method, a screen printing method, or a gravure printing method. The external electrodes 26a to 26d may be configured to include a base layer in contact with the surface of the laminate 25 and an outer layer covering the base layer, similar to the external electrodes 10a and 10b shown in FIGS. 3 and 4.

[0106] The manufacturing method of the multilayer ceramic capacitor 1C is the same as the manufacturing method of the multilayer ceramic capacitor 1. First, a mother laminate is produced, and the mother laminate is cut to produce a plurality of unfired laminates 25. Subsequently, after subjecting the unfired laminate 25 to a degreasing treatment, the degreased laminate 25 is fired. Subsequently, by subjecting the fired laminate 2 to a barrel polishing treatment, a laminate 25 as shown in FIG. 24 is obtained. By forming the external electrodes 26a to 26d on the obtained laminate 25, the multilayer ceramic capacitor 1C can be manufactured.

[0107] As shown in FIGS. 24 and 25, the multilayer ceramic capacitor 1C has a configuration in which the dummy electrodes 33a to 34d have a greater thickness in the third direction (z-axis direction) than the single-layer internal electrode layer 32. Thereby, the multilayer ceramic capacitor 1C can reduce the number of dissimilar material interfaces in the covering portions 33 and 34 as compared with the conventional multilayer ceramic capacitor. As a result, the occurrence of delamination between layers in the covering portions 33 and 34 when the laminate 25 is barrel polished can be reduced, and the reliability of the multilayer ceramic capacitor 1C can be improved.

[0108] The multilayer ceramic capacitor 1C only needs to be configured such that at least one of the dummy electrodes 33a to 34d is thicker than the internal electrode layer 32. The multilayer ceramic capacitor 1C may include dummy electrodes 33a to 34d having a thickness equal to or less than the thickness of the internal electrode layer 32, such as the second dummy electrode 61b, the third dummy electrode 62a, and the fourth dummy electrode 62b shown in FIG. 5. For example, when the thickness of the dummy electrode 33b is equal to or less than the thickness of the internal electrode layer 32, the laminate 25 may have auxiliary electrode portions similar to the auxiliary electrode portions 61ba, 62aa, and 62ba shown in FIG. 5 inside (below) the dummy electrode 33b in the third direction (z-axis direction).

[0109] The dummy electrodes 33a to 34d may be single-piece dummy electrodes. The dummy electrodes 33a to 34d may be formed by laminating a plurality of dummy electrode layers, such as the dummy electrodes 61a to 62b shown in FIG. 6. In this case, it becomes easy to form the dummy electrodes 33a to 34d with dimensions as designed, and the reliability of the multilayer ceramic capacitor 1C can be improved.

[0110] The interface between at least one of the dummy electrodes 33a, 33b, 33c, and 33d and the first dielectric part 33e may have an uneven structure, such as the interfaces 61d and 62d shown in FIG. 7. In this case, when the multilayer ceramic capacitor 1C is soldered and mounted on an external substrate, even if a crack occurs from the first covering part 33, it is possible to suppress the crack from extending to the active part 30. As a result, the moisture resistance of the multilayer ceramic capacitor 1C can be increased and the reliability can be improved. The interface between at least one of the dummy electrodes 34a, 34b, 34c, and 34d and the second dielectric part 34e may have an uneven structure. Also in this case, as described above, the moisture resistance of the multilayer ceramic capacitor 1C can be increased and the reliability can be improved.

[0111] As described above, the embodiments of the present disclosure have been described in detail. However, the present disclosure is not limited to the above-described embodiments, and various changes, improvements, etc. are possible without departing from the gist of the present disclosure.

[0112] FIG. 27 is a cross-sectional view showing a multilayer ceramic capacitor 1D according to still another embodiment of the present disclosure. This embodiment is similar to the embodiment of FIG. 3, and corresponding parts are denoted by the same reference numerals, and redundant descriptions are omitted. The multilayer ceramic capacitor 1D of this embodiment may further be provided with intermediate dummy electrodes 61a1, 61b1, 62a1, and 62b1. The intermediate dummy electrodes 61a1 and 61b1 are, for example, inside (below) the first and second dummy electrodes 61a and 61b in the third direction (z-axis direction), and between the electrode layers close to the lower sides of the first and second dummy electrodes 61a and 61b, intermediate dummy electrodes 61f and 61g may be provided. The intermediate dummy electrodes 61a1 and 61b1 are electrically insulated by a dielectric layer made of a dielectric material similar to the dielectric part, and the dielectric layer may be made of a ceramic material. Further, the intermediate dummy electrodes 62a1 and 62b1 may be configured such that intermediate dummy electrodes 61a1 and 61b1 are provided inside (above) the third and fourth dummy electrodes 62a and 62b, respectively, and between the electrode layers close to the third and fourth dummy electrodes 62a and 62b. Thereby, the area of the exposed portions of the intermediate dummy electrodes 61a1, 61b1, 62a1, and 62b1 on the end faces 8a, 8b, and side faces 9a, 9b can be increased. Therefore, the reliability of the multilayer ceramic capacitor 1D can be effectively improved. Further, when the underlying layer 11 is formed by plating, for example, a plating film growing from the end of the first internal electrode layer 5a exposed from the first end face 8a can easily reach the dummy electrode 61a via the intermediate dummy electrode 61a1, and the underlying layer 11 can be easily formed.

[0113] The intermediate dummy electrodes 61a1, 61b1, 62a1, and 62b1 may have the same shape as the dummy electrodes 61a, 61b, 62a, and 62b in plan view, or may have a different shape from the dummy electrodes 61a, 61b, 62a, and 62b. Also, the intermediate dummy electrodes 61f, 61g, 62f, and 62g may have a greater thickness in the third direction (z-axis direction) than the internal electrode layer 5. The intermediate dummy electrodes 61a1, 61b1, 62a1, and 62b1 may have substantially the same dimensions as each other. The intermediate dummy electrodes 61a1, 61b1, 62a1, and 62b1 may be made of the same material as the metal material constituting the dummy electrodes 61a, 61b, 62a, and 62b. By positioning the intermediate dummy electrodes 61a1, 61b1, 62a1, and 62b1 between the active part 3 and the covering parts 61 and 62, a plating film is more likely to be formed from the active part 3 to the main surface side.

[0114] FIG. 28 is a cross-sectional view showing a multilayer ceramic capacitor 1E according to still another embodiment of the present disclosure. Note that this embodiment is similar to the embodiment of FIG. 25, and corresponding parts are denoted by the same reference numerals, and redundant descriptions are omitted. The multilayer ceramic capacitor 1E of this embodiment may further be provided with intermediate dummy electrodes 33a1, 33c1, 33b1, 33d1, 34a1, 34c1, 34b1, and 34d1. The intermediate dummy electrodes 33a1, 33c1, 33b1, and 33d1 are, for example, inside (below) each of the dummy electrodes 33a, 33c, 33b, 33d, 34a, 34c, 34b, and 34d in the third direction (z-axis direction), and may be configured such that the intermediate dummy electrodes 33a1, 33c1, 33b1, and 33d1 are provided between the dummy electrodes 33a, 33c, 33b, 33d, 34a, 34c, 34b, and 34d and an electrode layer adjacent thereto. The intermediate dummy electrodes 33a1, 33c1, 33b1, and 33d1 are electrically insulated by a dielectric layer made of a dielectric material similar to that of the dielectric part, and the dielectric layer may be made of a ceramic material. Further, the intermediate dummy electrodes 34a1, 34c1, 34b1, and 34d1 are inside (above) each of the dummy electrodes 34a, 34c, 34b, and 34d, and may be configured such that the intermediate dummy electrodes 34a1, 34c1, 34b1, and 34d1 are provided between the dummy electrodes 34a, 34c, 34b, and 34d and an electrode layer adjacent thereto.

[0115] The intermediate dummy electrodes 33a1, 33c1, 33b1, 33d1, 34a1, 34c1, 34b1, and 34d1 may have the same shape as the dummy electrodes 33a, 33c, 33b, 33d, 34a, 34c, 34b, and 34d in plan view, or may have a shape different from that of the dummy electrodes 33a, 33c, 33b, 33d, 34a, 34c, 34b, and 34d. Further, the intermediate dummy electrodes 33a1, 33c1, 33b1, 33d1, 34a1, 34c1, 34b1, and 34d1 may have a greater thickness in the third direction (z-axis direction) than the internal electrode layer 32. The dummy electrodes 33a, 33c, 33b, 33d, 34a, 34c, 34b, and 34d may have substantially the same dimensions as each other. The intermediate dummy electrodes 33a1, 33c1, 33b1, 33d1, 34a1, 34c1, 34b1, and 34d1 may be made of the metal material constituting the dummy electrodes 33a, 33c, 33b, 33d, 34a, 34c, 34b, and 34d. The dummy electrodes 33a, 33c, 33b, 33d, 34a, 34c, 34b, and 34d may have a length in the y-axis direction shorter than that of the underlying layer.

[0116] Thereby, while maintaining the property that solder hardly adheres to the side surfaces 9a and 9b, the plating film is likely to be formed from the active part to the main surface side.

[0117] FIG. 29 is a perspective view showing a laminate 2B of a multilayer ceramic capacitor according to still another embodiment of the present disclosure. Note that this embodiment is similar to the embodiment of FIG. 20, and corresponding parts are denoted by the same reference numerals, and redundant descriptions are omitted. The multilayer ceramic capacitor of this embodiment may further include intermediate dummy electrodes 61a1, 61b1, 62a1, 62b1 provided on the four dummy electrodes 61a, 61b, 62c, 62d included in the first covering portion 61. The intermediate dummy electrodes 61a1, 61b1 may be provided, for example, inside (below) each of the first and second dummy electrodes 61a, 61b in the third direction (z-axis direction) and between the first and second dummy electrodes 61a, 61b and an electrode layer close thereto. The intermediate dummy electrodes 62a1, 62b1 are electrically insulated by a dielectric layer made of a dielectric material similar to that of the dielectric portion, and the dielectric layer may be made of a ceramic material. Further, the intermediate dummy electrodes 62a1, 62b1 may be provided inside (above) each of the two dummy electrodes 34a, 34b, 34c, 34d included in the second covering portion 62 and between the third and fourth dummy electrodes 62a, 62b and an electrode layer close thereto. Thereby, the area of the exposed portions of the dummy electrodes on the end faces and side faces can be increased, so that the reliability of the multilayer ceramic capacitor can be effectively improved.

[0118] The intermediate dummy electrodes 61a1, 61b1, 62a1, and 62b1 may have the same shape as the dummy electrodes 61a, 61b, 62a, and 62b in a plan view, or may have a different shape from the dummy electrodes 61a, 61b, 62a, and 62b. Also, the intermediate dummy electrodes 61a1, 61b1, 62a1, and 62b1 may have a greater thickness in the third direction (z-axis direction) than the dummy electrodes 61a, 61b, 62a, and 62b. The dummy electrodes 61a, 61b, 62a, and 62b may have substantially the same dimensions as each other. The intermediate dummy electrodes 61a1, 61b1, 62a1, and 62b1 may be made of the metal material that constitutes the dummy electrodes 61a, 61b, 62a, and 62b. By positioning the intermediate dummy electrodes 61a1, 61b1, 62a1, and 62b1 between the active part 3 and the covering parts 61 and 62, a plating film is more likely to be formed from the active part to the main surface side.

[0119] The multilayer ceramic capacitor of the present disclosure can increase the bonding strength between the multilayer body and the external electrodes while suppressing the occurrence of delamination between the layers in the covering part. Therefore, according to the multilayer ceramic capacitor of the present disclosure, a multilayer ceramic capacitor with improved reliability can be provided.

[0120] The multilayer ceramic capacitor of the present disclosure can be implemented with the following configurations (1) to (10).

[0121] (1) An active part in which a dielectric layer and an internal electrode layer are alternately laminated, and a first covering part and a second covering part respectively positioned at both ends of the active part in the lamination direction of the dielectric layer and the internal electrode layer, which is a substantially rectangular parallelepiped-shaped multilayer body having a first surface and a second surface facing each other in the lamination direction, a first end face and a second end face facing each other, and a first side face and a second side face facing each other, A first external electrode positioned from the first end face to the first surface, the second surface, the first side face, and the second side face, A second external electrode positioned from the second end face to the first surface, the second surface, the first side face, and the second side face, The first external electrode and the second external electrode are connected to different internal electrode layers of the internal electrode layer, The first covering portion includes a first dielectric portion, a first dummy electrode and a second dummy electrode that are respectively located at both ends of the first dielectric portion in a first direction perpendicular to the first end face. The second covering portion includes a second dielectric portion, a third dummy electrode and a fourth dummy electrode that are respectively located at both ends of the second dielectric portion in the first direction. The first dummy electrode and the third dummy electrode are exposed on the first end face, and the second dummy electrode and the fourth dummy electrode are exposed on the second end face. The laminated ceramic capacitor, wherein at least one of the first dummy electrode, the second dummy electrode, the third dummy electrode, and the fourth dummy electrode is thicker than the internal electrode layer.

[0122] (2) The first dummy electrode and the second dummy electrode are further exposed on the first surface. The laminated ceramic capacitor according to the above configuration (1), wherein the third dummy electrode and the fourth dummy electrode are further exposed on the second surface.

[0123] (3) The first dummy electrode and the second dummy electrode are further exposed on the first side surface and the second side surface. The laminated ceramic capacitor according to the above configuration (1) or (2), wherein the third dummy electrode and the fourth dummy electrode are further exposed on the first side surface and the second side surface.

[0124] (4) The laminated ceramic capacitor according to any one of the above configurations (1) to (3), wherein at least one of the first dummy electrode, the second dummy electrode, the third dummy electrode, and the fourth dummy electrode includes a plurality of laminated dummy electrode layers.

[0125] (5) The laminated ceramic capacitor according to the above configuration (4), wherein the plurality of dummy electrode layers include a common material made of a dielectric material.

[0126] (6) At least one of the first dummy electrode and the second dummy electrode has an uneven structure at the interface with the first dielectric part. The multilayer ceramic capacitor according to any one of the above configurations (1) to (5), wherein at least one of the third dummy electrode and the fourth dummy electrode has an uneven structure at the interface with the second dielectric part.

[0127] (7) The first covering part further has a fifth dummy electrode and a sixth dummy electrode respectively located at both ends of the first dielectric part in the first direction. The second covering part further has a seventh dummy electrode and an eighth dummy electrode respectively located at both ends of the second dielectric part in the first direction. The multilayer ceramic capacitor according to any one of the above configurations (1) to (6), wherein the fifth dummy electrode and the seventh dummy electrode are exposed on the first end face, and the sixth dummy electrode and the eighth dummy electrode are exposed on the second end face.

[0128] (8) The first dummy electrode, the second dummy electrode, the fifth dummy electrode, and the sixth dummy electrode are further exposed on the first surface. The multilayer ceramic capacitor according to the above configuration (7), wherein the third dummy electrode, the fourth dummy electrode, the seventh dummy electrode, and the eighth dummy electrode are further exposed on the second surface.

[0129] (9) The first dummy electrode and the second dummy electrode are further exposed on the first side surface. The fifth dummy electrode and the sixth dummy electrode are further exposed on the second side surface. The third dummy electrode and the fourth dummy electrode are further exposed on the first side surface. The multilayer ceramic capacitor according to the above configuration (7) or (8), wherein the seventh dummy electrode and the eighth dummy electrode are further exposed on the second side surface.

[0130] (10) A first intermediate dummy electrode located between the first dummy electrode and the internal electrode layer in the stacking direction and having a thickness greater than that of the internal electrode layer A second intermediate dummy electrode located between the second dummy electrode and the internal electrode layer in the stacking direction and having a thickness greater than that of the internal electrode layer, A third intermediate dummy electrode located between the third dummy electrode and the internal electrode layer in the stacking direction and having a thickness greater than that of the internal electrode layer, A fourth intermediate dummy electrode located between the fourth dummy electrode and the internal electrode layer in the stacking direction and having a thickness greater than that of the internal electrode layer, and the multilayer ceramic capacitor according to any one of the above configurations (1) to (9).

[0131] Although the embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to the above-described embodiments, and various changes and improvements are possible within the scope not departing from the gist of the present disclosure. Needless to say, all or part of each of the above embodiments can be combined as appropriate within a non - conflicting range.

Description of Reference Numerals

[0132] 1, 1A, 1B, 1C, 1D, 1E Multilayer ceramic capacitor 2, 2A, 2B Stacked body 2f Opposing region 3 Active part 4 Dielectric layer 5 Internal electrode layer 5a First internal electrode layer 5aa Capacitance forming part 5ab Lead - out part 5b Second internal electrode layer 5ba Capacitance forming part 5bb Lead - out part 61 First covering part 61a First dummy electrode 61b Second dummy electrode 61ba Auxiliary electrode part 61c First dielectric part 61d Interface 61e Interface 62 Second coating part 62a Third dummy electrode 62aa Auxiliary electrode part 62b Fourth dummy electrode 62ba Auxiliary electrode part 62c Second dielectric part 62d Interface 63 Dummy electrode layer 63a Common material 64 Dielectric layer 65 Dielectric layer 66 Electrode layer 7a First surface 7b Second surface 8a First end face 8b Second end face 9a First side face 9b Second side face 10a First external electrode 10b Second external electrode 10t Inner end part 11 First layer (underlayer) 12 Second layer (outer layer) 13,13’ Ceramic green sheet (green sheet) 14 Electrode pattern 15 Pattern sheet 16 Support sheet 17 First cover sheet 18 Electrode pattern 19 Dielectric pattern 20 Second cover sheet 21 Mother laminate 22 Virtual division line 23 Mother laminate 24 Virtual division line 25 Laminate 26a First external electrode 26b Second external electrode 26c Third external electrode 26d Fourth external electrode 27a First surface 27b Second surface 28a First end face 28b Second end face 29a First side face 29b Second side 30 Active part 31 Dielectric layer 32 Internal electrode layer 32a First internal electrode layer 32aa Capacitance forming part 32ab First lead-out part 32ac Second lead-out part 32b Second internal electrode layer 32ba Capacitance forming part 32bb Third lead-out part 32bc Fourth lead-out part 33 First covering part 33a, 33b, 33c, 33dDummy electrode 33e First dielectric part 34 Second covering part 34a, 34b, 34c, 34dDummy electrode 34e Second dielectric part

Claims

1. A substantially rectangular parallelepiped laminate including an active part in which a dielectric layer and an internal electrode layer are alternately laminated, and a first covering part and a second covering part respectively positioned at both ends of the active part in the lamination direction of the dielectric layer and the internal electrode layer, the laminate having a first surface and a second surface facing each other in the lamination direction, a first end surface and a second end surface facing each other, and a first side surface and a second side surface facing each other, a first external electrode positioned from the first end surface to the first surface and the second surface, a second external electrode positioned from the second end surface to the first surface and the second surface, and the first external electrode and the second external electrode are connected to different internal electrode layers of the internal electrode layer, the first covering part has a first dielectric part, and a dummy electrode positioned at an end of the first dielectric part in a first direction orthogonal to the first end surface, the dummy electrode includes a plurality of dummy electrode layers directly laminated on each other, is thicker than the internal electrode layer, is embedded in the first covering part, and is exposed on the first surface, a multilayer ceramic capacitor.

2. The dummy electrode is continuously exposed on the first surface, The multilayer ceramic capacitor according to Claim 1.

3. The dummy electrode is continuously exposed from the first surface to the first end surface, The multilayer ceramic capacitor according to Claim 1.

4. The dummy electrode has a layered structure, The multilayer ceramic capacitor according to Claim 1.

5. The dummy electrode is mainly composed of a metal material, The multilayer ceramic capacitor according to Claim 1.

6. The dummy electrode contains more co-material made of a dielectric material than the internal electrode layer, The multilayer ceramic capacitor according to Claim 1.

7. The thickness of the dummy electrode is 3 times or more the thickness of the internal electrode layer, The multilayer ceramic capacitor according to Claim 1.

8. Further having an intermediate dummy electrode positioned between the dummy electrode and the internal electrode layer in the lamination direction and having a greater thickness than the internal electrode layer, The multilayer ceramic capacitor according to Claim 1.

9. The intermediate dummy electrode is thinner than the dummy electrode, The multilayer ceramic capacitor according to Claim 8.

10. Of the dummy electrodes, the entire end on the side opposite to the first end surface in the first direction is embedded in the first covering part and forms an interface with the first dielectric part, The multilayer ceramic capacitor according to claim 1.

11. The multilayer ceramic capacitor according to claim 10, wherein the interface has an uneven structure.

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