Semiconductor device, electronic appliance, and vehicle

Abstract

To achieve both a power source reverse connection protection function and an active clamp function.SOLUTION: A semiconductor device 1 includes a power source terminal T1, an output terminal T2, and a ground terminal T4, an internal output node OUT_R that is electrically connected to the output terminal T2, an internal ground node GND_INT that is electrically connected to the ground terminal T4, an output transistor 10 connected between the power source terminal T1 and the output terminal T2, a gate driver 31 that drives the output transistor 10, a reverse connection protection circuit 110 that turns on the output transistor 10 without depending on the gate driver 31 when the ground terminal T4 has a higher potential than the power source terminal T1, and a through-rate control circuit 130 that raises the off-time through rate of the gate driver 31 when the internal output node OUT_R has a lower potential than the internal ground node GND_INT.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, an electronic device, and a vehicle.

Background Art

[0002] The applicant of the present application has proposed a number of new technologies so far regarding in-vehicle semiconductor devices (for example, IPD [intelligent power device] or SPS [smart power switch]) (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] However, there has been room for improvement in the protection function of conventional semiconductor devices when the power supply is reversely connected (especially in compatibility with the active clamp function).

[0005] For example, the semiconductor device according to the present disclosure includes a power supply terminal, an output terminal, and a ground terminal, an internal output node configured to be conductive with the output terminal, an internal ground node configured to be conductive with the ground terminal, an output transistor connected between the power supply terminal and the output terminal, a gate driver configured to drive the output transistor, a reverse connection protection circuit configured to turn on the output transistor without depending on the gate driver when the ground terminal is at a higher potential than the power supply terminal, and a slew rate control circuit configured to increase the off-state slew rate of the gate driver when the internal output node is at a lower potential than the internal ground node.

Brief Description of the Drawings

[0006]

Figure 1

Figure 2

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Figure 4

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Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

[0007] [Detailed Description] <Electronic Device> FIG. 1 is a diagram showing a configuration example of an electronic device including a semiconductor device. The electronic device A in this configuration example includes a semiconductor device 1, a DC power supply 2, and a load 3. The DC power supply 2 may be an in-vehicle battery. The load 3 may be an engine control ECU [electronic control unit], an air conditioner, a body device, or the like.

[0008] The semiconductor device 1 is a high-side switch IC (a type of IPD) that conducts / blocks between the DC power supply 2 and the load 3. In terms of this figure, the semiconductor device 1 is formed by integrating an output transistor 10 (for example, an NMOSFET [N-channel type metal oxide semiconductor field effect transistor]) and a controller 11.

[0009] In this specification, a MOSFET refers to a transistor whose gate structure consists of at least three layers: "a layer made of a conductor or a semiconductor such as polysilicon with a low resistance value", "an insulating layer", and "a P-type, N-type, or intrinsic semiconductor layer". That is, the gate structure of a MOSFET is not limited to a three-layer structure of metal, oxide, and semiconductor.

[0010] The semiconductor device 1 also includes external terminals T1 to T4 as means for establishing electrical connection with the outside of the device.

[0011] The external terminal T1 is a power supply terminal (VBB pin) for receiving the supply of a power supply voltage VB (for example, 12V) from the DC power supply 2. The external terminal T2 is a load connection terminal or output terminal (OUT pin) for externally connecting a load 3 (such as a bulb lamp, relay coil, solenoid, light-emitting diode, or motor). The external terminal T3 is a signal input terminal (IN pin) for receiving an external input of an external control signal Si from an ECU or the like. The external terminal T4 is a ground terminal (GND pin) to which a ground voltage GND is applied.

[0012] The output transistor 10 is an example of an insulated-gate power transistor. In accordance with this figure, the output transistor 10 is connected between the external terminal T1 and the external terminal T2. The output transistor 10 is driven in response to a gate drive signal G1 input to the gate. The output transistor 10 thus connected functions as a high-side switch element for conducting / blocking between the external terminal T1 and the external terminal T2.

[0013] The controller 11 includes a plurality of types of functional circuits that realize various functions. For example, the plurality of types of functional circuits include a circuit for generating a gate drive signal G1 for driving and controlling the output transistor 10 based on the external control signal Si.

[0014] The external terminal T1 supplies the drain of the output transistor 10 and the controller 11 with the power supply voltage VB. The external terminal T2 is connected to the source of the output transistor 10 and supplies the load 3 with the output voltage Vo and the output current Io. An inductance component L (and a resistance component) generally accompanies the signal line (e.g., a wire harness) laid between the external terminal T2 and the load 3. The external terminal T3 transmits the external control signal Si to the controller 11. The external control signal Si can be understood as the drive voltage of the controller 11. The external terminal T4 transmits the ground voltage GND to the controller 11. A resistance component R generally accompanies between the external terminal T4 and the ground terminal.

[0015] <Semiconductor device (overall configuration)> FIG. 2 is a diagram showing the overall configuration of the semiconductor device 1 (particularly an example of the specific internal configuration of the controller 11). The semiconductor device 1 includes, as components of the controller 11, a sense transistor 20, a gate control unit 30, a control logic unit 40, a signal input unit 50, an internal power supply unit 60, an abnormal protection unit 70, an output current detection unit 80, a signal output unit 90, an active clamp circuit 100, an inverse connection protection circuit 110, and a reverse current prevention circuit 120.

[0016] In addition to the above-mentioned external terminals T1 to T4, the semiconductor device 1 further includes external terminals T5 and T6. The external terminal T5 is a signal input terminal (EN pin) for receiving an external input of an external enable signal Se from an ECU or the like. The external terminal T6 is a signal output terminal (SENSE pin) for externally outputting a status notification signal So to an ECU or the like. Note that a pull-down resistor may be externally attached between the external terminal T6 and the ground terminal.

[0017] The output transistor 10 is a high-voltage withstand (for example, 42V withstand voltage) power transistor with its drain connected to the external terminal T1 and its source connected to the external terminal T2. The output transistor 10 connected in this way functions as a switch element (high-side switch) for conducting / interrupting the current path from the applied end of the power supply voltage VB to the ground end via the load 3. Note that the output transistor 10 turns on when the gate drive signal G1 is at a high level and turns off when the gate drive signal G1 is at a low level.

[0018] Also, the output transistor 10 may be designed such that its on-resistance Ron is several mΩ to several tens of mΩ (for example, 4mΩ). However, the lower the on-resistance Ron of the output transistor 10, the easier it is for an overcurrent to flow and abnormal heat generation to occur when a ground fault (= a short-circuit abnormality to the ground end or a low-potential end equivalent thereto) occurs at the external terminal T2. Therefore, the lower the on-resistance Ron of the output transistor 10, the higher the importance of the overcurrent protection circuit 71 and the temperature protection circuit 73 described later.

[0019] Note that an NMOSFET exhibits an on-resistance that is 2 to 3 times better than that of a PMOSFET [P-channel type MOSFET] with the same element area. Therefore, an NMOSFET is suitable as the output transistor 10. However, in order to fully turn on the NMOSFET, a boost voltage VG higher than the power supply voltage VB is required.

[0020] The sense transistor 20 (e.g., NMOSFET) generates a sense current Is corresponding to the output current Io flowing through the output transistor 10. The size ratio between the output transistor 10 and the sense transistor 20 is m:1 (where m > 1). Therefore, the sense current Is has a magnitude obtained by reducing the output current Io by 1 / m. The sense transistor 20 has a gate common with the output transistor 10 and is driven synchronously with the output transistor 10 in response to the gate drive signal G1. That is, the sense transistor 20, like the output transistor 10, turns on when the gate drive signal G1 is at a high level and turns off when the gate drive signal G1 is at a low level.

[0021] The gate control unit 30 generates a gate drive signal G1 with enhanced current capability of the gate control signal S1 and outputs it to the gates of the output transistor 10 and the sense transistor 20. Thereby, the gate control unit 30 performs on / off control of the output transistor 10. Note that the gate control unit 30 has a function of controlling the output transistor 10 so as to limit the output current Io in response to the overcurrent protection signal S71.

[0022] Referring to this figure, the gate control unit 30 includes a gate driver 31, an oscillator 32, and a charge pump 33.

[0023] The gate driver 31 receives the supply of the boosted voltage VG from the charge pump 33 and generates a gate drive signal G1 with enhanced current capability of the gate control signal S1. Note that the gate drive signal G1 becomes high level (=VG) when the gate control signal S1 is at a high level and becomes low level (=Vo) when the gate control signal S1 is at a low level.

[0024] The oscillator 32 generates a clock signal CLK with a predetermined frequency and outputs it to the charge pump 33. The operation enable / disable of the oscillator 32 is controlled in response to the enable signal SA from the control logic unit 40.

[0025] The charge pump 33 drives the flying capacitor using the clock signal CLK to generate a boosted voltage VG higher than the power supply voltage VB and supply it to the gate driver 31. The operation of the charge pump 33 is controlled according to the enable signal SB from the control logic unit 40.

[0026] Note that the oscillator 32 and the charge pump 33 may each operate receiving the supply of the power supply voltage VB and an internal node voltage VBBM5 (= VB - 5V) that is lower than the power supply voltage VB by a predetermined value (for example, 5V).

[0027] The control logic unit 40 generates the gate control signal S1 receiving the supply of the internal power supply voltage Vreg. For example, when the external control signal Si is at a high level (the logic level when turning on the output transistor 10), the internal power supply voltage Vreg is supplied from the internal power supply unit 60. As a result, the control logic unit 40 enters an operating state, and the gate control signal S1 becomes a high level (= Vreg). On the other hand, when the external control signal Si is at a low level (the logic level when turning off the output transistor 10), the internal power supply voltage Vreg is not supplied from the internal power supply unit 60. As a result, the control logic unit 40 enters a non-operating state, and the gate control signal S1 becomes a low level (= GND).

[0028] Note that the control logic unit 40 monitors various abnormal protection signals (overcurrent protection signal S71, open protection signal S72, temperature protection signal S73, and undervoltage protection signal S74). Also, the control logic unit 40 has a function of generating an output switching signal S2 based on a fault signal S70 according to the monitoring results of the overcurrent protection signal S71, the open protection signal S72, and the temperature protection signal S73 among the above-described abnormal protection signals.

[0029] The signal input unit 50 includes Schmitt triggers 51 and 52. The Schmitt trigger 51 receives an external control signal Si from an external terminal T3 and transmits it to the internal power supply unit 60. The external control signal Si goes high when the output transistor 10 is turned on, and goes low when the output transistor 10 is turned off. The Schmitt trigger 52 receives an external enable signal Se from an external terminal T5 and transmits it to the internal power supply unit 60. Note that a signal independent of the external control signal Si may be input as the external enable signal Se. Also, the external control signal Si may be input to serve as the external enable signal Se (i.e., Se=Si).

[0030] The internal power supply unit 60 generates a predetermined internal power supply voltage Vreg from the power supply voltage VB and supplies it to each unit of the semiconductor device 1. The internal power supply unit 60 may generate an internal node voltage VBBM5 from the power supply voltage VB. The operation of the internal power supply unit 60 is controlled according to an external control signal Si and an external enable signal Se. For example, when at least one of the external control signal Si and the external enable signal Se is at a high level, the internal power supply unit 60 is in an operating state, that is, in a state in which the internal power supply voltage Vreg and the internal node voltage VBBM5 are generated. On the other hand, when both the external control signal Si and the external enable signal Se are at a low level, the internal power supply unit 60 is in an inoperable state, that is, in a state in which the generation of the internal power supply voltage Vreg and the internal node voltage VBBM5 is stopped.

[0031] The abnormality protection unit 70 is a circuit block that detects various abnormalities in the semiconductor device 1. With reference to this figure, the abnormality protection unit 70 includes an overcurrent protection circuit 71, an open protection circuit 72, a temperature protection circuit 73, and an undervoltage protection circuit 74.

[0032] The overcurrent protection circuit 71 generates an overcurrent protection signal S71 according to the result of monitoring the sense current Is (=whether or not an overcurrent abnormality occurs in the output current Io). For example, the overcurrent protection signal S71 goes to a low level when no abnormality is detected, and goes to a high level when an abnormality is detected.

[0033] The open protection circuit 72 generates an open protection signal S72 according to the monitoring result of the output voltage Vo (= whether there is an open abnormality in the load 3). The open protection signal S72, for example, is at a low level when no abnormality is detected and at a high level when an abnormality is detected.

[0034] The temperature protection circuit 73 includes a temperature detection element (not shown) that detects abnormal heat generation in the semiconductor device 1 (particularly around the output transistor 10), and generates a temperature protection signal S73 according to the detection result (= whether there is abnormal heat generation). The temperature protection signal S73, for example, is at a low level when no abnormality is detected and at a high level when an abnormality is detected.

[0035] The undervoltage protection circuit 74 generates an undervoltage protection signal S74 according to the monitoring results of the power supply voltage VB and the internal power supply voltage Vreg (= whether there is an undervoltage abnormality). The undervoltage protection signal S74, for example, is at a low level when no abnormality is detected and at a high level when an abnormality is detected.

[0036] The output current detection unit 80 generates a sense current Is (= Io / m) corresponding to the output current Io by matching the source voltage Vs of the sense transistor 20 with the output voltage Vo using bias means (not shown), and outputs it to the signal output unit 90.

[0037] The signal output unit 90 selectively outputs either the sense current Is (corresponding to the detection result of the output current Io) or the fixed voltage V90 (corresponding to the abnormal flag) to the external terminal T6 based on the output switching signal S2. A sense resistor Rs can be connected between the external terminal T6 and the ground terminal. When the sense current Is is selectively output, the output detection voltage V80 (= Is × Rs) obtained by converting the sense current Is with the sense resistor Rs is transmitted to the ECU as the status notification signal So. The output detection voltage V80 increases as the output current Io increases and decreases as the output current Io decreases. On the other hand, when the fixed voltage V90 is selectively output, the fixed voltage V90 is transmitted to the ECU as the status notification signal So. When reading the current value of the output current Io from the status notification signal So, the status notification signal So may be subjected to A / D [analog-to-digital] conversion. On the other hand, when reading the abnormal flag from the status notification signal So, the logic level of the status notification signal So may be determined using a threshold value slightly lower than the fixed voltage V90.

[0038] The active clamp circuit 100 is connected between the external terminal T1 and the gate of the output transistor 10. In the electronic device A where the inductive load 3 is connected to the external terminal T2, when the output transistor 10 is switched from the on state to the off state, the output voltage Vo becomes a negative voltage (Vo < GND) due to the back electromotive force of the load 3. Therefore, the active clamp circuit 100 is provided for energy absorption.

[0039] In the reverse connection protection circuit 110, in the power supply reverse connection state (a state where the positive and negative polarities of the DC power supply 2 are erroneously connected in the reverse direction), the external terminal T1 becomes a lower potential than the external terminal T4 (VB < GND). At this time, the reverse connection protection circuit 110 turns on the output transistor 10 regardless of the external control signal Si, thereby conducting between the external terminal T1 and the external terminal T2. As a result, the current flowing from the external terminal T4 toward the external terminal T1 through the load 3 and the external terminal T2 flows through the output transistor 10 having a lower on-resistance value than the body diode of the output transistor 10. Therefore, the power consumption (and thus the heat generation) of the semiconductor device 1 can be reduced.

[0040] When the external terminal T1 is at a lower potential (VB < GND) than the external terminal T4, the reverse current prevention circuit 120 cuts off the current path from the external terminal T4 to the external terminal T1 through the internal elements (such as the control logic unit 40) integrated in the semiconductor device 1. Thereby, destruction of the internal elements integrated in the semiconductor device 1 can be prevented without externally attaching discrete elements such as current limiting resistors or reverse current prevention diodes to the external terminal T4.

[0041] <Active clamp circuit> FIG. 3 is a diagram showing a configuration example of the active clamp circuit 100. The active clamp circuit 100 of this configuration example includes a Zener diode string 101 of m stages (where m is an integer of 1 or more, and m = 2 in this figure), a diode string 102 of n stages (where n is an integer of 1 or more, and n = 1 in this figure), a transistor 103 (for example, NMOSFET), and resistors 104 and 105.

[0042] The cathode of the Zener diode string 101 and the drain of the transistor 103 are connected to the external terminal T1 together with the drain of the output transistor 10. The anode of the Zener diode string 101 is connected to the anode of the diode string 102. The cathode of the diode string 102 and the first end of the resistor 104 are both connected to the gate of the transistor 103. The source of the transistor 103 and the first end of the resistor 105 are both connected to the gate of the output transistor 10 (= the applied end of the gate drive signal G1). The source of the output transistor 10 and the second ends of the resistors 104 and 105 are all connected to the external terminal T2. An inductive load such as a coil or a solenoid can be connected to the external terminal T2 as the load 3 (see FIG. 1).

[0043] Hereinafter, the active clamp operation by the active clamp circuit 100 will be described, where the gate-source voltages of the output transistor 10 and the transistor 103 are Vgs1 and Vgs2, respectively, the breakdown voltage of the Zener diode string 101 is mVz, and the forward voltage drop of the diode string 102 is nVf.

[0044] FIG. 4 is a diagram showing an example of the active clamp operation by the active clamp circuit 100. In this figure, the external control signal Si, the output voltage Vo, and the output current Io are depicted in order from the top. Note that it is assumed that an inductive load is connected as the load 3.

[0045] At time t11, when the external control signal Si is raised to a high level (= the logic level when turning on the output transistor 10), the gate drive signal G1 rises to a high level, and the output transistor 10 turns on. Accordingly, the output current Io starts to flow, and the output voltage Vo rises to near the power supply voltage VB.

[0046] Thereafter, at time t12, when the external control signal Si is lowered to a low level (= the logic level when turning off the output transistor 10), the gate drive signal G1 falls to a low level, and the output transistor 10 turns off. At this time, the inductive load (such as a coil or a solenoid) connected as the load 3 continues to flow the output current Io until it discharges the energy stored during the on period of the output transistor 10. As a result, the output voltage Vo drops to a negative voltage lower than the ground voltage GND.

[0047] However, due to the operation of the active clamp circuit 100, the voltage Vgs1 between the gate and source of the output transistor 10 is maintained near the on threshold voltage Vth of the output transistor 10. Therefore, the output transistor 10 does not turn fully off. Accordingly, the output current Io is discharged through the output transistor 10. At this time, the output voltage Vo is limited to be equal to or higher than a lower limit voltage VB - Vclp (for example, VB - 50V) which is lower than the power supply voltage VB by the active clamp voltage Vclp (= mVz + nVf + Vgs1 + Vgs2).

[0048] In this way, the active clamp circuit 100 restricts the drain-source voltage Vds (= VB - Vo) of the output transistor 10 to be equal to or less than a predetermined active clamp voltage Vclp by not fully turning off the output transistor 10 during the off-transition of the output transistor 10.

[0049] <Semiconductor device (first embodiment)> FIG. 5 is a diagram showing a first embodiment of the semiconductor device 1 (which corresponds to a comparative example to be compared with the second embodiment described later). In this figure, as components of the semiconductor device 1, the external terminals T1, T2, and T4 described above, the output transistor 10, the gate driver 31, the active clamp circuit 100, and the reverse connection protection circuit 110 are depicted. Also, in this figure, as internal nodes of the semiconductor device 1, the internal output node OUT_R and the internal ground node GND_INT are depicted. Further, in this figure, a resistor R0 connected between the external terminal T2 and the internal output node OUT_R is depicted.

[0050] The external terminal T1 is a power supply terminal (VBB pin) to which the power supply voltage VB is applied when the DC power supply 2 is connected with the correct polarity. The external terminal T2 is an output terminal (OUT pin) to which the load 3 is externally connected. The external terminal T2 is electrically connected to the internal output node OUT_R via the resistor R0. The external terminal T4 is a ground terminal (GND pin) to which the ground voltage GND is applied when the DC power supply 2 is connected with the correct polarity.

[0051] The gate driver 31 is connected between the application terminal of the boosted voltage VG and the internal output node OUT_R. The gate driver 31 generates a gate current Ig1 to drive the output transistor 10. The gate driver 31 has a function of stopping the generation operation of the gate current Ig1 in response to the drive-off signal GDoff output from the active clamp circuit 100.

[0052] The output transistor 10 is a power transistor with its drain connected to the external terminal T1 and its source connected to the external terminal T2. During the on / off transition period of the output transistor 10, a gate current Ig flows through the output transistor 10. The gate current Ig can be understood as the sum current (Ig = Ig1 + Ig2 + Iac) of the gate currents Ig1 and Ig2 and the active clamp current Iac.

[0053] The active clamp circuit 100 limits the drain-source voltage Vds (= VB - Vo) of the output transistor 10 to a predetermined active clamp voltage Vclp or less during the off transition of the output transistor 10. During the active clamp operation, an active clamp current Iac flows from the external terminal T1 through the active clamp circuit 100 to the gate of the output transistor 10. As a result, the output transistor 10 enters an on state (a state where it does not turn fully off). The active clamp circuit 100 has a function of outputting a drive off signal GDoff at the timing when the drain-source voltage Vds of the output transistor 10 reaches the active clamp voltage Vclp (or the timing immediately before that).

[0054] The reverse connection protection circuit 110 turns on the output transistor 10 without relying on the gate driver 31 when the external terminal T4 is at a higher potential than the external terminal T1. Speaking with reference to this figure, the reverse connection protection circuit 110 includes transistors M1a and M1b (for example, depletion-type NMOSFETs), a diode D1, and resistors R1 and R2. Note that enhancement-type NMOSFETs may be used as the transistors M1a and M1b.

[0055] The first terminal of resistor R1 is connected to the gate of output transistor 10. The second terminal of resistor R1 is connected to the drain of transistor M1a. The source of transistor M1a is connected to the drain of transistor M1b. The source of transistor M1b is connected to external terminal T4. The back gates of transistors M1a and M1b and the anode of diode D1 are connected to internal ground node GND_INT. The cathode of diode D1 and the first terminal of resistor R2 are connected to the gates of transistors M1a and M1b respectively. The second terminal of resistor R2 is connected to external terminal T4.

[0056] Thus, the reverse connection protection circuit 110 includes resistor R1 connected in series between the gate of output transistor 10 and external terminal T4, transistors M1a and M1b, diode D1 whose cathode is connected to the gates of transistors M1a and M1b respectively and whose anode is connected to internal ground node GND_INT, and resistor R2 connected between the gates of transistors M1a and M1b and external terminal T4.

[0057] Note that internal ground node GND_INT is electrically connected to external terminal T4 via diode D1 and resistor R2.

[0058] When DC power supply 2 is connected with the wrong polarity, that is, when external terminal T4 is at a higher potential than external terminal T1, both transistors M1a and M1b are turned on. Therefore, gate current Ig2 flows from external terminal T4 toward the gate of output transistor 10, so output transistor 10 is turned on. At this time, the reverse current flowing from external terminal T4 through load 3 and external terminal T2 toward external terminal T1 flows through output transistor 10 which is a low on-resistance element (several mΩ) instead of the body diode associated with output transistor 10. As a result, the power consumption (and thus heat generation) of the body diode is suppressed, making it difficult for semiconductor device 1 to be destroyed when the power supply is reverse-connected.

[0059] <Considerations on the Compatibility between Active Clamp Circuit 100 and Reverse Connection Protection Circuit 110> FIG. 6 is a diagram showing the turn-off behavior of the first embodiment when the DC power supply 2 is connected with the correct polarity. In this figure, from top to bottom, an external control signal Si, an output voltage Vo, an output current Io, gate currents Ig1 (solid line) and Ig2 (dashed line), and a gate current Ig are depicted.

[0060] Note that as the load 3, an inductive load is assumed to be connected. Also, regarding the flowing directions of the gate currents Ig1, Ig2, and Ig respectively, the direction flowing into the gate of the output transistor 10 is defined as positive, and the direction flowing out from the gate of the output transistor 10 is defined as negative.

[0061] At time t21, when the external control signal Si is raised to a high level (= the logic level when turning on the output transistor 10), the gate drive signal G1 rises to a high level and the output transistor 10 turns on. Accordingly, the output current Io starts to flow and the output voltage Vo rises to near the power supply voltage VB.

[0062] Note that during the high-level period (time t21 to t22) of the external control signal Si, the gate driver 31 generates a positive-direction gate current Ig1 (= +Ix). On the other hand, a negative-direction gate current Ig2 flows through the depletion-type transistors M1a and M1b in the reverse connection protection circuit 110.

[0063] Here, in order to raise the gate drive signal G1 to a high level, it is necessary to charge the gate capacitance by flowing a gate current Ig (= Ig1 + Ig2) toward the gate of the output transistor 10. Therefore, during time t21 to t22, the positive-direction gate current Ig1 must be larger than the negative-direction gate current Ig2. Note that if the transistors M1a and M1b are enhancement type, the negative-direction gate current Ig2 does not flow.

[0064] At time t22, when the external control signal Si is lowered to the low level (the logic level when turning off the output transistor 10), the gate drive signal G1 falls to the low level and the output transistor 10 turns off. At this time, the inductive load (such as a coil or solenoid) connected as the load 3 continues to conduct the output current Io until it discharges the energy stored during the on period of the output transistor 10. As a result, at time t23, the output voltage Vo drops to a negative voltage lower than the ground voltage GND.

[0065] Note that when the external control signal Si is lowered to the low level, the gate driver 31 generates a negative gate current Ig1 (= -Ix). On the other hand, in the reverse protection circuit 110, a gate current Ig2 flows in a direction corresponding to the positive or negative of the output voltage Vo.

[0066] Speaking with reference to this figure, during the period when the output voltage Vo is at a higher potential than the ground voltage GND (times t22 to t23), a negative gate current Ig2 flows through the reverse protection circuit 110. However, the negative gate current Ig2 gradually decreases as the output voltage Vo approaches the ground voltage GND.

[0067] On the other hand, during the period when the output voltage Vo is at a lower potential than the ground voltage GND (times t23 to t25), a positive gate current Ig2 flows through the reverse protection circuit 110. Thus, a positive gate current Ig2 can flow through the reverse protection circuit 110 not only during power reverse connection but also during active clamp operation.

[0068] Here, in order to lower the gate drive signal G1 to the low level, it is necessary to discharge the gate capacitance by extracting a gate current Ig (= Ig1 + Ig2) from the gate of the output transistor 10. Therefore, between times t23 and t24, the negative gate current Ig1 must be larger than the positive gate current Ig2.

[0069] At time t24, when the drain-source voltage Vds (= VB - Vo) of the output transistor 10 reaches the active clamp voltage Vclp, an active clamp current Iac flows into the gate of the output transistor 10, and the output transistor 10 enters an on state (a state where it does not fully turn off). As a result, the output voltage Vo is limited to be equal to or higher than a lower limit voltage VB - Vclp, which is lower than the power supply voltage VB by the active clamp voltage Vclp.

[0070] At this time, the gate driver 31 stops the generation operation of the gate current Ig1 in response to the drive-off signal GDoff. On the other hand, a forward gate current Ig2 continues to flow through the reverse protection circuit 110.

[0071] At time t25, when all the energy stored in the load 3 is released, the output current Io stops flowing, so the output voltage Vo becomes 0V. As a result, the active clamp operation ends, and the gate current Ig also stops flowing.

[0072] By the way, at times t23 to t24, if the forward gate current Ig2 is larger than the negative gate current Ig1, the discharge of the gate capacitance cannot continue, so the gate control signal G1 can be clamped near the ground voltage GND. Therefore, there is a possibility that the drain-source voltage Vds of the output transistor 10 may not reach the desired active clamp voltage Vclp.

[0073] Therefore, in order to operate the active clamp circuit 100 normally, as described above, at times t23 to t24, the negative gate current Ig1 must be larger than the forward gate current Ig2.

[0074] Note that the reverse protection circuit 110 needs to have a gate driving ability to raise the gate driving signal G1 to a high level even in a situation where parasitic elements of the semiconductor device 1 operate and a leakage current flows out from the gate of the output transistor 10 when the power supply is reverse-connected.

[0075] Therefore, in order to operate the active clamp circuit 100 normally, instead of reducing the positive gate current Ig2, the negative gate current Ig1 must be set to a large value. However, the larger the current value (±Ix) of the gate current Ig1, the larger the slew rate of the gate driver 31. Note that the on-slew rate of the gate driver 31 can be understood as the rising speed of the output voltage Vo. On the other hand, the off-slew rate of the gate driver 31 can be understood as the falling speed of the output voltage Vo.

[0076] Thus, the rapidly changing output voltage Vo can be a noise source. Also, in the ground fault test of the inductive load imposed on the semiconductor device 1, when the slew rate of the gate driver 31 is large, the output current Io rises with a delay after the output voltage Vo rises. Therefore, a large amount of energy is stored in the inductive load before overcurrent protection is applied, which may lead to a decrease in the ground fault tolerance.

[0077] In view of the above considerations, a second embodiment that can achieve both the power reverse connection protection function and the active clamp function is proposed below.

[0078] <Semiconductor Device (Second Embodiment)> FIG. 7 is a diagram showing a second embodiment of the semiconductor device 1. The semiconductor device 1 of this embodiment includes a slew rate control circuit 130 while being based on the above-described first embodiment (FIG. 5). The slew rate control circuit 130 increases the off-slew rate of the gate driver 31 when the internal output node OUT_R is at a lower potential than the internal ground node GND_INT.

[0079] For example, the slew rate control circuit 130 switches the magnitude of the gate current Ig1 generated by the gate driver 31 during the off-transition period of the output transistor 10 according to whether the internal output node OUT_R is at a lower potential than the internal ground node GND_INT.

[0080] Note that, referring to this figure, the slew rate control circuit 130 includes transistors M2 and M3 (e.g., NMOSFETs), transistors M4 and M5 (e.g., PMOSFETs), diode D2, and resistors R3 and R4.

[0081] The first end of resistor R3 is connected to the internal ground node GND_INT. The second end of resistor R3 is connected to the drain of transistor M2. The gates of transistors M2 and M3 are each connected to the drain of transistor M2. The sources and back gates of transistors M2 and M3 are each connected to the internal output node OUT_R.

[0082] Transistors M2 and M3 connected in this way form a current mirror CM1 that mirrors the current signal I1 flowing through the drain of transistor M2 as the current signal I2 flowing through the drain of transistor M3.

[0083] The sources and back gates of transistors M4 and M5 are both connected to the external terminal T1. The gates of transistors M4 and M5 are both connected to the drain of transistor M4. The drain of transistor M4 is connected to the drain of transistor M3. The drain of transistor M5 is connected to the applied end of the slew rate control signal SRctr.

[0084] Transistors M4 and M5 connected in this way form a current mirror CM2 that mirrors the current signal I2 flowing through the drain of transistor M4 as the current signal I3 flowing through the drain of transistor M5.

[0085] The cathode of diode D2 and the first end of resistor R4 are both connected to the applied end of the slew rate control signal SRctr. The anode of diode D2 and the second end of resistor R4 are both connected to the internal output node OUT_R.

[0086] When the internal output node OUT_R is at a lower potential than the internal ground node GND_INT, a current signal I1 flows from the internal ground node GND_INT through the resistor R3 and the transistor M2 towards the internal output node OUT_R. Therefore, since the current signals I2 and I3 flow, the slew rate control signal SRctr becomes high level (≈ VB).

[0087] On the other hand, when the internal output node OUT_R is at a higher potential than the internal ground node GND_INT, the current signal I1 does not flow. Therefore, since the current signals I2 and I3 also do not flow, the slew rate control signal SRctr becomes low level (≈ GND).

[0088] In this way, the slew rate control circuit 130 includes a resistor R3 connected between the internal ground node GND_INT and the internal output node OUT_R, current mirrors CM1 and CM2 that mirror the current signal I1 flowing through the resistor R3 when the internal output node OUT_R is at a lower potential than the internal ground node GND_INT to generate the slew rate control signal SRctr, a resistor R4 connected between the output terminal of the slew rate control signal SRctr and the internal output node OUT_R, and a diode D2 whose cathode is connected to the output terminal of the slew rate control signal SRctr and whose anode is connected to the internal output node OUT_R.

[0089] The gate driver 31 switches the current value of the gate current Ig1 according to the slew rate control signal SRctr. For example, when the slew rate control signal SRctr is at high level, the gate driver 31 sets the gate current Ig1 to the current value ±Ix. On the other hand, when the slew rate control signal SRctr is at low level, the gate driver 31 sets the gate current Ig1 to the current value ±Iy whose absolute value is smaller than the current value ±Ix.

[0090] FIG. 8 is a diagram showing the turn-off behavior of the second embodiment when the DC power supply 2 is connected with the correct polarity. In this figure, as in the previous FIG. 6, from top to bottom in order, the external control signal Si, the output voltage Vo, the output current Io, the gate currents Ig1 (solid line) and Ig2 (dashed line), and the gate current Ig are depicted.

[0091] Note that as the load 3, an inductive load is assumed to be connected. Also, regarding the flowing directions of the gate currents Ig1, Ig2, and Ig respectively, the direction flowing into the gate of the output transistor 10 is defined as positive, and the direction flowing out from the gate of the output transistor 10 is defined as negative.

[0092] At time t31, when the external control signal Si is raised to the high level (= the logic level when turning on the output transistor 10), the gate drive signal G1 rises to the high level and the output transistor 10 turns on. Accordingly, the output current Io starts to flow and the output voltage Vo rises to near the power supply voltage VB.

[0093] Note that during the high level period of the external control signal Si (time t31 to t32), the output voltage Vo becomes a positive voltage (OUT_R > GND_INT). Accordingly, the slew rate control signal SRctr becomes the low level. At this time, the gate driver 31 sets the positive direction gate current Ig1 to the current value +Iy (< +Ix). As a result, compared with the previous first embodiment (FIG. 6), the on-time slew rate of the gate driver 31 is suppressed to be small, so that the output voltage Vo rises relatively gently. Note that regarding the point that the positive direction gate current Ig1 (= +Iy) must be larger than the negative direction gate current Ig2 at times t31 to t32, it is the same as the previous first embodiment (FIG. 6).

[0094] At time t32, when the external control signal Si is lowered to a low level (= the logic level when turning off the output transistor 10), the gate drive signal G1 falls to the low level and the output transistor 10 turns off. At this time, the inductive load (such as a coil or solenoid) connected as the load 3 continues to flow the output current Io until it discharges the energy stored during the on-period of the output transistor 10. As a result, at time t33, the output voltage Vo drops to a negative voltage lower than the ground voltage GND.

[0095] While the output voltage Vo is a positive voltage (OUT_R > GND_INT), the slew rate control signal SRctr becomes a low level. At this time, the gate driver 31 sets the negative gate current Ig1 to the current value -Iy (>-Ix). As a result, compared with the above-described first embodiment (FIG. 6), the off-time slew rate of the gate driver 31 is suppressed to be small, so that the output voltage Vo rises relatively gently.

[0096] At time t33, when the output voltage Vo drops to a negative voltage (OUT_R < GND_INT), the slew rate control signal SRctr becomes a high level. At this time, the gate driver 31 switches the negative gate current Ig1 to the current value -Ix (<-Iy). That is, the off-time slew rate of the gate driver 31 is increased. The negative gate current Ig1 (=-Ix) may be set to a current value larger than the positive gate current Ig2. As a result, even if the positive gate current Ig2 flows through the reverse connection protection circuit 110, the gate current Ig (= Ig1 + Ig2) can be extracted from the gate of the output transistor 10, so that the gate drive signal G1 is lowered to the low level.

[0097] At time t34, when the drain-source voltage Vds (= VB - Vo) of the output transistor 10 reaches the active clamp voltage Vclp, an active clamp current Iac flows into the gate of the output transistor 10, and the output transistor 10 enters an on state (a state where it does not fully turn off). As a result, the output voltage Vo is limited to be equal to or higher than a lower limit voltage VB - Vclp, which is lower than the power supply voltage VB by the active clamp voltage Vclp.

[0098] At this time, the gate driver 31 stops the operation of generating the gate current Ig1 in response to the drive-off signal GDoff. On the other hand, a forward gate current Ig2 continues to flow through the reverse protection circuit 110.

[0099] At time t35, when all the energy stored in the load 3 is released, the output current Io stops flowing, so the output voltage Vo becomes 0V. As a result, the active clamp operation ends, and the gate current Ig also stops flowing. Note that after time t34, it is basically the same as after time t24 in the first embodiment (Fig. 6).

[0100] As described above, in the semiconductor device 1 of this embodiment, the current value of the gate current Ig1 is switched according to whether the output voltage Vo is a negative voltage. Specifically, when the output voltage Vo is a positive voltage (OUT_R > GND_INT), the gate currents Ig1 in the positive and negative directions are set to relatively small current values ±Iy (times t21 to t22 and times t22 to t23). That is, both the on-state slew rate and the off-state slew rate of the gate driver 31 are suppressed to be small. Therefore, the output voltage Vo varies relatively gently, and it is difficult for noise to occur.

[0101] Also, in the ground fault test of the inductive load imposed on the semiconductor device 1, when the slew rate of the gate driver 31 is reduced, the delay of the rise of the output current Io with respect to the rise of the output voltage Vo becomes smaller. Generally, when the output voltage Vo and the output current Io rise simultaneously, the heat generation of the output transistor 10 increases, so it is easier for overheat protection to be applied before overcurrent protection is applied. As a result, it becomes difficult to store excessive energy in the inductive load, so the ground fault tolerance can be improved.

[0102] On the other hand, when the output voltage Vo is a negative voltage (OUT_R < GND_INT), the negative gate current Ig1 is set to a relatively large current value -Ix (at times t23 to t24). That is, the off-time slew rate of the gate driver 31 is increased. Therefore, even if a positive gate current Ig2 flows through the reverse connection protection circuit 110, the gate current Ig is surely drawn out from the gate of the output transistor 10, so the gate drive signal G1 is lowered to a low level. As a result, the drain-source voltage Vds of the output transistor 10 reaches the desired active clamp voltage Vclp.

[0103] <Polysilicon diode> FIG. 9 is a diagram showing a schematic configuration of a diode integrated in the semiconductor device 1 (= a diagram showing a longitudinal sectional structure of the semiconductor device 1). The semiconductor device 1 of this configuration example includes an n-type substrate 201, an n-type epitaxial layer 202, an n-type polysilicon region 203, and a p-type polysilicon region 204.

[0104] The n-type substrate 201 corresponds to the drain electrode of the output transistor 10. Therefore, a power supply voltage VB (however, a ground voltage GND when the power supply is reverse-connected) can be applied to the n-type substrate 201.

[0105] The n-type epitaxial layer 202 is an n-type epitaxial growth layer formed by laminating on the surface of the n-type substrate 201. Note that the n-type epitaxial layer 202 is electrically conductive with the n-type substrate 201. Therefore, the same power supply voltage VB (ground voltage GND when the power supply is reverse-connected) as that of the n-type substrate 201 can be applied to the n-type epitaxial layer 202.

[0106] The n-type polysilicon region 203 and the p-type polysilicon region 204 each form a pn junction on the surface layer of the n-type epitaxial layer 202. Note that the n-type polysilicon region 203 is formed by ion-implanting n-type impurities into a polysilicon film and functions as the cathode of the polysilicon diode Dpoly. On the other hand, the p-type polysilicon region 204 is formed by ion-implanting p-type impurities into a polysilicon film and functions as the anode of the polysilicon diode Dpoly.

[0107] By the way, if a MOS diode Depi is formed inside the n-type epitaxial layer 202, first, a p-type well 205 is formed inside the n-type epitaxial layer 202, and then an n-type semiconductor region 206 and a p-type semiconductor region 207 are respectively formed inside the p-type well 205. According to such an element structure, the p-type well 205 and the p-type semiconductor region 207 function as the anode of the MOS diode Depi, and the n-type semiconductor region 206 functions as the cathode of the MOS diode Depi.

[0108] However, in the semiconductor device 1 having the MOS diode Depi, a parasitic transistor Qp (= npn bipolar transistor) is associated with the n-type semiconductor region 206 as the emitter, the p-type well 205 and the p-type semiconductor region 207 as the base, and the n-type substrate 201 and the n-type epitaxial layer 202 as the collector. Therefore, an unintended current can flow from the n-type substrate 201 through the parasitic transistor Qp.

[0109] On the other hand, since the above-mentioned polysilicon diode Dpoly is electrically separated from the n-type substrate 201 and the n-type epitaxial layer 202, it is not affected by parasitic elements. Therefore, the polysilicon diode Dpoly can be preferably used, for example, as the diode D1 (see FIGS. 5 and 7) forming the reverse protection circuit 110.

[0110] <Application to Vehicles> FIG. 10 is a diagram showing the appearance of a vehicle. The vehicle X of this configuration example is equipped with various electronic devices that operate by receiving power supply from a battery.

[0111] In addition to engine vehicles, the vehicle X also includes electric vehicles (xEVs) such as battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles / plug-in hybrid vehicles (PHEVs / PHVs), or fuel cell electric vehicles / fuel cell vehicles (FCEVs / FCVs).

[0112] Note that the semiconductor device 1 described above can be incorporated into any of the electronic devices mounted on the vehicle X.

[0113] <Supplementary Note> According to the present disclosure, it is possible to achieve both a protection function and an active clamp function during reverse power connection. Hereinafter, the present disclosure will be supplemented.

[0114] [Supplementary Note 1] A power supply terminal (T1), an output terminal (T2), and a ground terminal (T4), An internal output node (OUT_R) configured to be conductive with the output terminal (T2), An internal ground node (GND_INT) configured to be conductive with the ground terminal (T4), An output transistor (10) connected between the power supply terminal (T1) and the output terminal (T2), A gate driver (31) configured to drive the output transistor (10), A reverse connection protection circuit (110) configured to turn on the output transistor (31) without relying on the gate driver (31) when the ground terminal (T4) is at a higher potential than the power supply terminal (T1), A slew rate control circuit (130) configured to increase the off-state slew rate of the gate driver (31) when the internal output node (OUT_R) is at a lower potential than the internal ground node (GND_INT); A semiconductor device (1) comprising the same.

[0115] [Appendix 2] The reverse protection circuit (110) includes: A first resistor (R1) and a first transistor (M1a, M1b) connected in series between the control terminal of the output transistor (10) and the ground terminal (T4); A first diode (D1) having a cathode connected to the control terminal of the first transistor (M1a, M1b) and an anode connected to the internal ground node (GND_INT); A second resistor (R2) connected between the control terminal of the first transistor (M1a, M1b) and the ground terminal (T4); The semiconductor device (1) according to Appendix 1, including the same.

[0116] [Appendix 3] The first diode (D1) is a polysilicon diode (Dpoly) configured to be electrically separated from the substrate (201) of the semiconductor device (1). The semiconductor device (1) according to Appendix 2.

[0117] [Appendix 4] The slew rate control circuit (130) switches the magnitude of the gate current (Ig1) generated by the gate driver (31) during the off-transition period of the output transistor (10) according to whether the internal output node (OUT_R) is at a lower potential than the internal ground node (GND_INT). The semiconductor device (1) according to any one of Appendices 1 to 3.

[0118] [Appendix 5] The slew rate control circuit (130) includes: A third resistor (R3) connected between the internal ground node (GND_INT) and the internal output node (OUT_R); A current mirror (CM1 and CM2) configured to generate a slew rate control signal (SRctr) by mirroring a current signal (I1) flowing through the third resistor (R3) when the internal output node (OUT_R) is at a lower potential than the internal ground node (GND_INT); A fourth resistor (R4) connected between an output terminal of the slew rate control signal (SRctr) and the internal output node (OUT_R); A second diode (D2) having a cathode connected to the output terminal of the slew rate control signal (SRctr) and an anode connected to the internal output node (OUT_R); The semiconductor device (1) according to any one of Appendices 1 to 4, including the above.

[0119] [Appendix 6] The semiconductor device (1) according to any one of Appendices 1 to 5, further comprising a resistor (R0) connected between the output terminal (T2) and the internal output node (OUT_R).

[0120] [Appendix 7] The semiconductor device (1) according to any one of Appendices 1 to 6, further comprising an active clamp circuit (100) configured to limit the voltage (VB-Vo) across both ends of the output transistor (10) to be equal to or lower than a clamp voltage (Vclp).

[0121] [Appendix 8] The semiconductor device (1) according to any one of Appendices 1 to 7; A load (3) connected to the output terminal (T2) of the semiconductor device (1); An electronic device (A) comprising the above.

[0122] [Appendix 9] The electronic device (A) according to Appendix 8, wherein the load (3) is an inductive load.

[0123] [Appendix 10] A vehicle (X) comprising the electronic device (A) according to Appendix 8 or 9.

[0124] <Others> In addition, various technical features disclosed in this specification can be modified in various ways without departing from the gist of the technical creation in addition to the above embodiments. That is, the above embodiments should be considered as illustrative in all respects and not restrictive. Also, the technical scope of the present disclosure is defined by the scope of the claims, and it should be understood that all modifications belonging to the meaning and scope equivalent to the scope of the claims are included.

Description of Reference Numerals

[0125] 1 Semiconductor device (high-side switch IC) 2 DC power supply 3 Load 10 Output transistor (NMOSFET) 11 Controller 20 Sense transistor (NMOSFET) 30 Gate control unit 31 Gate driver 32 Oscillator 33 Charge pump 40 Control logic unit 50 Signal input unit 51, 52 Schmitt buffer 60 Internal power supply unit 70 Abnormal protection unit 71 Overcurrent protection circuit 72 Open protection circuit 73 Temperature protection circuit 74 Undervoltage protection circuit 80 Output current detection unit 90 Signal output unit 100 Active clamp circuit 101 Zener diode array 102 Diode array 103 Transistor (NMOSFET) 104, 105 Resistor 110 Reverse connection protection circuit 120 Backflow prevention circuit 130 Through rate control circuit 201 n-type substrate 202 n-type epi layer 203 n-type polysilicon region 204 p-type polysilicon region 205 p-type well 206 n-type semiconductor region 207 p-type semiconductor region A Electronic device CM1, CM2 Current mirror D1, D2 Diode Depi MOS diode Dpoly Polysilicon diode GND_INT Internal ground node L Inductance component M1a, M1b Transistor (depletion-type NMOSFET) M2, M3 Transistor (NMOSFET) M4, M5 Transistor (PMOSFET) OUT_R Internal output node Qp Parasitic transistor (npn) R Resistance component R0, R1, R2, R3, R4 Resistor T1~T6 External terminal X Vehicle

Claims

1. A power supply terminal, an output terminal, and a ground terminal, an internal output node configured to be electrically connected to the output terminal, an internal ground node configured to be electrically connected to the ground terminal, an output transistor connected between the power supply terminal and the output terminal, a gate driver configured to drive the output transistor, a reverse connection protection circuit configured to turn on the output transistor without relying on the gate driver when the ground terminal is at a higher potential than the power supply terminal, a slew rate control circuit configured to increase the off-transition slew rate of the gate driver when the internal output node is at a lower potential than the internal ground node, A semiconductor device comprising the above.

2. The reverse connection protection circuit includes a first resistor and a first transistor connected in series between a control terminal of the output transistor and the ground terminal, a first diode having a cathode connected to the control terminal of the first transistor and an anode connected to the internal ground node, a second resistor connected between the control terminal of the first transistor and the ground terminal, The semiconductor device according to claim 1.

3. The semiconductor device according to claim 2, wherein the first diode is a polysilicon diode configured to be electrically separated from a substrate of the semiconductor device.

4. The semiconductor device according to claim 1, wherein the slew rate control circuit switches the magnitude of a gate current generated by the gate driver during an off-transition period of the output transistor according to whether the internal output node is at a lower potential than the internal ground node.

5. The slew rate control circuit includes a third resistor connected between the internal ground node and the internal output node, a current mirror configured to mirror a current signal flowing through the third resistor when the internal output node is at a lower potential than the internal ground node to generate a slew rate control signal, a fourth resistor connected between an output terminal of the slew rate control signal and the internal output node, a second diode having a cathode connected to the output terminal of the slew rate control signal and an anode connected to the internal output node, The semiconductor device according to claim 1.

6. The semiconductor device according to claim 1, further comprising a resistor connected between the output terminal and the internal output node.

7. The semiconductor device according to claim 1, further comprising an active clamp circuit configured to limit the voltage across both ends of the output transistor to be equal to or lower than a clamp voltage.

8. A semiconductor device according to any one of claims 1 to 7, a load connected to the output terminal of the semiconductor device, and an electronic device comprising the same.

9. The electronic device according to claim 8, wherein the load is an inductive load.

10. A vehicle comprising the electronic device according to claim 8.

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