Chip component

Abstract

To provide a chip component capable of reducing poor connection.SOLUTION: A first conductive layer 32 of a chip component 10 is provided on a first insulating layer 31 covering a first electrode layer 23 and a contact portion 212. A second conductive layer 34 is provided on a second insulating layer 33 covering the first conductive layer 32. The first insulating layer 31 includes a plurality of first openings 311. First conductive connection parts 36 are embedded in the first openings 311 of the first insulating layer 31, separately from the first conductive layer 32. Second conductive connection parts 37 are embedded in second openings 312 of the first insulating layer 31, separately from the first conductive layer 32. The first conductive layer 32 includes: a first connection part 321 which is electrically connected to the first electrode layer 23 by the plurality of first conductive connection parts 36; and a second connection part 322 which is electrically connected to the contact portion 212 by the plurality of second conductive connection parts 37. The second conductive layer 34 is electrically connected to the second connection part 322.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to chip components.

Background Art

[0002] Patent Document 1 discloses a chip capacitor including a substrate, a first conductor film and a first pad film disposed on the substrate, a dielectric film disposed on the first conductor film and the first pad film, and a second conductor film disposed on the dielectric film. The first conductor film includes a first connection region and a first capacitor formation region. The second conductor film includes a second connection region electrically connected to the first pad film and a second capacitor formation region facing the first capacitor formation region of the first conductor film with the dielectric film interposed therebetween. A first external electrode is joined to the first connection region of the first conductor film, and a second external electrode is joined to the second connection region of the second conductor film.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] In chip components, connection failures may occur between internal components.

[0005] A chip component according to one aspect of the present disclosure includes a semiconductor substrate including a first substrate surface and a second substrate surface opposite to the first substrate surface, a trench recessed from the first substrate surface, a dielectric layer provided on an inner surface of the trench, an embedded portion provided in the trench and surrounded by the dielectric layer, and a protruding portion protruding upward from the first substrate surface, a first electrode layer; an electrode portion provided around the trench in the semiconductor substrate; a contact portion extending laterally from the electrode portion and provided on the first substrate surface, a second electrode layer; a first insulating layer covering both the first electrode layer and the contact portion and having a first opening exposing the first electrode layer and a second opening exposing the contact portion; a first conductive layer provided on the first insulating layer; a second insulating layer covering the first conductive layer; a second conductive layer provided on the second insulating layer; a first conductive connection portion provided separately from the first conductive layer and embedded in the first opening; and a second conductive connection portion provided separately from the first conductive layer and embedded in the second opening. A capacitor is formed by opposing the first electrode layer and the electrode portion of the second electrode layer with the dielectric layer therebetween. The first conductive layer includes a first connection portion electrically connected to the first electrode layer by the first conductive connection portion, and a second connection portion electrically insulated from the first connection portion and electrically connected to the contact portion by the second conductive connection portion. The second conductive layer is electrically connected to the second connection portion.

Brief Description of the Drawings

[0006]

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[0007] [Detailed Description] Hereinafter, some embodiments of the chip component of the present disclosure will be described with reference to the accompanying drawings. Note that, in order to make the description simple and clear, the components shown in the drawings are not necessarily drawn at a constant scale. Also, for ease of understanding, in the cross-sectional views, the hatching lines may be omitted. The accompanying drawings are merely illustrative of the embodiments of the present disclosure and should not be regarded as limiting the present disclosure. Terms such as "first", "second", "third", etc. in the present disclosure are merely used to distinguish objects and do not rank the objects.

[0008] The following detailed description includes apparatuses, systems, and methods that embody exemplary embodiments of the present disclosure. This detailed description is merely for explanatory purposes and is not intended to limit the embodiments of the present disclosure or the application and use of such embodiments.

[0009] As used herein, the expression "at least one" means "one or more" of the desired options. As an example, as used herein, the expression "at least one" means "only one option" or "both of the two options" if the number of options is two. As another example, as used herein, the expression "at least one" means "only one option" or "any combination of two or more options" if the number of options is three or more.

[0010] (First Embodiment) (Schematic Configuration of Chip Component) FIG. 1 is a schematic perspective view showing an example of the chip component 10 of the first embodiment. FIG. 2 is a schematic plan view showing an example of the chip component 10 of FIG. 1.

[0011] The chip component 10 is formed in a rectangular parallelepiped shape. In FIGS. 1 and 2, the length direction of the rectangular parallelepiped chip component 10 is the X direction, the width direction of the chip component 10 is the Y direction, and the thickness direction of the chip component 10 is the Z direction. The X direction and the Y direction are orthogonal to each other. The Z direction is orthogonal to the X direction and the Y direction. Viewing the target component from the Z direction is called a plan view. The chip component 10 has a length L1 in the X direction, a width W1 in the Y direction, and a thickness T1 in the Z direction. The length L1 may be, for example, 0.4 mm or more and 2 mm or less. The width W1 may be, for example, 0.2 mm or more and 2 mm or less. The thickness T1 may be, for example, 0.05 mm or more and 0.5 mm or less. The thickness T1 may or may not include the first external electrode 51 and the second external electrode 52.

[0012] The chip component 10 may be a small electronic component called, for example, a 1608 (1.6 mm × 0.8 mm) chip, a 1005 (1.0 mm × 0.5 mm) chip, a 0603 (0.6 mm × 0.3 mm) chip, a 0402 (0.4 mm × 0.2 mm) chip, a 03015 (0.3 mm × 0.15 mm) chip, etc. using the size designation (length L1 (mm) × width W1 (mm)).

[0013] The chip component 10 includes a semiconductor substrate 11, a wiring portion 30, a first external electrode 51, and a second external electrode 52. The semiconductor substrate 11 constitutes the base of the chip component 10. The chip component 10 includes a wiring portion 30 supported by the semiconductor substrate 11. The wiring portion 30 includes a plurality of insulating layers and a plurality of conductive layers laminated on the semiconductor substrate 11.

[0014] The semiconductor substrate 11 is formed in a rectangular parallelepiped shape. The semiconductor substrate 11 includes a first substrate surface 111, a second substrate surface 112, and a substrate side surface 113. The first substrate surface 111 and the second substrate surface 112 face opposite sides in the Z direction. The second substrate surface 112 is the surface opposite to the first substrate surface 111. The substrate side surface 113 connects the first substrate surface 111 and the second substrate surface 112. The substrate side surface 113 includes a plurality of substrate side surfaces 114, 115, 116, 117. The substrate side surfaces 114 to 117 face either the X direction or the Y direction. The first substrate side surface 114 and the second substrate side surface 115 face opposite sides in the X direction. The third substrate side surface 116 and the fourth substrate side surface 117 face opposite sides in the Y direction. The first to fourth substrate side surfaces 114 to 117 may also be referred to as the first to fourth end faces.

[0015] As shown in FIGS. 1 and 2, in one example, the semiconductor substrate 11 may have a round shape with chamfered corners in plan view. The semiconductor substrate 11 may not have a round shape. When the corners are chamfered, the substrate side surface 113 may not be clearly partitioned into the first to fourth substrate side surfaces 114 to 117.

[0016] The chip component 10 includes a resin insulating layer 41 disposed on the wiring portion 30. The first external electrode 51 and the second external electrode 52 are disposed on the resin insulating layer 41. The first external electrode 51 and the second external electrode 52 are arranged to be separated from each other in the X direction. In one example, the first external electrode 51 and the second external electrode 52 are formed in a rectangular shape in a plan view, in which the length in the Y direction orthogonal to the length in the X direction in which they are separated from each other is long. It can be said that the first external electrode 51 is formed in a rectangular shape in a plan view, in which the direction along the first substrate side surface 114 is the longitudinal direction. It can be said that the second external electrode 52 is formed in a rectangular shape in a plan view, in which the direction along the second substrate side surface 115 is the longitudinal direction.

[0017] The first external electrode 51 and the second external electrode 52 constitute both terminals of the chip component 10. The chip component 10 may be referred to as a horizontal chip component. The horizontal chip component 10 can be used, for example, by flip-chip mounting on a mounting substrate. Also, the first external electrode 51 and the second external electrode 52 may be referred to as a first terminal electrode and a second terminal electrode, respectively, or a first external terminal and a second external terminal.

[0018] The first external electrode 51 is an area on the first substrate surface 111 of the semiconductor substrate 11, and is formed in an area spaced inward from the three substrate side surfaces 114, 116, and 117. Thereby, it can be said that the first external electrode 51 is surrounded by the resin insulating layer 41 on the first substrate surface 111 of the semiconductor substrate 11 in a plan view. The first external electrode 51 is away from the periphery of the first substrate surface 111 of the semiconductor substrate 11. The first external electrode 51 is away from the periphery of the first substrate surface 111 by a distance L51. The distance L51 may be 5 μm or more and 50 μm or less. It can be said that the first external electrode 51 is away from the first to fourth substrate side surfaces 114 to 117 that form the periphery of the first substrate surface 111. The distance L51 includes distances L511, L512, and L513 from the substrate side surfaces 114, 116, and 117. The distances L511, L512, and L513 may be the same, or at least one of them may be different.

[0019] The second external electrode 52 is formed in a region on the first substrate surface 111 of the semiconductor substrate 11 and spaced inwardly from the three substrate side surfaces 115, 116, and 117. Thus, it can be said that the second external electrode 52 is surrounded by the resin insulating layer 41 on the first substrate surface 111 of the semiconductor substrate 11 in plan view. The second external electrode 52 is away from the periphery of the first substrate surface 111 of the semiconductor substrate 11. The second external electrode 52 is separated from the periphery of the first substrate surface 111 by a distance L52. The distance L52 may be 5 μm or more and 50 μm or less. It can be said that the second external electrode 52 is away from the first to fourth substrate side surfaces 114 to 117 that form the periphery of the first substrate surface 111. The distance L52 includes distances L521, L522, and L523 from the substrate side surfaces 115, 116, and 117. The distances L521, L522, and L523 may be the same or at least one of them may be different.

[0020] (Overview of the internal structure of the chip component) FIG. 3 is a schematic cross-sectional view schematically showing the internal structure of the chip component 10 of FIG. 2. Note that FIG. 3 shows the cross-sectional structure of the main part of the chip component 10 for easy understanding of the structure of the chip component 10, and does not show the cross-sectional structure at a specific cut surface of the chip component 10. The dimensions of each component shown in FIG. 3 and the dimensional ratios between the components do not match the dimensions of each component shown in FIGS. 1 and 2 and the dimensional ratios between the components.

[0021] The semiconductor substrate 11 may be made of a material containing Si (silicon). In one example, the semiconductor substrate 11 may be a silicon substrate. The semiconductor substrate 11 may or may not contain impurities. The impurities may be impurities of the first conductivity type. In one example, it may be a silicon substrate containing impurities of the first conductivity type. The first conductivity type may be, for example, p-type. The thickness of the semiconductor substrate 11 may be, for example, 50 μm or more and 500 μm or less. The specific resistance of the semiconductor substrate 11 may be 5 mΩ·cm or more and 100 mΩ·cm or less by introducing p-type impurities.

[0022] The semiconductor substrate 11 includes a trench 12 that is recessed from the first substrate surface 111. The trench 12 is formed by removing a part of the semiconductor substrate 11 from the first substrate surface 111. The inner surface 121 of the trench 12 includes a pair of opposing side surfaces 122 and a bottom surface 123 that connects the pair of side surfaces 122. The bottom surface 123 may be curved so as to protrude toward the second substrate surface 112.

[0023] A plurality of trenches 12 are arranged. The width W12 of the trench 12 may be, for example, 0.5 μm or more and 5 μm or less. In one example, the width W12 of the trench 12 may be 0.8 μm. The depth T12 of the trench 12 may be, for example, 1 μm or more and 100 μm or less. In one example, the depth T12 of the trench 12 may be 15 μm.

[0024] The chip component 10 includes a capacitor 20. The capacitor 20 is selectively formed on the first substrate surface 111 of the semiconductor substrate 11. The capacitor 20 is composed of a second electrode layer 21 formed on the semiconductor substrate 11, a dielectric layer 22 and a first electrode layer 23 formed on the semiconductor substrate 11. The capacitor 20 is a functional device included in the chip component 10. The first electrode layer 23, the dielectric layer 22, and the second electrode layer 21 that constitute the capacitor 20 can be referred to as a device region 25 included in the chip component 10. The device region 25 can be said to include the capacitor 20.

[0025] The second electrode layer 21 is formed on the semiconductor substrate 11. The second electrode layer 21 may be an impurity region formed by introducing impurities into the semiconductor substrate 11. The impurity may be, for example, a second conductivity type different from the first conductivity type that is the conductivity type of the semiconductor substrate 11. The second conductivity type may be, for example, an n-type. The second electrode layer 21 may be formed as an N+ diffusion layer containing impurities of the second conductivity type with respect to the semiconductor substrate 11 of the first conductivity type. The thickness of the second electrode layer 21 may be, for example, 0.2 μm or more and 10 μm or less.

[0026] The second electrode layer 21 includes an electrode portion 211 provided around the trench 12 and a contact portion 212 extending laterally from the electrode portion 211 and provided on the first substrate surface 111. The electrode portion 211 is formed from the inner surface 121 of the trench 12 into the semiconductor substrate 11. Two adjacent trenches 12 may be formed such that the second electrode layer 21 therebetween is common. Also, two adjacent trenches 12 may be formed such that their respective second electrode layers 21 are separated from each other. The contact portion 212 may be a region into which impurities are introduced from the first substrate surface 111 of the semiconductor substrate 11 toward the second substrate surface 112.

[0027] The dielectric layer 22 is provided in the trench 12. The dielectric layer 22 covers the inner surface 121 of the trench 12. Also, the dielectric layer 22 is provided on the first substrate surface 111 of the semiconductor substrate 11. The dielectric layer 22 covers the first substrate surface 111 of the semiconductor substrate 11. It can be said that the dielectric layer 22 covers the surface of the second electrode layer 21. The chip component 10 can be said to include the dielectric layer 22 that covers the surface of the second electrode layer 21 formed on the semiconductor substrate 11.

[0028] The dielectric layer 22 has insulating properties. In one example, the dielectric layer 22 may be a SiN film. The dielectric layer 22 may be an oxide film such as SiO2. The dielectric layer 22 may be a SiO2 / SiN laminated film or a SiO2 / SiN / SiO2 laminated film. The dielectric layer 22 may be an ON film or an ONO film, or a laminated film thereof. The dielectric layer 22 may be an insulating film made of a high-k material. The thickness of the dielectric layer 22 may be, for example, 100 Å or more and 10000 Å or less (10 nm or more and 1000 nm or less).

[0029] The first electrode layer 23 is formed on the dielectric layer 22. The first electrode layer 23 includes an embedded portion 231 provided in the trench 12 and surrounded by the dielectric layer 22 and a protruding portion 232 protruding upward from the first substrate surface 111. The embedded portion 231 is filled in the dielectric layer 22 that covers the inner surface 121 of the trench 12.

[0030] The protruding portion 232 may include a recessed portion 234 that is recessed toward the trench 12 above the trench 12. The protruding portion 232 may include a flat upper surface above the trench 12. The protruding portion 232 may include the recessed portion 234 above the trench 12 and the flat upper surface 235 above the trench 12.

[0031] The first electrode layer 23 includes a contact opening 233 at a position overlapping the contact portion 212 of the second electrode layer 21 in the Z direction. It can be said that the protruding portion 232 includes the contact opening 233. The contact opening 233 of the first electrode layer 23 exposes the dielectric layer 22 above the contact portion 212 of the second electrode layer 21.

[0032] In one example, the first electrode layer 23 is made of polysilicon. When the first electrode layer 23 is made of polysilicon, it may contain impurities. The impurities may be, for example, impurities of the second conductivity type. The first electrode layer 23 may be made of one or more metal materials such as Cu (copper). The thickness of the first electrode layer 23 may be indicated, for example, by the thickness of the protruding portion 232. The thickness of the first electrode layer 23 may be, for example, 4000 Å or more and 30000 Å or less (400 nm or more and 3000 nm or less).

[0033] (Wiring portion) The chip component 10 includes a wiring portion 30 disposed on the first substrate surface 111 of the semiconductor substrate 11. The wiring portion 30 includes a first insulating layer 31, a first conductive layer 32, a second insulating layer 33, a second conductive layer 34, and a surface insulating film 35.

[0034] The first insulating layer 31 is formed on the first substrate surface 111. The first insulating layer 31 covers the first electrode layer 23. The first insulating layer 31 is in contact with the dielectric layer 22 within the contact opening 233 of the first electrode layer 23. It can be said that the first insulating layer 31 covers the first electrode layer 23 and the dielectric layer 22.

[0035] The first insulating layer 31 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film. As an example of the silicon oxide film, the first insulating layer 31 may include at least one of a NSG (Non-doped Silicate Glass) film, a PSG (Phosphor Silicate Glass) film, and a BPSG (Boron Phosphor Silicate Glass) film. In one example, the first insulating layer 31 includes a NSG film and a BPSG film. The thickness of the first insulating layer 31 may be, for example, 0.3 μm or more and 2 μm or less. In one example, the thickness of the first insulating layer 31 can be 0.7 μm.

[0036] The first insulating layer 31 includes a first opening 311 and a second opening 312. The first opening 311 is disposed between adjacent trenches 12. It can be said that the first opening 311 is disposed so as to avoid the upper part of the trench 12. It can be said that the first opening 311 is disposed at a position where no recess 234 is formed with respect to the protruding portion 232 of the first electrode layer 23. The first opening 311 penetrates the first insulating layer 31 and exposes a part of the first electrode layer 23.

[0037] The second opening 312 is disposed on the contact portion 212 of the second electrode layer 21. In a plan view, the second opening 312 is disposed within the contact opening 233 of the first electrode layer 23. The second opening 312 penetrates the first insulating layer 31 and the dielectric layer 22. The second opening 312 exposes a part of the contact portion 212 of the second electrode layer 21.

[0038] The chip component 10 includes a first conductive connection portion 36 and a second conductive connection portion 37. The first conductive connection portion 36 is disposed within the first opening 311. It can also be said that the first conductive connection portion 36 is embedded in the first opening 311. The first conductive connection portion 36 is composed of a material containing W (tungsten). The first conductive connection portion 36 can also be referred to as a W plug. The second conductive connection portion 37 is disposed within the second opening 312. It can also be said that the second conductive connection portion 37 is embedded in the second opening 312. The second conductive connection portion 37 is composed of a material containing W. The first conductive connection portion 36 can also be referred to as a W plug.

[0039] The first conductive layer 32 is provided on the first insulating layer 31. The first conductive layer 32 includes a first connection portion 321 and a second connection portion 322. The first connection portion 321 and the second connection portion 322 are arranged separately from each other. The first connection portion 321 is electrically connected to the first conductive connection portion 36. It can be said that the first conductive connection portion 36 is provided separately from the first conductive layer 32. The first conductive connection portion 36 electrically connects the first connection portion 321 of the first conductive layer 32 and the first electrode layer 23. The second connection portion 322 is electrically connected to the second conductive connection portion 37. It can be said that the second conductive connection portion 37 is provided separately from the first conductive layer 32. The second conductive connection portion 37 electrically connects the second connection portion 322 of the first conductive layer 32 and the second electrode layer 21. It can be said that the first conductive layer 32 includes the first connection portion 321 electrically connected to the first conductive connection portion 36 and the second connection portion 322 electrically connected to the second conductive connection portion 37. The first connection portion 321 and the second connection portion 322 are electrically insulated from each other. The first conductive layer 32 is composed of a material containing Al (aluminum). In one example, the first conductive layer 32 is composed of AlCu. The first conductive layer 32 may be composed of AlSi, AlSiCu, etc.

[0040] The second insulating layer 33 covers the first conductive layer 32. The second insulating layer 33 enters between the first connection portion 321 and the second connection portion 322 of the first conductive layer 32. Accordingly, in the first conductive layer 32, the first connection portion 321 and the second connection portion 322 are insulated from each other by the second insulating layer 33.

[0041] The second insulating layer 33 includes a first opening 331 and a second opening 332. The first opening 331 is disposed above the first connection portion 321 of the first conductive layer 32. The first opening 331 penetrates the second insulating layer 33. The first opening 331 exposes a part of the first connection portion 321 of the first conductive layer 32. It can be said that the second insulating layer 33 includes the first opening 331 that exposes a part of the first connection portion 321 of the first conductive layer 32.

[0042] The second opening 332 is disposed above the second connection portion 322 of the first conductive layer 32. The second opening 332 penetrates the second insulating layer 33. The second opening 332 exposes a part of the second connection portion 322 of the first conductive layer 32. It can be said that the second insulating layer 33 includes the second opening 332 that exposes a part of the second connection portion 322 of the first conductive layer 32.

[0043] The second insulating layer 33 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film. As an example of the silicon oxide film, the second insulating layer 33 may include at least one of an NSG film, a PSG film, and a BPSG film. In one example, the second insulating layer 33 includes an NSG film.

[0044] The second conductive layer 34 is provided on the second insulating layer 33. The second conductive layer 34 includes a first connection portion 341 and a second connection portion 342. The first connection portion 341 of the second conductive layer 34 is electrically connected to the first connection portion 341 of the first conductive layer 32 through the first opening 331 of the second insulating layer 33. The second connection portion 342 of the second conductive layer 34 is electrically connected to the second connection portion 322 of the first conductive layer 32 through the second opening 332 of the second insulating layer 33. It can be said that the second conductive layer 34 includes a first connection portion 341 electrically connected to the first connection portion 321 of the first conductive layer 32 and a second connection portion 342 electrically connected to the second connection portion 322 of the first conductive layer 32. The first connection portion 341 and the second connection portion 342 are electrically insulated from each other. The second conductive layer 34 is composed of a material containing Al (aluminum). In one example, the second conductive layer 34 is composed of AlCu. The second conductive layer 34 may be composed of AlSi, AlSiCu, etc.

[0045] The surface insulating film 35 covers the second conductive layer 34. The surface insulating film 35 is composed of a material containing Si. In one example, the surface insulating film 35 is composed of a SiN film. The surface insulating film 35 may be an oxide film such as a SiO2 film. The dielectric layer 22 may be a SiO2 / SiN laminated film or a SiO2 / SiN / SiO2 laminated film. The dielectric layer 22 may be an oxynitride film such as a SiON film. The surface insulating film 35 may be referred to as a passivation film.

[0046] The surface insulating film 35 includes a first pad opening 351 and a second pad opening 352. The first pad opening 351 and the second pad opening 352 penetrate the surface insulating film 35. The first pad opening 351 is disposed above the first connection portion 341 of the second conductive layer 34. The first pad opening 351 exposes a part of the first connection portion 341 of the second conductive layer 34. The second pad opening 352 is disposed above the second connection portion 342 of the second conductive layer 34. The second pad opening 352 exposes a part of the second connection portion 342 of the second conductive layer 34.

[0047] The chip component 10 may include a barrier layer 38. The barrier layer 38 includes a portion disposed between the first conductive layer 32 and the first insulating layer 31. The barrier layer 38 includes a portion formed on the inner surface of the first opening 311 of the first insulating layer 31 and a portion formed on the inner surface of the second opening 312 of the first insulating layer 31. It can be said that the wiring portion 30 includes the barrier layer 38.

[0048] A first conductive connection portion 36 is embedded in the first opening 311 of the first insulating layer 31. It can also be said that the first conductive connection portion 36 is surrounded by the barrier layer 38. A second conductive connection portion 37 is embedded in the second opening 312 of the first insulating layer 31. It can also be said that the second conductive connection portion 37 is surrounded by the barrier layer 38. The barrier layer 38 may be composed of a material containing Ti (titanium). In one example, the barrier layer 38 includes a TiN film.

[0049] The resin insulating layer 41 covers the surface insulating film 35. The resin insulating layer 41 is formed of, for example, polyimide. The resin insulating layer 41 includes a first opening 411 and a second opening 412. In one example, the resin insulating layer 41 includes a plurality of first openings 411 and a plurality of second openings 412. The plurality of first openings 411 are formed on the first connection portion 341 of the second conductive layer 34. In one example, the plurality of first openings 411 are arranged in the X direction. The plurality of first openings 411 expose the first connection portion 341 of the second conductive layer 34.

[0050] The plurality of second openings 412 are formed on the second connection portion 342 of the second conductive layer 34. In one example, the plurality of second openings 412 are arranged in the X direction. The plurality of second openings 412 expose the second connection portion 342 of the second conductive layer 34.

[0051] The first external electrode 51 is in contact with the first connection portion 341 of the second conductive layer 34 through a plurality of first openings 411 in the resin insulating layer 41. The first external electrode 51 is electrically connected to the first connection portion 341 of the second conductive layer 34. The second external electrode 52 is in contact with the second connection portion 342 of the second conductive layer 34 through a plurality of second openings 412 in the resin insulating layer 41. The second external electrode 52 is electrically connected to the second connection portion 342 of the second conductive layer 34.

[0052] (An example of the internal structure of the chip component) Figs. 4 to 9 are explanatory diagrams showing an example of the internal structure of the chip component 10 in Fig. 2. In Fig. 3, the configuration elements of the capacitor 20 and the wiring portion 30 of the chip component 10 were mainly shown in the thickness direction (Z direction) of the chip component 10. Figs. 4 to 9 show the planar structure of the configuration elements of the capacitor 20 and the wiring portion 30 of the chip component 10.

[0053] Fig. 4 is a schematic plan view showing an example of the trench 12 and the first electrode layer 23 in Fig. 3. Fig. 5 is a schematic plan view showing an enlarged part of Fig. 4. Fig. 6 is a schematic plan view showing an enlarged part of Fig. 4. Fig. 7 is a schematic plan view showing an example of the trench 12 and the contacts 361 to 363 in Fig. 5. Figs. 5 and 6 show the positional relationship between the trench 12 and the first conductive connection portion 36 and the second conductive connection portion 37 in a plan view. Also, in Figs. 4 to 7, the contact opening 233 of the first electrode layer 23 is indicated by a dashed-dotted line. Fig. 8 is a schematic plan view showing an example of the connection between the second electrode layer 21 and the first conductive layer 32 in Fig. 3. Fig. 9 is a schematic plan view showing an example of the connection between the first conductive layer 32 and the second conductive layer 34 in Fig. 3. In Figs. 4, 8, and 9, the second conductive layer 34 is indicated by a dashed-dotted line.

[0054] (Trench, first conductive connection portion, second conductive connection portion, first electrode layer) As shown in FIG. 4, a plurality of trenches 12 are formed on the first substrate surface 111 of the semiconductor substrate 11. The chip component 10 includes a capacitor 20 composed of a second electrode layer 21 around the trench 12, a dielectric layer 22 and a first electrode layer 23 in the trench 12. The capacitor 20 is a functional device of the chip component 10. The capacitor 20 is included in the device region 25. Therefore, the region where the trench 12 is formed is also a capacitor region including the capacitor 20. The capacitor region 25 may be described using the same reference numeral as the device region 25.

[0055] The capacitor region 25 is disposed closer to the second substrate side surface 115 of the semiconductor substrate 11. The capacitor region 25 is disposed so as to overlap the region between the first external electrode 51 and the second external electrode 52 and the second external electrode 52. The capacitor region 25 is disposed so as to overlap the second connection portion 342 of the second conductive layer 34. Further, the capacitor region 25 is a part of the first connection portion 341 of the second conductive layer 34 and is disposed so as to overlap the portion closer to the second connection portion 342.

[0056] In plan view, the capacitor region 25 has a rectangular shape in which the length in the X direction is longer than the length in the Y direction. The capacitor region 25 includes a first side 251 and a second side 252 which are both ends in the X direction, and a third side 253 and a fourth side 254 which are both ends in the Y direction. The first side 251 is a side closer to the first substrate side surface 114. The second side 252 is a side closer to the second substrate side surface 115. The third side 253 is a side closer to the third substrate side surface 116. The fourth side 254 is a side closer to the fourth substrate side surface 117.

[0057] As shown in FIG. 4, the distance L11 between the second side 252 of the capacitor region 25 disposed near the second substrate side surface 115 and the second substrate side surface 115 is 5 μm or more and 50 μm or less. Also, the distance L12 between the third side 253 of the capacitor region 25 and the third substrate side surface 116 is 5 μm or more and 50 μm or less. The distance L13 between the fourth side 254 of the capacitor region 25 and the fourth substrate side surface 117 is 5 μm or more and 50 μm or less. The distances L11, L12, and L13 can be said to be the distances from the periphery of the first substrate surface 111 to the device region 25.

[0058] The trench 12 is formed by selectively removing the semiconductor substrate 11 from the first substrate surface 111 of the semiconductor substrate 11. The semiconductor substrate 11 can be said to include a main body portion surrounding the capacitor region 25 including the trench 12 in plan view. Also, the semiconductor substrate 11 can be said to include a wall portion forming the trench 12 in the capacitor region 25.

[0059] As shown in FIGS. 4 to 7, the plurality of trenches 12 in the capacitor region 25 include a plurality of continuous trenches 61 and a plurality of divided trenches 64. The plurality of continuous trenches 61 extend in the Y direction in plan view. It can be said that the plurality of continuous trenches 61 extend from the third side 253 to the fourth side 254. The plurality of continuous trenches 61 are arranged at intervals from each other in the X direction in plan view.

[0060] The continuous trench 61 includes a first continuous trench 62 and a second continuous trench 63. The first continuous trench 62 and the second continuous trench 63 have different shapes from each other in plan view. The plurality of first continuous trenches 62 and the plurality of second continuous trenches 63 are arranged alternately in the X direction.

[0061] As shown in FIGS. 5 to 7, the first continuous trench 62 includes a plurality of straight portions 621 extending in the X direction orthogonal to the Y direction in which the first continuous trench 62 extends, and a plurality of connecting portions 622 connecting the straight portions 621 adjacent in the Y direction. The plurality of straight portions 621 are arranged at intervals in the Y direction in which the first continuous trench 62 extends. The plurality of connecting portions 622 are arranged so as to connect the plurality of straight portions 621 in series.

[0062] The second continuous trench 63 includes a plurality of first inclined portions 631 inclined with respect to the Y direction in which the second continuous trench 63 extends, and a plurality of second inclined portions 632 inclined in a direction opposite to the first inclined portion 631 with respect to the Y direction. The plurality of first inclined portions 631 and the plurality of second inclined portions 632 are alternately arranged in the Y direction. The plurality of first inclined portions 631 and the plurality of second inclined portions 632 are connected to each other.

[0063] The plurality of divided trenches 64 are arranged between the first continuous trench 62 and the second continuous trench 63 adjacent in the X direction. The plurality of divided trenches 64 include a first divided trench 65 and a second divided trench 66. The first divided trench 65 and the second divided trench 66 have different shapes from each other in plan view.

[0064] The first divided trench 65 includes at least one straight portion 651 extending in the X direction. The plurality of divided trenches 64 may include the first divided trench 65 including one straight portion 651 and the first divided trench 65 including two straight portions 651. The first divided trench 65 including two straight portions 651 includes a connecting portion 652 connecting the two straight portions 651. In one example, the first divided trench 65 including one straight portion 651 is arranged along the third side 253 and the fourth side 254. It can be said that the first divided trench 65 including one straight portion 651 is arranged along the third substrate side surface 116 and the fourth substrate side surface 117 of the semiconductor substrate 11. The first divided trench 65 including two straight portions 651 is arranged between the first divided trenches 65 including one straight portion 651 in the Y direction.

[0065] The second dividing trench 66 includes at least one of a first inclined portion 661 and a second inclined portion 662. The plurality of dividing trenches 64 may include a second dividing trench 66 including either the first inclined portion 661 or the second inclined portion 662, and a second dividing trench 66 including both the first inclined portion 661 and the second inclined portion 662. In one example, the second dividing trench 66 including only the first inclined portion 661 is arranged along the third side 253. It can be said that the second dividing trench 66 including only the first inclined portion 661 is arranged along the third substrate side surface 116 of the semiconductor substrate 11. The second dividing trench 66 including only the second inclined portion 662 is arranged along the fourth side 254. It can be said that the second dividing trench 66 including only the second inclined portion 662 is arranged along the fourth substrate side surface 117 of the semiconductor substrate 11. The second dividing trench 66 including both the first inclined portion 661 and the second inclined portion 662 is arranged between the second dividing trenches 66 including the first inclined portion 661 or the second inclined portion 662.

[0066] As shown in FIG. 3, the semiconductor substrate 11 includes a second electrode layer 21 formed on the first substrate surface 111. In FIGS. 4 to 6, it can be said that the portions other than the trench 12 show the second electrode layer 21 formed on the first substrate surface 111. As shown in FIGS. 3 and 6, the second electrode layer 21 includes an electrode portion 211 provided around the trench 12, and a contact portion 212 that extends laterally from the electrode portion 211 and is provided on the first substrate surface 111. In FIG. 6, the second electrode layer 21 is shown by a dashed line. As shown in FIG. 6, the contact portion 212 is formed in the region surrounded by the continuous trench 61 and the dividing trench 64. The electrode portion 211 of the second electrode layer 21 is formed so as to surround the contact portion 212 in plan view.

[0067] As shown in FIG. 3, the second electrode layer 21 includes a plurality of contact portions 212. The plurality of contact portions 212 are arranged in the X direction in which the plurality of trenches 12 are arranged and the Y direction in which the plurality of trenches 12 extend in plan view. It can be said that the plurality of contact portions 212 are arranged in a matrix in plan view.

[0068] As shown in FIGS. 5 to 7, a second conductive connection portion 37 is disposed at the contact portion 212. As shown in FIG. 3, the second conductive layer 34 includes a plurality of contact portions 212, and the plurality of contact portions 212 are arranged in a matrix in a plan view. Therefore, it can be said that the second conductive connection portions 37 are arranged in a matrix in a plan view. The dividing trench 64 can be said to be divided for each of the contact portions 212 arranged in the Y direction in a plan view.

[0069] As shown in FIGS. 5 and 6, in one example, three second conductive connection portions 37 are disposed for one contact portion 212. The three second conductive connection portions 37 are arranged along the Y direction in one example. The three second conductive connection portions 37 have a rectangular shape in which the length in the X direction is longer than the length in the Y direction in a plan view in one example. The number of the second conductive connection portions 37 for one contact portion 212 can be any number of one, two, or four or more. The shape of the second conductive connection portion 37 in a plan view can be any shape such as a square shape, a circular shape, an elliptical shape, or the like. In a plan view, the plurality of second conductive connection portions 37 may be arranged in the X direction and formed to extend in the Y direction. The plurality of second conductive connection portions 37 may be arranged in a matrix.

[0070] As shown in FIGS. 5 to 7, in a plan view, a first conductive connection portion 36 is disposed between the trenches 12. The first conductive connection portion 36 is formed to extend along the trench 12 in a plan view. The trench 12 includes a plurality of continuous trenches 61 and a plurality of dividing trenches 64.

[0071] The first conductive connection portion 36 may include a first contact 361, a second contact 362, and a third contact 363. The first contact 361 and the second contact 362 are disposed between the trenches 12 in the X direction.

[0072] The first contact 361 is disposed between the first continuous trench 62 and the second continuous trench 63 adjacent in the X direction. The first contact 361 extends in the Y direction along the first continuous trench 62 and the second continuous trench 63. The first contact 361 extends from the third side 253 to the fourth side 254 of the capacitor region 25 shown in FIG. 3 along the second continuous trench 63. As shown in FIG. 7, the width W21 of the first contact 361 may be, for example, 0.4 μm.

[0073] As shown in FIGS. 5 to 7, the second contact 362 is disposed between the divided trench 64 and the continuous trench 61, and between the first divided trench 65 and the second divided trench 66 of the divided trench 64. The second contact 362 has a curved shape along the connecting portion 622 in one example. As shown in FIG. 7, the width W22 of the second contact 362 may be, for example, 0.4 μm.

[0074] As shown in FIGS. 5 to 7, the third contact 363 may be provided corresponding to the first continuous trench 62. The third contact 363 is disposed between a plurality of straight portions 621 of the first continuous trench 62. The third contact 363 and the straight portions 621 of the first continuous trench 62 are alternately arranged in the Y direction. The third contact 363 has a rectangular shape extending along the straight portion 621. As shown in FIG. 7, the width W23 of the third contact 363 may be, for example, 0.4 μm. The distance L21 between the third contact 363 and the straight portion 621 of the first continuous trench 62 may be, for example, 0.4 μm.

[0075] As shown in FIGS. 4 to 6, the first electrode layer 23 includes a contact opening 233 at a position overlapping the contact portion 212 in plan view. The contact opening 233 is formed in a rectangular shape long in the X direction in one example. In FIGS. 4 to 6, the contact opening 233 is indicated by a dashed line. The first insulating layer 31 enters the contact opening 233. The second conductive connection portion 37 is embedded in a second opening 312 penetrating the first insulating layer 31 in the Z direction.

[0076] As shown in FIG. 4, the contact portions 212 of the second electrode layer 21 are arranged in a matrix in plan view. The contact openings 233 of the first electrode layer 23 are arranged in a matrix corresponding to the respective contact portions 212. The contact openings 233 are arranged spaced apart in the X direction and the Y direction in plan view.

[0077] The width W31 of the second conductive connection portion 37 may be, for example, 0.4 μm. The interval L31 between the second conductive connection portions 37 adjacent in the Y direction may be equal to or greater than the width W31 of the second conductive connection portion 37. The interval L31 between the second conductive connection portions 37 may be, for example, 0.4 μm.

[0078] (First conductive layer) As shown in FIG. 9, the first conductive layer 32 includes a first connection portion 321 and a second connection portion 322.

[0079] The first connection portion 321 is formed so as to overlap the second conductive layer 34. In one example, the first conductive layer 32 has a rectangular shape in plan view with a longer length in the X direction than the length in the Y direction. The first conductive layer 32 includes a plurality of openings 323 disposed in a portion overlapping the capacitor region 25. The plurality of openings 323 are arranged so as to overlap the contact openings 233 of the first electrode layer 23. It can be said that the first conductive layer 32 includes a plurality of openings 323 arranged in a matrix. It can be said that the first conductive layer 32 is formed in a lattice shape by a plurality of openings 323 arranged in a matrix. The openings 323 of the first conductive layer 32 are arranged so as to surround the contact openings 233 of the first electrode layer 23 in plan view.

[0080] The second connection portion 322 is disposed within a plurality of openings 323 of the first conductive layer 32. The plurality of second connection portions 322 are spaced apart from the first connection portion 321 within the plurality of openings 323. The second connection portion 322 is disposed so as to cover the contact opening 233 of the first electrode layer 23 in plan view. The second connection portion 322 is formed larger than the contact opening 233 of the first electrode layer 23 in plan view. The contact opening 233 of the first electrode layer 23 is disposed above the contact portion 212 of the second electrode layer 21. Therefore, it can be said that the second connection portion 322 is formed across the contact portion 212 of the second electrode layer 21 and the first electrode layer 23.

[0081] (Connection between the first conductive layer and the second conductive layer) FIG. 9 shows the first opening 331 and the second opening 332 of the second insulating layer 33. In FIG. 9, the first opening 331 and the second opening 332 are hatched. The second insulating layer 33 covers the first conductive layer 32. In FIG. 9, the first insulating layer 31 is shown by a solid line.

[0082] The second insulating layer 33 includes a plurality of first openings 331 and a plurality of second openings 332. The plurality of first openings 331 are disposed in a range where the first connection portion 321 of the first conductive layer 32 and the first connection portion 341 of the second conductive layer 34 overlap. In one example, the plurality of first openings 331 are arranged in a matrix along the X direction and the Y direction. The arrangement of the plurality of first openings 331 may be changed as appropriate. The plurality of first openings 331 have a rectangular shape in which the length in the X direction is longer than the length in the Y direction in plan view in one example. The shape of the plurality of first openings 331 may be appropriately changed to any shape such as a square shape or a circular shape. The first connection portion 341 of the second conductive layer 34 is electrically connected to the first conductive layer 32 through the plurality of first openings 331.

[0083] The plurality of second openings 332 are arranged in a range where the second connection portion 322 of the first conductive layer 32 and the second connection portion 342 of the second conductive layer 34 overlap. The second openings 332 are provided for each of the second connection portions 322 of the first conductive layer 32. In one example, the plurality of second openings 332 have a rectangular shape in which the length in the X direction is longer than the length in the Y direction in plan view. The shape of the plurality of second openings 332 may be appropriately changed to any shape such as a square shape or a circular shape. The second connection portion 342 of the second conductive layer 34 is electrically connected to the plurality of second connection portions 322 of the first conductive layer 32 through the plurality of second openings 332.

[0084] (Resin insulating layer, external electrodes) FIG. 10 is a schematic plan view showing an example of the second conductive layer 34, the resin insulating layer 41, and the external electrodes 51 and 52 in FIG. 3. FIG. 11 is a schematic cross-sectional view showing an enlarged view of the external electrodes 51 and 52 in FIG. 3.

[0085] As shown in FIGS. 10 and 11, the resin insulating layer 41 covers the second conductive layer 34. The resin insulating layer 41 is disposed at a position overlapping the first external electrode 51. As shown in FIG. 10, the resin insulating layer 41 includes a plurality of first openings 411 at a position overlapping the first external electrode 51. The plurality of first openings 411 are arranged in the X direction. The plurality of first openings 411 extend in the Y direction.

[0086] As shown in FIG. 11, the resin insulating layer 41 includes an upper surface 413 and a plurality of first side surfaces 414 that form the plurality of first openings 411. In one example, the resin insulating layer 41 may include a curved surface between the upper surface 413 and the first side surfaces 414.

[0087] The resin insulating layer 41 includes a first protrusion 42 sandwiched by first openings 411 in the X direction. The upper surface 421 of the first protrusion 42 is curved so as to bulge upward. The first protrusion 42 has a first width W42 in the X direction. The first width W42 of the first protrusion 42 is the distance between adjacent first openings 411 in the X direction. The first opening 411 has a first opening width W41 in the X direction. In one example, the first opening width W41 of the first opening 411 is larger than the first width W42 of the first protrusion 42. In one example, the first width W42 of the first protrusion 42 is about 12 μm, and the first opening width W41 of the first opening 411 is about 13 μm. The first opening width W41 of the first opening 411 may be equal to the first width W42 of the first protrusion 42. The first opening width W41 of the first opening 411 may be smaller than the first width W42 of the first protrusion 42.

[0088] The first protrusion 42 has a first height T42 in the Z direction. In one example, the first height T42 of the first protrusion 42 is equal to the height T41 of the portion of the resin insulating layer 41 other than the first protrusion 42. In this specification, "equal" includes the case where the difference between two measured values is within a predetermined ratio of one of the measured values, for example, within 5%, when the two measured values are the same value. The portion other than the first protrusion 42 may be, for example, a portion overlapping with the first external electrode 51, or a portion between the first external electrode 51 and the second external electrode 52. The first height T42 of the first protrusion 42 may be smaller than the height T41 of the portion of the resin insulating layer 41 other than the first protrusion 42.

[0089] The resin insulating layer 41 includes an upper surface 413 and a plurality of second side surfaces 415 forming a plurality of second openings 412. In one example, the resin insulating layer 41 may include a curved surface between the upper surface 413 and the second side surfaces 415.

[0090] The resin insulating layer 41 includes a second protrusion 43 sandwiched by the second openings 412 in the X direction. The upper surface 431 of the second protrusion 43 is curved so as to bulge upward. The second protrusion 43 has a second width W44 in the X direction. The second width W44 of the second protrusion 43 is the distance between the second openings 412 adjacent to each other in the X direction. The second opening 412 has a second opening width W43 in the X direction. In one example, the second opening width W43 of the second opening 412 is larger than the second width W44 of the second protrusion 43. In one example, the second width W44 of the second protrusion 43 is about 12 μm, and the second opening width W43 of the second opening 412 is about 13 μm. The second opening width W43 of the second opening 412 may be equal to the second width W44 of the second protrusion 43. The second opening width W43 of the second opening 412 may be smaller than the second width W44 of the second protrusion 43.

[0091] The second protrusion 43 has a second height T43 in the Z direction. In one example, the second height T43 of the second protrusion 43 is equal to the height T41 of the portion of the resin insulating layer 41 other than the second protrusion 43. The portion other than the second protrusion 43 may be, for example, a portion overlapping with the second external electrode 52, or a portion between the second external electrode 52 and the first external electrode 51. The second height T43 of the second protrusion 43 may be smaller than the height T41 of the portion of the resin insulating layer 41 other than the second protrusion 43.

[0092] The first external electrode 51 includes a first electrode surface 53 and a second electrode surface 54. The first electrode surface 53 faces the side of the second conductive layer 34. The second electrode surface 54 faces the side opposite to the first electrode surface 53. The first electrode surface 53 includes a resin contact portion 531 in contact with the resin insulating layer 41 and a conductive contact portion 532 in contact with the second conductive layer 34. The resin contact portion 531 is in contact with the upper surface 413 of the resin insulating layer 41. The conductive contact portion 532 is in contact with the upper surface 343 of the second conductive layer 34. Therefore, it can be said that the conductive contact portions 532 in contact with the upper surface 413 of the resin insulating layer 41 and the upper surface 343 of the second conductive layer 34 are arranged at different positions from each other in the Z direction. The first electrode surface 53 forms a back surface step 533.

[0093] The second electrode surface 54 includes a first surface region 541 positioned above the resin contact portion 531 and a second surface region 542 positioned above the conductive contact portion 532. The conductive contact portion 532 is in contact with the second conductive layer 34 through a plurality of first openings 411 in the resin insulating layer 41. It can be said that the second surface region 542 is positioned above the plurality of first openings 411. In one example, the first surface region 541 is formed as a flat surface. The second surface region 542 may include, in one example, a recess 543 that is recessed toward the second conductive layer 34. In one example, the recess 543 is formed to be recessed toward the center of the first opening 411 in the X direction from the resin insulating layer 41. The surface step 544 between the first surface region 541 and the second surface region 542 may be indicated by the difference between the portion of the first surface region 541 that is farthest from the second conductive layer 34 and the portion of the second surface region 542 that is closest to the second conductive layer 34. The surface step 544 of the second electrode surface 54 formed by the first surface region 541 and the second surface region 542 is smaller than the back surface step 533 of the first electrode surface 53 formed by the resin contact portion 531 and the conductive contact portion 532.

[0094] The second external electrode 52 includes the first electrode surface 53 and the second electrode surface 54. The first electrode surface 53 faces the side of the second conductive layer 34. The second electrode surface 54 faces the side opposite to the first electrode surface 53. The first electrode surface 53 includes a resin contact portion 531 in contact with the resin insulating layer 41 and a conductive contact portion 532 in contact with the second conductive layer 34. The resin contact portion 531 is in contact with the upper surface 413 of the resin insulating layer 41. The conductive contact portion 532 is in contact with the upper surface 343 of the second conductive layer 34. Therefore, it can be said that the conductive contact portion 532 in contact with the upper surface 413 of the resin insulating layer 41 and the upper surface 343 of the second conductive layer 34 are arranged at different positions in the Z direction. The first electrode surface 53 forms a back surface step 533.

[0095] The second electrode surface 54 includes a first surface region 541 located above the resin contact portion 531 and a second surface region 542 located above the conductive contact portion 532. The conductive contact portion 532 is in contact with the second conductive layer 34 through a plurality of second openings 412 in the resin insulating layer 41. It can be said that the second surface region 542 is located above the plurality of second openings 412. In one example, the first surface region 541 is formed as a flat surface. The second surface region 542 may include, for example, a recess 543 that is recessed toward the second conductive layer 34. In one example, the recess 543 is formed to be recessed from the resin insulating layer 41 toward the center of the second opening 412 in the X direction. The surface step 544 between the first surface region 541 and the second surface region 542 may be indicated by the difference between the portion of the first surface region 541 that is farthest from the second conductive layer 34 and the portion of the second surface region 542 that is closest to the second conductive layer 34. The surface step 544 of the second electrode surface 54 formed by the first surface region 541 and the second surface region 542 is smaller than the back surface step 533 of the first electrode surface 53 formed by the resin contact portion 531 and the conductive contact portion 532.

[0096] The first external electrode 51 and the second external electrode 52 may include, for example, a first metal layer 561, a second metal layer 562, and a solder layer 563 arranged in order from the side of the second conductive layer 34. The first metal layer 561 may be composed of a material containing Cu. In one example, the first metal layer 561 is a Cu layer. The second metal layer 562 may be composed of a material containing Ni. In one example, the second metal layer 562 is a Ni layer. The solder layer 563 may be composed of a material containing Sn (tin). In one example, the solder layer 563 is a SnAg layer containing Sn and Ag (silver). The solder layer 563 may be a SnSb layer containing Sn and Sb (antimony).

[0097] The first external electrode 51 and the second external electrode 52 may include a seed layer 564. The first metal layer 561, the second metal layer 562, and the solder layer 563 may be plating layers formed by plating growth by a plating method. The seed layer 564 may be composed of a material containing Cu. The seed layer 564 may be composed of a material containing Cu and Ti. The seed layer 564 may include a first layer composed of a material containing Ti and a second layer composed of a material containing Cu. The first layer containing Ti may be called an under barrier metal.

[0098] The thickness T5 of the first metal layer 561 and the second metal layer 562 may be a value obtained by summing the thickness of the first metal layer 561 and the thickness of the second metal layer 562. The thickness T5 of the first metal layer 561 and the second metal layer 562 may include the thickness of the seed layer 564. The first opening width W41 of the first opening 411 and the second opening width W43 of the second opening 412 are larger than the thickness T5 of the first metal layer 561 and the second metal layer 562. The first opening width W41 of the first opening 411 and the second opening width W43 of the second opening 412 may also be smaller than the thickness T5 of the first metal layer 561 and the second metal layer 562.

[0099] The first metal layer 561 and the second metal layer 562 are formed, for example, by a plating method. The first metal layer 561 is formed by plating growth from the surface of the seed layer 564. The second metal layer 562 is formed by plating growth from the surface of the first metal layer 561. In the first metal layer 561 and the second metal layer 562 formed in this way, due to the first opening width W41 of the first opening 411 and the second opening width W43 of the second opening 412, the depth of the recess on the surface of the second metal layer 562 is smaller than the depth of the recess on the surface of the first metal layer 561.

[0100] Furthermore, the depth of the recess 543 in the second electrode surface 54, which is the surface of the solder layer 563, becomes smaller than the depth of the recess on the surface of the second metal layer 562 by forming the solder layer 563 by electroplating growth from the surface of the second metal layer 562. Therefore, the surface step 544 of the second electrode surface 54 can be made smaller than the back surface step 533 of the first electrode surface 53 of the solder layer 563. For this reason, the surface of the solder layer 563, which is the second electrode surface 54, can be made closer to a flat surface.

[0101] (Unit cell) As shown in FIG. 8, the constituent members of the chip component 10 may be divided into a plurality of unit cells 26. In FIG. 8, the range of one unit cell 26 is shown as a rectangular frame of a dashed line.

[0102] In one example, the unit cell 26 is set as a rectangular region centered on the second connection portion 322. The unit cell 26 may be set as a rectangular region connecting the centers of the second connection portions 322. In one example, the unit cell 26 has a rectangular shape in which the length in the X direction is longer than the length in the Y direction in a plan view.

[0103] The unit cell 26 may include a capacitor 201 formed around the second connection portion 322. The capacitor 201 included in each unit cell 26 can also be called a unit capacitor. The capacitor 201 of each unit cell 26 is conceptually distinguished from the capacitor 201 of an adjacent unit cell 26, but physically and electrically, the capacitors 201 of adjacent unit cells 26 are continuous with each other. The capacitors 201 included in each of the plurality of unit cells 26 constitute the capacitor 20 of the chip component 10.

[0104] The unit cell 26 may include the first connection portion 321 and the second connection portion 322 of the first conductive layer 32, the first conductive connection portion 36, and the second conductive connection portion 37. The unit cell 26 may include the first insulating layer 31 and the second insulating layer 33.

[0105] The unit cell 26 has a first length L61 in the X direction and a second length L62 in the Y direction. The first length L61 may be 5 μm or more and 50 μm or less. The second length L62 may be 5 μm or more and 50 μm or less. In one example, the first length L61 may be 21 μm and the second length L62 may be 12 μm.

[0106] (Example of capacitor and wiring part) FIG. 12 is a schematic cross-sectional view showing the structure of the capacitor region. FIG. 12 shows an example of the cross-sectional shape of the capacitor 20 and the wiring part 30 formed by the manufacturing method of the chip component 10 described later. FIG. 13 is a schematic cross-sectional view showing an enlarged part of FIG. 12. FIG. 14 is an explanatory view showing the states of the capacitor 20 and the resistance components R10 and R11 in the chip component 10. FIG. 15 is an equivalent circuit diagram of the chip component 10. FIGS. 12 to 14 schematically show the structure of the chip component 10 cut along the contact portion 212 arranged in the X direction orthogonal to the Z direction as an example of the structure of the capacitor region 25.

[0107] As shown in FIGS. 12 and 13, the second connection part 322 is formed across the contact part 212 of the second electrode layer 21 and the first insulating layer 31. The first electrode layer 23 has a contact opening 233 that exposes the dielectric layer 22 at a position overlapping the contact part 212 of the second electrode layer 21. The first insulating layer 31 enters into the contact opening 233. Therefore, it can be said that the first insulating layer 31 includes a covering part 313 that covers the contact part 212 of the second electrode layer 21. The upper surface of the covering part 313 is located closer to the first substrate surface 111 of the semiconductor substrate 11 than the upper surface of the part covering the first electrode layer 23.

[0108] The second connection part 322 formed on the first insulating layer 31 is formed across the contact part 212 of the second electrode layer 21 and the first insulating layer 31. Therefore, the upper surface of the second connection part 322 is recessed toward the contact part 212 of the second electrode layer 21. It can be said that the part of the second connection part 322 corresponding to the contact opening 233 of the first electrode layer 23 is recessed toward the semiconductor substrate 11.

[0109] The second insulating layer 33 covers the first conductive layer 32 and includes a second opening 332 that exposes a part of the upper surface of the second connection portion 322. The second insulating layer 33 covers the entire first connection portion 321 of the first conductive layer 32 and also covers the end portion of the second conductive layer 34.

[0110] As shown in FIG. 9, the second connection portion 342 of the second conductive layer 34 is formed to cover the first conductive layer 32 in the capacitor region 25. As shown in FIGS. 12 and 13, the second connection portion 342 of the second conductive layer 34 is electrically connected to the second connection portion 322 of the first conductive layer 32 through the second opening 332 of the second insulating layer 33 that exposes a part of the second connection portion 322 of the first conductive layer 32. Therefore, the second connection portion 342 of the second conductive layer 34 is formed to cover, from above the second insulating layer 33, the second connection portion 322 exposed by the second opening 332 of the second insulating layer 33. For this reason, it can be said that the second connection portion 342 of the second conductive layer 34 includes a first covering portion 344 that covers the second insulating layer 33 and a second covering portion 345 that covers the second connection portion 322 of the first conductive layer 32. Further, it can be said that the second connection portion 342 of the second conductive layer 34 is formed in the Z direction along the second opening 332 of the second insulating layer 33 and includes a wall portion 346 that electrically connects the first covering portion 344 and the second covering portion 345.

[0111] FIG. 14 shows the capacitors 20 formed by each trench 12 and the resistance components between the capacitors 20, the first external electrode 51, and the second external electrode 52. The chip component 10 includes a capacitor configured such that the first electrode layer 23 and the electrode portion 211 of the second electrode layer 21 face each other with the dielectric layer 22 interposed therebetween. In FIG. 14, four capacitors 20 configured such that the embedded portions 231 of the first electrode layer 23 disposed in each trench 12 face the electrode portion 211 of the second electrode layer 21 with the dielectric layer 22 interposed therebetween are shown.

[0112] The capacitor 20 is connected to the first external electrode 51 through the first electrode layer 23, the first conductive connection portion 36, and the first connection portion 321 of the first conductive layer 32. The capacitors 20 at both ends of the trench 12 are connected to the second external electrode 52 through the second electrode layer 21, the second conductive connection portion 37, the second connection portion 322 of the first conductive layer 32, and the second conductive layer 34. In this first embodiment, the electrode portion 211 of the second electrode layer 21 provided around between adjacent trenches 12 is continuously formed between adjacent trenches 12. Therefore, the capacitors 20 of each trench 12 are connected to each other through the electrode portion 211 of the second electrode layer 21.

[0113] FIG. 15 shows an equivalent circuit diagram of the unit capacitor 20 formed by the first electrode layer 23, the second electrode layer 21, and the dielectric layer 22 arranged for four trenches 12. The unit capacitor 20 includes four capacitors 20 connected in parallel. This unit capacitor 20 is a capacitor component formed by the trench 12 arranged between two contact portions 212 arranged in the X direction shown in FIG. 8. The chip component 10 includes contact portions 212 arranged in the X direction and the Y direction. Therefore, it can be said that the chip component 10 includes a plurality of unit capacitors 20 connected in parallel between the first external electrode 51 and the second external electrode 52.

[0114] (Details of the chip side surface) FIG. 16 is a schematic perspective view showing an enlarged part of the side surface of the chip component 10. FIG. 17 is a partial schematic cross-sectional view of the chip component 10.

[0115] The semiconductor substrate 11 includes a plurality of unevennesses 13 on the substrate side surface 113. The plurality of unevennesses 13 are arranged from the first substrate surface 111 to the second substrate surface 112 of the semiconductor substrate 11. The plurality of unevennesses 13 all extend along the side of the substrate side surface 113 of the semiconductor substrate 11. It can be said that the plurality of unevennesses 13 extend in a streak shape along the side of the substrate side surface 113. On the first substrate side surface 114 and the second substrate side surface 115 facing opposite sides in the X direction, the plurality of unevennesses 13 extend in a streak shape in the Y direction. On the third substrate side surface 116 and the fourth substrate side surface 117 facing opposite sides in the Y direction, the plurality of unevennesses 13 extend in a streak shape in the X direction.

[0116] As shown in FIG. 17, the plurality of unevennesses 13 may have the same size from the first substrate surface 111 to the second substrate surface 112 of the semiconductor substrate 11. The size of the unevenness 13 may be represented by the width W7 in the thickness direction (Z direction) of the semiconductor substrate 11 in one recess constituting the unevenness 13. The size of the unevenness 13 may be represented by the depth D7 in a direction orthogonal to the thickness direction of the semiconductor substrate 11 in one recess constituting the unevenness 13. The width W7 of the unevenness 13 may be 0.1 μm or more and 5 μm or less. The depth D7 of the unevenness 13 may be 0.1 μm or more and 5 μm or less.

[0117] (Operation of the First Embodiment) (Comparative Example) Here, some comparative examples of the chip component 10 of the first embodiment and the operation of the first embodiment with respect to the comparative examples will be described. In the description of the comparative examples, the same names and reference numerals are used for the constituent members similar to those of the chip component 10 of the first embodiment.

[0118] (First Comparative Example) Figs. 20 to 22 show the chip component 91 of the first comparative example. The chip component 91 of the first comparative example includes a first conductive layer 901 and a second conductive layer 902. The first conductive layer 901 and the second conductive layer 902 are arranged to be spaced apart from each other in a direction orthogonal to the Z direction. The same first conductive layer 901 includes a first base portion 9011 and a plurality of first extending portions 9012 extending from the first base portion 9011 in the X direction. The second conductive layer 902 includes a second base portion 9021 and a plurality of second extending portions 9022 extending from the second base portion 9021 in the X direction. The first base portion 9011 and the second base portion 9021 are arranged to be spaced apart at both ends in the X direction, and the first external electrode 51 and the second external electrode 52 are respectively connected thereto. The plurality of first extending portions 9012 and the plurality of second extending portions 9022 extend in opposite directions to each other and are alternately arranged in the Y direction. The first extending portion 9012 is formed wider than the second extending portion 9022.

[0119] As shown in Fig. 21, the plurality of trenches 12 are arranged at positions overlapping the first extending portions 9012. In each trench 12, a second electrode layer 911, a dielectric layer 912, and a first electrode layer 913 are formed. The second electrode layer 911, the dielectric layer 912, and the first conductive layer 901 extend on the semiconductor substrate 11. The first conductive layer 901 is formed to be in contact with the first conductive layer 901. The first conductive layer 901 is formed to be in contact with the second electrode layer 911 extending on the semiconductor substrate 11.

[0120] The capacitor 20 formed by each trench 12 is connected to the first external electrode 51 through the first electrode layer 913 and the first conductive layer 901. Therefore, mainly the resistance component R913 of the first electrode layer 913 embedded in the trench 12 is interposed between each capacitor 20 and the first external electrode 51. On the other hand, the capacitor 20 formed in each trench 12 is connected to the second external electrode 52 through the second electrode layer 911 in the trench 12, the portion of the second electrode layer 911 extending on the semiconductor substrate 11, and the second conductive layer 902.

[0121] In FIG. 21, between the capacitor 20 formed in the trench 12 at the right end and the second external electrode 52, there are interposed the second electrode layer 911 in the trench 12 at the right end, the portion of the second electrode layer 911 on the semiconductor substrate 11, and the second conductive layer 902. Between the capacitor 20 formed in the second trench 12 from the right and the second external electrode 52, there are interposed the second electrode layer 911 in the second trench 12, the second electrode layer 911 in the trench 12 at the right end, the portion of the second electrode layer 911 on the semiconductor substrate 11, and the second conductive layer 902. That is, for the capacitor 20 formed in each trench 12, depending on the position of the trench 12, the number of the second electrode layers 911 in the trench 12 interposed between the capacitor 20 and the second external electrode 52 is different.

[0122] Therefore, as shown in FIG. 22, the chip component 91 of the first comparative example includes a plurality of capacitors 20 connected in parallel between the first external electrode 51 and the second external electrode 52. And the number of the resistance components R911 connected in series between each capacitor 20 and the second external electrode 52 increases as the trench 12 in which the capacitor 20 is formed is farther from the second conductive layer 902. For this reason, the chip component 91 of the first comparative example has a high equivalent series resistance (ESR) between the first external electrode 51 and the second external electrode 52, and it is difficult to reduce the equivalent series resistance.

[0123] The chip component 10 of the first embodiment includes a semiconductor substrate 11, a trench 12, a dielectric layer 22, a first electrode layer 23, a second electrode layer 21, a first conductive layer 32, and a second conductive layer 34. The semiconductor substrate 11 includes a first substrate surface 111 and a second substrate surface 112. The trench 12 is recessed from the first substrate surface 111. The dielectric layer 22 is provided on the inner surface 121 of the trench 12. The first electrode layer 23 includes an embedded portion 231 provided in the trench 12 and surrounded by the dielectric layer 22, and a protruding portion 232 protruding upward from the first substrate surface 111. The second electrode layer 21 includes an electrode portion 211 provided around the trench 12, and a contact portion 212 extending laterally from the electrode portion 211 and provided on the first substrate surface 111. A capacitor 20 is formed by the first electrode layer 23 and the second electrode layer 21 facing each other with the dielectric layer 22 interposed therebetween.

[0124] The first conductive layer 32 is provided on a first insulating layer 31 that covers both the first electrode layer 23 and the contact portion 212. The second conductive layer 34 is provided on a second insulating layer 33 that covers the first conductive layer 32. The first insulating layer 31 includes a first opening 311 that exposes the first electrode layer 23 and a second opening 312 that exposes the contact portion 212. The first insulating layer 31 includes a plurality of first openings 311. A first conductive connection portion 36 is embedded in the first opening 311 separately from the first conductive layer 32, and a second conductive connection portion 37 is embedded in the second opening 312 separately from the first conductive layer 32. The first conductive layer 32 includes a first connection portion 321 electrically connected to the first electrode layer 23 by a plurality of first conductive connection portions 36, and a second connection portion 322 electrically connected to the contact portion 212 by a plurality of second conductive connection portions 37. The second conductive layer 34 is electrically connected to the second connection portion 322. Therefore, the electrode portion 211 of the second electrode layer 21 is electrically connected to the second conductive layer 34 through the contact portion 212 of the second electrode layer 21, the second conductive connection portion 37, and the second connection portion 322.

[0125] In the chip component 10 of the first embodiment, a first connection portion 321 of a first conductive layer 32 electrically connected to a first electrode layer 23 constituting a capacitor 20 and a second conductive layer 34 electrically connected to an electrode portion 211 of a second electrode layer 21 constituting the capacitor 20 are disposed on a trench 12. Therefore, regardless of the position of the trench 12, the number of resistance components R10 connected in series to the capacitor 20 can be reduced. For this reason, the chip component 10 of the first embodiment can achieve low resistance. Further, in the chip component 10 of the first embodiment, an equivalent series resistance (ESR) can be reduced.

[0126] In the chip component 10 of the first embodiment, the first conductive layer 32 includes a first connection portion 321 electrically connected to the first electrode layer 23 and a second connection portion 322 electrically connected to a contact portion 212 of the second electrode layer 21. The first conductive layer 32 is formed on a first insulating layer 31 that covers the first electrode layer 23. The first connection portion 321 of the first conductive layer 32 is formed so as to cover a capacitor region 25 and includes a plurality of openings 323 disposed in a portion overlapping with the capacitor region 25. The second connection portion 322 of the first conductive layer 32 is disposed in each of the plurality of openings 323. Therefore, both the first connection portion 321 and the second connection portion 322 of the first conductive layer 32 can be physically disposed within a common capacitor region 25 while being electrically separated from each other. For this reason, the upper portion of the capacitor region 25 can be effectively utilized, and an increase in the size of the chip component 10 can be suppressed.

[0127] (Second Comparative Example) FIG. 23 shows a chip component 92 of the second comparative example. The chip component 92 of the second comparative example has a different connection of a first conductive layer 32X to the first electrode layer 23 and the second electrode layer 21 as compared with the chip component 10 of the first embodiment. In the chip component 92 of the second comparative example, the first conductive layer 32X is directly connected to the first electrode layer 23 and the second electrode layer 21.

[0128] The chip component 92 of the second comparative example includes a first insulating layer 31X having a first opening 311X that exposes the protruding portion 232 of the first electrode layer 23. The first connection portion 321 of the first conductive layer 32X enters into the first opening 311X of the first insulating layer 31X and is electrically connected to the protruding portion 232 of the first electrode layer 23.

[0129] Also, the first insulating layer 31X includes a second opening 312X that exposes the contact portion 212 of the second electrode layer 21. The second connection portion 322X of the first conductive layer 32X enters into the second opening 312X of the first insulating layer 31X and is electrically connected to the contact portion 212.

[0130] The protruding portion 232 of the first electrode layer 23 includes a concave portion 234 that is concave upward and toward the trench 12 above the trench 12. After the first insulating layer 31X is formed to cover the first electrode layer 23, the portion above the trench 12 of the first electrode layer 23 is removed to connect the first electrode layer 23. In the removal of this first insulating layer 31X, a thin film may remain due to the concave portion 234 on the upper surface of the first electrode layer 23. The thin film on the first electrode layer 23 may peel off during the manufacturing process and reattach to different locations of the product, forming a structure not assumed in the design, which may cause problems in electrical characteristics and durability. Also, the peeled thin film may adhere to the manufacturing equipment, causing process contamination.

[0131] The second connection portion 322X of the first conductive layer 32X is electrically connected to the contact portion 212 of the second electrode layer 21 formed on the semiconductor substrate 11. When the first conductive layer 32X is made of a material containing Al, an alloy spike may occur at the connection portion, possibly impairing the ohmic contact between the second connection portion 322X of the first conductive layer 32X and the contact portion 212 of the second electrode layer 21.

[0132] The second connection portion 322X of the first conductive layer 32X is formed across the first insulating layer 31X that covers the first electrode layer 23 formed on the first substrate surface 111 from the first substrate surface 111 of the semiconductor substrate 11 where the contact portion 212 is formed. Therefore, there is a large height difference between the central portion connected to the contact portion 212 and the peripheral portion on the first insulating layer 31X of the second connection portion 322X, and the upper surface inclination from the peripheral portion to the central portion is large. For this reason, there is a large height difference between the portion connecting the second conductive layer 34X in the second connection portion 322X and the upper surface of the second insulating layer 33 on which the second conductive layer 34X is formed. For this reason, the step coverage in the second conductive layer 34X decreases, and there is a possibility that the second conductive layer 34X and the second connection portion 322X of the first conductive layer 32X are not sufficiently connected.

[0133] As shown in FIGS. 3 and 12, in the chip component 10 of the first embodiment, the first insulating layer 31 includes a first opening 311 that exposes a part of the protruding portion 232 of the first electrode layer 23. In plan view, the first opening 311 is provided at a position different from the trench 12. Therefore, it is difficult for a thin film to remain on the portion of the first electrode layer 23 exposed by the first opening 311. For this reason, it is possible to suppress the formation of a structure that peels off during the manufacturing process and reattaches to different locations of the product and is not assumed in the design, and it is possible to suppress defects in electrical characteristics and durability. Further, it is possible to suppress process contamination by the peeled thin film adhering to the manufacturing apparatus.

[0134] In the chip component 10 of the first embodiment, the first insulating layer 31 includes a second opening 312 that exposes a part of the contact portion 212 of the second electrode layer 21. The second opening 312 penetrates the dielectric layer 22. A second conductive connection portion 37 provided separately from the first conductive layer 32 is embedded in the second opening 312. Therefore, the step and inclination on the upper surface of the second connection portion 322 are smaller than those of the chip component 92 of the second comparative example. For this reason, the step coverage of the second conductive layer 34 with respect to the second connection portion 322 can be increased, and the connection between the second conductive layer 34 and the second connection portion 322 of the first conductive layer 32 can be surely made. Further, a barrier layer 38 is provided between the first conductive layer 32 and the first insulating layer 31 and on the inner surface of the second opening 312 of the first insulating layer 31. In one example, the barrier layer 38 is made of a material containing Ti. Therefore, the contact between the first conductive layer 32 made of a material containing Al and the semiconductor substrate 11 can be suppressed, and the generation of alloy spikes can be suppressed.

[0135] (Third Comparative Example) Figs. 24 to 26 show the chip component 93 of the third comparative example. The chip component 93 of the third comparative example has different shapes of the first external electrode 51 and the second external electrode 52 from those of the chip component 10 of the first embodiment. In the chip component 93 of the third comparative example shown in Figs. 24 to 26, the portions related to the first external electrode 51 and the second external electrode 52 are illustrated, and only the capacitor region 25 of the capacitor portion is shown for simplification.

[0136] As shown in FIGS. 24 and 25, the resin insulating layer 41X of the chip component 93 of the third comparative example includes one first opening 411X that exposes a part of the first connection portion 341 of the second conductive layer 34, and one second opening 412X that exposes a part of the second connection portion 342 of the second conductive layer 34X. The first external electrode 51X is formed across the first connection portion 341 exposed by the first opening 411X and the resin insulating layer 41X around the first opening 411X. Therefore, the first external electrode 51X includes a recess 54X having a shape corresponding to the thickness of the resin insulating layer 41X and the size of the first opening 411X in the central portion. Similarly, the second external electrode 52X is formed across the second connection portion 342 exposed by the second opening 412X and the resin insulating layer 41X around the second opening 412X. Therefore, the second external electrode 52X includes a recess 54X having a shape corresponding to the thickness of the resin insulating layer 41X and the size of the second opening 412X in the central portion.

[0137] FIG. 26 shows a case where the chip component 93 of the third comparative example is mounted. The chip component 93 of the third comparative example is flip-chip mounted on the circuit board 81. That is, the chip component 93 of the third comparative example is arranged with the first external electrode 51X and the second external electrode 52X facing the connection pads 811 of the circuit board 81. Then, for example, by a reflow process, the solder layers 563 of the first external electrode 51X and the second external electrode 52X are joined to the connection pads 811. At this time, voids may occur in the solder layer 563 due to the recesses 54X of the first external electrode 51X and the second external electrode 52X. The voids generated in this way can be a factor in reducing the mounting strength of the chip component 93 with respect to the circuit board 81. That is, the chip component 93 of the third comparative example may have reduced mountability.

[0138] As shown in FIGS. 3 and 11, in the chip component 10 of the first embodiment, the first external electrode 51 and the second external electrode 52 include a first electrode surface 53 facing the side of the second conductive layer 34 and a second electrode surface 54 facing the side opposite to the first electrode surface 53. The back surface step 533 of the first electrode surface 53 corresponds to the height T41 of the resin insulating layer 41. The surface step 544 of the second electrode surface 54 is smaller than the back surface step 533 of the first electrode surface 53. The second electrode surface 54 is the surface of the solder layer 563. Therefore, when the chip component 10 of the first embodiment is mounted on the circuit board 81 shown in FIG. 26, the gap between the connection pad 811 of the circuit board 81 and the solder layer 563 is smaller than the recess of the chip component 93 of the third comparative example. For this reason, voids are less likely to occur in the solder layer 563. As a result, the mounting strength of the chip component 10 of the first embodiment can be improved. Therefore, the mountability of the chip component 10 of the first embodiment can be improved.

[0139] (Operation of the First Embodiment by Components Not Compared with the Comparative Example) The unevenness 13 on the substrate side surface 113 of the semiconductor substrate 11 is formed by, for example, plasma etching. Plasma etching can also be referred to as plasma dicing. In plasma etching, isotropic etching and anisotropic etching are alternately repeated approximately. For this reason, the unevenness 13 is formed on the substrate side surface 113. The size of the unevenness 13 may be set by, for example, the time of isotropic etching.

[0140] FIGS. 18 and 19 are schematic plan views showing a part of the wafers 100 and 100X on which the constituent members of the plurality of chip components 10 are formed. FIG. 18 shows the arrangement of the chip components 10 when separating each chip component 10 by plasma etching. FIG. 19 shows the arrangement of the chip components 10 when separating each chip component 10 by a cutting blade. In FIG. 19, the frame of the alternate long and short dash line indicates the size of the chip component 10 shown in FIG. 18.

[0141] As shown in FIG. 19, when using a cutting blade, a boundary region 15X with a width corresponding to the thickness of the cutting blade and the runout of the cutting blade is required. Also, when using a cutting blade, since the cutting blade cuts into the boundary region 15X of the wafer 100X, chipping or the like may occur in the chip component 10. For this reason, the constituent members of the chip component 10 are formed within a range where chipping or the like does not occur, or the boundary region 15X is set so that chipping or the like does not occur in the constituent members. For this reason, the size of the chip component 10 may increase, or the region for forming the constituent members of the chip component 10 may decrease, resulting in a decrease in the capacitance value of the chip component 10.

[0142] As shown in FIG. 18, when forming the chip component 10 by plasma etching, it is not necessary to consider the runout or chipping of the cutting blade. For this reason, the width of the boundary region 15 may be set by the amount of the groove formed by plasma etching. Also, in plasma etching, chipping or the like is less likely to occur in the chip component 10. For this reason, the boundary region 15 can be brought closer to the constituent members of the chip component 10, so that the chip component 10 can be miniaturized. Also, since the constituent members of the chip component 10 can be formed up to near the boundary region 15, the capacitance value of the chip component 10 can be increased.

[0143] (Method for manufacturing a chip component) Next, an example of the method for manufacturing the chip component 10 according to the first embodiment shown in FIGS. 1 to 5 will be described.

[0144] FIGS. 27 to 38 are schematic cross-sectional views showing exemplary manufacturing steps of the chip component 10. FIGS. 27 to 38 correspond to the cross-sectional structure of the chip component 10 shown in FIG. 3. For ease of understanding, in FIGS. 27 to 38, members that are the same as the final constituent elements of the chip component 10 are labeled with the same reference numerals as in FIG. 3.

[0145] As shown in FIG. 27, the method for manufacturing the chip component 10 includes preparing a semiconductor substrate 11. The semiconductor substrate 11 may be, for example, a silicon wafer containing impurities of a first conductivity type. In FIG. 27, the range for forming one chip component 10 is indicated by a dashed line. The outside of the dashed line is the boundary region 15.

[0146] As shown in FIG. 28, the method for manufacturing the chip component 10 includes forming a trench 12. The trench 12 is formed by selectively removing the semiconductor substrate 11, for example, by dry etching.

[0147] As shown in FIG. 29, the method for manufacturing the chip component 10 includes forming a second electrode layer 21. The second electrode layer 21 is formed by implanting impurities of a second conductivity type into the semiconductor substrate 11 from the first substrate surface 111 and the inner surface 121 of the trench 12 and performing a heat treatment.

[0148] As shown in FIG. 30, the method for manufacturing the chip component 10 includes forming a dielectric layer 22. The dielectric layer 22 is formed, for example, by the CVD method so as to cover the entire first substrate surface 111 of the semiconductor substrate 11 and the inner surface 121 of the trench 12.

[0149] As shown in FIG. 31, the method for manufacturing the chip component 10 includes forming a first electrode layer 23. The first electrode layer 23 is formed by forming a conductive film, for example, by the CVD method on the dielectric layer 22 and selectively etching the conductive film.

[0150] As shown in FIG. 32, the method for manufacturing the chip component 10 includes forming a first insulating layer 31. The first insulating layer 31 is formed, for example, by the CVD method so as to cover the first electrode layer 23 and the dielectric layer 22.

[0151] The method for manufacturing the chip component 10 includes forming a first opening 311 and a second opening 312 in the first insulating layer 31. The first opening 311 and the second opening 312 are formed, for example, by selectively etching the first insulating layer 31.

[0152] As shown in FIG. 33, the manufacturing method of the chip component 10 includes forming a barrier layer 38. The barrier layer 38 is formed, for example, by a CVD method. The manufacturing method of the chip component 10 includes forming a first conductive connection portion 36 and a second conductive connection portion 37. The first conductive connection portion 36 and the second conductive connection portion 37 are formed, for example, by a CVD method.

[0153] As shown in FIG. 34, the manufacturing method of the chip component 10 includes forming a first conductive layer 32. The first conductive layer 32 is formed, for example, by patterning the material of the first conductive layer 32 formed by sputtering.

[0154] As shown in FIG. 35, the manufacturing method of the chip component 10 includes forming a second insulating layer 33. The second insulating layer 33 is formed, for example, by a CVD method so as to cover the first conductive layer 32.

[0155] The manufacturing method of the chip component 10 includes forming a first opening 331 and a second opening 332 in the second insulating layer 33. The first opening 331 and the second opening 332 are formed, for example, by selectively etching the first insulating layer 31.

[0156] The manufacturing method of the chip component 10 includes forming a second conductive layer 34. The second conductive layer 34 is formed, for example, by patterning the material of the second conductive layer 34 formed by sputtering.

[0157] As shown in FIG. 36, the manufacturing method of the chip component 10 includes forming a surface insulating film 35 and a resin insulating layer 41. The surface insulating film 35 is formed, for example, by patterning the material of the surface insulating film 35 formed by a CVD method so as to cover the second conductive layer 34 and the second insulating layer 33.

[0158] The resin insulating layer 41 is formed of, for example, a photosensitive resin. The resin insulating layer 41 is formed, for example, by patterning the material of the spin-coated resin insulating layer 41 by photolithography or the like.

[0159] As shown in FIG. 37, the manufacturing method of the chip component 10 includes forming a first external electrode 51 and a second external electrode 52. The first external electrode 51 and the second external electrode 52 are formed by sequentially laminating a seed layer 564, a first metal layer 561, a second metal layer 562, and a solder layer 563.

[0160] As shown in FIGS. 37 and 38, the manufacturing method of the chip component 10 includes thinning the semiconductor substrate 11. In FIG. 37, the second substrate surface 112 of the chip component 10 is indicated by a dashed line. As shown in FIG. 38, the thinned semiconductor substrate 11 is disposed, for example, on a support sheet S1 having adhesiveness. The support sheet S1 may be a dicing tape.

[0161] As shown in FIG. 38, the manufacturing method of the chip component 10 includes forming a substrate side surface 113. The substrate side surface 113 is formed by removing the boundary region 15 of the semiconductor substrate 11 shown in FIG. 18 by, for example, plasma etching. By removing the boundary region 15, the chip component 10 is separated into individual pieces. Through the above steps, the chip component 10 shown in FIG. 3 can be formed.

[0162] (Effect of the First Embodiment) As described above, according to the chip component 10 of the first embodiment, the following effects can be obtained. (1-1) The chip component 10 includes a semiconductor substrate 11, a trench 12, a dielectric layer 22, a first electrode layer 23, a second electrode layer 21, a first conductive layer 32, and a second conductive layer 34. The semiconductor substrate 11 includes a first substrate surface 111 and a second substrate surface 112. The trench 12 is recessed from the first substrate surface 111. The dielectric layer 22 is provided on the inner surface 121 of the trench 12. The first electrode layer 23 includes an embedded portion 231 provided in the trench 12 and surrounded by the dielectric layer 22, and a protruding portion 232 protruding upward from the first substrate surface 111. The second electrode layer 21 includes an electrode portion 211 provided around the trench 12, and a contact portion 212 extending laterally from the electrode portion 211 and provided on the first substrate surface 111. A capacitor 20 is formed by the first electrode layer 23 and the second electrode layer 21 facing each other with the dielectric layer 22 interposed therebetween.

[0163] The first conductive layer 32 is provided on a first insulating layer 31 that covers both the first electrode layer 23 and the contact portion 212. The second conductive layer 34 is provided on a second insulating layer 33 that covers the first conductive layer 32. The first insulating layer 31 includes a first opening 311 that exposes the first electrode layer 23 and a second opening 312 that exposes the contact portion 212. The first insulating layer 31 includes a plurality of first openings 311. A first conductive connection portion 36 is embedded in the first opening 311 separately from the first conductive layer 32, and a second conductive connection portion 37 is embedded in the second opening 312 separately from the first conductive layer 32. The first conductive layer 32 includes a first connection portion 321 electrically connected to the first electrode layer 23 by a plurality of first conductive connection portions 36, and a second connection portion 322 electrically connected to the contact portion 212 by a plurality of second conductive connection portions 37. The second conductive layer 34 is electrically connected to the second connection portion 322. Therefore, the electrode portion 211 of the second electrode layer 21 is electrically connected to the second conductive layer 34 through the contact portion 212 of the second electrode layer 21, the second conductive connection portion 37, and the second connection portion 322.

[0164] In the chip component 10 of the first embodiment, a first connection portion 321 of a first conductive layer 32 electrically connected to a first electrode layer 23 constituting a capacitor 20 and a second conductive layer 34 electrically connected to an electrode portion 211 of a second electrode layer 21 constituting the capacitor 20 are disposed on a trench 12. Therefore, regardless of the position of the trench 12, the number of resistance components R10 connected in series to the capacitor 20 can be reduced. For this reason, the chip component 10 of the first embodiment can achieve low resistance. Further, in the chip component 10 of the first embodiment, an equivalent series resistance (ESR) can be reduced.

[0165] (1-2) In the chip component 10, the first conductive layer 32 includes a first connection portion 321 electrically connected to the first electrode layer 23 and a second connection portion 322 electrically connected to a contact portion 212 of the second electrode layer 21. The first conductive layer 32 is formed on a first insulating layer 31 covering the first electrode layer 23. The first connection portion 321 of the first conductive layer 32 is formed to cover a capacitor region 25 and includes a plurality of openings 323 disposed in a portion overlapping the capacitor region 25. The second connection portion 322 of the first conductive layer 32 is disposed in each of the plurality of openings 323. Therefore, both the first connection portion 321 and the second connection portion 322 of the first conductive layer 32 can be physically disposed within a common capacitor region 25 while being electrically separated from each other. For this reason, the upper portion of the capacitor region 25 can be effectively utilized, and an increase in the size of the chip component 10 can be suppressed.

[0166] (1 - 3) In the chip component 10, the first external electrode 51 and the second external electrode 52 include a first electrode surface 53 facing the side of the second conductive layer 34 and a second electrode surface 54 facing the side opposite to the first electrode surface 53. The back surface step 533 of the first electrode surface 53 corresponds to the height T41 of the resin insulating layer 41. The surface step 544 of the second electrode surface 54 is smaller than the back surface step 533 of the first electrode surface 53. The second electrode surface 54 is the surface of the solder layer 563. Therefore, when mounting the chip component 10 of the first embodiment on the circuit board 81, the gap between the connection pad 811 of the circuit board 81 and the solder layer 563 can be reduced. For this reason, voids are less likely to occur in the solder layer 563. As a result, the mounting strength of the chip component 10 of the first embodiment can be improved. Therefore, the chip component 10 of the first embodiment can improve the mountability.

[0167] (1 - 4) In the chip component 10, the first insulating layer 31 includes a first opening 311 that exposes a part of the protruding portion 232 of the first electrode layer 23. In plan view, the first opening 311 is provided at a position different from the trench 12. Therefore, it is difficult for a thin film to remain on the portion of the first electrode layer 23 exposed by the first opening 311. For this reason, it is possible to suppress the peeling during the manufacturing process and the reattachment to different locations of the product to form a structure not assumed in the design, and it is possible to suppress defects in electrical characteristics and durability. Also, the process contamination can be suppressed by the adhesion of the peeled thin film to the manufacturing apparatus.

[0168] (1-5) In the chip component 10, the first insulating layer 31 includes a second opening 312 that exposes a part of the contact portion 212 of the second electrode layer 21. The second opening 312 penetrates the dielectric layer 22. A second conductive connection portion 37 provided separately from the first conductive layer 32 is embedded in the second opening 312. Therefore, the step and inclination on the upper surface of the second connection portion 322 can be reduced. For this reason, the step coverage of the second conductive layer 34 with respect to the second connection portion 322 can be increased, and the connection between the second conductive layer 34 and the second connection portion 322 of the first conductive layer 32 can be surely made. Further, a barrier layer 38 is provided between the first conductive layer 32 and the first insulating layer 31 and on the inner surface of the second opening 312 of the first insulating layer 31. The barrier layer 38 is, for example, composed of a material containing Ti. Therefore, the contact between the first conductive layer 32 composed of a material containing Al and the semiconductor substrate 11 can be suppressed, and the generation of alloy spikes can be suppressed.

[0169] (1-6) The semiconductor substrate 11 of the chip component 10 includes a plurality of irregularities 13 on the substrate side surface 113. The plurality of irregularities 13 are arranged from the first substrate surface 111 to the second substrate surface 112 of the semiconductor substrate 11. The plurality of irregularities 13 are all formed in a streak shape so as to extend parallel to each other along the side of the substrate side surface 113 of the semiconductor substrate 11. On the first substrate side surface 114 and the second substrate side surface 115 facing opposite sides in the X direction, the plurality of irregularities 13 are formed in a streak shape extending in the Y direction. On the third substrate side surface 116 and the fourth substrate side surface 117 facing opposite sides in the Y direction, the plurality of irregularities 13 are formed in a streak shape extending in the X direction.

[0170] When the semiconductor substrate 11 is cut by a cutting blade, cracks, chips, etc. may occur during processing. Cracks and chips generated in the semiconductor substrate 11 can be factors such as the crack becoming larger or chipping occurring after the chip component 10 is formed. On the other hand, in the chip component 10 of the first embodiment, the semiconductor substrate 11 including the plurality of irregularities 13 is less likely to generate cracks, chips, etc. For this reason, the occurrence of chipping and the like in the chip component 10 can be reduced.

[0171] (1-7) The unevenness 13 on the side surface 113 of the substrate is formed by plasma etching in one example. When forming the chip component 10 by plasma etching, it is not necessary to consider the deviation or chipping of the cutting blade. Therefore, the width of the boundary region 15 may be set by the width of the groove formed by plasma etching. Also, in plasma etching, chipping and the like are less likely to occur in the chip component 10. For this reason, since the boundary region 15 can be brought closer to the constituent members of the chip component 10, the chip component 10 can be miniaturized. Also, since the constituent members of the chip component 10 can be formed up to near the boundary region 15, the capacitance value of the chip component 10 can be increased.

[0172] (Second Embodiment) FIG. 39 is a schematic perspective view showing an example of the chip component 10A of the second embodiment. FIG. 40 is a schematic plan view showing an example of the chip component 10A of the second embodiment in FIG. 39. FIG. 41 is a schematic cross-sectional view schematically showing the internal configuration of the chip component 10A in FIG. 40. Note that FIG. 41 shows the cross-sectional structure of the main part of the chip component 10A in order to facilitate understanding of the structure of the chip component 10A, and does not show the cross-sectional structure at a specific cut surface of the chip component 10A. The dimensions of each component shown in FIG. 41 and the dimensional ratios between the components do not match the dimensions of each component shown in FIGS. 39 and 40 and the dimensional ratios between the components.

[0173] For the chip component 10A of the second embodiment, the same reference numerals are given to the same components as those of the chip component 10 of the first embodiment. Hereinafter, the description of the same components as those of the first embodiment will be omitted, and the components different from those of the first embodiment will be described.

[0174] As shown in FIGS. 39 and 40, the chip component 10A of the second embodiment includes a first external electrode 51A and a second external electrode 52A. The first external electrode 51A and the second external electrode 52A are disposed on the resin insulating layer 41A. The first external electrode 51A and the second external electrode 52A constitute both terminals of the chip component 10A.

[0175] As shown in FIG. 41, the chip component 10A of the second embodiment includes a resin insulating layer 41A disposed on the wiring portion 30. The resin insulating layer 41A of the second embodiment includes one first opening 411A and one second opening 412A. The first opening 411A exposes a part of the first connection portion 341 of the second conductive layer 34. The second opening 412A exposes a part of the second connection portion 342 of the second conductive layer 34. In one example, the first pad opening 351 of the surface insulating film 35 has the same size as the first opening 411A of the resin insulating layer 41A in a plan view. The first pad opening 351 of the surface insulating film 35 may be larger than the first opening 411A of the resin insulating layer 41A in a plan view. In one example, the second pad opening 352 of the surface insulating film 35 has the same size as the second opening 412A of the resin insulating layer 41A in a plan view. The second pad opening 352 of the surface insulating film 35 may be larger than the second opening 412A of the resin insulating layer 41A in a plan view.

[0176] The first external electrode 51A straddles the first connection portion 341 exposed by the first opening 411A and the resin insulating layer 41A around the first opening 411A. The first external electrode 51A is electrically connected to the first connection portion 341 of the second conductive layer 34. The second external electrode 52A straddles the second connection portion 342 exposed by the second opening 412A and the resin insulating layer 41A around the second opening 412A. The second external electrode 52A is electrically connected to the second connection portion 342 of the second conductive layer 34.

[0177] The first external electrode 51A and the second external electrode 52A may include a first electrode portion 571 and a second electrode portion 572. The first electrode portion 571 of the first external electrode 51A may include a portion disposed within the first opening 411A and a portion covering the resin insulating layer 41A. The first electrode portion 571 of the second external electrode 52A may include a portion disposed within the second opening 412A and a portion covering the resin insulating layer 41A.

[0178] The first electrode portion 571 may be formed of a plated metal in one example. The first electrode portion 571 is formed of a material containing Ni in one example. The second electrode portion 572 covers the surface of the first electrode portion 571. The second electrode portion 572 may be formed of a plated metal-like material in one example. The second electrode portion 572 may be composed of a single metal film or a plurality of metal films. In one example, the second electrode portion 572 may include a Pd (palladium) film and an Au (gold) film.

[0179] The chip component 10A may include a side insulating film 39 that covers the substrate side surface 113. The side insulating film 39 may cover the substrate side surface 113 over the entire periphery of the semiconductor substrate 11. In one example, the side insulating film 39 covers the end portion of the first insulating layer 31. The side insulating film 39 may not cover the end portion of the first insulating layer 31. The side insulating film 39 may cover the end faces of the first insulating layer 31 and the second insulating layer 33. The side insulating film 39 may cover the end faces of the first insulating layer 31, the second insulating layer 33, and the surface insulating film 35.

[0180] The side insulating film 39 is formed of a material containing, for example, Si. The side insulating film 39 is formed of, for example, SiO2 or SiN. In one example, the side insulating film 39 is formed of SiO2. The side insulating film 39 may be composed of a plurality of insulating films.

[0181] (Details of the chip side surface) FIG. 42 is a schematic perspective view showing an enlarged part of the side surface of the chip component 10A of the second embodiment. FIG. 43 is a partial schematic cross-sectional view of the chip component 10A of the second embodiment.

[0182] The semiconductor substrate 11 includes a plurality of unevennesses 13 on the substrate side surface 113. The plurality of unevennesses 13 are arranged from the first substrate surface 111 to the second substrate surface 112 of the semiconductor substrate 11. The plurality of unevennesses 13 are all formed in a streak shape so as to extend parallel to each other along the side of the substrate side surface 113 of the semiconductor substrate 11. On the first substrate side surface 114 and the second substrate side surface 115 facing opposite sides in the X direction, the plurality of unevennesses 13 are formed in a streak shape extending in the Y direction. On the third substrate side surface 116 and the fourth substrate side surface 117 facing opposite sides in the Y direction, the plurality of unevennesses 13 are formed in a streak shape extending in the X direction.

[0183] As shown in FIG. 43, the plurality of unevennesses 13 may include a first unevenness 131 and a second unevenness 132 having different sizes. The size of the unevenness 13 may be represented by the width in the thickness direction (Z direction) of the semiconductor substrate 11 in one recess constituting the unevenness 13. The size of the unevenness 13 may be represented by the depth in a direction orthogonal to the thickness direction of the semiconductor substrate 11 in one recess constituting the unevenness 13. The fact that the sizes of the unevennesses 13 are different is intended to mean that at least one of the width and the depth of the unevennesses 13 is different.

[0184] The substrate side surface 113 of the semiconductor substrate 11 may include a first unevenness region 141 in which a plurality of first unevennesses 131 are formed and a second unevenness region 142 in which a plurality of second unevennesses 132 are formed. The substrate side surface 113 may include three or more unevenness regions.

[0185] The first concavo-convex region 141 is arranged closer to the first substrate surface 111 than the second concavo-convex region 142 on the substrate side surface 113. The second concavo-convex region 142 is arranged closer to the second substrate surface 112 than the first concavo-convex region 141 on the substrate side surface 113. In one example, the first concavo-convex region 141 is a region in the range from the second concavo-convex region 142 to the first substrate surface 111 on the substrate side surface 113. The second concavo-convex region 142 is a region in the range from the first concavo-convex region 141 to the second substrate surface 112 on the substrate side surface 113. In one example, in the thickness direction (Z direction) of the semiconductor substrate 11, the length L71 of the first concavo-convex region 141 is smaller than the length L71 of the second concavo-convex region 142. The length L71 of the first concavo-convex region 141 may be equal to the length L72 of the second concavo-convex region 142. The length L71 of the first concavo-convex region 141 may be larger than the length L72 of the second concavo-convex region 142.

[0186] In the first concavo-convex region 141, a plurality of first concavo-convex portions 131 are arranged in the thickness direction (Z direction) of the semiconductor substrate 11 at a first pitch. The first pitch of the first concavo-convex portion 131 may be represented by the width in the thickness direction (Z direction) of the semiconductor substrate 11 in one recess constituting the first concavo-convex portion 131. In the second concavo-convex region 142, a plurality of second concavo-convex portions 132 are arranged in the thickness direction (Z direction) of the semiconductor substrate 11 at a second pitch. The second pitch of the second concavo-convex portion 132 may be represented by the width in the thickness direction (Z direction) of the semiconductor substrate 11 in one recess constituting the second concavo-convex portion 132. It can be said that the first pitch of the first concavo-convex portion 131 in the first concavo-convex region 141 is smaller than the second pitch of the second concavo-convex portion 132 in the second concavo-convex region 142.

[0187] The size of the first concavo-convex portion 131 is smaller than the size of the second concavo-convex portion 132. As the size of the first concavo-convex portion 131, the width W71 of one recess constituting the first concavo-convex portion 131 may be 0.1 μm or more and 2 μm or less. In one example, the width W71 of the first concavo-convex portion 131 may be 0.5 μm. The depth D71 of one recess constituting the first concavo-convex portion 131 may be 0.1 μm or more and 2 μm or less. In one example, the depth D71 of the first concavo-convex portion 131 may be 0.25 μm.

[0188] The size of the second unevenness 132 is smaller than the size of the second unevenness 132. As the size of the second unevenness 132, the width W72 of one recess constituting the second unevenness 132 may be 0.5 μm or more and 5 μm or less. In one example, the width W72 of the second unevenness 132 may be 1.5 μm. The depth D72 of one recess constituting the second unevenness 132 may be 0.5 μm or more and 5 μm or less. In one example, the depth D72 of the second unevenness 132 may be 0.5 μm.

[0189] As shown in FIG. 43, the side insulating film 39 includes a first insulating film 391 that covers a plurality of first unevennesses 131 and a second insulating film 392 that covers a plurality of second unevennesses 132. The first insulating film 391 includes a first surface 393 located on the side opposite to the substrate side surface 113 of the semiconductor substrate 11. The first insulating film 391 covers the substrate side surface 113 of the semiconductor substrate 11 so as to fill a plurality of first unevennesses 131 in the first unevenness region 141. The first surface 393 of the first insulating film 391 may be formed as a flat surface in one example.

[0190] The second insulating film 392 includes a second surface 394 located on the side opposite to the substrate side surface 113 of the semiconductor substrate 11. The second insulating film 392 is formed so as to cover a plurality of second unevennesses 132 in the second unevenness region 142. The second surface 394 of the second insulating film 392 may be formed in an uneven shape according to the second unevenness 132.

[0191] (Method for manufacturing a chip component) An example of a method for manufacturing the chip component 10A according to the second embodiment shown in FIGS. 39 to 43 will be described.

[0192] FIGS. 44 to 47 are schematic cross-sectional views showing exemplary manufacturing steps of the chip component 10A according to the second embodiment. FIGS. 44 to 47 correspond to the cross-sectional structure of the chip component 10A shown in FIG. 41. For ease of understanding, in FIGS. 44 to 47, members that are the same as the final components of the chip component 10A are given the same reference numerals as in FIG. 41.

[0193] FIG. 44 is a schematic cross-sectional view showing an example of the manufacturing process of the chip component 10A in FIG. 47, and is a schematic cross-sectional view showing the manufacturing process following FIG. 35 of the first embodiment. That is, the chip component 10A of the second embodiment is formed by the manufacturing process related to the schematic cross-sectional views shown in FIGS. 27 to 35 in the chip component 10 of the first embodiment and the manufacturing process related to the schematic cross-sectional views shown in FIGS. 44 to 47.

[0194] As shown in FIG. 44, the manufacturing method of the chip component 10A includes forming a resin insulating layer 41A. The resin insulating layer 41A is formed, for example, by patterning the material of the spin-coated resin insulating layer 41A by photolithography.

[0195] As shown in FIG. 45, the manufacturing method of the chip component 10A includes forming a substrate side surface 113. The substrate side surface 113 is formed by removing the boundary region 15 of the semiconductor substrate 11 shown in FIG. 18 by plasma etching, for example. By plasma etching, a groove 16 reaching from the first substrate surface 111 to the middle in the thickness direction of the semiconductor substrate 11 is formed in the semiconductor substrate 11.

[0196] As shown in FIG. 46, the manufacturing method of the chip component 10A includes forming a side insulating film 39. The side insulating film 39 is formed by, for example, CVD method. As shown in FIG. 47, the manufacturing method of the chip component 10A includes forming a first external electrode 51A and a second external electrode 52A. The first external electrode 51A and the second external electrode 52A are formed by sequentially laminating a first electrode portion 571 and a second electrode portion 572.

[0197] The manufacturing method of the chip component 10A includes singulating the chip component 10A. The chip component 10A is separated and singulated by the groove 16, for example, by grinding the semiconductor substrate 11 shown in FIG. 47 from the second substrate surface 112B to form the second substrate surface 112 indicated by the broken line.

[0198] (Effect of the Second Embodiment) As described above, according to the chip component 10A of the second embodiment, in addition to the effects of the chip component 10 of the first embodiment, the following effects are achieved.

[0199] (2-1) The chip component 10A of the second embodiment includes a substrate side surface 113 that connects the first substrate surface 111 and the second substrate surface 112. The substrate side surface 113 includes a first uneven region 141 in which unevenness 131 is formed, and a second uneven region 142 in which unevenness 132 larger than the first uneven region 141 is formed. The first uneven region 141 is disposed closer to the first substrate surface 111 than the second uneven region 142 on the substrate side surface 113.

[0200] By reducing the pitch of the unevenness 131 on the first substrate surface 111 side of the semiconductor substrate 11, when forming the substrate side surface 113 by the groove 16, the damage applied to the first substrate surface 111 side of the semiconductor substrate 11 can be reduced. As a result, the generation of cracks at the opening end of the groove 16, particularly on the first substrate surface 111 of the semiconductor substrate 11, can be more effectively suppressed.

[0201] (2-2) The plurality of first unevennesses 131 in the first uneven region 141 can reduce the damage at the corner on the first substrate surface 111 side of the semiconductor substrate 11 in the chip component 10A after singulation. As a result, the generation of cracks on the first substrate surface 111 side of the semiconductor substrate 11 of the chip component 10A can be more effectively suppressed.

[0202] (Modification example) The above embodiment can be modified as follows, for example. The above embodiment and each of the following modification examples can be combined with each other as long as no technical contradiction occurs. In the following modification examples, parts common to the above embodiment are denoted by the same reference numerals as in the above embodiment, and the description thereof is omitted.

[0203] · The shapes of the first conductive connection portion 36 and the second conductive connection portion 37 may be appropriately changed. As shown in FIG. 48, the first conductive connection portion 36 disposed between the first continuous trench 62 and the second continuous trench 63 may be configured as a plurality of spaced-apart first conductive connection portions 36 in the Y direction in which the first continuous trench 62 and the second continuous trench 63 are continuous.

[0204] · The shapes of the first opening 411 and the second opening 412 of the resin insulating layer 41 may be appropriately changed. FIG. 49 is a schematic cross-sectional view showing the first opening 411 and the second opening 412 of the resin insulating layer 41 of the modified example.

[0205] The resin insulating layer 41 includes a plurality of first openings 411 and a plurality of second openings 412. The resin insulating layer 41 includes an upper surface 413, a lower surface 416 opposite to the upper surface 413, and a plurality of first side surfaces 414 that form the plurality of first openings 411. The first side surface 414 has a curved surface on the side of the lower surface 416 so that the first opening width W41 of the first opening 411 becomes smaller. The first protrusion 42 sandwiched between the first openings 411 in the X direction has a corner between the first side surface 414 and the upper surface 413.

[0206] The resin insulating layer 41 includes a plurality of second side surfaces 415 that form the plurality of second openings 412. The second side surface 415 has a curved surface on the side of the lower surface 416 so that the second opening width W43 of the second opening 412 becomes smaller. The second protrusion 43 sandwiched between the second openings 412 in the X direction has a corner between the second side surface 415 and the upper surface 413.

[0207] With respect to the resin insulating layer 41 formed in this way, the surface step 544 on the second electrode surface 54 of the first external electrode 51 and the second external electrode 52 can be made smaller than the back surface step 533 of the first electrode surface 53. Therefore, the mountability of the chip component 10 can be improved.

[0208] · The configuration and shape of the device region in the chip component may be appropriately changed. FIG. 50 is a schematic plan view showing a chip component 10B of a modified example. The chip component 10B of this modified example includes a device region 25 extending from a portion overlapping with the first external electrode 51 to a portion overlapping with the second external electrode 52. The device region 25 may include at least one of a capacitor, a diode, and a resistor as a functional device of the chip component 10B. The device region 25 may be formed so as to overlap at least a part of one of the first external electrode 51 and the second external electrode 52. Further, the device region 25 may be formed between the first external electrode 51 and the second external electrode 52.

[0209] The chip component 10B shown in FIG. 50 includes a recess 17 in the substrate side surface 114. The recess 17 may be formed so as to be visible. The recess 17 may be provided for confirming the direction of the chip component 10B. The direction of the chip component 10B may be set according to the characteristics and polarities of the functional devices included in the device region 25 of the chip component 10B. In one example, the recess 17 indicates the polarity (anode or cathode) of the diode included in the device region 25.

[0210] · In the chip component 10 of the first embodiment, a plurality of irregularities 13 having different sizes may be formed on the substrate side surface 113 of the semiconductor substrate 11. In the chip component 10 of the first embodiment, the semiconductor substrate 11 may include a plurality of irregularity regions.

[0211] · In the chip component 10A of the second embodiment, one irregularity region, that is, the irregularities 13 having the same size may be formed on the substrate side surface 113 of the semiconductor substrate 11 from the first substrate surface 111 toward the second substrate surface 112.

[0212] · On the substrate side surface 113 of the semiconductor substrate 11, a plurality of irregularities 13 may be formed such that the pitch gradually increases from the first substrate surface 111 side to the second substrate surface 112 side of the semiconductor substrate 11. Further, a plurality of irregularities 13 may be formed such that the pitch gradually decreases from the first substrate surface 111 side to the second substrate surface 112 side of the semiconductor substrate 11.

[0213] · In the chip component 10 of the first embodiment, a side insulating film 39 covering the substrate side surface 113 of the semiconductor substrate 11 may be included. · In the chip component 10A of the second embodiment, the side insulating film 39 may be omitted.

[0214] As used herein, the term "on" includes both the meanings of "on" and "above" unless the context clearly indicates otherwise. Therefore, the expression "the first layer is formed on the second layer" is intended to mean that in some embodiments, the first layer may be directly disposed on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. That is, the term "on" does not exclude a structure in which other layers are formed between the first layer and the second layer.

[0215] The Z-axis direction used in the present disclosure does not necessarily have to be the vertical direction and does not have to completely coincide with the vertical direction. Therefore, various structures according to the present disclosure (for example, the structure shown in FIG. 1) are not limited to the "upper" and "lower" in the Z-axis direction described in this specification being the "upper" and "lower" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0216] (Supplementary Note) The technical idea that can be grasped from the present disclosure is described below. Note that, for the purpose of assisting understanding rather than limiting, the components described in the supplementary note are assigned the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples for assisting understanding, and the components described in each supplementary note should not be limited to the components indicated by the reference numerals.

[0217] (Supplementary Note A) In a chip component, connection failure may occur between internal components. According to the following items, a chip component capable of reducing connection failure can be provided. (Supplementary Note A1) A semiconductor substrate (11) including a first substrate surface (111) and a second substrate surface (112) opposite to the first substrate surface (111), A trench (12) recessed from the first substrate surface (111), A dielectric layer (22) provided on the inner surface of the trench (12), A first electrode layer (23) including an embedded portion (231) provided in the trench (12) and surrounded by the dielectric layer (22), and a protruding portion (232) protruding upward from the first substrate surface (111), A second electrode layer (21) including an electrode portion (211) provided around the trench (12) in the semiconductor substrate (11), and a contact portion (212) extending laterally from the electrode portion (211) and provided on the first substrate surface (111), A first insulating layer (31) covering both the first electrode layer (23) and the contact portion (212), and including a first opening (311) exposing the first electrode layer (23) and a second opening (312) exposing the contact portion (212), A first conductive layer (32) provided on the first insulating layer (31), A second insulating layer (33) covering the first conductive layer (32), A second conductive layer (34) provided on the second insulating layer (33), A first conductive connection portion (36) provided separately from the first conductive layer (32) and embedded in the first opening (311), A second conductive connection portion (37) provided separately from the first conductive layer (32) and embedded in the second opening (312), Including, A capacitor is formed by the first electrode layer (23) and the electrode portion (211) of the second electrode layer (21) facing each other with the dielectric layer (22) interposed therebetween, The first conductive layer (32) is, A first connection portion (321) electrically connected to the first electrode layer (23) by the first conductive connection portion (36), A second connection part (322) that is electrically insulated from the first connection part (321) and is electrically connected to the contact part (212) by the second conductive connection part (37); including the second conductive layer (34) and the second connection part (322) are electrically connected; a chip component.

[0218] (Appendix A2) The second connection part (322) is disposed across both above the contact part (212) and the protruding part (232). The chip component according to Appendix A1.

[0219] (Appendix A3) Including a barrier layer provided on the inner surface of the first opening (311) and the inner surface of the second opening (312) between the first conductive layer (32) and the first insulating layer (31). The chip component according to Appendix A1 or Appendix A2.

[0220] (Appendix A4) The first conductive connection part (36) and the second conductive connection part (37) are made of a material containing W. The chip component according to any one of Appendices A1 to A3.

[0221] (Appendix A5) An opening (332) for exposing the second connection part (322) is provided in the second insulating layer (33). The second conductive layer (34) includes a portion provided in the opening (332) and in contact with the second connection part (322). The chip component according to any one of Appendices A1 to A4.

[0222] (Appendix A6) The second electrode layer (21) is composed of a diffusion layer containing impurities of a first conductivity type. The chip component according to any one of Appendices A1 to A5.

[0223] (Appendix A7) A plurality of the trenches (12) are arranged, and the electrode portion (211) of the second electrode layer (21) is provided around the trenches (12). The chip component according to any one of Appendices A1 to A6.

[0224] (Appendix A8) The first opening (311) in which the first conductive connection portion (36) is embedded is provided at a position different from that of the trench (12) in a plan view as viewed from a direction perpendicular to the first substrate surface (111). The chip component according to any one of Appendices A1 to A7.

[0225] (Appendix A9) In a plan view as viewed from a direction perpendicular to the first substrate surface (111), the first conductive connection portion (36) is disposed between adjacent trenches (12). The chip component according to any one of Appendices A1 to A8.

[0226] (Appendix A10) In a plan view as viewed from a direction perpendicular to the first substrate surface (111), the first opening (311) and the first conductive connection portion (36) extend along the trench (12). The chip component according to any one of Appendices A1 to A9.

[0227] (Appendix A11) In a plan view as viewed from a direction perpendicular to the first substrate surface (111), the trench (12) has a curved portion, and the first conductive connection portion (36) is curved along the trench (12). The chip component according to any one of Appendices A1 to A10.

[0228] (Appendix A12) In a plan view seen from a direction perpendicular to the first substrate surface (111), the trench (12) extends in a first direction and includes a plurality of straight portions (621) arranged in a second direction orthogonal to the first direction, and the first conductive connection portion (36) is disposed between the straight portions (621) adjacent to each other in the second direction. The chip component according to any one of Appendices A1 to A11.

[0229] (Appendix A13) In a plan view seen from a direction perpendicular to the first substrate surface (111), the distance between two adjacent trenches (12) is wider than the width of the trench (12), and the first conductive connection portion (36) is provided between the two adjacent trenches (12). The chip component according to any one of Appendices A1 to A12.

[0230] (Appendix A14) The second conductive layer (34) includes a plurality of the contact portions (212). The chip component according to any one of Appendices A1 to A13.

[0231] (Appendix A15) The plurality of contact portions (212) are arranged in a matrix in a plan view seen from a direction perpendicular to the first substrate surface (111). The chip component according to Appendix A14.

[0232] (Appendix A16) The electrode portion (211) is arranged so as to surround the contact portion (212) in a plan view seen from a direction perpendicular to the first substrate surface (111). The chip component according to Appendix A14 or Appendix A15.

[0233] (Appendix A17) The first electrode layer (23) includes a contact opening (233) disposed at a position overlapping the contact portion (212) in a plan view seen from a direction perpendicular to the first substrate surface (111). The first insulating layer (31) includes a second opening (312) in which the second conductive connection portion (37) is embedded inside the contact opening (233). The chip component according to any one of Appendices A1 to A16.

[0234] (Appendix A18) The semiconductor substrate (11) includes a substrate side surface (113) connecting the first substrate surface (111) and the second substrate surface (112). A plurality of irregularities (13) are formed on the substrate side surface (113) from the first substrate surface (111) toward the second substrate surface (112). The plurality of irregularities (13) extend along the side of the substrate side surface (113) of the semiconductor substrate (11). The chip component according to any one of Appendices A1 to A17.

[0235] (Appendix A19) The semiconductor substrate (11) includes a substrate side surface (113) connecting the first substrate surface (111) and the second substrate surface (112). The substrate side surface (113) A first uneven region (141) in which a first unevenness (131) is formed, and A second uneven region (142) in which a second unevenness (132) larger than the first unevenness (131) is formed, and includes The first uneven region (141) is disposed closer to the first substrate surface (111) than the second uneven region (142) on the substrate side surface (113). The chip component according to any one of Appendices A1 to A17.

[0236] (Appendix A20) The first unevenness (131) and the second unevenness (132) extend along the side of the semiconductor substrate (11). The chip component according to Appendix A19.

[0237] (Appendix A21) The first concavo-convex region (141) is provided between the second concavo-convex region (142) and the first substrate surface (111), and the second concavo-convex region (142) is provided between the first concavo-convex region (141) and the second substrate surface (112). The chip component according to appended note A19 or appended note A20.

[0238] (Appended note A22) The depth of the first concavo-convex (131) is 0.1 μm or more and 2 μm or less, and the depth of the second concavo-convex (132) is 0.5 μm or more and 5 μm or less. The chip component according to any one of appended notes A19 to A21.

[0239] (Appended note A23) The width of the first concavo-convex (131) is 0.1 μm or more and 2 μm or less, and the width of the second concavo-convex (132) is 0.5 μm or more and 5 μm or less. The chip component according to any one of appended notes A19 to A22.

[0240] (Appended note A24) In a plan view seen from a direction perpendicular to the first substrate surface (111), the distance from the periphery of the first substrate surface (111) to the capacitor region including the capacitor is 5 μm or more and 50 μm or less. The chip component according to any one of appended notes A18 to A22.

[0241] (Appended note A25) It is provided on the first substrate surface (111) and includes external electrodes (51, 52) electrically connected to the capacitor. In a plan view seen from a direction perpendicular to the first substrate surface (111), the distance from the periphery of the first substrate surface (111) to the external electrodes (51, 52) is 5 μm or more and 50 μm or less. The chip component according to any one of appended notes A1 to A23.

[0242] (Appended note A26) A resin insulating layer (41) covering the second conductive layer (34) and including a plurality of openings (411, 412) exposing a part of the second conductive layer (34), External electrodes (51, 52) in contact with the second conductive layer (34) within the plurality of openings (411, 412), comprising The external electrodes (51, 52) include a first electrode surface (53) including a resin contact portion (531) in contact with the resin insulating layer (41) and a conductive contact portion (532) in contact with the second conductive layer (34), a second electrode surface (54) on the side opposite to the first electrode surface (53), comprising The second electrode surface (54) includes a first surface region (541) located above the resin contact portion (531) and a second surface region (542) located above the conductive contact portion (532), A surface step (544) between the first surface region (541) and the second surface region (542) is smaller than a back surface step (533) between the resin contact portion (531) and the second conductive layer (34) on the first electrode surface (53). The chip component according to any one of Appendices A1 to A23.

[0243] (Appendix A27) The external electrodes (51, 52) include a first metal layer (561), a second metal layer (562), and a solder layer (563) laminated in order from the side of the second conductive layer (34). The chip component according to Appendix A26.

[0244] (Appendix A28) A distance between two adjacent openings (411, 412) is larger than thicknesses of the first metal layer (561) and the second metal layer (562). The chip component according to Appendix A27.

[0245] (Appendix A29) The distance between two adjacent ones of the openings (411, 412) is smaller than the thicknesses of the first metal layer (561) and the second metal layer (562). The chip component according to Addendum A27.

[0246] (Addendum A30) The width of the opening (411, 412) is larger than the distance between the openings (411, 412). The chip component according to Addendum A28 or Addendum A29.

[0247] (Addendum A31) The width of the opening (411, 412) is equal to the distance between the openings (411, 412). The chip component according to Addendum A28 or Addendum A29.

[0248] (Addendum A32) The width of the opening (411, 412) is smaller than the distance between the openings (411, 412). The chip component according to Addendum A28 or Addendum A29.

[0249] (Addendum A33) The height of the protrusions (42, 43) between two adjacent ones of the openings (411, 412) is equal to the height of the resin insulating layer (41) other than the protrusions. The chip component according to any one of Addenda A26 to A32.

[0250] (Addendum A34) The height of the protrusions (42, 43) between two adjacent ones of the openings (411, 412) is smaller than the height of the resin insulating layer (41) other than the protrusions. The chip component according to any one of Addenda A26 to A32.

[0251] (Addendum A35) The second conductive layer (34) includes a first connection portion (341) electrically connected to the first electrode layer (23) and a second connection portion (342) electrically connected to the second electrode layer (21). A resin insulating layer (41A) covering the second conductive layer (34) and including one first opening (411A) exposing a part of the first connection portion (341) and one second opening (412A) exposing a part of the second connection portion (342); A first external electrode (51A) in contact with the first connection portion (341) of the second conductive layer (34) within the first opening (411A); A second external electrode (52A) in contact with the second connection portion (342) of the second conductive layer (34) within the second opening (412A); comprising; The chip component according to any one of Appendices A1 to A24.

[0252] (Appendix B) In a chip component, improvement in mountability of an external electrode may be required. According to the following items, a chip component capable of improving mountability can be provided.

[0253] (Appendix B1) A semiconductor substrate (11) including a first substrate surface (111) and a second substrate surface (112) opposite to the first substrate surface (111); A device region (25) provided on the first substrate surface (111); A conductive layer (34) electrically connected to the device region (25); A resin insulating layer (41) covering the conductive layer (34) and including a plurality of openings (411, 412) exposing a part of the conductive layer (34); External electrodes (51, 52) in contact with the conductive layer (34) through the plurality of openings (411, 412); comprising; The external electrodes (51, 52) include a first electrode surface (53) including a resin contact portion (531) in contact with the resin insulating layer (41) and a conductive contact portion (532) in contact with the conductive layer (34); A second electrode surface (54) on the side opposite to the first electrode surface (53); comprising; The second electrode surface (54) includes a first surface region (541) located above the resin contact portion (531) and a second surface region (542) located above the conductive contact portion (532). The surface step (544) between the first surface region (541) and the second surface region (542) is smaller than the back surface step (533) between the resin contact portion (531) and the conductive layer (41) on the first electrode surface (53). Chip component.

[0254] (Appendix B2) The external electrodes (51, 52) include a first metal layer (561), a second metal layer (562), and a solder layer (563) laminated in order from the side of the conductive layer (34). The chip component according to Appendix B1.

[0255] (Appendix B3) The distance between two adjacent openings (411, 412) is greater than the thicknesses of the first metal layer (561) and the second metal layer (562). The chip component according to Appendix B2.

[0256] (Appendix B4) The distance between two adjacent openings (411, 412) is smaller than the thicknesses of the first metal layer (561) and the second metal layer (562). The chip component according to Appendix B2 or Appendix B3.

[0257] (Appendix B5) The width of the openings (411, 412) is greater than the distance between the openings (411, 412). The chip component according to any one of Appendix B1 to Appendix B4.

[0258] (Appendix B6) The width of the openings (411, 412) is equal to the distance between the openings (411, 412). The chip component according to any one of Appendix B1 to Appendix B4.

[0259] (Supplementary Note B7) The width of the openings (411, 412) is smaller than the distance between the openings (411, 412). The chip component according to any one of Supplementary Notes B1 to B4.

[0260] (Supplementary Note B8) The height of the protrusions (42, 43) between two adjacent openings (411, 412) is equal to the height of the resin insulating layer (41) other than the protrusions. The chip component according to any one of Supplementary Notes B1 to B7.

[0261] (Supplementary Note B9) The height of the protrusions (42, 43) between two adjacent openings (411, 412) is lower than the height of the resin insulating layer (41) other than the protrusions. The chip component according to any one of Supplementary Notes B1 to B7.

[0262] (Supplementary Note B10) The semiconductor substrate (11) is a Si substrate. The chip component according to any one of Supplementary Notes B1 to B9.

[0263] (Supplementary Note B11) The device region (25) includes at least one of a capacitor, a diode, and a resistor. The chip component according to any one of Supplementary Notes B1 to B10.

[0264] (Supplementary Note B12) The device region (25) is a region including a capacitor, a trench (12) recessed from the first substrate surface (111), a dielectric layer (22) provided on the inner surface of the trench (12), a first electrode layer (23) including an embedded portion (231) provided in the trench (12) and surrounded by the dielectric layer (22), and a protruding portion (232) protruding upward from the first substrate surface (111). An electrode portion (211) provided around the trench (12) in the semiconductor substrate (11), and a contact portion (212) that extends laterally from the electrode portion (211) and is provided on the first substrate surface (111), a second electrode layer (21) including the contact portion (212); including; a capacitor is configured by the electrode portion (211) of the first electrode layer (23) and the second electrode layer (21) facing each other through the dielectric layer (22); The chip component according to any one of Appendices B1 to B10.

[0265] (Appendix B13) A first insulating layer (31) covering both the first electrode layer (23) and the contact portion (212), including a first opening (311) exposing the first electrode layer (23) and a second opening (312) exposing the contact portion (212); A first conductive layer (32) provided on the first insulating layer (31); A second insulating layer (33) covering the first conductive layer (32); A second conductive layer (34) provided on the second insulating layer (33); A first conductive connection portion (36) provided separately from the first conductive layer (32) and embedded in the first opening (311); A second conductive connection portion (37) provided separately from the first conductive layer (32) and embedded in the second opening (312); including; The first conductive layer (32) includes; a first connection portion (321) electrically connected to the first electrode layer (23) by the first conductive connection portion (36); a second connection portion (322) electrically insulated from the first connection portion (321) and electrically connected to the contact portion (212) by the second conductive connection portion (37); including; the second conductive layer (34) is electrically connected to the second connection portion (322); The chip component according to Appendix B12.

[0266] (Appendix B14) The second connection part (322) is arranged across both the upper part of the contact part (212) and the protruding part (232). The chip component according to Appendix B13.

[0267] (Appendix B15) Including a barrier layer provided on the inner surface of the first opening (311), the inner surface of the second opening (312), and between the first conductive layer (32) and the first insulating layer (31). The chip component according to Appendix B13 or Appendix B14.

[0268] (Appendix B16) The first conductive connection part (36) and the second conductive connection part (37) are made of a material containing W. The chip component according to any one of Appendix B13 to Appendix B15.

[0269] (Appendix B17) An opening (332) for exposing the second connection part (322) is provided in the second insulating layer (33). The second conductive layer (34) includes a portion (345) provided in the opening (332) and in contact with the second connection part (322). The chip component according to any one of Appendix B13 to Appendix B16.

[0270] (Appendix B18) The second electrode layer (21) is composed of a diffusion layer containing impurities of the first conductivity type. The chip component according to any one of Appendix B13 to Appendix B17.

[0271] (Appendix B19) A plurality of trenches (12) are arranged, and the electrode part (211) of the second electrode layer (21) is provided around the trenches (12). The chip component according to any one of Appendix B13 to Appendix B18.

[0272] (Appendix B20) The first opening (311) in which the first conductive connection portion (36) is embedded is provided at a position different from the trench (12) in a plan view as viewed from a direction perpendicular to the first substrate surface (111). The chip component according to any one of Appendices B13 to B19.

[0273] (Appendix B21) The first opening (311) in which the first conductive connection portion (36) is embedded is disposed between adjacent trenches (12) in a plan view as viewed from a direction perpendicular to the first substrate surface (111). The chip component according to any one of Appendices B13 to B20.

[0274] (Appendix B22) In a plan view as viewed from a direction perpendicular to the first substrate surface (111), the first opening (311) and the first conductive connection portion (36) extend along the trench (12). The chip component according to any one of Appendices B13 to B21.

[0275] (Appendix B23) In a plan view as viewed from a direction perpendicular to the first substrate surface (111), the trench (12) has a curved portion, and the first conductive connection portion (36) is curved along the trench (12). The chip component according to any one of Appendices B13 to B22.

[0276] (Appendix B24) In a plan view as viewed from a direction perpendicular to the first substrate surface (111), the trench (12) extends in a first direction and includes a plurality of straight portions (621) arranged in a second direction orthogonal to the first direction, and the first conductive connection portion (36) is disposed between the straight portions (621) adjacent in the second direction. The chip component according to any one of Appendices B13 to B23.

[0277] (Appendix B25) In a plan view seen from a direction perpendicular to the first substrate surface (111), the distance between two adjacent trenches (12) is wider than the width of the trench (12), and the first conductive connection portion (36) is provided between the two adjacent trenches (12). The chip component according to any one of Appendices B13 to B24.

[0278] (Appendix B26) The second conductive layer (34) includes a plurality of the contact portions (212). The chip component according to any one of Appendices B13 to B25.

[0279] (Appendix B27) The plurality of contact portions (212) are arranged in a matrix in a plan view seen from a direction perpendicular to the first substrate surface (111). The chip component according to Appendix B26.

[0280] (Appendix B28) The electrode portion (211) is arranged so as to surround the contact portion (212) in a plan view seen from a direction perpendicular to the first substrate surface (111). The chip component according to Appendix B26 or Appendix B27.

[0281] (Appendix B29) The first electrode layer (23) includes a contact opening (233) arranged at a position overlapping the contact portion (212) in a plan view seen from a direction perpendicular to the first substrate surface (111). The first insulating layer (31) includes a second opening portion (312) in which the second conductive connection portion (37) is embedded inside the contact opening (233). The chip component according to any one of Appendices B13 to B28.

[0282] (Appendix B30) The semiconductor substrate (11) includes a substrate side surface (113) connecting the first substrate surface (111) and the second substrate surface (112). On the side surface (113) of the substrate, a plurality of concavo-convex portions are formed from the first substrate surface (111) toward the second substrate surface (112). The plurality of concavo-convex portions extend along the side of the side surface (113) of the semiconductor substrate (11). The chip component according to any one of Appendices B1 to B29.

[0283] (Appendix B31) The semiconductor substrate (11) includes a side surface (113) connecting the first substrate surface (111) and the second substrate surface (112). The side surface (113) of the substrate A first concavo-convex region (141) in which a first concavo-convex portion (131) is formed, A second concavo-convex region (142) in which a second concavo-convex portion (132) larger than the first concavo-convex portion (131) is formed, and includes The first concavo-convex region (141) is disposed closer to the first substrate surface (111) than the second concavo-convex region (142) on the side surface (113) of the substrate. The chip component according to any one of Appendices B1 to B29.

[0284] (Appendix B32) The first concavo-convex portion (131) and the second concavo-convex portion (132) extend along the side of the semiconductor substrate (11). The chip component according to Appendix B31.

[0285] (Appendix B33) The first concavo-convex region (141) is provided between the second concavo-convex region (142) and the first substrate surface (111), and the second concavo-convex region (142) is provided between the first concavo-convex region (141) and the second substrate surface (112). The chip component according to Appendix B31 or Appendix B32.

[0286] (Appendix B34) The depth of the first unevenness (131) is 0.1 μm or more and 2 μm or less, and the depth of the second unevenness (132) is 0.5 μm or more and 5 μm or less. The chip component according to any one of Appendices B31 to B33.

[0287] (Appendix B35) The width of the first unevenness (131) is 0.1 μm or more and 2 μm or less, and the width of the second unevenness (132) is 0.5 μm or more and 5 μm or less. The chip component according to any one of Appendices B31 to B34.

[0288] (Appendix B36) In a plan view, the distance from the periphery of the first substrate surface (111) to the device region (25) is 5 μm or more and 50 μm or less. The chip component according to any one of Appendices B1 to B35.

[0289] (Appendix B37) In a plan view, the distance from the periphery of the first substrate surface (111) to the external electrodes (51, 52) is 5 μm or more and 50 μm or less. The chip component according to any one of Appendices B1 to B36.

[0290] (Appendix C) In a chip component, connection failures may occur between internal components. According to the following items, a chip component capable of reducing connection failures can be provided. (Appendix C1) A semiconductor substrate (11) including a first substrate surface (111) and a second substrate surface (112) on the side opposite to the first substrate surface (111), A trench (12) recessed from the first substrate surface (111), A dielectric layer (22) provided on the inner surface of the trench (12), A first electrode layer (23) including an embedded portion (231) provided in the trench (12) and surrounded by the dielectric layer (22), and a protruding portion (232) protruding upward from the first substrate surface (111), An electrode portion (211) provided around the trench (12) in the semiconductor substrate (11), and a contact portion (212) that extends laterally from the electrode portion (211) and is provided on the first substrate surface (111), including a second electrode layer (21). A first insulating layer (31) that covers both the first electrode layer (23) and the contact portion (212) and includes a first opening (311) that exposes the first electrode layer (23). A first conductive layer (32) provided on the first insulating layer (31). A first conductive connection portion (36) provided separately from the first conductive layer (32) and embedded in the first opening (311). Including A capacitor is formed by the first electrode layer (23) and the electrode portion (211) of the second electrode layer (21) facing each other with the dielectric layer (22) interposed therebetween. The first conductive layer (32) includes a first connection portion (321) that is electrically connected to the first electrode layer (23) by the first conductive connection portion (36). The first opening (311) in which the first conductive connection portion (36) is embedded is provided at a position different from the trench (12) in a plan view as viewed from a direction perpendicular to the first substrate surface (111). Chip component.

[0291] (Appendix C2) In a plan view as viewed from a direction perpendicular to the first substrate surface (111), the first conductive connection portion (36) is disposed between two adjacent trenches (12). The chip component according to Appendix C1.

[0292] (Appendix C3) In a plan view as viewed from a direction perpendicular to the first substrate surface (111), the first opening (311) and the first conductive connection portion (36) extend along the trench (12). The chip component according to Appendix C1 or Appendix C2.

[0293] (Appendix C4) The trench (12) has a curved portion, and the first conductive connection portion (36) is curved along the trench (12). The chip component according to any one of Appendices C1 to C3.

[0294] (Appendix C5) In a plan view seen from a direction perpendicular to the first substrate surface (111), the trench (12) extends in a first direction and includes a plurality of straight portions (621) arranged in a second direction orthogonal to the first direction, and the first conductive connection portion (36) is disposed between the adjacent straight portions (621) in the second direction. The chip component according to any one of Appendices C1 to C4.

[0295] (Appendix C6) In a plan view seen from a direction perpendicular to the first substrate surface (111), the distance between two adjacent trenches (12) is wider than the width of the trench (12). The first conductive connection portion (36) is provided between two adjacent trenches (12) in a plan view seen from a direction perpendicular to the first substrate surface (111). The chip component according to any one of Appendices C1 to C5.

[0296] (Appendix C7) The first conductive connection portion (36) is composed of a material containing W. The chip component according to any one of Appendices C1 to C6.

[0297] (Appendix C8) The second electrode layer (21) is composed of a diffusion layer containing impurities of a first conductivity type. The chip component according to any one of Appendices C1 to C7.

[0298] (Appendix C9) A plurality of the trenches (12) are arranged, and the electrode portion (211) of the second electrode layer (21) is provided around the trenches (12). The chip component according to any one of Supplementary Notes C1 to C8.

[0299] (Supplementary Note C10) A second insulating layer (33) covering the first conductive layer (32), A second conductive layer (34) provided on the second insulating layer (33), including The first insulating layer (31) includes a second opening (312) that exposes the contact portion (212), A second conductive connection portion (37) is embedded in the second opening (312) separately from the first conductive layer (32), The first conductive layer (32) includes a second connection portion (322) that is electrically insulated from the first connection portion (321) and is electrically connected to the contact portion (212) by the second conductive connection portion (37), The second conductive layer (34) and the second connection portion (322) are electrically connected, The chip component according to any one of Supplementary Notes C1 to C9.

[0300] (Supplementary Note C11) The second conductive connection portion (37) is disposed across both above the contact portion (212) and the protruding portion (232), The chip component according to Supplementary Note C10.

[0301] (Supplementary Note C12) The second conductive connection portion (37) is made of a material containing W, The chip component according to Supplementary Note C10 or C11.

[0302] (Supplementary Note C13) Including a barrier layer provided between the first conductive layer (32) and the first insulating layer (31), on the inner surface of the first opening (311), and on the inner surface of the second opening (312), The chip component according to any one of Supplementary Notes C10 to C12.

[0303] (Supplementary Note C14) The second insulating layer (33) is provided with an opening (332) for exposing the second connection portion (322). The second conductive layer (34) includes a portion provided in the opening (332) and in contact with the second connection portion (322). The chip component according to any one of Appendices C10 to C13.

[0304] (Appendix C15) A resin insulating layer (41) covering the second conductive layer (34) and including a plurality of openings (411, 412) for exposing a part of the second conductive layer (34); External electrodes (51, 52) in contact with the second conductive layer (34) within the plurality of openings (411, 412); including The external electrodes (51, 52) include a first electrode surface (53) including a resin contact portion (531) in contact with the resin insulating layer (41) and a conductive contact portion (532) in contact with the second conductive layer (34); a second electrode surface (54) on the side opposite to the first electrode surface (53); including The second electrode surface (54) includes a first surface region (541) located above the resin contact portion (531) and a second surface region (542) located above the conductive contact portion (532). A surface step (544) between the first surface region (541) and the second surface region (542) is smaller than a back surface step (533) between the resin contact portion (531) and the second conductive layer (34) on the first electrode surface (53). The chip component according to any one of Appendices C10 to C14.

[0305] (Appendix C16) The external electrodes (51, 52) include a first metal layer (561), a second metal layer (562), and a solder layer (563) laminated in order from the side of the second conductive layer (34). The chip component according to Appendix C15.

[0306] (Appendix C17) The distance between two adjacent said openings (411, 412) is greater than the thicknesses of said first metal layer (561) and said second metal layer (562). The chip component according to appended note C16.

[0307] (Appended note C18) The distance between two adjacent said openings (411, 412) is smaller than the thicknesses of said first metal layer (561) and said second metal layer (562). The chip component according to appended note C16.

[0308] (Appended note C19) The width of said openings (411, 412) is greater than the distance between said openings (411, 412). The chip component according to appended note C17 or appended note C18.

[0309] (Appended note C20) The width of said openings (411, 412) is equal to the distance between said openings (411, 412). The chip component according to appended note C17 or appended note C18.

[0310] (Appended note C21) The width of said openings (411, 412) is smaller than the distance between said openings (411, 412). The chip component according to appended note C17 or appended note C18.

[0311] (Appended note C22) The height of the protrusions (42, 43) between two adjacent said openings (411, 412) is equal to the height of the resin insulating layer (41) other than the protrusions. The chip component according to any one of appended notes C15 to C21.

[0312] (Appended note C23) The height of the protrusions (42, 43) between two adjacent said openings (411, 412) is smaller than the height of the resin insulating layer (41) other than the protrusions. The chip component according to any one of Supplementary Notes C15 to C21.

[0313] (Supplementary Note C24) The semiconductor substrate (11) includes a substrate side surface (113) connecting the first substrate surface (111) and the second substrate surface (112). On the substrate side surface (113), a plurality of irregularities (13) are formed from the first substrate surface (111) toward the second substrate surface (112). The plurality of irregularities (13) extend along the side of the substrate side surface (113) of the semiconductor substrate (11). The chip component according to any one of Supplementary Notes C1 to C23.

[0314] (Supplementary Note C25) The semiconductor substrate (11) includes a substrate side surface (113) connecting the first substrate surface (111) and the second substrate surface (112). The substrate side surface (113) a first uneven region (141) where a first unevenness (131) is formed, a second uneven region (142) where a second unevenness (132) larger than the first unevenness (131) is formed, and includes The first uneven region (141) is arranged closer to the first substrate surface (111) than the second uneven region (142) on the substrate side surface (113). The chip component according to any one of Supplementary Notes C1 to C23.

[0315] (Supplementary Note C26) The first unevenness (131) and the second unevenness (132) extend along the side of the semiconductor substrate (11). The chip component according to Supplementary Note C25.

[0316] (Supplementary Note C27) The first concavo-convex region (141) is provided between the second concavo-convex region (142) and the first substrate surface (111), and the second concavo-convex region (142) is provided between the first concavo-convex region (141) and the second substrate surface (112). The chip component according to appended note C25 or appended note C26.

[0317] (Appended note C28) The depth of the first concavo-convex (131) is 0.1 μm or more and 2 μm or less, and the depth of the second concavo-convex (132) is 0.5 μm or more and 5 μm or less. The chip component according to any one of appended notes C25 to C27.

[0318] (Appended note C29) The width of the first concavo-convex (131) is 0.1 μm or more and 2 μm or less, and the width of the second concavo-convex (132) is 0.5 μm or more and 5 μm or less. The chip component according to any one of appended notes C25 to C28.

[0319] (Appended note C30) In a plan view seen from a direction perpendicular to the first substrate surface (111), the distance from the periphery of the first substrate surface (111) to the capacitor region including the capacitor is 5 μm or more and 50 μm or less. The chip component according to any one of appended notes C25 to C29.

[0320] (Appended note C31) Including external electrodes (51, 52) provided on the first substrate surface (111) and electrically connected to the capacitor, In a plan view seen from a direction perpendicular to the first substrate surface (111), the distance from the periphery of the first substrate surface (111) to the external electrodes (51, 52) is 5 μm or more and 50 μm or less. The chip component according to any one of appended notes C15 to C30.

[0321] (Appended note C32) The second conductive layer (34) includes a first connection portion (341) electrically connected to the first electrode layer (23) and a second connection portion (342) electrically connected to the second electrode layer (21). A resin insulating layer (41A) covering the second conductive layer (34) and including one first opening (411A) exposing a part of the first connection portion (341) and one second opening (412A) exposing a part of the second connection portion (342). A first external electrode (51A) in contact with the first connection portion (31) of the second conductive layer (34) within the first opening (411A). A second external electrode (52A) in contact with the second connection portion (342) of the second conductive layer (34) within the second opening (412A). Including The chip component according to any one of Appendices C1 to C14.

[0322] (Appendix D) In chip components, defects such as chips missing from the substrate may occur. According to the following items, a chip component capable of reducing the occurrence of defects can be provided. (Appendix D1) A semiconductor substrate (11) including a first substrate surface (111), a second substrate surface (112) opposite to the first substrate surface (111), and a substrate side surface (113) connecting the first substrate surface (111) and the second substrate surface (112). A trench (12) recessed from the first substrate surface (111). A dielectric layer (22) provided on the inner surface of the trench (12). A first electrode layer (23) provided in the trench (12) and surrounded by the dielectric layer (22), including an embedded portion (231) and a protruding portion (232) protruding upward from the first substrate surface (111). A second electrode layer (21) including an electrode portion (211) provided around the trench (12) in the semiconductor substrate (11) and a contact portion (212) extending laterally from the electrode portion (211) and provided on the first substrate surface (111). Including A capacitor is formed by the electrode portion (211) of the first electrode layer (23) facing the second electrode layer (21) through the dielectric layer (22). The substrate side surface (113) includes a first concavo-convex region (141) where a first concavo-convex (131) is formed, and a second concavo-convex region (142) where a second concavo-convex (132) larger than the first concavo-convex (131) is formed. The first concavo-convex region (141) is disposed closer to the first substrate surface (111) than the second concavo-convex region (142) on the substrate side surface (113). Chip component.

[0323] (Appendix D2) The first concavo-convex (131) and the second concavo-convex (132) extend along the side of the semiconductor substrate (11). The chip component according to Appendix D1.

[0324] (Appendix D3) The first concavo-convex region (141) is provided between the second concavo-convex region (142) and the first substrate surface (111), and the second concavo-convex region (142) is provided between the first concavo-convex region (141) and the second substrate surface (112). The chip component according to Appendix D1 or Appendix D2.

[0325] (Appendix D4) The depth of the first concavo-convex (131) is 0.1 μm or more and 2 μm or less, and the depth of the second concavo-convex (132) is 0.5 μm or more and 5 μm or less. The chip component according to any one of Appendix D1 to Appendix D3.

[0326] (Appendix D5) The width of the first concavo-convex (131) is 0.1 μm or more and 2 μm or less, and the width of the second concavo-convex (132) is 0.5 μm or more and 5 μm or less. The chip component according to any one of Appendix D1 to Appendix D4.

[0327] ​ (Supplementary Note D6) It includes an external electrode provided on the first substrate surface (111) and electrically connected to the capacitor, In a plan view seen from a direction perpendicular to the first substrate surface (111), the distance from the periphery of the first substrate surface (111) to the external electrode is 5 μm or more and 50 μm or less. The chip component according to any one of Supplementary Notes D1 to D5.

[0328] (Supplementary Note D7) In a plan view seen from a direction perpendicular to the first substrate surface (111), the distance from the periphery of the first substrate surface (111) to the region where the capacitor is formed is 5 μm or more and 50 μm or less. The chip component according to any one of Supplementary Notes D1 to D6.

[0329] (Supplementary Note D8) A first insulating layer (31) covering both the first electrode layer (23) and the contact portion (212), A first conductive layer (32) provided on the first insulating layer (31), The first insulating layer (31) is provided with a first opening (311) for exposing the first electrode layer (23), In the first opening (311), a first conductive connection portion (36) is embedded separately from the first conductive layer (32), The first conductive layer (32) includes a first connection portion (321) electrically connected to the first electrode layer (23) via the first conductive connection portion (36), The first opening (311) in which the first conductive connection portion (36) is embedded is provided at a position different from the trench (12) in a plan view seen from a direction perpendicular to the first substrate surface (111). The chip component according to any one of Supplementary Notes D1 to D7.

[0330] (Supplementary Note D9) The first opening (311) in which the first conductive connection part (36) is embedded is arranged between two adjacent trenches (12) in a plan view seen from a direction perpendicular to the first substrate surface (111). The chip component according to Supplementary Note D8.

[0331] (Supplementary Note D10) In a plan view seen from a direction perpendicular to the first substrate surface (111), the first opening (311) and the first conductive connection part (36) extend along the trench (12). The chip component according to Supplementary Note D8 or Supplementary Note D9.

[0332] (Supplementary Note D11) The trench (12) has a curved portion, and the first conductive connection part (36) is curved along the trench (12). The chip component according to any one of Supplementary Notes D8 to D10.

[0333] (Supplementary Note D12) In a plan view seen from a direction perpendicular to the first substrate surface (111), the trench (12) extends in a first direction and includes a plurality of straight portions (621) arranged in a second direction orthogonal to the first direction, and the first conductive connection part (36) is arranged between the straight portions (621) adjacent in the second direction. The chip component according to any one of Supplementary Notes D8 to D11.

[0334] (Supplementary Note D13) In a plan view seen from a direction perpendicular to the first substrate surface (111), the distance between two adjacent trenches (12) is wider than the width of the trench (12). The first conductive connection part (36) is provided between two adjacent trenches (12) in a plan view seen from a direction perpendicular to the first substrate surface (111). The chip component according to any one of Supplementary Notes D8 to D12.

[0335] (Supplementary Note D14) The first conductive connection part (36) is made of a material containing W. The chip component according to any one of Appendices D8 to D13.

[0336] (Appendix D15) The second electrode layer (21) is composed of a diffusion layer containing impurities of the first conductivity type. The chip component according to any one of Appendices D8 to D14.

[0337] (Appendix D16) A plurality of the trenches (12) are arranged, and the electrode part (211) of the second electrode layer (21) is provided around the trenches (12). The chip component according to any one of Appendices D8 to D15.

[0338] (Appendix D17) A second insulating layer (33) covering the first conductive layer (32), A second conductive layer (34) provided on the second insulating layer (33), are included, The first insulating layer (31) includes a second opening (312) exposing the contact part (212), A second conductive connection part (37) is embedded in the second opening (312) separately from the first conductive layer (32), The first conductive layer (32) includes a second connection part (322) that is electrically insulated from the first connection part (321) and is electrically connected to the contact part (212) via the second conductive connection part (37), The second conductive layer (34) and the second connection part (322) are electrically connected. The chip component according to any one of Appendices D8 to D16.

[0339] (Appendix D18) The second conductive connection part (37) is arranged so as to straddle both above the contact part (212) and the protruding part (232). The chip component according to Appendix D17.

[0340] (Appendix D19) The second conductive connection part (37) is made of a material containing W. The chip component described in Appendix D17 or Appendix D18.

[0341] (Appendix D20) Including a barrier layer provided on the inner surface of the first opening (311) and the inner surface of the second opening (312) between the first conductive layer (32) and the first insulating layer (31). The chip component described in any one of Appendix D17 to Appendix D19.

[0342] (Appendix D21) An opening (332) for exposing the second connection part (322) is provided in the second insulating layer (33). The second conductive layer (34) includes a portion provided in the opening (332) and in contact with the second connection part (322). The chip component described in any one of Appendix D17 to Appendix D20.

[0343] (Appendix D22) A resin insulating layer (41) including a plurality of openings (411, 412) that cover the second conductive layer (34) and expose a part of the second conductive layer (34); External electrodes (51, 52) in contact with the second conductive layer (34) within the plurality of openings (411, 412); Including The external electrodes (51, 52) A first electrode surface (53) including a resin contact part (531) in contact with the resin insulating layer (41) and a conductive contact part (532) in contact with the second conductive layer (34); A second electrode surface (54) on the side opposite to the first electrode surface (53); Including The second electrode surface (54) includes a first surface area (541) located above the resin contact part (531) and a second surface area (542) located above the conductive contact part (532). The surface step (544) between the first surface region (541) and the second surface region (542) is smaller than the back surface step (533) between the resin contact portion (531) on the first electrode surface (53) and the second conductive layer (34). The chip component according to any one of Appendices D17 to D21.

[0344] (Appendix D23) The external electrodes (51, 52) include a first metal layer (561), a second metal layer (562), and a solder layer (563) laminated in order from the side of the second conductive layer (34). The chip component according to Appendix D22.

[0345] (Appendix D24) The distance between two adjacent openings (411, 412) is greater than the thicknesses of the first metal layer (561) and the second metal layer (562). The chip component according to Appendix D23.

[0346] (Appendix D25) The distance between two adjacent openings (411, 412) is smaller than the thicknesses of the first metal layer (561) and the second metal layer (562). The chip component according to Appendix D23.

[0347] (Appendix D26) The width of the openings (411, 412) is greater than the distance between the openings (411, 412). The chip component according to Appendix D24 or Appendix D25.

[0348] (Appendix D27) The width of the openings (411, 412) is equal to the distance between the openings (411, 412). The chip component according to Appendix D24 or Appendix D25.

[0349] (Appendix D28) The width of the openings (411, 412) is smaller than the distance between the openings (411, 412). The chip component described in Supplementary Note D24 or Supplementary Note D25.

[0350] (Supplementary Note D29) The height of the protrusions (42, 43) between two adjacent said openings (411, 412) is equal to the height of the resin insulating layer (41) other than the protrusions. The chip component described in any one of Supplementary Notes D22 to D28.

[0351] (Supplementary Note D30) The height of the protrusions (42, 43) between two adjacent said openings (411, 412) is smaller than the height of the resin insulating layer (41) other than the protrusions. The chip component described in any one of Supplementary Notes D22 to D28.

[0352] (Supplementary Note D31) The second conductive layer (34) includes a first connection portion (341) electrically connected to the first electrode layer (23) and a second connection portion (342) electrically connected to the second electrode layer (21). A resin insulating layer (41A) covering the second conductive layer (34) and including a first opening (411A) exposing a part of the first connection portion (341) and a second opening (412A) exposing a part of the second connection portion (342). A first external electrode (51A) in contact with the first connection portion (341) of the second conductive layer (34) within the first opening (411A). A second external electrode (52A) in contact with the second connection portion (342) of the second conductive layer (34) within the second opening (412A). Including The chip component described in any one of Supplementary Notes D1 to D14.

[0353] The above description is merely illustrative. Those skilled in the art will recognize that there are many more possible combinations and substitutions other than the components and methods (manufacturing processes) enumerated for the purpose of explaining the technology of the present disclosure. The present disclosure is intended to encompass all alternatives, modifications, and variations that are included within the scope of the present disclosure, including the claims.

Description of Reference Numerals

[0354] 10, 10A, 10B Chip components 11 Semiconductor substrate 111 First substrate surface 112 Second substrate surface 113 Substrate side surface 114 - 117 First - fourth substrate side surfaces 12 Trench 121 Inner surface 122 Side surface 123 Bottom surface 13 Concavo - convex 131 First concavo - convex 132 Second concavo - convex 141 First concavo - convex region 142 Second concavo - convex region 15 Boundary region 16 Groove 17 Recess 20 Capacitor 21 Second electrode layer 211 Electrode portion 212 Contact portion 22 Dielectric layer 23 First electrode layer 231 Embedded portion 232 Overhanging portion 233 Contact opening 234 Recess 235 Upper surface 25 Capacitor region 25 Device region 251 First side 252 Second side 253 Third side 254 Fourth side 26 Unit cell 201 Capacitor 30 Wiring part 31 First insulating layer 311 First opening 312 Second opening 313 Coating part 32 First conductive layer 321 First connection part 322 Second connection part 323 Opening 33 Second insulating layer 331 First opening 332 Second opening 34 Second conductive layer 341 First connection part 342 Second connection part 343 Upper surface 344 First coated part 345 Second coated part 346 Wall part 35 Surface insulating film 351 First pad opening 352 Second pad opening 36 First conductive connection part 361 First contact 362 Second contact 363 Third contact 37 Second conductive connection part 38 Barrier layer 39 Side insulating film 391 First insulating film 392 Second insulating film 393 First surface 394 Second surface 41 Resin insulating layer 411 First opening 412 Second opening 413 Upper surface 414 First side surface 415 Second side surface 416 Lower surface 42 First protrusion 421 Upper surface 43 Second protrusion 431 Upper surface 41A Resin insulating layer 411A First opening 412A Second Opening 51 First External Electrode 52 Second External Electrode 53 First Electrode Surface 531 Resin Contact Portion 532 Conductive Contact Portion 533 Back Surface Step 54 Second Electrode Surface 541 First Surface Region 542 Second Surface Region 543 Concave Portion 544 Surface Step 561 First Metal Layer 562 Second Metal Layer 563 Solder Layer 564 Seed Layer 51A First External Electrode 52A Second External Electrode 571 First Electrode Portion 572 Second Electrode Portion 61 Continuous Trench 62 First Continuous Trench 621 Straight Portion 622 Connection Portion 63 Second Continuous Trench 631 First Inclined Portion 632 Second Inclined Portion 64 Discontinuous Trench 65 First Discontinuous Trench 651 Straight Portion 652 Connection Portion 66 Second Discontinuous Trench 661 First Inclined Portion 662 Second Inclined Portion

Claims

1. A semiconductor substrate including a first substrate surface and a second substrate surface opposite to the first substrate surface; A trench recessed from the first substrate surface; A dielectric layer provided on the inner surface of the trench; A first electrode layer including an embedded portion provided in the trench and surrounded by the dielectric layer, and a protruding portion protruding upward from the first substrate surface; A second electrode layer including an electrode portion provided around the trench in the semiconductor substrate, and a contact portion extending laterally from the electrode portion and provided on the first substrate surface; A first insulating layer covering both the first electrode layer and the contact portion, and including a first opening exposing the first electrode layer and a second opening exposing the contact portion; A first conductive layer provided on the first insulating layer; A second insulating layer covering the first conductive layer; A second conductive layer provided on the second insulating layer; A first conductive connection portion provided separately from the first conductive layer and embedded in the first opening; A second conductive connection portion provided separately from the first conductive layer and embedded in the second opening; Comprising; A capacitor is formed by opposing the first electrode layer and the electrode portion of the second electrode layer across the dielectric layer; The first conductive layer, A first connection portion electrically connected to the first electrode layer by the first conductive connection portion; A second connection portion electrically insulated from the first connection portion and electrically connected to the contact portion by the second conductive connection portion; Comprising; The second conductive layer is electrically connected to the second connection portion, Chip component.

2. The second connection portion is disposed across both above the contact portion and the protruding portion, The chip component according to Claim 1.

3. Including a barrier layer provided between the first conductive layer and the first insulating layer, on the inner surface of the first opening, and on the inner surface of the second opening, The chip component according to Claim 1.

4. The first conductive connection portion and the second conductive connection portion are made of a material containing W, The chip component according to Claim 1.

5. An opening for exposing the second connection portion is provided in the second insulating layer, The second conductive layer includes a portion provided in the opening and in contact with the second connection portion, The chip component according to Claim 1.

6. The second electrode layer is formed of a diffusion layer containing impurities of a first conductivity type, The chip component according to Claim 1.

7. A plurality of the trenches are arranged, and the electrode portions of the second electrode layer are provided around the trenches. The chip component according to claim 1.

8. The first opening in which the first conductive connection portion is embedded is provided at a position different from the trench in a plan view as viewed from a direction perpendicular to the first substrate surface. The chip component according to claim 1.

9. The first opening in which the first conductive connection portion is embedded is arranged between adjacent trenches. The chip component according to claim 1.

10. In a plan view as viewed from a direction perpendicular to the first substrate surface, the first opening and the first conductive connection portion extend along the trench. The chip component according to claim 1.

11. In a plan view as viewed from a direction perpendicular to the first substrate surface, the trench has a curved portion, and the first conductive connection portion is curved along the trench. The chip component according to claim 1.

12. In a plan view as viewed from a direction perpendicular to the first substrate surface, the trench extends in a first direction and includes a plurality of straight portions arranged in a second direction orthogonal to the first direction, and the first conductive connection portion is arranged between the straight portions adjacent in the second direction. The chip component according to claim 1.

13. The second electrode layer includes a plurality of the contact portions. The chip component according to claim 1.

14. The plurality of contact portions are arranged in a matrix in a plan view as viewed from a direction perpendicular to the first substrate surface. The chip component according to claim 13.

15. The electrode portion is arranged so as to surround the contact portion in a plan view as viewed from a direction perpendicular to the first substrate surface. The chip component according to claim 13.

16. The first electrode layer includes a contact opening arranged at a position overlapping the contact portion in a plan view as viewed from a direction perpendicular to the first substrate surface. The first insulating layer includes a second opening in which the second conductive connection portion is embedded inside the contact opening. The chip component according to claim 1.

17. The semiconductor substrate includes a substrate side surface connecting the first substrate surface and the second substrate surface. A plurality of concavo-convex portions are formed on the substrate side surface from the first substrate surface toward the second substrate surface. The plurality of concavo-convex portions extend along the side of the substrate side surface of the semiconductor substrate. The chip component according to claim 1.

18. The semiconductor substrate includes a substrate side surface connecting the first substrate surface and the second substrate surface. The substrate side surface includes a first uneven region where first unevenness is formed, and a second uneven region where second unevenness larger than the first unevenness is formed. The first uneven region is disposed closer to the first substrate surface than the second uneven region on the substrate side surface. The chip component according to claim 1.

19. The first uneven region is provided between the second uneven region and the first substrate surface, and the second uneven region is provided between the first uneven region and the second substrate surface. The chip component according to claim 18.

20. A resin insulating layer including a plurality of openings that cover the second conductive layer and expose a part of the second conductive layer; External electrodes in contact with the second conductive layer within the plurality of openings; The external electrodes include a first electrode surface including a resin contact portion in contact with the resin insulating layer and a conductive contact portion in contact with the second conductive layer, and a second electrode surface on the side opposite to the first electrode surface. The second electrode surface includes a first surface region located above the resin contact portion and a second surface region located above the conductive contact portion. The surface step between the first surface region and the second surface region is smaller than the back surface step between the resin contact portion and the second conductive layer on the first electrode surface. The chip component according to claim 1.

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