Semiconductor light-emitting element and method for manufacturing semiconductor light-emitting element

Abstract

To provide a semiconductor light-emitting element which can efficiently remove hydrogen from a p-type semiconductor layer, and a method for manufacturing the semiconductor light-emitting element.SOLUTION: A semiconductor light-emitting element includes: a growth substrate (11); a wall-like semiconductor (22) standing in a vertical direction with respect to the main surface of the growth substrate (11) and extending in the direction of the main surface of the growth substrate (11), the wall-like semiconductor including a p-type semiconductor layer in the inside; a buried semiconductor layer (18) in which the wall-like semiconductor layer (22) is buried; a removal region (23) exposing a p-type semiconductor layer, a part of the wall-like semiconductor layer (22) and a part of the buried semiconductor layer (18) being removed from the removal region.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor light-emitting device and a method for manufacturing the semiconductor light-emitting device.

Background Art

[0002] A semiconductor light-emitting device emits light by recombination of holes and electrons in an active layer. Conventionally, a flat sheet-like well layer has been used as the active layer. In recent years, however, the development of semiconductor light-emitting devices having a three-dimensional nanostructure has been active. Patent Document 1 discloses an example of a semiconductor light-emitting device having such a structure.

[0003] The main body of the semiconductor light-emitting device according to Patent Document 1 is formed of a thin wire structure called a nanowire. The nanowire has a structure in which an active layer is formed around an n-type core layer, a p-type semiconductor layer and a tunnel junction layer are formed around the active layer, and the periphery thereof is embedded with an n-type buried semiconductor layer. A plurality of nanowires are connected by the buried semiconductor layer to ensure strength.

[0004] Here, the p-type semiconductor layer and the tunnel junction layer of the semiconductor light-emitting device according to Patent Document 1 need to be activated by removing hydrogen. For this purpose, these layers are exposed during the process and annealed. However, since these layers are embedded in the n-type buried semiconductor layer, hydrogen cannot be effectively removed, and thus sufficient activation cannot be achieved. If the activation is insufficient, these layers become highly resistive, and the device efficiency of the semiconductor light-emitting device decreases. In the semiconductor light-emitting device according to Patent Document 1, a removal region for exposing these layers is provided on the upper part of the semiconductor light-emitting device, and hydrogen is removed from this removal region.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, in the conventional semiconductor light-emitting element and its manufacturing method, since the upper part of the p-type semiconductor layer is exposed and annealed, the exposed area of the nanowire structure is small and hydrogen is detached from the upper part. Therefore, in order to sufficiently perform the activation treatment down to the lower part, the annealing treatment tends to take a long time.

[0007] Therefore, the present invention has been made in view of the above-described conventional problems, and an object thereof is to provide a semiconductor light-emitting element capable of efficiently performing hydrogen detachment from a p-type semiconductor layer and a method for manufacturing the semiconductor light-emitting element.

Means for Solving the Problems

[0008] In order to solve the above problems, the semiconductor light-emitting element of the present invention includes a growth substrate, a wall-shaped semiconductor layer that stands perpendicular to the main surface of the growth substrate and extends in the main surface direction of the growth substrate, and includes a p-type semiconductor layer inside, an embedded semiconductor layer that embeds the wall-shaped semiconductor layer, and a removal region in which a part of the wall-shaped semiconductor layer and a part of the embedded semiconductor layer are removed to expose the p-type semiconductor layer.

[0009] In such a semiconductor light-emitting element of the present invention, since a part of the wall-shaped semiconductor layer and a part of the embedded semiconductor layer are removed to form a removal region for exposing the p-type semiconductor layer, it is possible to efficiently perform hydrogen detachment from the p-type semiconductor layer.

[0010] In one aspect of the present invention, the wall-shaped semiconductor layer includes an n-type core layer disposed at the center, an active layer disposed on the outer periphery of the n-type core layer, and the p-type semiconductor layer disposed on the outer periphery of the active layer.

[0011] In another aspect of the present invention, the p-type semiconductor layer includes a p-type semiconductor layer disposed on the outer periphery of the active layer and a tunnel junction layer disposed on the outer periphery of the p-type semiconductor layer, and the embedded semiconductor layer is an n-type semiconductor layer.

[0012] In another aspect of the present invention, a plurality of the wall-shaped semiconductor layers are included, and the removal region is formed to include a part of each of all the wall-shaped semiconductor layers.

[0013] In another aspect of the present invention, the entire wall-shaped part of the wall-shaped semiconductor layer is integrally connected, and the removal region is formed to include a part of the wall-shaped semiconductor layer.

[0014] In order to solve the above problems, a method for manufacturing a semiconductor light-emitting device according to the present invention includes a mask forming step of forming a mask having an opening on a growth substrate, a wall-shaped semiconductor layer forming step of forming a wall-shaped semiconductor layer including a p-type semiconductor layer in the opening using selective growth, an embedded semiconductor layer forming step of forming an embedded semiconductor layer on the growth substrate so as to embed the wall-shaped semiconductor layer, a removal region forming step of removing a part of the wall-shaped semiconductor layer and a part of the embedded semiconductor layer to expose the p-type semiconductor layer, and an activation step of annealing the whole to activate the p-type semiconductor layer.

Advantages of the Invention

[0015] The present invention can provide a semiconductor light-emitting device capable of efficiently performing hydrogen desorption from a p-type semiconductor layer and a method for manufacturing the semiconductor light-emitting device.

Brief Description of the Drawings

[0016]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Mode for Carrying Out the Invention

[0017] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In this embodiment, a form in which the semiconductor light-emitting device according to the present invention is applied to a semiconductor light-emitting device having nanowalls will be exemplified and described. The nanowall (wall-shaped structure) refers to a structure that stands perpendicular to the main surface of the substrate of the semiconductor light-emitting device and includes fine walls extending in the main surface direction of the substrate. Also, the same or equivalent components, members, and processes shown in each drawing are denoted by the same reference numerals, and repeated explanations are appropriately omitted. Further, the materials and numerical values cited in the following description are merely examples and are not limited thereto.

[0018] Referring to FIGS. 1 to 7, a semiconductor light-emitting device and a method for manufacturing the semiconductor light-emitting device according to the present embodiment will be described. FIG. 1 is a perspective view showing a semiconductor light-emitting device 10 according to the present embodiment. As shown in FIG. 1, the semiconductor light-emitting device 10 includes a growth substrate 11, an underlying layer 12, an embedded semiconductor layer 18, an insulating protective film 19, a cathode electrode 20, an anode electrode 21, and a nanowall 22 as a wall-shaped semiconductor layer. A removal region 23 and a removal region 24 are formed in the semiconductor light-emitting device 10.

[0019] The growth substrate 11 is a substantially flat member made of a material capable of crystal growth of a semiconductor material. The growth substrate 11 may be composed of a single material, or a material obtained by growing a plurality of semiconductor layers such as a buffer layer (not shown) on a single crystal substrate may be used. The growth substrate 11 may be a single crystal substrate composed of a material for growing a semiconductor single crystal layer via a buffer layer. When the semiconductor light-emitting device 10 is made of a nitride semiconductor, a c-plane sapphire substrate is preferable, but other heterogeneous substrates such as Si may also be used. The buffer layer is a layer formed between the single crystal substrate and the underlying layer 12 to relieve the lattice mismatch between the two. When a c-plane sapphire substrate is used as the single crystal substrate, GaN is preferably used as the material of the buffer layer, but AlN, AlGaN, etc. may also be used.

[0020] The underlying layer 12 is a single crystal semiconductor layer formed on the growth substrate 11 or a buffer layer (not shown). It is preferable to form undoped GaN with a thickness of several μm and compose it of a plurality of layers including an n-type semiconductor layer such as an n-type contact layer thereon. The n-type contact layer is a semiconductor layer doped with an n-type impurity. For example, n-type Al 0.05 Ga 0.95 N, etc. may be mentioned.

[0021] Referring to FIG. 2(a), the nanowall 22 according to this embodiment will be described. The nanowall 22 is a semiconductor layer grown in the opening 13a provided in the mask 13, stands perpendicular to the main surface of the growth substrate 11, and extends in a wall shape in the main surface direction of the growth substrate 11. As shown in FIG. 2(a), the semiconductor light-emitting device 10 includes one or more (illustrated as four cases in FIG. 2(a)) nanowalls 22 as wall-shaped semiconductor layers. The nanowall 22 can be obtained by setting appropriate growth conditions according to the semiconductor material to be formed and performing selective growth in which a specific crystal plane orientation grows. For example, it is conceivable that the plate-like side surface of the nanowall 22 is the non-polar m-plane. In the example shown in FIG. 2(a), since a plurality of openings 13a are periodically formed in the mask 13, the nanowalls 22 are also periodically formed on the growth substrate 11. In this embodiment, a form of forming the nanowall 22 by crystal growth is illustrated and described, but the present invention is not limited thereto, and it may be formed by etching or the like.

[0022] The mask 13 is a layer made of a dielectric material formed on the surface of the underlying layer 12. As the material constituting the mask 13, a material that makes it difficult for semiconductor crystal growth to occur from the mask 13 is selected. For example, SiO2, SiNx, Al2O3, etc. are suitable. A plurality of openings 13a are formed in the mask 13, and a semiconductor layer can grow from the underlying layer 12 partially exposed from the openings 13a.

[0023] Referring to FIG. 2(b), the internal structure of the nanowall 22 will be described. As shown in FIG. 2(b), the nanowall 22 includes an n-type core layer 14, an active layer 15, a p-type semiconductor layer 16, and a tunnel junction layer 17. The nanowall 22 is further embedded by an embedded semiconductor layer 18. In this embodiment, the p-type semiconductor layer 16 and the tunnel junction layer 17 are the p-type semiconductor layers to be activated.

[0024] The n-type core layer 14 is a wall-shaped semiconductor layer selectively grown on the underlying layer 12 exposed from the opening 13a of the mask 13, and is composed of, for example, GaN doped with n-type impurities.

[0025] The active layer 15 is a semiconductor layer grown on the outer periphery of the n-type core layer 14. Examples include a multiple quantum well active layer formed by stacking 5 periods of a GaInN quantum well layer with a thickness of 5 nm and a GaN barrier layer with a thickness of 10 nm. Here, a multiple quantum well active layer is given as an example, but it may also be a single quantum well structure or a bulk active layer. Since the active layer 15 is formed on the side surface and the upper surface of the n-type core layer 14, the area of the active layer 15 can be ensured.

[0026] The p-type semiconductor layer 16 is a semiconductor layer grown on the outer periphery of the active layer 15. For example, it is composed of GaN doped with p-type impurities. Since the p-type semiconductor layer 16 is formed on the side surface and the upper surface of the active layer 15, a double heterostructure is formed by the n-type core layer 14, the active layer 15, and the p-type semiconductor layer 16, and carriers can be well confined in the active layer 15 to improve the probability of radiative recombination.

[0027] The tunnel junction layer 17 is a semiconductor layer grown on the outer periphery of the p-type semiconductor layer 16. For example, it has a two-layer structure in which a p+ layer highly doped with p-type impurities on the inner side and an n+ layer highly doped with n-type impurities on the outer side are grown in sequence. The p+ layer is a semiconductor layer highly doped with p-type impurities. For example, GaN with a thickness of 5 nm and an Mg concentration of 2×10 20 cm- 3 can be used. The n+ layer can be, for example, GaN with a thickness of 10 nm and an Si concentration of 2×10 20 cm -3 . A tunnel junction is formed by these p+ layer and n+ layer. That is, the tunnel junction layer 17 according to the present embodiment is composed of a two-layer structure of a p+ layer and an n+ layer.

[0028] The embedded semiconductor layer 18 is a semiconductor layer formed in the region up to the mask 13, covering the upper surface and the side surface of the nanowalls 22. The material of the embedded semiconductor layer 18 is, for example, n-type GaN. The embedded semiconductor layer 18 connects a plurality of nanowalls 22, ensuring the strength of the semiconductor light-emitting device 10.

[0029] Referring to FIG. 1 again, the cathode electrode 20 is a negative electrode for supplying current to the semiconductor light-emitting element 10. As shown in FIG. 1, the cathode electrode 20 is formed in the removal region 24. The removal region 24 is a region where the underlying layer 12 is exposed, and is composed of a laminated structure of a metal material that makes an ohmic contact with the exposed underlying layer 12 and a pad electrode. The anode electrode 21 is a positive electrode for supplying current to the semiconductor light-emitting element 10. The anode electrode 21 is formed on a part of the embedded semiconductor layer 18, and is composed of a laminated structure of a metal material that makes an ohmic contact with the outermost surface of the embedded semiconductor layer 18 and a pad electrode. Note that the anode electrode 21 may be a transparent electrode extended so as to cover substantially the whole of the embedded semiconductor layer 18.

[0030] The insulating protection film 19 is a so-called passivation film, which covers a predetermined surface of the semiconductor light-emitting element 10 to protect the semiconductor light-emitting element 10 from an external environment such as moisture.

[0031] In the semiconductor light-emitting element 10 according to the present embodiment, a removal region 23 is further formed. The removal region 23 has a function of removing hydrogen from the p-type semiconductor layer 16, which is a p-type semiconductor layer, and the tunnel junction layer 17 in the manufacturing process of the semiconductor light-emitting element 10. That is, as described above, even in a semiconductor light-emitting element having a wall-like structure, hydrogen can be efficiently removed from the p-type semiconductor layer.

[0032] Here, an example in which the removal region 23 is formed until the underlying layer 12 is exposed has been shown. However, if it is the depth at which the p-type semiconductor layer 16 included in the nanowalls 22 is exposed, it may be removed even halfway through the embedded semiconductor layer 18. In order to efficiently perform the hydrogen desorption by annealing treatment, it is preferable to increase the exposed area of the p-type semiconductor layer 16 and form the removal region 23 until the underlying layer 12 is exposed in order to facilitate the hydrogen desorption in the lower part. Further, the removal region 23 is formed including a part of each of the plurality of nanowalls 22 included in the semiconductor light-emitting element 10. The removal region 23 is provided for the purpose of efficiently performing hydrogen desorption from the plurality of nanowalls 22 in the annealing process. Details of the action of the removal region 23 will be described later.

[0033] With reference to FIGS. 3 to 5, a method for manufacturing the semiconductor light-emitting element 10 according to the present embodiment will be described. FIGS. 3(a), (b), and (c) are cross-sectional views and perspective views showing a base layer forming step, a mask forming step, and an opening forming step, respectively. Here, in FIGS. 3 to 5, <1> shows a cross-sectional view and <2> shows a perspective view. FIGS. 4(a), (b), and (c) are cross-sectional views and perspective views showing an n-type core layer forming step, a wall-shaped semiconductor layer forming step, and an embedded semiconductor layer forming step, respectively. FIGS. 5(a), (b), and (c) are cross-sectional views and perspective views showing a removal region forming / activation step, an insulating protective film forming step, and an electrode forming step, respectively. Note that the semiconductor light-emitting element 10 is manufactured in a state of a semiconductor wafer in which a plurality of element forming regions are arranged. In the following description, one of the element forming regions will be focused on and described.

[0034] First, in the base layer forming step shown in FIG. 3(a), as an example, a buffer layer (not shown) made of GaN and a base layer 12 made of GaN and AlGaN are grown on a growth substrate 11 made of a sapphire single crystal by using metalorganic chemical vapor deposition (MOCVD). Note that, as described above, as the growth substrate 11, a substrate made of a single material, for example, an n-type GaN substrate may be used.

[0035] Next, in the mask formation step shown in Fig. 3(b), a mask 13 made of SiO2 is deposited on the underlying layer 12 by sputtering to a thickness of about 30 nm.

[0036] Next, in the opening formation step shown in Fig. 3(c), an opening 13a with a width of about 150 nm is formed using a fine pattern formation method such as nanoimprint lithography.

[0037] Next, in the n-type core layer formation step shown in Fig. 4(a), an n-type core layer 14 made of GaN is grown on the underlying layer 12 exposed from the opening 13a by selective growth using the MOCVD method. As the growth conditions for the n-type core layer 14, for example, TMG and ammonia are used as source gases, the growth temperature is 1050 °C, the V / III ratio is 10, and hydrogen is used as the carrier gas at a pressure of 900 hPa.

[0038] Next, in the wall-shaped semiconductor layer formation step (nanowall formation step) shown in Fig. 4(b), an active layer 15 in which a 5-nm-thick GaInN quantum well layer and a 10-nm-thick GaN barrier layer are stacked 5 times, a p-type semiconductor layer 16 made of GaN doped with p-type impurities, a p+-layer made of GaN with a thickness of 5 nm and a Mg concentration of 2×10 20 cm -3 and an n+-layer made of GaN with a thickness of 10 nm and a Si concentration of 2×10 20 cm -3 are sequentially grown on the side and top surfaces of the n-type core layer 14 to form a tunnel junction layer 17. As an example, the size of the nanowall 22 is about 0.4 μm in width and about 150 μm to 300 μm in length.

[0039] As the growth conditions of the active layer 15, for example, the growth temperature is 800°C, the V / III ratio is 3000, nitrogen is used as the carrier gas at a pressure of 1000 hPa, and TMG, TMI (TriMethyl Indium), and ammonia are used as the source gases. As the growth conditions of the p-type semiconductor layer 16, for example, the growth temperature is 950°C, the V / III ratio is 1000, hydrogen is used as the carrier gas at a pressure of 300 hPa, and TMG, Cp2Mg (bisCycropentadienyl Magnesium), and ammonia are used as the source gases. As the growth conditions of the tunnel junction layer 17, for example, the growth temperature is 800°C, the V / III ratio is 3000, and nitrogen is used as the carrier gas at a pressure of 500 hPa.

[0040] Next, in the embedded semiconductor layer formation step shown in Fig. 4(c), an embedded semiconductor layer 18 made of n-type GaN is grown to embed the outer periphery and the upper surface of the tunnel junction layer 17 with the embedded semiconductor layer 18. In the growth of the embedded semiconductor layer 18, TMG, silane, and ammonia are used as the source gases.

[0041] Next, in the removal region formation step of the removal region formation / activation step shown in Fig. 5(a), the upper surface around the embedded semiconductor layer 18 to the underlying layer 12 is selectively etched to form a mesa 25. As the etching, for example, dry etching is used. At this time, the removal region 23 and the removal region 24 are formed simultaneously. As described above, the removal region 23 is used for hydrogen desorption from the p-type semiconductor layer (p-type semiconductor layer 16, tunnel junction layer 17), and the removal region 24 is used for the formation of the cathode electrode 20. By the formation of the removal region 23, the cross-section of the nanowall 22 (wall-shaped semiconductor layer) is exposed, and the p-type semiconductor layer 16 and the tunnel junction layer 17 are exposed to the outside air. In the formation of the mesa 25, the etching of the side surface other than the removal region 24 may be from the upper surface of the embedded semiconductor layer 18 to the mask 13.

[0042] After the formation of the removal region 23, the longitudinal length from the exposed surface of the nanowall 22 is preferably 150 μm or less. This is for efficiently performing the activation process described later. In the present embodiment, the form in which the removal region 23 is provided at one end of the nanowall 22 has been exemplified and described, but the present invention is not limited thereto, and the removal region 23 may be provided at both ends. When the removal region 23 is provided at both ends of the nanowall 22, the length from the exposed surface to the exposed surface is preferably 300 μm or less.

[0043] After forming the mesa 25, an activation step is carried out to remove hydrogen from the p-type semiconductor layer 16 and the tunnel junction layer 17 (see FIG. 2(b)) of the nanowall 22 exposed from the embedded semiconductor layer 18, and an activation process is performed. Here, the method of the activation process is not limited, but as an example, heat treatment (annealing) at 600° C. in an air atmosphere can be mentioned. Here, heat treatment in an air atmosphere has been exemplified, but any heat treatment may be used as long as it can activate the p-type semiconductor layer and is a heat treatment in an atmosphere where atomic hydrogen does not exist.

[0044] Next, in the insulating protective film forming step shown in FIG. 5(b), an insulating protective film 19 is formed on the side surface of the mesa 25 (embedded semiconductor layer 18). The material of the insulating protective film 19 is, for example, SiO2.

[0045] Next, in the electrode forming step shown in FIG. 5(c), a cathode electrode 20 is formed on the surface of the underlayer 12 of the removal region 24, and an anode electrode 21 is formed on the embedded semiconductor layer 18. Note that the formation position of the cathode electrode 20 is not limited to the position shown in FIG. 5(c), and it may be formed, for example, on the underlayer 12 of the removal region 23 in consideration of the flow of current and the like. Thereafter, the semiconductor wafer is subjected to a scribing (element division) process to be separated into individual semiconductor light-emitting elements 10. The semiconductor light-emitting element 10 is mounted on a package or the like as necessary and used for practical applications.

[0046] In the semiconductor light-emitting device 10 of the present embodiment, when a voltage is applied between the cathode electrode 20 and the anode electrode 21, current flows in the order of anode electrode 21 → embedded semiconductor layer 18 → tunnel junction layer 17 → p-type semiconductor layer 16 → active layer 15 → n-type core layer 14 → underlying layer 12 → cathode electrode 20, and light is generated by radiative recombination in the active layer 15. The light emitted from the active layer 15 is extracted outside the semiconductor light-emitting device 10.

[0047] In the semiconductor light-emitting device 10 of the present embodiment, the active layer 15 is formed on the outer periphery of the n-type core layer 14, and further, a tunnel junction layer 17 is formed on the outer periphery thereof, and it is further embedded in the embedded semiconductor layer 18. Therefore, the current injected from the anode electrode 21 is injected into the active layer 15 as a tunnel current from the side wall of the p-type semiconductor layer via the tunnel junction layer 17 from the embedded semiconductor layer 18. Current injection by the tunnel current through the tunnel junction layer 17 has a low resistance and can perform current injection well. In addition, since the embedded semiconductor layer 18, which is an n-type semiconductor layer, allows current to diffuse more easily than the p-type semiconductor layer, the current can be well diffused to the vicinity of the bottom surface on the side surface of the nanowall 22, and current injection can be performed from the entire tunnel junction layer 17. As a result, the current injected from the anode electrode 21 is well injected into the p-type semiconductor layer 16 not only from the upper surface of the nanowall 22 but also from the entire side surface. As a result, current can be well injected into the active layer 15, a high current density can be realized, and the external quantum efficiency can be improved.

[0048] As described in detail above, according to the semiconductor light-emitting device and the method for manufacturing a semiconductor light-emitting device according to the present embodiment, it is possible to provide a semiconductor light-emitting device and a method for manufacturing a semiconductor light-emitting device capable of efficiently removing hydrogen from a p-type semiconductor layer.

[0049] Next, with reference to FIG. 6, another form of the nanowall 22 will be described. In the above embodiment, as the form of the semiconductor light-emitting device 10, a form composed of a plurality of nanowalls 22 (wall-shaped semiconductor layers) has been exemplified and described, but the present invention is not limited thereto. FIG. 6 shows an example of variations in the form of the nanowall.

[0050] FIG. 6(a) shows an example of a nanowall 22a having a lattice (mesh) structure with rectangles (or squares) as elements. <1> in FIG. 6(a) shows a plan view, and <2> shows a perspective view. The nanowall 22a connects each of the nanowalls 22 shown in FIG. 2(a) with a wall-like portion in a direction orthogonal to the nanowall 22. In the removal region formation / activation step of the manufacturing process of the semiconductor light-emitting device 10 described above, the removal region 23 for hydrogen desorption can be, for example, the removal region 23a shown in FIG. 6(a) <1> in the present embodiment.

[0051] Here, one of the features of the nanowall 22a with respect to the nanowall 22 is that the entire wall-like semiconductor layer is connected integrally without a break. That is, in this case, the removal region 23 for hydrogen desorption does not necessarily have to be provided from one end to the other end of the semiconductor light-emitting device 10. For example, as shown in FIG. 6(a) <1>, it may be a removal region 23b that removes a part of the wall-like portion of the nanowall 22a.

[0052] FIG. 6(b) shows an example of a nanowall 22b having a lattice (mesh) structure with equilateral triangles as elements. <1> in FIG. 6(b) shows a plan view, and <2> shows a perspective view. The removal region 23 for hydrogen desorption can be, for example, the removal region 23c shown in FIG. 6(b) <1> in the present embodiment. Also for the nanowall 22b, the entire wall-like semiconductor layer is connected integrally without a break. Therefore, also for the nanowall 22b, it is not necessarily required to provide the removal region 23 for hydrogen desorption from one end to the other end of the semiconductor light-emitting device 10. Furthermore, the same applies to the nanowall 22a, and it is not necessary to provide it at the peripheral portion of the semiconductor light-emitting device 10. For example, as shown in FIG. 6(b) <1>, it may be a removal region 23d that circularly removes a part of the wall-like semiconductor layer inside the nanowall 22b. Here, since the nanowall 22b is based on an equilateral triangle, there is an effect that it is easy to make the wall surface the non-polar m plane.

[0053] In the present embodiment, a nanowall having a lattice-like regular shape has been described as an example, but the present invention is not limited to this. The nanowall can have any shape and does not necessarily have a regular shape. Further, it is not necessary for the whole to be continuously connected without a break, and it may be separated into a plurality of parts.

[0054] Next, with reference to FIG. 7, a light-emitting device in which the semiconductor light-emitting element 10 according to the present embodiment is mounted will be described. The light-emitting device referred to here refers to a configuration including the semiconductor light-emitting element 10 and its peripheral members for application to actual use. The structure of the light-emitting device is roughly classified into a face-up structure in which the growth substrate 11 is mounted on the bottom and a flip-chip structure in which the growth substrate 11 is mounted on the top.

[0055] FIG. 7(a) is a cross-sectional view showing an example of the configuration of a light-emitting device 50 having a face-up structure. As shown in FIG. 7(a), in the light-emitting device 50, the bottom surface of the growth substrate 11 is fixed to the heat dissipation substrate 51 by the resin 52. Anode wiring 56 and cathode wiring 57 are formed on the heat dissipation substrate 51. Then, the anode electrode 21 of the semiconductor light-emitting element 10 is connected to the anode wiring 56 by the wire 55, and the cathode electrode 20 is connected to the cathode wiring 57 by the wire 55. The anode wiring 56 and the cathode wiring 57 are connected to a power source (not shown), and the semiconductor light-emitting element 10 emits light by supplying current from the power source.

[0056] FIG. 7(b) is a cross-sectional view showing an example of the configuration of a light-emitting device 50a having a flip-chip structure. The light-emitting device 50a is also fixed to a heat dissipation substrate 51 on which a cathode wiring 58 and an anode wiring 59 are formed. That is, as shown in FIG. 7(b), in the light-emitting device 50a, the cathode electrode 20 is connected to the cathode wiring 58 by the post 53, and the anode electrode 21 is connected to the anode wiring 59 by the bump 54. The cathode wiring 58 and the anode wiring 59 are connected to a power source (not shown), and the semiconductor light-emitting element 10 emits light by supplying current from the power source.

[0057] Here, from the perspective of the light-emitting area, the results of comparing nanowires and nanowalls are mentioned. Since both nanowires and nanowalls mainly emit light from the side surfaces, the effective light-emitting area on this side surface is defined as the light-emitting area. Naturally, the larger the light-emitting area, the greater the intensity of the emitted light. In this comparison, the following preconditions were set so that the nanowires and nanowalls could be fairly compared. Note that the nanowires were arranged in a triangular lattice array with nanowires at each vertex of a plurality of equilateral triangles. Also, only the m-plane was considered for the light-emitting part (the side surface of the nanowire / nanowall). <Preconditions for calculating the light-emitting area> · Size of the growth range of the nanowire / nanowall: 300 μm × 300 μm · Diameter of the nanowire / width of the nanowall: 0.4 μm · Pitch of the nanowire / nanowall: 1 μm · Height of the nanowire / nanowall: 1 μm

[0058] Based on the above preconditions, the calculation results of the light-emitting areas of the nanowires and nanowalls are as follows. Light-emitting area of the nanowire = 125581 μm 2 Light-emitting area of the nanowall = 180000 μm 2 That is, it can be seen that the light-emitting area of the nanowall is about 1.4 times that of the nanowire. Thus, nanowalls are expected to be the subject of future research from the perspective of improving light intensity.

[0059] Note that the present invention is not limited to the above-described embodiments, and various modifications are possible within the scope indicated in the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present invention.

Description of reference numerals

[0060] 10... Semiconductor light-emitting element 11... Growth substrate 12... Underlayer 13... Mask 13a…Opening 14…n-type core layer 15…Active layer 16…p-type semiconductor layer 17…Tunnel junction layer 18…Embedded semiconductor layer 19…Insulating protective film 20…Cathode electrode 21…Anode electrode 22, 22a, 22b…Nanowalls 23, 23a, 23b, 23c, 23d…Removal regions 24…Removal region 25…Mesa 50, 50a…Light-emitting device 51…Heat dissipation substrate 52…Resin 53…Post 54…Bump 55…Wire 56…Anode wiring 57…Cathode wiring 58…Cathode wiring 59…Anode wiring

Claims

1. A growth substrate, a wall-shaped semiconductor layer that stands perpendicular to the main surface of the growth substrate and extends in the main surface direction of the growth substrate, and includes a p-type semiconductor layer therein, an embedded semiconductor layer that embeds the wall-shaped semiconductor layer, and a semiconductor light-emitting device comprising a removal region in which a part of the wall-shaped semiconductor layer and a part of the embedded semiconductor layer are removed to expose the p-type semiconductor layer.

2. The semiconductor light-emitting device according to Claim 1, wherein the wall-shaped semiconductor layer includes an n-type core layer disposed at the center, an active layer disposed on the outer periphery of the n-type core layer, and the p-type semiconductor layer disposed on the outer periphery of the active layer.

3. The semiconductor light-emitting device according to Claim 1, wherein the p-type semiconductor layer includes a p-type semiconductor layer disposed on the outer periphery of the active layer and a tunnel junction layer disposed on the outer periphery of the p-type semiconductor layer, and the embedded semiconductor layer is an n-type semiconductor layer.

4. The semiconductor light-emitting device according to Claim 1, including a plurality of the wall-shaped semiconductor layers, and the removal region is formed including a part of each of all the wall-shaped semiconductor layers.

5. The semiconductor light-emitting device according to Claim 1, wherein the entire wall-shaped part of the wall-shaped semiconductor layer is integrally connected, and the removal region is formed including a part of the wall-shaped semiconductor layer.

6. A mask forming step of forming a mask having an opening on a growth substrate, a wall-shaped semiconductor layer forming step of forming a wall-shaped semiconductor layer including a p-type semiconductor layer in the opening using selective growth, an embedded semiconductor layer forming step of forming an embedded semiconductor layer on the growth substrate so as to embed the wall-shaped semiconductor layer, a removal region forming step of removing a part of the wall-shaped semiconductor layer and a part of the embedded semiconductor layer to expose the p-type semiconductor layer, and an activation step of annealing the whole to activate the p-type semiconductor layer.

Images