Semiconductor device

Abstract

To stabilize electric characteristics of a thin film transistor including an oxide semiconductor in an active layer by preventing changes in composition, film quality, interface, and the like of an oxide semiconductor region forming the active layer.SOLUTION: In a thin film transistor including a first oxide semiconductor region as an active layer, a second oxide semiconductor region with lower conductivity than that of the first oxide semiconductor is formed between the first oxide semiconductor region and a protective insulating layer of the thin film transistor. The second oxide semiconductor region thus functions as a protective layer for the first oxide semiconductor region. Therefore, the change in composition or the deterioration in film quality of the first oxide semiconductor region can be prevented and the electric characteristics of the thin film transistor can be stabilized.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device using an oxide semiconductor, a display device using the semiconductor device, and a method for manufacturing the same.

Background Art

[0002] In recent years, liquid crystal display devices typified by liquid crystal displays have been widely spread. As the liquid crystal display, an active matrix type provided with thin film transistors (TFTs) in each pixel is often used. For the thin film transistors of the active matrix type liquid crystal display, amorphous silicon or polycrystalline silicon is used as the active layer. The thin film transistor using amorphous silicon has a low field effect mobility, but can be easily formed on a large area substrate such as a large glass plate. On the other hand, the thin film transistor using polycrystalline silicon has a high field effect mobility, but requires a crystallization process such as laser annealing, and it takes an enormous amount of time to form on a large area substrate such as a large glass substrate.

[0003]

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] The electrical characteristics of the above-described oxide semiconductor layer are greatly affected by the composition, film quality, interface, etc. of the oxide semiconductor layer. And the composition, film quality, interface, etc. of the oxide semiconductor layer can be easily changed by exposure to the atmosphere or contact with a film containing impurities.

[0006] In order to prevent oxygen and moisture in the atmosphere from entering the oxide semiconductor layer of the thin film transistor, a protective insulating layer made of an oxide (silicon oxide) or a nitride (silicon nitride) mainly composed of silicon is formed on the oxide semiconductor layer.

[0007] However, simply forming a protective insulating layer mainly composed of silicon is insufficient to stabilize the composition, film quality, interface, etc. of the oxide semiconductor layer.

[0008] In addition, when patterning the oxide semiconductor layer, the resist mask and resist stripping solution formed may also change the film quality and composition of the oxide semiconductor layer due to contact with the oxide semiconductor layer.

[0009] As described above, there is a problem that the electrical characteristics of the thin film transistor using the oxide semiconductor layer also change with changes in the composition, film quality, interface, etc. of the oxide semiconductor layer. [Means for Solving the Problems]

[0010] One aspect of the present invention is that when forming a thin film transistor, a first oxide is used as an active layer ​​​​​​​Using a semiconductor region, between the first oxide semiconductor region and the protective insulating layer of the thin film transistor, a second oxide semiconductor region having a lower conductivity than the first oxide semiconductor region and functioning as a protective layer for the first oxide semiconductor region is formed.

[0011] One aspect of the present invention includes a gate electrode layer, a gate insulating layer on the gate electrode layer, a source electrode layer and a drain electrode layer on the gate insulating layer, a first oxide semiconductor region on the source electrode layer and the drain electrode layer, and a second oxide semiconductor region on the first oxide semiconductor region. A part of the first oxide semiconductor region is in contact with the gate insulating layer and the side surfaces of the source electrode layer and the drain electrode layer between the source electrode layer and the drain electrode layer. The conductivity of the second oxide semiconductor region is smaller than the conductivity of the first oxide semiconductor region, and the first oxide semiconductor region is electrically connected to the source electrode layer and the drain electrode layer. It is a semiconductor device characterized by this.

[0012] Another aspect of the present invention includes a gate electrode layer, a gate insulating layer on the gate electrode layer, a source electrode layer and a drain electrode layer on the gate insulating layer, a buffer layer having an n-type conductivity type on the source electrode layer and the drain electrode layer, a first oxide semiconductor region on the buffer layer having an n-type conductivity type, and a second oxide semiconductor region on the first oxide semiconductor region. A part of the first oxide semiconductor region is in contact with the gate insulating layer and the side surfaces of the source electrode layer and the drain electrode layer between the source electrode layer and the drain electrode layer. The carrier concentration of the buffer layer is higher than the carrier concentration of the first oxide semiconductor region, the conductivity of the second oxide semiconductor region is smaller than the conductivity of the first oxide semiconductor region, and the conductivity of the buffer layer is between the first oxide semiconductor region and the second oxide semiconductor region. Higher than the conductivity of the oxide semiconductor region, and electrically connected to the upper surfaces of the first oxide semiconductor region, the source electrode layer, and the drain electrode layer via a buffer layer. A semiconductor device is characterized by this. There is.

[0013] Another aspect of the present invention includes a gate electrode layer, a gate insulating layer on the gate electrode layer, a source electrode layer and a drain electrode layer on the gate insulating layer, and an oxide semiconductor layer on the source electrode layer and the drain electrode layer. A part of the oxide semiconductor layer is located between the source electrode layer and the drain electrode layer and is in contact with the gate insulating layer and the side surfaces of the source electrode layer and the drain electrode layer. The oxide semiconductor layer is an oxide semiconductor layer containing at least one of indium, gallium, zinc, or tin. A part of the oxide semiconductor layer is in contact with the side surfaces of the source electrode layer and the drain electrode layer via an insulating layer, and the oxide semiconductor layer is electrically connected to the source electrode layer and the drain electrode layer. A semiconductor device is characterized by this. That is. And. There is.

[0014] Note that the first oxide semiconductor region, the second oxide semiconductor region, and the buffer layer preferably contain at least one of indium, gallium, zinc, or tin. Also, the oxygen vacancy defect density of the second oxide semiconductor region is preferably smaller than the oxygen vacancy defect density of the first oxide semiconductor region. Also, the first oxide semiconductor region and the second oxide semiconductor region may be formed as different oxide semiconductor layers or may be formed in the same oxide semiconductor layer. That is. There is. It is good. There is.

[0015] Note that the conductivity of the second oxide semiconductor region is preferably 1.0×10 -8 S / cm or less. Also, the carrier concentration of the buffer layer is 1×10 preferably. 18 / cm 3It is preferable that it is as described above. Preferably.

[0016] Further, a part of the first oxide semiconductor region preferably contacts side surfaces of the source electrode layer and the drain electrode layer via an oxide film. Also, the oxide film is preferably formed by thermal oxidation, oxygen plasma treatment, or ozone water treatment. Preferably.

[0017] Further, a part of the first oxide semiconductor region preferably contacts side surfaces of the source electrode layer and the drain electrode layer via a sidewall insulating layer. Also, the sidewall insulating layer is preferably formed of a silicon film, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film. Preferably. Preferably.

[0018] Another aspect of the present invention is to form a gate electrode layer on a substrate, form a gate insulating layer on the gate electrode layer, form a conductive film on the gate insulating layer, etch the conductive film to form a source electrode layer and a drain electrode layer, form a first oxide semiconductor film by sputtering on the gate insulating layer, the source electrode layer, and the drain electrode layer, form a second oxide semiconductor film by sputtering on the first oxide semiconductor film, etch the first oxide semiconductor film and the second oxide semiconductor film to form a first oxide semiconductor region and a second oxide semiconductor region, and provide the first oxide semiconductor region such that a part of the first oxide semiconductor region contacts the gate insulating layer and side surfaces of the source electrode layer and the drain electrode layer between the source electrode layer and the drain electrode layer, and increase the ratio of the oxygen gas flow rate during the formation of the second oxide semiconductor film compared to the ratio of the oxygen gas flow rate during the formation of the first oxide semiconductor film. This is a method for manufacturing a semiconductor device. Preferably. Preferably. Preferably. Preferably. Preferably. Preferably. Preferably. Preferably.

[0019] Incidentally, it is preferable that the first oxide semiconductor film and the second oxide semiconductor film contain at least one of indium, gallium, zinc or tin. Also, the first oxide semiconductor film and the second oxide semiconductor film may be formed collectively while increasing the flow rate of oxygen gas. Also , the ratio of the flow rate of oxygen gas during the formation of the first oxide semiconductor film is set to less than 70% by volume, and the ratio of the flow rate of oxygen gas during the formation of the second oxide semiconductor film is preferably set to 70% by volume or more.

[0020] Incidentally, the ordinal numbers attached as the first and second are used for convenience and do not indicate the process order or the stacking order. Also, they do not indicate unique names as matters for specifying the invention in this specification.

[0021] Incidentally, in this specification, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics, and all electro-optical devices, semiconductor circuits, and electronic devices are semiconductor devices.

Advantages of the Invention

[0022] One aspect of the present invention is in a thin film transistor using a first oxide semiconductor region as an active layer. Between the first oxide semiconductor region and the protective insulating layer of the thin film transistor, a second oxide semiconductor region having a lower conductivity than the first oxide semiconductor and functioning as a protective layer is formed. By doing so, the second oxide semiconductor region can prevent changes in the composition and deterioration of the film quality of the first oxide semiconductor region, and stabilize the electrical characteristics of the thin film transistor.

[0023] By using the thin film transistor in the pixel portion and the drive circuit portion of the display device, a display device with high electrical characteristics and high reliability can be provided.

Brief Description of the Drawings

[0024]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Figure 28

Figure 29

Figure 30

Embodiments for Carrying Out the Invention

[0025] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not to be construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are commonly used among different drawings for the same part or parts having the same function, and the repeated description thereof will be omitted. and without departing from the spirit and scope of the present invention. Thus, the present invention is not to be construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are commonly used among different drawings for the same part or parts having the same function, and the repeated description thereof will be omitted. In the following description of the configuration of the invention, the same reference numerals are commonly used among different drawings for the same part or parts having the same function, and the repeated description thereof is omitted. For the same part or parts having the same function, the same reference numerals are commonly used among different drawings, and the repeated description thereof is omitted. and the repeated description thereof will be omitted.

[0026] (Embodiment 1) In this embodiment, the structure of the thin film transistor will be described with reference to FIG. 1.

[0027] The thin-film transistor with a bottom gate structure according to this embodiment is shown in FIG. 1. FIG. 1(A) is a cross-sectional view and FIG. 1(B) is a plan view. FIG. 1(A) is a cross-section along line A1-A2 in FIG. 1(B).

[0028] In the thin-film transistor shown in FIG. 1, a gate electrode layer 101 is provided on a substrate 100, and a gate insulating layer 102 is provided on the gate electrode layer 101. A source electrode layer or drain electrode layers 105a and 105b are provided on the gate insulating layer 102. A first oxide semiconductor region 103 is provided on the gate insulating layer 102 and on the source electrode layer or drain electrode layers 105a and 105b. A second oxide semiconductor region 104 with a lower conductivity than that of the first oxide semiconductor region 103 is provided on the first oxide semiconductor region 103. Note that the first oxide semiconductor region 10 3 and the second oxide semiconductor region 104 may be formed together in the same oxide semiconductor layer or may be formed separately as different oxide semiconductor layers. Also, an intermediate region of an oxide semiconductor with a stepwise or continuous change in conductivity may exist between the first oxide semiconductor region 103 and the second oxide semiconductor region 104. Further, the oxide semiconductor intermediate region may be formed together with the first oxide semiconductor region 103 and the second oxide semiconductor region 104 in the same oxide semiconductor layer or may be formed separately as different oxide semiconductor layers. The gate electrode layer 101 is made of a metal material such as aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, or an alloy material mainly composed of these metal materials, or a nitride containing these metal materials as components, and is formed as a single layer or a laminate

[0029] ​​​​​​​​It is formed. It is desirable to form it with a low-resistance conductive material such as aluminum or copper, but since there are problems such as low heat resistance or easy corrosion, it is preferably used in combination with a heat-resistant conductive material. Examples of heat-resistant conductive materials include molybdenum, titanium, chromium, tantalum , tungsten, neodymium, scandium, etc.

[0030] For example, as the laminated structure of the gate electrode layer 101, a two-layer laminated structure in which a molybdenum layer is laminated on an aluminum layer, or a two-layer structure in which a molybdenum layer is laminated on a copper layer, or a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is laminated on a copper layer, or a two-layer structure in which a titanium nitride layer and a molybdenum layer are laminated is preferable. As a three-layer laminated structure, it is preferable to have a structure in which a tungsten layer or a tungsten nitride layer, an alloy layer of aluminum and silicon or an alloy layer of aluminum and titanium, and a titanium nitride layer or a titanium layer are laminated. For example, as the laminated structure of the gate electrode layer 101, a two-layer laminated structure in which a molybdenum layer is laminated on an aluminum layer, or a two-layer structure in which a molybdenum layer is laminated on a copper layer, or a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is laminated on a copper layer, or a two-layer structure in which a titanium nitride layer and a molybdenum layer are laminated is preferable. As a three-layer laminated structure, it is preferable to have a structure in which a tungsten layer or a tungsten nitride layer, an alloy layer of aluminum and silicon or an alloy layer of aluminum and titanium, and a titanium nitride layer or a titanium layer are laminated. For example, as the laminated structure of the gate electrode layer 101, a two-layer laminated structure in which a molybdenum layer is laminated on an aluminum layer, or a two-layer structure in which a molybdenum layer is laminated on a copper layer, or a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is laminated on a copper layer, or a two-layer structure in which a titanium nitride layer and a molybdenum layer are laminated is preferable. As a three-layer laminated structure, it is preferable to have a structure in which a tungsten layer or a tungsten nitride layer, an alloy layer of aluminum and silicon or an alloy layer of aluminum and titanium, and a titanium nitride layer or a titanium layer are laminated. For example, as the laminated structure of the gate electrode layer 101, a two-layer laminated structure in which a molybdenum layer is laminated on an aluminum layer, or a two-layer structure in which a molybdenum layer is laminated on a copper layer, or a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is laminated on a copper layer, or a two-layer structure in which a titanium nitride layer and a molybdenum layer are laminated is preferable. As a three-layer laminated structure, it is preferable to have a structure in which a tungsten layer or a tungsten nitride layer, an alloy layer of aluminum and silicon or an alloy layer of aluminum and titanium, and a titanium nitride layer or a titanium layer are laminated. For example, as the laminated structure of the gate electrode layer 101, a two-layer laminated structure in which a molybdenum layer is laminated on an aluminum layer, or a two-layer structure in which a molybdenum layer is laminated on a copper layer, or a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is laminated on a copper layer, or a two-layer structure in which a titanium nitride layer and a molybdenum layer are laminated is preferable. As a three-layer laminated structure, it is preferable to have a structure in which a tungsten layer or a tungsten nitride layer, an alloy layer of aluminum and silicon or an alloy layer of aluminum and titanium, and a titanium nitride layer or a titanium layer are laminated. For example, as the laminated structure of the gate electrode layer 101, a two-layer laminated structure in which a molybdenum layer is laminated on an aluminum layer, or a two-layer structure in which a molybdenum layer is laminated on a copper layer, or a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is laminated on a copper layer, or a two-layer structure in which a titanium nitride layer and a molybdenum layer are laminated is preferable. As a three-layer laminated structure, it is preferable to have a structure in which a tungsten layer or a tungsten nitride layer, an alloy layer of aluminum and silicon or an alloy layer of aluminum and titanium, and a titanium nitride layer or a titanium layer are laminated. For example, as the laminated structure of the gate electrode layer 101, a two-layer laminated structure in which a molybdenum layer is laminated on an aluminum layer, or a two-layer structure in which a molybdenum layer is laminated on a copper layer, or a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is laminated on a copper layer, or a two-layer structure in which a titanium nitride layer and a molybdenum layer are laminated is preferable. As a three-layer laminated structure, it is preferable to have a structure in which a tungsten layer or a tungsten nitride layer, an alloy layer of aluminum and silicon or an alloy layer of aluminum and titanium, and a titanium nitride layer or a titanium layer are laminated.

[0031] As the oxide semiconductor layer for forming the first oxide semiconductor region 103 and the second oxide semiconductor region 104, an oxide semiconductor having a structure represented by InMO3(ZnO) (m>0) is preferably used, and particularly preferably an In-Ga-Zn-O-based oxide semiconductor is used. Here, M represents one metal element or a plurality of metal elements selected from gallium (Ga), iron (Fe), nickel (Ni), manganese (Mn), and cobalt (Co). For example, in addition to the case where M is Ga, there may be cases where the above metal elements other than Ga, such as Ga and Ni or Ga and Fe, are included. Also, in the above oxide semiconductor, in addition to the metal elements contained as M m (m>0) is preferably used, and particularly preferably an In-Ga-Zn-O-based oxide semiconductor is used. Here, M represents one metal element or a plurality of metal elements selected from gallium (Ga), iron (Fe), nickel (Ni), manganese (Mn), and cobalt (Co). For example, in addition to the case where M is Ga, there may be cases where the above metal elements other than Ga, such as Ga and Ni or Ga and Fe, are included. Also, in the above oxide semiconductor, in addition to the metal elements contained as M (m>0) is preferably used, and particularly preferably an In-Ga-Zn-O-based oxide semiconductor is used. Here, M represents one metal element or a plurality of metal elements selected from gallium (Ga), iron (Fe), nickel (Ni), manganese (Mn), and cobalt (Co). For example, in addition to the case where M is Ga, there may be cases where the above metal elements other than Ga, such as Ga and Ni or Ga and Fe, are included. Also, in the above oxide semiconductor, in addition to the metal elements contained as M (m>0) is preferably used, and particularly preferably an In-Ga-Zn-O-based oxide semiconductor is used. Here, M represents one metal element or a plurality of metal elements selected from gallium (Ga), iron (Fe), nickel (Ni), manganese (Mn), and cobalt (Co). For example, in addition to the case where M is Ga, there may be cases where the above metal elements other than Ga, such as Ga and Ni or Ga and Fe, are included. Also, in the above oxide semiconductor, in addition to the metal elements contained as M (m>0) is preferably used, and particularly preferably an In-Ga-Zn-O-based oxide semiconductor is used. Here, M represents one metal element or a plurality of metal elements selected from gallium (Ga), iron (Fe), nickel (Ni), manganese (Mn), and cobalt (Co). For example, in addition to the case where M is Ga, there may be cases where the above metal elements other than Ga, such as Ga and Ni or Ga and Fe, are included. Also, in the above oxide semiconductor, in addition to the metal elements contained as M (m>0) is preferably used, and particularly preferably an In-Ga-Zn-O-based oxide semiconductor is used. Here, M represents one metal element or a plurality of metal elements selected from gallium (Ga), iron (Fe), nickel (Ni), manganese (Mn), and cobalt (Co). For example, in addition to the case where M is Ga, there may be cases where the above metal elements other than Ga, such as Ga and Ni or Ga and Fe, are included. Also, in the above oxide semiconductor, in addition to the metal elements contained as M (m>0) is preferably used, and particularly preferably an In-Ga-Zn-O-based oxide semiconductor is used. Here, M represents one metal element or a plurality of metal elements selected from gallium (Ga), iron (Fe), nickel (Ni), manganese (Mn), and cobalt (Co). For example, in addition to the case where M is Ga, there may be cases where the above metal elements other than Ga, such as Ga and Ni or Ga and Fe, are included. Also, in the above oxide semiconductor, in addition to the metal elements contained as M Some contain impurity elements such as Fe, Ni, other transition metal elements, or oxides of the transition metals. In this specification, among the oxide semiconductors having a structure represented by InMO3(ZnO) (m>0), an oxide semiconductor having a structure containing at least Ga as M is called an n-Ga-Zn-O-based oxide semiconductor, and the thin film is also called an In-Ga-Zn-O-based non-single crystal film. Some contain impurity elements such as Fe, Ni, other transition metal elements, or oxides of the transition metals. In this specification, among the oxide semiconductors having a structure represented by InMO3(ZnO) (m>0), an oxide semiconductor having a structure containing at least Ga as M is called an n-Ga-Zn-O-based oxide semiconductor, and the thin film is also called an In-Ga-Zn-O-based non-single crystal film. m represented by Among the oxide semiconductors having a structure represented by InMO3(ZnO) (m>0), an oxide semiconductor having a structure containing at least Ga as M is called an n-Ga-Zn-O-based oxide semiconductor, and the thin film is also called an In-Ga-Zn-O-based non-single crystal film.

[0032] The crystal structure of the In-Ga-Zn-O-based non-single crystal film is observed as an amorphous structure by XRD (X-ray diffraction) analysis. Note that the In-Ga-Zn-O-based non-single crystal film is heat-treated at 200°C to 500°C, typically 300°C to 400°C for 10 minutes to 100 minutes after film formation by sputtering. The crystal structure of the In-Ga-Zn-O-based non-single crystal film is observed as an amorphous structure by XRD (X-ray diffraction) analysis. Note that the In-Ga-Zn-O-based non-single crystal film is heat-treated at 200°C to 500°C, typically 300°C to 400°C for 10 minutes to 100 minutes after film formation by sputtering. The crystal structure of the In-Ga-Zn-O-based non-single crystal film is observed as an amorphous structure by XRD (X-ray diffraction) analysis. Note that the In-Ga-Zn-O-based non-single crystal film is heat-treated at 200°C to 500°C, typically 300°C to 400°C for 10 minutes to 100 minutes after film formation by sputtering.

[0033] By using the In-Ga-Zn-O-based non-single crystal film as the active layer of a thin film transistor, a thin film transistor having electrical characteristics with an on-off ratio of 10 or more and a mobility of 10 or more at a gate voltage of ±20V can be fabricated. By using the In-Ga-Zn-O-based non-single crystal film as the active layer of a thin film transistor, a thin film transistor having electrical characteristics with an on-off ratio of 10 or more and a mobility of 10 or more at a gate voltage of ±20V can be fabricated. 9 or more and a mobility of 10 or more can be fabricated.

[0034] However, the oxide semiconductor layers forming the first oxide semiconductor region 103 and the second oxide semiconductor region 104 are not limited to the oxide semiconductor layers having a structure represented by InMO3(ZnO) (m>0), and may include at least one of indium, gallium, zinc, or tin. For example, an oxide semiconductor layer composed of zinc oxide (ZnO), tin oxide (SnO), indium zinc oxide (IZO), indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), zinc oxide added with gallium (GZO), etc. may be used. However, the oxide semiconductor layers forming the first oxide semiconductor region 103 and the second oxide semiconductor region 104 are not limited to the oxide semiconductor layers having a structure represented by InMO3(ZnO) (m>0), and may include at least one of indium, gallium, zinc, or tin. For example, an oxide semiconductor layer composed of zinc oxide (ZnO), tin oxide (SnO), indium zinc oxide (IZO), indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), zinc oxide added with gallium (GZO), etc. may be used. m represented by (m>0) However, the oxide semiconductor layers forming the first oxide semiconductor region 103 and the second oxide semiconductor region 104 are not limited to the oxide semiconductor layers having a structure represented by InMO3(ZnO) (m>0), and may include at least one of indium, gallium, zinc, or tin. For example, an oxide semiconductor layer composed of zinc oxide (ZnO), tin oxide (SnO), indium zinc oxide (IZO), indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), zinc oxide added with gallium (GZO), etc. may be used. However, the oxide semiconductor layers forming the first oxide semiconductor region 103 and the second oxide semiconductor region 104 are not limited to the oxide semiconductor layers having a structure represented by InMO3(ZnO) (m>0), and may include at least one of indium, gallium, zinc, or tin. For example, an oxide semiconductor layer composed of zinc oxide (ZnO), tin oxide (SnO), indium zinc oxide (IZO), indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), zinc oxide added with gallium (GZO), etc. may be used. For example, an oxide semiconductor layer composed of zinc oxide (ZnO), tin oxide (SnO), indium zinc oxide (IZO), indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), zinc oxide added with gallium (GZO), etc. may be used. For example, an oxide semiconductor layer composed of zinc oxide (ZnO), tin oxide (SnO), indium zinc oxide (IZO), indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), zinc oxide added with gallium (GZO), etc. may be used.

[0035] Also, a part of the first oxide semiconductor region 103 is between the source electrode layer or drain electrode layer 105 a, 105b, and the first oxide semiconductor region 103 is provided so as to be in contact with the side surfaces of the gate insulating layer 102 and the source electrode layer or drain electrode layer 105a , 105b. The thickness of the first oxide semiconductor region 103 is set to be 10 nm to 300 nm, preferably 20 n m to 100 nm.

[0036] The conductivity of the first oxide semiconductor region 103 is preferably 1.0×10 -8 S / cm or more It is preferable. Also, the conductivity of the first oxide semiconductor region 103 is preferably less than 1.0×10 -3 S / cm The carrier concentration range of the first oxide semiconductor region 103 is 1×10 1 7 / cm 3 less (more preferably 1×10 11 / cm 3 or more) is preferable. If the carrier concentration range of the first oxide semiconductor region 103 exceeds the above range, the thin film transistor may become non-maryon.

[0037] Also, the sodium concentration in the first oxide semiconductor region 103 is 5×10 19 / cm 3 or less and preferably 1×10 18 / cm 3 or less.

[0038] The second oxide semiconductor region 104 has a lower conductivity than the first oxide semiconductor region 103, and the conductivity of the second oxide semiconductor region 104 is less than 1.0×10 S / cm -8 This is preferable. Further, the second oxide semiconductor region 104 preferably has a smaller oxygen vacancy defect density than that of the first oxide semiconductor region 10 3. This is because oxygen vacancy defects in the oxide semiconductor contribute to the conductivity of the oxide semiconductor. Also, the thickness of the second oxide semiconductor region 104 is preferably 5 nm or more and 1000 nm or less, more preferably 10 nm or more and 100 nm or less. By increasing the ratio of the flow rate of oxygen gas to the total film-forming gas in the sputter film formation of the second oxide semiconductor region 104 compared to the ratio of the flow rate of oxygen gas to the total film-forming gas in the sputter film formation of the first oxide semiconductor region 103, the oxygen vacancy defect density of the second oxide semiconductor region 104 can be reduced compared to that of the first oxide semiconductor region 103, and the conductivity can be decreased. The film-forming conditions for the second oxide semiconductor region 104 preferably have the ratio of the flow rate of oxygen gas to the total film-forming gas at 70% by volume or more. Also, the film-forming conditions for the first oxide semiconductor region 103 preferably have the ratio of oxygen gas to the total film-forming gas at less than 70% by volume. 5nm or more and 1000nm or less is preferable, and 10nm or more and 100nm or less is more preferable.

[0039] In the sputter film formation of the first oxide semiconductor region 103, the ratio of the flow rate of oxygen gas to the total film-forming gas is smaller than that in the sputter film formation of the second oxide semiconductor region 104. The first oxide semiconductor region 103 and the second oxide semiconductor region 104 can be formed continuously, thereby improving the efficiency of manufacturing the display device and enhancing productivity. Also, by continuously forming the first oxide semiconductor region 103 and the second oxide semiconductor region 104, patterning of the first oxide semiconductor region 103 can be performed without exposing the upper surface of the first oxide semiconductor region 103 to the atmosphere. Moreover, by continuously forming the first oxide semiconductor region 103 and the second oxide semiconductor region 104 with the flow rate of oxygen gas... In the sputter film formation of the second oxide semiconductor region 104, the ratio of the flow rate of oxygen gas to the total film-forming gas is preferably 70% by volume or more. In the sputter film formation of the first oxide semiconductor region 103, the ratio of oxygen gas to the total film-forming gas is preferably less than 70% by volume. This is preferable.

[0040] The first oxide semiconductor region 103 and the second oxide semiconductor region 104 can be formed continuously. Thus, the efficiency of manufacturing the display device can be improved, and productivity can be enhanced. Also, by continuously forming the first oxide semiconductor region 103 and the second oxide semiconductor region 104, patterning of the first oxide semiconductor region 103 can be performed without exposing the upper surface of the first oxide semiconductor region 103 to the atmosphere.

[0041] ​By increasing and forming a film in a batch, the conductivity of the first oxide semiconductor region 103 and the second oxide semiconductor region 104 can also be continuously changed.

[0042] The first oxide semiconductor region 103 functions as an active layer of a thin film transistor. On the other hand, the second oxide semiconductor region 104 having a lower conductivity than the first oxide semiconductor region 103 prevents exposure of the first oxide semiconductor region 103 to the atmosphere and contact with a film containing impurities that alter the composition and film quality of the oxide semiconductor, and functions as a protective layer. Therefore, the first oxide semiconductor region 103 having a channel formation region and determining the electrical characteristics of the thin film transistor is in contact with the second oxide semiconductor region having similar composition and film quality, so changes in composition, film quality, and interface due to impurities can be prevented. Further, the second oxide semiconductor region 104 functioning as a protective layer is in contact with a film containing impurities that alter the composition and film quality of the oxide semiconductor, but since its conductivity is lower than that of the first oxide semiconductor region 103, it

[0043] does not affect the electrical characteristics of the thin film transistor. From the above, in a thin film transistor using the first oxide semiconductor region as an active layer, by forming a second oxide semiconductor region having a lower conductivity than the first oxide semiconductor region between the first oxide semiconductor region and the protective insulating layer of the thin film transistor and functioning as a protective layer, changes in the composition of the first oxide semiconductor

[0044] region and deterioration of the film quality can be prevented, and the electrical characteristics of the thin film b. It has a three-layer structure composed of the second conductive films 113a and 113b and the third conductive films 114a and 114b. As the materials for the first conductive films 112a and 112b to the third conductive films 114a and 114b, metal materials such as aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, etc., or alloy materials mainly composed of these metal materials, or nitrides containing these metal materials as components can be used. It is desirable to form them with low-resistance conductive materials such as aluminum and copper, but since they have problems such as low heat resistance or being prone to corrosion, it is preferable to use them in combination with heat-resistant conductive materials. As the heat-resistant conductive materials, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, etc. are used.

[0045] For example, it is preferable to use titanium, which is a heat-resistant conductive material, for the first conductive films 112a and 112b and the third conductive films 114a and 114b, and an aluminum alloy containing neodymium, which has low resistance, for the second conductive films 113a and 113b. By adopting such a configuration, while taking advantage of the low resistance of aluminum, the generation of hillocks can be reduced. In this embodiment, the source electrode layer or drain electrode layer 105a and 105b has a three-layer structure composed of the first conductive films 112a and 112b, the second conductive films 113a and 113b, and the third conductive films 114a and 114b, but it is not limited thereto, and

[0046] it may have a single-layer structure, a two-layer structure, or a structure with four or more layers. In a thin film transistor, between the first oxide semiconductor region and the protective insulating layer of the thin film transistor, a second oxide semiconductor region having a lower conductivity than the first oxide semiconductor region and functioning as a protective layer is formed, thereby preventing changes in the composition and deterioration of the film quality of the first oxide semiconductor region and stabilizing the electrical characteristics of the thin film transistor. Furthermore, the configuration shown in this embodiment can be used by appropriately combining the configurations shown in other embodiments. (Embodiment 2) In this embodiment, the manufacturing process of the display device including the thin film transistor shown in Embodiment 1 will be described with reference to FIGS. 2 to 9. FIGS. 2 and 3 are cross-sectional views, FIGS. 4 to 7 are plan views, and lines A1 - A2 and B1 - B2 in FIGS. 4 to 7 correspond to lines A1 - A2 and B1 - B2 shown in the cross-sectional views of FIGS. 2 and 3.

[0047] First, a substrate 100 is prepared. The substrate 100 can be an alkali-free glass substrate, a ceramic substrate, such as barium borosilicate glass, aluminoborosilicate glass, or aluminosilicate glass, which is manufactured by a fusion method or a float method, or a plastic substrate having heat resistance capable of withstanding the processing temperature of this manufacturing process. Alternatively, a substrate having an insulating film provided on the surface of a metal substrate such as a stainless alloy can be applied. The size of the substrate 100 can be 320 mm × 400 mm, 370 mm × 470 mm, 550 mm × 650 mm, 600 mm × 720 mm, 680 mm × 880 mm, 730 mm × 920 mm, 1000 mm × 1200 mm, 1100 mm × 1250 mm, 1150 mm × 1300 mm, 1500 mm × 1850 mm, etc.

[0048] (Embodiment 2) In this embodiment, the manufacturing process of the display device including the thin film transistor shown in Embodiment 1 will be described with reference to FIGS. 2 to 9. FIGS. 2 and 3 are cross-sectional views, FIGS. 4 to 7 are plan views, and lines A1 - A2 and B1 - B2 in FIGS. 4 to 7 correspond to lines A1 - A2 and B1 - B2 shown in the cross-sectional views of FIGS. 2 and 3. First, a substrate 100 is prepared. The substrate 100 can be an alkali-free glass substrate, a ceramic substrate, such as barium borosilicate glass, aluminoborosilicate glass, or aluminosilicate glass, which is manufactured by a fusion method or a float method, or a plastic substrate having heat resistance capable of withstanding the processing temperature of this manufacturing process. Alternatively, a substrate having an insulating film provided on the surface of a metal substrate such as a stainless alloy can be applied. The size of the substrate 100 can be 320 mm × 400 mm, 370 mm × 470 mm, 550 mm × 650 mm, 600 mm × 720 mm, 680 mm × 880 mm, 730 mm × 920 mm, 1000 mm × 1200 mm, 1100 mm × 1250 mm, 1150 mm × 1300 mm, 1500 mm × 1850 mm, etc.

[0049] First, a substrate 100 is prepared. The substrate 100 can be an alkali-free glass substrate, a ceramic substrate, such as barium borosilicate glass, aluminoborosilicate glass, or aluminosilicate glass, which is manufactured by a fusion method or a float method, or a plastic substrate having heat resistance capable of withstanding the processing temperature of this manufacturing process. Alternatively, a substrate having an insulating film provided on the surface of a metal substrate such as a stainless alloy can be applied. The size of the substrate 100 can be 320 mm × 400 mm, 370 mm × 470 mm, 550 mm × 650 mm, 600 mm × 720 mm, 680 mm × 880 mm, 730 mm × 920 mm, 1000 mm × 1200 mm, 1100 mm × 1250 mm, 1150 mm × 1300 mm, 1500 mm × 1850 mm, etc. ​​​​​​​​​​800 mm, 1900 mm × 2200 mm, 2160 mm × 2460 mm, 2400 mm × 2800 mm, or 2850 mm × 3050 mm, etc. can be used.

[0050] Also, an insulating film may be formed as an underlayer film on the substrate 100. As the underlayer film, using a CVD method, a sputtering method, etc., a single layer or a laminate of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film may be formed. When using a substrate containing mobile ions such as a glass substrate as the substrate 100, by using a film containing nitrogen such as a silicon nitride film or a silicon oxynitride film as the underlayer film, it is possible to prevent mobile ions from penetrating into the oxide semiconductor layer.

[0051] Next, a conductive film for forming a gate wiring including a gate electrode layer 101, a capacitor wiring 108, and a first terminal 121 is formed over the entire surface of the substrate 100 by a sputtering method or a vacuum evaporation method. Next, a first photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form wirings and electrodes (a gate wiring including a gate electrode layer 101, a capacitor wiring 108, and a first terminal 121). At this time, in order to prevent disconnection, it is preferable to etch so that a tapered shape is formed at least at the end of the gate electrode layer 101. A cross-sectional view at this stage is shown in Fig. 2(A). Note that the plan view at this stage corresponds to Fig. 4.

[0052] The gate wiring including the gate electrode layer 101, the capacitor wiring 108, and the first terminal 121 of the terminal portion can be formed as a single layer or a laminate using the conductive material shown in Embodiment 1.

[0053] Next, a gate insulating layer 102 is formed over the entire surface of the gate electrode layer 101. The gate insulating layer 1 02 is formed to have a film thickness of 50 to 250 nm using a CVD method, a sputtering method, or the like.

[0054] For example, a silicon oxide film is used as the gate insulating layer 102 by a CVD method or a sputtering method, and is formed to have a thickness of 100 nm. Of course, the gate insulating layer 102 is not limited to such a silicon oxide film, but other insulating films such as a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a tantalum oxide film, etc. may be used, and a single layer or a laminated structure made of these materials may be formed.

[0055] Also, as the gate insulating layer 102, it is also possible to form a silicon oxide layer by a CVD method using an organic silane gas. As the organic silane gas, tetraethyl orthosilicate (TEOS: chemical formula Si(OC2H5)4), tetramethylsilane (TMS: chemical formula Si(CH3)4), tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (Si H(OC2H5)3), tris(dimethylamino)silane (SiH(N(CH3)2)3), etc. silicon-containing compounds can be used.

[0056] Also, as the gate insulating layer 102, a compound containing at least two of oxides, nitrides, oxynitrides, or nitride oxides of aluminum, yttrium, or hafnium, or a compound thereof can also be used.

[0057] Note that in this specification, oxynitride means that, in its composition, the number of oxygen atoms is more than that of nitrogen atoms. ​​​​​​Nitrogen oxide refers to a substance that has more nitrogen atoms than oxygen atoms. For example, a silicon oxynitride film has a composition that contains a large number of nitrogen atoms. The number of oxygen atoms is greater than that of the electrons, and the Rutherford backscattering method (RBS) Backscattering Spectrometry and Hydrogen Forward Scattering Spectrometry (H When measured using FS (Hydrogen Forward Scattering) In this case, the concentration range is 50 to 70 atomic % for oxygen, 0.5 to 15 atomic % for nitrogen, and 0.5 to 15 atomic % for silicon. Nitriding means that the content of niobium is in the range of 25 to 35 atomic percent, and hydrogen is in the range of 0.1 to 10 atomic percent. Silicon oxide film is a film whose composition has more nitrogen atoms than oxygen atoms, and has RBS and H When measured using FS, the concentration ranges were 5 to 30 atomic percent for oxygen and 20 to 55 atomic percent for nitrogen. atomic %, silicon 25-35 atomic %, and hydrogen 10-30 atomic %. However, the total number of atoms constituting silicon oxynitride or silicon nitride oxide is 100. When expressed as %, the content ratios of nitrogen, oxygen, silicon and hydrogen are within the above ranges. It shall be so.

[0058] Next, a second photolithography process is performed, and a resist mask is formed on the gate insulating layer 102. Then, unnecessary portions are removed by etching to form wiring made of the same material as the gate electrode layer 101. A contact hole reaching the gate electrode layer is formed in the gate insulating layer 102. The terminal is provided to directly connect to the conductive film to be formed later. For example, the first terminal 1 of the terminal portion When a terminal electrically connected to 21 is to be formed, a contact hole is formed.

[0059] Next, a first conductive film 112, a second conductive film 11 3, and a third conductive film 114 made of a metal material are formed on the gate insulating layer 102 by sputtering or vacuum evaporation. A cross-sectional view at this stage is shown in Fig. 2(B).

[0060] As materials for the first conductive film 112, the second conductive film 113, and the third conductive film 114, they can be formed in a single layer or laminated using the conductive materials shown in Embodiment Form 1. In this embodiment For the first conductive film 112 and the third conductive film 114, titanium, which is a heat-resistant conductive material, is used And an aluminum alloy containing neodymium is used as the second conductive film 113. By adopting such a Configuration, while taking advantage of the low resistivity of aluminum, the generation of hillocks can be reduced It is possible to do so.

[0061] Next, a third photolithography process is performed to form a resist mask 131, and unnecessary portions are removed by etching To form the source electrode layer or drain electrode layer 105a, 105b, and The connection electrode 120. As the etching method at this time, wet etching or Dry etching is used. For example, when titanium is used for the first conductive film 112 and the third conductive film 114, and an aluminum alloy containing neodymium is used for the second conductive film 113, hydrogen peroxide Water, heated hydrochloric acid, or an aqueous nitric acid solution containing ammonium fluoride can be used as the etchant for Wet etching. For example, using KSMF-240 (manufactured by Kanto Chemical Co., Inc.) The first conductive film 112 to the third conductive film 114 can be etched collectively.

[0062] Also, the etching of the first conductive film 112 to the third conductive film 114 is performed with hydrogen peroxide water, heated hydrochloric acid Etching can be performed at once using an aqueous nitric acid solution containing ammonium fluoride as an etchant. Therefore, the ends of the conductive films of the source electrode layer or drain electrode layer 105a, 105b can be aligned and made into a continuous structure. Further, by etching the ends of the source electrode layer or drain electrode layer 105a, 105b into a tapered shape, the coverage of the first oxide semiconductor region 103 can be improved, and the step break of the first oxide semiconductor region 103 due to the step shape can be prevented. A cross-sectional view at this stage is shown in Fig. 2(C). Note that the plan view at this stage corresponds to Fig. 5. Moreover, in this third photolithography process, a second terminal 122 made of the same material as the source electrode layer or drain electrode layer 105a, 105b is left at the terminal portion. Note that the second terminal 122 is electrically connected to the source wiring (source wiring including the source electrode layer or drain electrode layer 105a, 105b). Also, in the terminal portion, the connection electrode 120 is directly connected to the first terminal 121 of the terminal portion through a contact hole formed in the gate insulating layer 102. Next, surface treatment is performed on the gate insulating layer 102, the source electrode layer or drain electrode layer 105a, 105b. As the surface treatment, plasma treatment using an inert gas or a reactive gas can be performed. After removing the resist mask 131, argon gas is introduced into the chamber in which the substrate 100 is installed to generate plasma and perform reverse sputtering to remove impurities adhering to the surface of the gate insulating layer 102. Also, by performing reverse sputtering, the surface of the gate insulating layer 102 is made smooth.

[0063] In addition, in this third photolithography process, a second terminal 122 made of the same material as the source electrode layer or drain electrode layer 105a, 105b is left at the terminal portion. Note that the second terminal 122 is electrically connected to the source wiring (source wiring including the source electrode layer or drain electrode layer 105a, 105b). Moreover, in this third photolithography process, a second terminal 122 made of the same material as the source electrode layer or drain electrode layer 105a, 105b is left at the terminal portion. Note that the second terminal 122 is electrically connected to the source wiring (source wiring including the source electrode layer or drain electrode layer 105a, 105b). 122 is electrically connected to the source wiring (source wiring including the source electrode layer or drain electrode layer 105a, 105b). is electrically connected to the source wiring (source wiring including the source electrode layer or drain electrode layer 105a, 105b).

[0064] Also, in the terminal portion, the connection electrode 120 is directly connected to the first terminal 121 of the terminal portion through a contact hole formed in the gate insulating layer 102. is directly connected to the first terminal 121 of the terminal portion through a contact hole formed in the gate insulating layer 102.

[0065] Next, surface treatment is performed on the gate insulating layer 102, the source electrode layer or drain electrode layer 105a, 105b. As the surface treatment, plasma treatment using an inert gas or a reactive gas can be performed. can be performed.

[0066] After removing the resist mask 131, argon gas is introduced into the chamber in which the substrate 100 is installed to generate plasma and perform reverse sputtering to remove impurities adhering to the surface of the gate insulating layer 102. is introduced into the chamber in which the substrate 100 is installed to generate plasma and perform reverse sputtering to remove impurities adhering to the surface of the gate insulating layer 102. Moreover, by performing reverse sputtering, the surface of the gate insulating layer 102 The flatness of the surface can also be improved. A cross-sectional view at this stage is shown in FIG. 2(D). Reverse sputtering is a method of forming plasma on a substrate by applying a voltage to the substrate side in an argon atmosphere without applying a voltage to the target side, and modifying the surface. Note that nitrogen, helium, etc. may be used instead of the argon atmosphere. Also, it may be performed in an atmosphere in which oxygen, water, N2O, etc. are added to the argon atmosphere. Also, it may be performed in an atmosphere in which Cl2, CF4, etc. are added to the argon atmosphere. After the reverse sputtering process, the first oxide semiconductor film is formed without exposing it to the atmosphere, thereby preventing dust and moisture from adhering to the interface between the gate insulating layer 102 and the first oxide semiconductor region 10 3. Next, an oxide semiconductor film for forming the first oxide semiconductor region 103 and the second oxide semiconductor region 104 is formed. In the present embodiment, the first oxide semiconductor region 103 and the second oxide semiconductor region 104 are formed of different oxide semiconductor layers. First, a first oxide semiconductor film for forming the first oxide semiconductor region 103 is formed on the gate insulating layer 102 by sputtering in an atmosphere of a rare gas such as argon and oxygen gas. As the first oxide semiconductor film, the oxide semiconductor shown in Embodiment 1 can be used, and an In-Ga-Zn -O-based oxide semiconductor is preferably used. Specific film formation condition examples of the first oxide semiconductor film include using an oxide semiconductor target (In2 O3:Ga2O3:ZnO = 1:1:1) containing In, Ga, and Zn with a diameter of 8 inches, a distance between the substrate and the target of 1

[0067] 70 mm, a pressure of 0.4 Pa, a DC power supply of 0.5 kW, and a film formation gas Ar:O2 = 50: Next, an oxide semiconductor film for forming the first oxide semiconductor region 103 and the second oxide semiconductor region 104 is formed. In the present embodiment, the first oxide semiconductor region 103 and the second oxide semiconductor region 104 are formed of different oxide semiconductor layers. First, a first oxide semiconductor film for forming the first oxide semiconductor region 103 is formed on the gate insulating layer 102 by sputtering in an atmosphere of a rare gas such as argon and oxygen gas. As the first oxide semiconductor film, the oxide semiconductor shown in Embodiment 1 can be used, and an In-Ga-Zn -O-based oxide semiconductor is preferably used. Specific film formation condition examples of the first oxide semiconductor film include using an oxide semiconductor target (In2 O3:Ga2O3:ZnO = 1:1:1) containing In, Ga, and Zn with a diameter of 8 inches, a distance between the substrate and the target of 1 70 mm, a pressure of 0.4 Pa, a DC power supply of 0.5 kW, and a film formation gas Ar:O2 = 50: 70 mm, a pressure of 0.4 Pa, a DC power supply of 0.5 kW, and a film formation gas Ar:O2 = 50: O3:Ga2O3:ZnO = 1:1:1) to form a film with a distance of 1 70 mm between the substrate and the target, a pressure of 0.4 Pa, a DC power supply of 0.5 kW, and a film formation gas Ar:O2 = 50: Perform sputtering film formation at a film formation temperature of room temperature with a flow rate of 5 (sccm). As the target, pellet-shaped Ga2O3 and ZnO may be arranged on an 8-inch diameter disk containing In2O3. When using a pulsed direct current (DC) power supply, dust can be reduced, and it is preferable because the film thickness distribution becomes uniform. The film thickness of the first oxide semiconductor film is set to 10 nm to 300 nm, preferably 20 nm to 100 nm.

[0068] Next, without exposing to the atmosphere, a second oxide semiconductor film for forming the second oxide semiconductor region 104 is formed by sputtering in an atmosphere of a noble gas such as argon and oxygen gas. As the second oxide semiconductor film, the oxide semiconductor shown in Embodiment 1 can be used, and it is preferable to use an In-Ga-Zn-O-based oxide semiconductor. By forming the second oxide semiconductor film without exposing to the atmosphere after forming the first oxide semiconductor film, dust and moisture are prevented from adsorbing at the interface between the first oxide semiconductor region 103 and the second oxide semiconductor region 104, and it is possible to prevent the film quality and composition of the first oxide semiconductor region 103 from changing. As specific film formation condition examples of the second oxide semiconductor film, an oxide semiconductor target (In2O3:Ga2O3:ZnO = 1:1:1) containing In, Ga, and Zn with a diameter of 8 inches is used to perform sputtering film formation with a distance between the substrate and the target of 170 mm, a pressure of 0.4 Pa, a direct current (DC) power supply of 0. 5 kW, a film formation gas of Ar:O2 = 50:1 (sccm), and a film formation temperature of room temperature. As the target, pellet-shaped Ga2O3 and ZnO may be arranged on an 8-inch diameter disk containing In2O3. When using a pulsed direct current (DC) power supply, dust can be reduced, and it is preferable because the film thickness distribution becomes uniform. pellet-shaped Ga2O3 and ZnO may be arranged on an 8-inch diameter disk containing In2O3. The distance between the substrate and the target is 170 mm, the pressure is 0.4 Pa, the direct current (DC) power supply is 0. 5 kW, the film formation gas is Ar:O2 = 50:1 (sccm), and sputtering film formation is performed at a film formation temperature of room temperature. As the target, pellet-shaped Ga2O3 and ZnO may be arranged on an 8-inch diameter disk containing In2O3. When using a pulsed direct current (DC) power supply, The use of the second oxide semiconductor is preferable because it reduces dust and makes the film thickness distribution uniform. The thickness of the body membrane is 5 nm to 1000 nm, and preferably 10 nm to 100 nm.

[0069] Here, the ratio of the oxygen gas flow rate to the total deposition gas flow rate in the sputter deposition of the first oxide semiconductor film is The ratio of the amount of the acid to the total deposition gas in the sputtering deposition of the second oxide semiconductor film is more important than the ratio of the amount of the acid to the total deposition gas in the sputtering deposition of the second oxide semiconductor film. The ratio of the flow rate of the oxygen gas to the flow rate of the oxygen gas is increased. As a result, the second oxide semiconductor film is thicker than the first oxide semiconductor film. The conductivity of the semiconductor film can be reduced. Preferably, the ratio of the oxygen gas flow rate to the total deposition gas is 70% by volume or more. The deposition conditions for the oxide semiconductor film are as follows: the ratio of oxygen gas to the total deposition gas is less than 70% by volume. It is preferable to set the above.

[0070] In this embodiment, the first oxide semiconductor region 103 and the second oxide semiconductor region 1 The oxide semiconductor film forming the insulating film 04 was formed as a different oxide semiconductor film. The first oxide semiconductor forming the first oxide semiconductor region 103 is not limited to the above. The oxide semiconductor film and the second oxide semiconductor film that forms the second oxide semiconductor region 104 are heated in a flow of oxygen gas. By forming a film in one go while continuously increasing the amount of the material, a film with a continuously changing conductivity was obtained. Alternatively, the flow rate of oxygen gas may be increased stepwise to form a single oxide semiconductor film. By forming an oxide semiconductor film multiple times while performing the above-mentioned process, a first oxide semiconductor region 103 The first oxide semiconductor film forming the second oxide semiconductor region 104 and the second oxide semiconductor film forming the second oxide semiconductor region 105 are It is also possible to form multiple oxide semiconductor films with stepwise changes in conductivity between the oxide semiconductor films. Cut.

[0071] In addition, the first oxide semiconductor film and the second oxide semiconductor film can be formed in succession. Therefore, the efficiency of manufacturing the display device can be improved, and the productivity can be increased.

[0072] The first oxide semiconductor film or the second oxide semiconductor film is formed on a substrate that has been subjected to reverse sputtering. The same chamber as that used for the previous sputtering may be used, or a different chamber may be used. The film may be formed in a chamber.

[0073] There are two types of sputtering: RF sputtering, which uses a high-frequency power source for the sputtering power supply, and DC sputtering. There is also the pulsed DC sputtering method, which applies a pulsed bias. The DC sputtering method is mainly used for depositing insulating films, while the DC sputtering method is mainly used for depositing metal films. It is used in.

[0074] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of films in the same chamber. It is also possible to form a film by discharging two or more materials at the same time.

[0075] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There is a sputtering apparatus that uses this method.

[0076] In addition, in a film formation method using a sputtering method, a target material and a sputtering gas component are mixed during film formation. Reactive sputtering is a method of forming thin films of compounds by chemically reacting them with each other, and There is also a bias sputtering method in which a voltage is also applied to the substrate.

[0077] Next, a fourth photolithography process is performed to form a resist mask, and the first oxide semiconductor film and the second oxide semiconductor film are etched. Here, by forming the resist mask on the second oxide semiconductor film, it is possible to prevent the resist mask from directly contacting the first oxide semiconductor film, and it is possible to prevent impurities from entering the first oxide semiconductor film from the resist mask. Also, when using O2 ashing or a resist stripper for removing the resist, by forming the second oxide semiconductor film on the first oxide semiconductor film, contamination of the first oxide semiconductor film can be prevented. By etching, unnecessary portions are removed to make the first oxide semiconductor film and the second oxide semiconductor film into island shapes, and a first oxide semiconductor region 103 made of the first oxide semiconductor film and a second oxide semiconductor region 104 made of the second oxide semiconductor film are formed. As the etching, wet etching using an organic acid such as citric acid or oxalic acid as an etchant can be performed. For example, when an In-Ga-Zn-O-based amorphous film is used as the first oxide semiconductor film and the second oxide semiconductor film, it is preferable to use ITO07N (manufactured by Kanto Chemical Co., Inc.). Note that the etching here is not limited to wet etching, and dry etching may be used. As the etching apparatus for dry etching, an etching apparatus using a reactive ion etching method (RIE method), an ECR (Electron Cyclotron Resonance), or an ICP (Inductively Coupled Plasma) can be used.

[0078]

[0079] A dry etching apparatus using a high-density plasma source such as asma can be used. In addition, as a dry etching apparatus, a uniform discharge is easily obtained over a wider area compared to an ICP etching apparatus. As a dry etching apparatus, there is an ECCP (Enhanced Capacitively Coupled Plasma) mode etching apparatus in which the upper electrode is grounded, a 13.56 MHz high-frequency power source is connected to the lower electrode, and a 3.2 MHz low-frequency power source is further connected to the lower electrode. With this ECCP mode etching apparatus, for example, even when using a substrate with a size exceeding 3 m of the 10th generation, it can be accommodated. In the above process, a thin film transistor 170 having the first oxide semiconductor region 103 as a channel formation region can be manufactured. The cross-sectional view at this stage is shown in FIG. 3(A). Note that the plan view at this stage corresponds to FIG. 6.

[0080] In the thin film transistor 170, the first oxide semiconductor region 103 functions as an active layer. On the other hand, the second oxide semiconductor region 104 having a lower conductivity than the first oxide semiconductor region 103 functions as a protective layer that prevents the exposure of the first oxide semiconductor region 103 to the atmosphere and contact with a film containing impurities that change the composition and film quality of the oxide semiconductor. Since the first oxide semiconductor region 103 having a channel formation region and determining the electrical characteristics of the thin film transistor is in contact with the second oxide semiconductor region 104 having a similar composition and film quality, changes in composition, film quality, interface, etc. due to impurities can be prevented. characteristics are not easily affected. Although the second oxide semiconductor region 104 functioning as a protective layer is in contact with a film containing impurities that change the composition and film quality of the oxide semiconductor, since its conductivity is lower than that of the first oxide semiconductor region 103, the electrical characteristics of the thin film transistor are not easily affected. It has no effect on the characteristics.

[0081] After removing the resist mask, heat treatment is preferably performed at 200°C to 600°C, typically 250°C to 500°C. Here, it is placed in a furnace and heat-treated at 350°C for 1 hour under a nitrogen atmosphere. This heat treatment causes atomic-level rearrangement of the In-Ga-Zn-O-based amorphous film. Since this heat treatment releases the strain that inhibits carrier movement, the heat treatment (including photo annealing) here is important. Note that the timing of the heat treatment is not particularly limited as long as it is after the formation of the second In-Ga-Zn-O-based amorphous film. For example, it may be performed after forming the pixel electrode.

[0082] Next, a protective insulating layer 107 covering the thin film transistor 170 is formed. The protective insulating layer 107 can be a silicon nitride film, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, a tantalum oxide film, etc., obtained by using a sputtering method or the like.

[0083] Next, a fifth photolithography process is performed to form a resist mask, and contact holes 125 reaching the source electrode layer or the drain electrode layer 105b are formed by etching the protective insulating layer 107. Also, contact holes 127 reaching the second terminal 122 and contact holes 126 reaching the connection electrode 120 are formed by the etching here. A cross-sectional view at this stage is shown in Fig. 3(B).

[0084] Next, after removing the resist mask, a transparent conductive film is formed. As materials for the transparent conductive film, indium oxide (In2O3), indium tin oxide alloy (In2O3 - SnO ​​​​​​​​​​​​2. (abbreviated as ITO) is formed by using a sputtering method, a vacuum evaporation method, or the like. In this way The etching treatment of such materials is performed with a hydrochloric acid-based solution. However, in particular, the etching of ITO is likely to generate residues. Therefore, indium zinc oxide alloy oxide (In2O3-ZnO) may be used to improve the etch processability.

[0085] Next, a sixth photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form the pixel electrode layer 110. The pixel electrode layer 110 is directly connected to the source electrode layer or the drain electrode layer 105b through the contact hole 125.

[0086] Also, in this sixth photolithography process, using the gate insulating layer 102 and the protective insulating layer 107 as dielectrics, a holding capacitor is formed between the capacitor wiring 108 and the pixel electrode layer 110.

[0087] Also, in this sixth photolithography process, the first terminal and the second terminal are covered with a resist mask to leave the transparent conductive films 128 and 129 formed in the terminal portion. The transparent conductive films 128 and 129 serve as electrodes or wirings used for connection with the FPC. The transparent conductive film 128 formed on the connection electrode 120 directly connected to the first terminal 121 serves as a connection terminal electrode that functions as an input terminal of the gate wiring. The transparent conductive film 12 formed on the second terminal 122 9 is a connection terminal electrode that functions as an input terminal of the source wiring.

[0088] Next, the resist mask is removed, and a cross-sectional view at this stage is shown in FIG. 3(C). Note that the plan view at this stage corresponds to FIG. 7.

[0089] FIG. 8(A1) and FIG. 8(A2) are a plan view and a cross-sectional view of the gate line terminal portion at this stage. 8(A1) is a cross-sectional view taken along line C1-C2 in FIG. 8(A2). In FIG. 8(A1), a transparent conductive film 15 is formed on a protective insulating film 154. 5 is a terminal electrode for connection that functions as an input terminal. In the terminal section, a first terminal 151 made of the same material as the gate wiring and a second terminal 152 made of the same material as the source wiring are provided. The connection electrode 153 made of a material overlaps the gate insulating layer 152 and comes into direct contact with the gate insulating layer 152 for electrical continuity. In addition, a connection electrode 153 and a transparent conductive film 155 are provided on a protective insulating film 154. The electrodes are in direct contact with each other through contact holes for electrical continuity.

[0090] FIG. 8(B1) and FIG. 8(B2) are a plan view and a cross-sectional view of a source line terminal portion, respectively. FIG. 8(B1) is a cross-sectional view taken along line D1-D2 in FIG. 8(B2). In FIG. 8(B1), a transparent conductive film 155 is formed on a protective insulating film 154. is a terminal electrode for connection that functions as an input terminal. In the sub-portion, an electrode 156 made of the same material as the gate wiring is electrically connected to the source wiring. The electrode 156 overlaps the second terminal 150 via the gate insulating layer 152. The electrode 156 is not electrically connected to the first terminal 150, and the electrode 156 is set to a potential different from that of the second terminal 150. For example, if you set it to floating, GND, 0V, etc., you can reduce the capacitance or The second terminal 150 can form a capacitance for anti-static measures. It is electrically connected to the transparent conductive film 155 via the insulating film 154 .

[0091] A plurality of gate wirings, source wirings, and capacitor wirings are provided according to the pixel density. . Also, in the terminal portion, a plurality of first terminals having the same potential as the gate wiring, second terminals having the same potential as the source wiring, third terminals having the same potential as the capacitor wiring, etc. are arranged side by side. The number of each terminal may be set to an arbitrary number, and the implementer may appropriately determine it.

[0092] In this way, through six photolithography processes and using six photomasks, a pixel thin film transistor portion having a thin film transistor 170 which is a bottom gate type n-channel thin film transistor can be completed. Then, by arranging these in a matrix corresponding to individual pixels to form a pixel portion, it can be used as one substrate for manufacturing an active matrix type display device. In this specification, for convenience, such a substrate is referred to as an active matrix substrate. When manufacturing an active matrix type liquid crystal display device, a liquid crystal layer is provided between the active matrix substrate

[0093] and a counter substrate provided with a counter electrode, and the active matrix substrate and the counter substrate are fixed. A common electrode that is electrically connected to the counter electrode provided on the counter substrate is provided on the active matrix substrate, and a fourth terminal that is electrically connected to the common electrode is provided in the terminal portion. This fourth terminal is a terminal for setting the common electrode to a fixed potential, for example, GND, 0V, etc.

[0094] Also, this embodiment is not limited to the pixel configuration of FIG. 7, and an example of a pixel configuration different from FIG. 7 is shown in FIG. 9. In FIG. 9, no capacitor wiring is provided, and the pixel electrode is connected to the gate wiring and the protective insulation of adjacent pixels ​​​This is an example of forming a holding capacitor by overlapping through a film and a gate insulating layer. In this case, the capacitance wiring and the third terminal connected to the capacitance wiring can be omitted. In FIG. 9, the same parts as those in FIG. 7 are described using the same reference numerals.

[0095] In an active matrix type liquid crystal display device, a display pattern is formed on the screen by driving pixel electrodes arranged in a matrix. Specifically, a voltage is applied between the selected pixel electrode and the counter electrode corresponding to the pixel electrode, whereby optical modulation of the liquid crystal layer disposed between the pixel electrode and the counter electrode is performed, and this optical modulation is recognized by the observer as the display pattern.

[0096] In the video display of a liquid crystal display device, since the response of the liquid crystal molecules themselves is slow, there are problems such as afterimages and blurring of the video. In order to improve the video characteristics of the liquid crystal display device, there is a driving technique called so-called black insertion, in which all-black display is performed every other frame.

[0097] Also, there is a driving technique called so-called double-speed driving, in which the vertical synchronization frequency is set to 1.5 times or more, preferably 2 times or more, of the normal value to improve the video characteristics.

[0098] In order to improve the video characteristics of the liquid crystal display device, a surface light source is configured using a plurality of LED (light emitting diode) light sources or a plurality of EL light sources as the backlight, and there is also a driving technique in which each light source constituting the surface light source is independently driven to blink intermittently within one frame period. As the surface light source, three or more types of LEDs may be used, or white light emitting LEDs may be used. Since a plurality of LEDs can be independently controlled, the LEDs are adjusted according to the switching timing of the optical modulation of the liquid crystal layer. It is also possible to synchronize the light emission timing of D. Since this driving technology can partially turn off the LEDs, especially in the case of video display with a large proportion of black display areas occupying one screen, power consumption can be reduced.

[0099] By combining these driving technologies, display characteristics such as the video characteristics of the liquid crystal display device can be improved compared to the prior art.

[0100] The n-channel type thin film transistor obtained in this embodiment uses an oxide semiconductor for the channel formation region and has good dynamic characteristics, so these driving technologies can be combined. Using an In-Ga-Zn-O based non-single crystal film for the channel formation region is even more preferable.

[0101] Also, when manufacturing a light-emitting display device, one electrode (also called the cathode) of the organic light-emitting element is set to a low power supply potential, such as GND, 0V, etc. Therefore, a fourth terminal for setting the cathode to a low power supply potential, such as GND, 0V, etc. is provided at the terminal portion. Also, when manufacturing a light-emitting display device, a power supply line is provided in addition to the source wiring and the gate wiring. Accordingly, a fifth terminal electrically connected to the power supply line is provided at the terminal portion.

[0102] As described above, between the first oxide semiconductor region functioning as the active layer and the protective insulating layer of the thin film transistor, by forming a second oxide semiconductor region having a lower conductivity than the first oxide semiconductor and functioning as a protective layer, changes in the composition and film quality deterioration of the first oxide semiconductor region can be prevented, and the electrical characteristics of the thin film transistor can be stabilized.

[0103] ​​By using the thin-film transistor in the pixel portion and the driving circuit portion of the display device, electrical characteristics a highly reliable display device with high electrical characteristics can be provided.

[0104] Note that the configurations shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. It is assumed that this is possible.

[0105] (Embodiment 3) In this embodiment, a thin-film transistor having a shape different from that of the thin-film transistor shown in Embodiment 1 will be described with reference to FIG. 10. Using FIG. 10, a thin-film transistor having a bottom gate structure according to this embodiment will be described.

[0106] The thin-film transistor having a bottom gate structure according to this embodiment is shown in FIG. 10. In the thin-film transistor shown in FIG. 10, a gate electrode layer 101 is provided on a substrate 100, and a gate insulating layer 102 is provided on the gate electrode layer 101. On the gate insulating layer 102, a source electrode layer or drain electrode layers 105a and 105b are provided. On the source electrode layer or drain electrode layers 105a and 105b, buffer layers 301a and 301b are provided. On the gate insulating layer 102 and the buffer layers 301a and 301b, a first oxide semiconductor region 103 is provided. On the first oxide semiconductor region 103, a second oxide semiconductor region 104 having a lower conductivity than the first oxide semiconductor region 103 is provided. Note that the first oxide semiconductor region 103 and the second oxide semiconductor region 104 may be formed together in the same oxide semiconductor layer, or may be formed separately as different oxide semiconductor layers. Further, an intermediate region of an oxide semiconductor in which the conductivity changes stepwise or continuously may exist between the first oxide semiconductor region 103 and the second oxide semiconductor region 104. The oxide semiconductor intermediate region may be formed between the first oxide semiconductor region 103 and the second oxide semiconductor region 104. 104, and a second oxide semiconductor region 1 having a lower conductivity than the first oxide semiconductor region 103. 04 is provided. The first oxide semiconductor region 103 and the second oxide semiconductor region 104 may be formed together in the same oxide semiconductor layer, or may be formed separately as different oxide semiconductor layers. Further, between the first oxide semiconductor region 103 and the second oxide semiconductor region 104, an intermediate region of an oxide semiconductor in which the conductivity changes stepwise or continuously may exist. There may be an intermediate region of an oxide semiconductor in which the conductivity changes stepwise or continuously. Also, the oxide semiconductor intermediate region may be formed between the first oxide semiconductor region 103 and the second oxide semiconductor region 104. The oxide semiconductor region 104 of 2 may be formed together in the same oxide semiconductor layer, or may be separately formed as different oxide semiconductor layers.

[0107] Further, the source electrode layer or drain electrode layer 105a, 105b is composed of the first conductive films 112a, 112b, the second conductive films 113a, 113b, and the third conductive films 114a, 114b, forming a three-layer structure. That is, the thin film transistor shown in FIG. 10 is the same as the first oxide semiconductor region 103 of the thin film transistor shown in FIG. 1 in Embodiment 1 and the source electrode layer or the drain electrode layers 105a, 105b, with buffer layers 301a, 301b provided therebetween. It is a thin film transistor having a structure.

[0108] The buffer layers 301a, 301b that function as the source region or drain region may be formed using the oxide semiconductor used to form the first oxide semiconductor region 103 and the second oxide semiconductor region 104 shown in Embodiment 1. Similar to the first oxide semiconductor region 103 and the second oxide semiconductor region 104, it is preferably formed using an In-Ga-Zn-O-based non-single crystal film that is an oxide semiconductor film containing In, Ga, and Zn. However, the buffer layers 301a, 301b have an n-type conductivity type, and their conductivity is made higher than that of the first oxide semiconductor region 103 and the second oxide semiconductor region 104. For example, the conductivity of the buffer layers 301a, 301b is preferably greater than 1.0×10 S / cm. Also, when using an In-Ga-Zn-O-based non-single crystal film for the buffer layers 301a, 301b, it is assumed to contain at least an amorphous component, and crystal grains (nanocrystals) are present in the amorphous structure. -3 It may also contain (tals). The crystal grains (nanocrystals) have a diameter of 1 nm to 10 nm, and typically is about 2 nm to 4 nm.

[0109] The oxide semiconductor films used for the buffer layers 301a and 301b are formed by sputtering. Oxidation As a specific example of the film formation conditions for the oxide semiconductor film, an oxide semiconductor target (In2O3:Ga2O3:ZnO = 1:1:1) containing In, Ga, and Zn with a diameter of 8 inches is used, and the distance between the substrate and the target is 170 mm, the pressure is 0.4 Pa, the DC power supply is 0.5 k W, the film formation gas is Ar:O2 = 50:1 (sccm), and the film formation temperature is room temperature, and sputtering film formation is performed. Note that the above crystal grains (nanocrystals) can be adjusted in terms of the presence or absence of crystal grains, the density of crystal grains, and the diameter size by appropriately adjusting the composition ratio of the target, the film formation pressure (0.1 Pa to 2.0 Pa), the power (250 W to 3000 W: 8 inches φ), the temperature (room temperature to 100 °C), and the film formation conditions for reactive sputtering. The film formation conditions of the oxide semiconductor films used for the buffer layers 301a and 301b are made different from those of the oxide semiconductor films used for the first oxide semiconductor region 103 and the second oxide semiconductor region 104. The ratio of the oxygen gas flow rate in the film formation conditions of the oxide semiconductor films used for the buffer layers 301a and 301b is made lower than the ratio of the oxygen gas flow rate in the film formation conditions of the oxide semiconductor films used for the first oxide semiconductor region 103 and the second oxide semiconductor region 104. For example the film formation conditions of the oxide semiconductor films used for the buffer layers 301a and 301b preferably have a ratio of oxygen gas to the total film formation gas of less than 10% by volume. Also, the film formation conditions of the oxide semiconductor films used for the buffer layers 301a

[0110] 301b do not contain oxygen gas in the film formation gas, and are Al The film formation conditions of the oxide semiconductor films used for the buffer layers 301a and 301b are made different from those of the oxide semiconductor films used for the first oxide semiconductor region 103 and the second oxide semiconductor region 104. The ratio of the oxygen gas flow rate in the film formation conditions of the oxide semiconductor films used for the buffer layers 301a and 301b is made lower than the ratio of the oxygen gas flow rate in the film formation conditions of the oxide semiconductor films used for the first oxide semiconductor region 103 and the second oxide semiconductor region 104. For example the film formation conditions of the oxide semiconductor films used for the buffer layers 301a and 301b preferably have a ratio of oxygen gas to the total film formation gas of less than 10% by volume. Also, the film formation conditions of the oxide semiconductor films used for the buffer layers 301a 301b do not contain oxygen gas in the film formation gas, and are Al For example, the film formation conditions of the oxide semiconductor films used for the buffer layers 301a and 301b preferably have a ratio of oxygen gas to the total film formation gas of less than 10% by volume. Also, the film formation conditions of the oxide semiconductor films used for the buffer layers 301a 301b do not contain oxygen gas in the film formation gas, and are Al For example, the film formation conditions of the oxide semiconductor films used for the buffer layers 301a and 301b preferably have a ratio of oxygen gas to the total film formation gas of less than 10% by volume. Also, the film formation conditions of the oxide semiconductor films used for the buffer layers 301a 301b do not contain oxygen gas in the film formation gas, and are Al It may be an atmosphere of rare gas such as neon.

[0111] The film thickness of the oxide semiconductor film used for the buffer layers 301a and 301b is set to be 5 nm to 20 nm. Of course, when crystal grains are included in the film, the size of the included crystal grains does not exceed the film thickness. In this embodiment, the film thickness of the oxide semiconductor film used for the buffer layers 301a and 301b is 5 nm.

[0112] Also, the buffer layers 301a and 301b may contain impurity elements for imparting n-type. As the impurity elements, for example, magnesium, aluminum, titanium, iron, tin, calcium, germanium, scandium, yttrium, zirconium, hafnium, boron, thallium, lead, etc. can be used. When magnesium, aluminum, titanium, etc. are included in the buffer layer, there is an oxygen blocking effect, etc., and the oxygen concentration of the oxide semiconductor layer can be maintained within an optimal range by heat treatment after film formation.

[0113] Also, the carrier concentration range of the buffer layer is preferably 1×10 18 / cm 3 or more (1×10 22 / c m 3 or less).

[0114] As described above, by providing the buffer layers 301a and 301b, the thermal stability can be improved between the first oxide semiconductor region 103 and the source electrode layer or drain electrode layers 105a and 105b as compared with the Schottky junction, and the operating characteristics of the thin film transistor can be stabilized. Also, since the conductivity is good, good mobility can be maintained even at a high drain voltage.

[0115] Note that for the structures and materials of the thin film transistor of this embodiment other than the buffer layers 301a and 301b, refer to Embodiment 1. For the materials other than the buffer layers 301a and 301b of the thin film transistor of this embodiment, refer to Embodiment 1.

[0116] The manufacturing process of the thin film transistor of this embodiment is substantially the same as the manufacturing process of the thin film transistor shown in Embodiment 2. First, by the method shown in Embodiment 2, the first conductive film 112 to the third conductive film 114 are formed, and an oxide semiconductor film 302 for continuously forming the buffer layers 301a and 301b is sputter-deposited using the above method (see Fig. 11(A)). Next, by the third photolithography process, the first conductive film 112 to the third conductive film 114 and the oxide semiconductor film 302 are etched into islands simultaneously, and the source electrode layer or the drain electrode layers 105a and 105b and the oxide semiconductor films 302a and 302b are formed, and reverse sputtering is performed in the same manner as in Embodiment 2 (see Fig. 11(B)). Then, when the first oxide semiconductor region 103 and the second oxide semiconductor region 104 are formed by the method shown in Embodiment 2, the oxide semiconductor films 302a and 302b are also etched simultaneously to form the buffer layers 301a and 301b (see Fig. 11(C)). The subsequent processes are the same as those in Embodiment 2. Note that the configurations shown in this embodiment can be used by appropriately combining the configurations shown in other embodiments. Note that the configurations shown in this embodiment can be used by appropriately combining the configurations shown in other embodiments. Note that the configurations shown in this embodiment can be used by appropriately combining the configurations shown in other embodiments. Note that the configurations shown in this embodiment can be used by appropriately combining the configurations shown in other embodiments.

[0117] Note that the configurations shown in this embodiment can be used by appropriately combining the configurations shown in other embodiments. It is assumed that the configurations shown in this embodiment can be used by appropriately combining the configurations shown in other embodiments.

[0118] (Embodiment 4) In this embodiment, a thin film transistor having a shape different from that of the thin film transistors shown in Embodiments 1 and 3 will be described with reference to Fig. 30. In this embodiment, a thin film transistor having a shape different from that of the thin film transistors shown in Embodiments 1 and 3 will be described with reference to Fig. 30.

[0119] The thin-film transistor with a bottom gate structure according to this embodiment is shown in FIGS. 30(A) and 30(B). As shown in FIGS. 30(A) and 30(B), in the thin-film transistor, a gate electrode layer 101 is provided on a substrate 100, a gate insulating layer 102 is provided on the gate electrode layer 101, a source electrode layer or a drain electrode layer 105a, 105b is provided on the gate insulating layer 102, a first oxide semiconductor region 103 is provided on the gate insulating layer 102 and the source electrode layer or the drain electrode layer 105a, 105b, and a second oxide semiconductor region 104 having a lower conductivity than the first oxide semiconductor region 103 is provided on the first oxide semiconductor region 103. Note that the first oxide semiconductor region 103 and the second oxide semiconductor region 104 may be formed together in the same oxide semiconductor layer, or may be formed separately as different oxide semiconductor layers. In addition, an intermediate region of an oxide semiconductor in which the conductivity changes stepwise or continuously may exist between the first oxide semiconductor region 103 and the second oxide semiconductor region 104. Further, the oxide semiconductor intermediate region may be formed together with the first oxide semiconductor region 103 and the second oxide semiconductor region 104 in the same oxide semiconductor layer, or may be formed separately as different oxide semiconductor layers. Also, the source electrode layer or the drain electrode layer 105a, 105b has a three-layer structure including a first conductive film 112a, 112b, a second conductive film 113a, 113b, and a third conductive film 114a, 114b. In addition, an insulating layer is provided on the side surfaces of the source electrode layer or the drain electrode layer 105a, 105b. In FIG. 30(A), oxide films 403a, 403b are formed on the side surfaces of the source electrode layer or the drain electrode layer 1 05a, 105b, and in FIG. 30(B), the

[0120] Moreover, the source electrode layer or the drain electrode layer 105a, 105b is composed of a three-layer structure including a first conductive film 112a, 112b, a second conductive film 113a, 113b, and a third conductive film 114a, 114b. Also, an insulating layer is provided on the side surfaces of the source electrode layer or the drain electrode layer 105a, 105b. In FIG. 30(A), oxide films 403a, 403b are formed on the side surfaces of the source electrode layer or the drain electrode layer 1 05a, 105b, and in FIG. 30(B), the source electrode layer or the drain electrode layer 105a, 105b is covered with an insulating film (not shown) on the side surface. On the side surfaces of the source electrode layer or drain electrode layers 105a and 105b, sidewall insulating layers 404 a and 404b are formed.

[0121] That is, the thin film transistor shown in Fig. 30(A) has a structure in which a part of the first oxide semiconductor region 103 of the thin film transistor shown in Fig. 1 in Embodiment 1 is in contact with the side portions of the source electrode layer or drain electrode layers 105a and 105b via the oxide films 403a and 403b. The thin film transistor shown in Fig. 30(B) has a structure in which a part of the first oxide semiconductor region 103 of the thin film transistor shown in Fig. 1 in Embodiment 1 is in contact with the side portions of the source electrode layer or drain electrode layers 105a and 105b via the sidewall insulating layers 404a and 404b. That is, the thin film transistor shown in Fig. 30(A) has a structure in which a part of the first oxide semiconductor region 103 of the thin film transistor shown in Fig. 1 in Embodiment 1 is in contact with the side portions of the source electrode layer or drain electrode layers 105a and 105b via the oxide films 403a and 403b. The thin film transistor shown in Fig. 30(B) has a structure in which a part of the first oxide semiconductor region 103 of the thin film transistor shown in Fig. 1 in Embodiment 1 is in contact with the side portions of the source electrode layer or drain electrode layers 105a and 105b via the sidewall insulating layers 404a and 404b. The oxide films 403a and 403b shown in Fig. 30(A) are formed by oxidizing the side surfaces of the source electrode layer or drain electrode layers 105a and 105b. As the oxidation method, it is preferable to perform thermal oxidation, oxygen plasma treatment, or ozone water washing. Specifically, the source electrode layer or drain electrode layers 105a and 105b shown in Fig. 2(C) of Embodiment 2 are formed, and thermal oxidation, plasma oxidation, or ozone water treatment is performed while leaving the resist mask 131. Thus, it is preferable to oxidize the side surfaces of the source electrode layer or drain electrode layers 105a and 105b to form the oxide films 403a and 403b. However, when the source electrode layer or drain electrode layers 105a and 105b have a laminated structure of different conductive films, the oxide films 403a and 403b also have a laminated structure of different oxide films. For example, titanium is used as the first conductive films 112a and 112b and the third conductive films 114a and 114b, and neodymium is used as the second conductive films 113a and 113b. That is, the thin film transistor shown in Fig. 30(A) has a structure in which a part of the first oxide semiconductor region 103 of the thin film transistor shown in Fig. 1 in Embodiment 1 is in contact with the side portions of the source electrode layer or drain electrode layers 105a and 105b via the oxide films 403a and 403b.

[0122] The oxide films 403a and 403b shown in Fig. 30(A) are formed by oxidizing the side surfaces of the source electrode layer or drain electrode layers 105a and 105b. As the oxidation method, it is preferable to perform thermal oxidation, oxygen plasma treatment, or ozone water washing. Specifically, the source electrode layer or drain electrode layers 105a and 105b shown in Fig. 2(C) of Embodiment 2 are formed, and thermal oxidation, plasma oxidation, or ozone water treatment is performed while leaving the resist mask 131. Thus, it is preferable to oxidize the side surfaces of the source electrode layer or drain electrode layers 105a and 105b to form the oxide films 403a and 403b. However, when the source electrode layer or drain electrode layers 105a and 105b have a laminated structure of different conductive films, the oxide films 403a and 403b also have a laminated structure of different oxide films. For example, titanium is used as the first conductive films 112a and 112b and the third conductive films 114a and 114b, and neodymium is used as the second conductive films 113a and 113b. That is, the thin film transistor shown in Fig. 30(A) has a structure in which a part of the first oxide semiconductor region 103 of the thin film transistor shown in Fig. 1 in Embodiment 1 is in contact with the side portions of the source electrode layer or drain electrode layers 105a and 105b via the oxide films 403a and 403b. The thin film transistor shown in Fig. 30(B) has a structure in which a part of the first oxide semiconductor region 103 of the thin film transistor shown in Fig. 1 in Embodiment 1 is in contact with the side portions of the source electrode layer or drain electrode layers 105a and 105b via the sidewall insulating layers 404a and 404b. That is, the thin film transistor shown in Fig. 30(A) has a structure in which a part of the first oxide semiconductor region 103 of the thin film transistor shown in Fig. 1 in Embodiment 1 is in contact with the side portions of the source electrode layer or drain electrode layers 105a and 105b via the oxide films 403a and 403b. The thin film transistor shown in Fig. 30(B) has a structure in which a part of the first oxide semiconductor region 103 of the thin film transistor shown in Fig. 1 in Embodiment 1 is in contact with the side portions of the source electrode layer or drain electrode layers 105a and 105b via the sidewall insulating layers 404a and 404b. When using an aluminum alloy containing [it], the oxide films 403a and 403b are, in order from the upper layer, a three-layer laminated structure of a titanium oxide film, an aluminum oxide alloy film containing neodymium, and a titanium oxide film. Note that the conductivity of the oxide films 403a and 403b shall be smaller than that of the first oxide semiconductor region 103.

[0123] The sidewall insulating layers 404a and 404b shown in Fig. 30(B) are formed of a silicon film, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film. Specifically, after forming the source electrode layer or drain electrode layer 105a, 105b shown in Fig. 2(C) of Embodiment Form 2 and removing the resist mask 131, a silicon film, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film is formed so as to cover the source electrode layer or drain electrode layer 105a, 105b by a method such as plasma CVD or sputtering. Then, by performing anisotropic etching mainly in the vertical direction, the newly formed silicon film, silicon oxide film, silicon oxynitride film, or silicon nitride oxide film is partially etched to form sidewall insulating layers 404a and 404b in contact with the side surfaces of the source electrode layer or drain electrode layer 105a, 105b. At this time, as the anisotropic etching, dry etching is preferable, and as the etching gas, a mixed gas of CHF3 and helium can be used. However, when using the same type of silicon film as the gate insulating layer as the sidewall insulating layer, the etching selectivity cannot be obtained, so the gate insulating layer 102 may also be etched by the above anisotropic etching.

[0124] ​​​​​​​​​​​​​​​As shown in FIGS. 30(A) and 30(B), by forming the oxide films 403a and 403b or the sidewall insulating layers 404a and 404b on the side surfaces of the source electrode layer or the drain electrode layers 105a and 105b, the path of the drain current can be made not a straight path connecting the source electrode layer or the drain electrode layers 105a and 105b, but a path that detours around the oxide films 403a and 403b or the sidewall insulating layers 404a and 404b. Thereby, the off-current that flows when the thin-film transistor is off can be reduced. Further, this is not limited to the configuration in which the second oxide semiconductor region 104 is provided, and even in a thin-film transistor having a structure in which the second oxide semiconductor region 104 is not provided and the active layer is a single oxide semiconductor layer, by providing the oxide films 403a and 403b or the sidewall insulating layers 404a and 404b on the side surfaces of the source electrode layer or the drain electrode layers 105a and 105b, the same effect can be obtained. Also, by providing the oxide films 403a and 403b or the sidewall insulating layers 404a and 404b on the side surfaces of the source electrode layer or the drain electrode layers 105a and 105b, the coverage of the first oxide semiconductor region 103 can be improved, and the step break of the first oxide semiconductor region 103 due to the step shape can be prevented. Further, also in this embodiment, as shown in Embodiment 3, a structure in which a buffer layer is provided between the first oxide semiconductor region 103 and the source electrode layer or the drain electrode layers 105a and 105b may be employed. Note that the oxide films 403a and 403b and the sidewall insulating layers 404a and 404b of this embodiment

[0125]

[0126]

[0127] ​ For structures and materials other than those of 04b, refer to Embodiment 1.

[0128] Note that the configurations shown in this embodiment can be used in appropriate combinations with the configurations shown in other embodiments. It is assumed that this is possible.

[0129] (Embodiment 5) In this embodiment, in a display device which is an example of a semiconductor device, an example of fabricating at least a part of a drive circuit and a thin film transistor to be arranged in a pixel portion on the same substrate will be described below. will be described.

[0130] The thin film transistor to be arranged in the pixel portion is formed in accordance with Embodiments 1 to 4. . Also, since the thin film transistors shown in Embodiments 1 to 4 are n-channel type TFTs, a part of the drive circuit that can be configured with n-channel type TFTs in the drive circuit is formed on the same substrate as the thin film transistor in the pixel portion. is formed on the same substrate as the thin film transistor in the pixel portion.

[0131] An example of a block diagram of an active matrix type liquid crystal display device which is an example of a semiconductor device is shown in FIG. 1 4(A). The display device shown in FIG. 14(A) includes a pixel portion 5301 having a plurality of pixels each including a display element on a substrate 5300, a scan line drive circuit 5302 for selecting each pixel, and a signal line drive circuit 5303 for controlling the input of a video signal to the selected pixel. The pixel portion 5301 is connected to the signal line drive circuit 5303 by a plurality of signal lines S1 to Sm (not shown) extending in the column direction from the signal line drive circuit 5303, and is connected to the scan line drive circuit 5302 by a plurality of scan lines G1 to Gn (not shown) extending in the row direction from the scan line drive circuit 5302.

[0132] The pixel portion 5301 is connected to the signal line drive circuit 5303 by a plurality of signal lines S1 to Sm (not shown) extending in the column direction from the signal line drive circuit 5303, and is connected to the scan line drive circuit 5302 by a plurality of scan lines G1 to Gn (not shown) extending in the row direction from the scan line drive circuit 5302. 5302 by a plurality of scan lines G1 to Gn (not shown) extending in the row direction from the scan line drive circuit 5302. It is connected to the scanning line driving circuit 5302 and has a plurality of pixels (not shown) arranged in a matrix corresponding to the signal lines S1 to Sm and the scanning lines G1 to Gn. And each pixel is connected to a signal line Sj (any one of the signal lines S1 to Sm) and a scanning line Gi (any one of the scanning lines G1 to Gn). And it has a plurality of pixels (not shown) arranged in a matrix corresponding to the signal lines S1 to Sm and the scanning lines G1 to Gn. And each pixel is connected to a signal line Sj (any one of the signal lines S1 to Sm) and a scanning line Gi (any one of the scanning lines G1 to Gn). One of the signal lines S1 to Sm) and a scanning line Gi (any one of the scanning lines G1 to Gn). And is connected to one of the scanning lines G1 to Gn).

[0133] Also, the thin film transistors shown in Embodiments 1 to 4 are n-channel type TFTs, and the signal line driving circuit composed of n-channel type TFTs will be described with reference to FIG. 15. And the signal line driving circuit shown in FIG. 15 will be described with reference to FIG. 15 using the signal line driving circuit composed of n-channel type TFTs.

[0134] The signal line driving circuit shown in FIG. 15 includes a driver IC 5601, a switch group 5602_1 to 56 02_M, a first wiring 5611, a second wiring 5612, a third wiring 5613, and wirings 56 21_1 to 5621_M. Each of the switch groups 5602_1 to 5602_M has a first thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor 5603c.

[0135] The driver IC 5601 is connected to the first wiring 5611, the second wiring 5612, and the third wiring 5613 and the wirings 5621_1 to 5621_M. And each of the switch groups 5602_1 to 5602_M is connected to the first wiring 5611, the second wiring 5612, the third wiring 561 3 and the wirings 5621_1 to 5621_M corresponding to each of the switch groups 5602_1 to 5602_M. And each of the wirings 5621_1 to 5621_M is connected to three signal lines (signal line Sm-2, signal line Sm-1, signal line S through the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c. through the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c. m) via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c. It is connected to m (m = 3M)). For example, the wiring 5621_J in the J-th column (any one of the wirings 5621_1 ~ 5621_M) is connected to the signal lines Sj-2, Sj-1, and Sj (j = 3J) via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c of the switch group 5602_J. Continued.

[0136] Note that signals are input to the first wiring 5611, the second wiring 5612, and the third wiring 5613, respectively. Input.

[0137] Note that the driver IC 5601 is preferably formed using a single crystal semiconductor. Furthermore, it is desirable that the switch groups 5602_1 to 5602_M are formed on the same substrate as the pixel portion. Therefore, the driver IC 5601 and the switch groups 5602_1 to 56 02_M may be connected via an FPC or the like. Alternatively, a single crystal semiconductor layer may be provided by bonding or the like on the same substrate as the pixel portion, and the driver IC 5601 may be formed. Stick together, etc. Next, the operation of the signal line driving circuit shown in FIG. 15 will be described with reference to the timing chart of FIG. 16. Note that the timing chart of FIG. 16 shows the timing chart when the scanning line Gi in the i-th row is selected. Furthermore, the selection period of the scanning line Gi in the i-th row

[0138] is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Furthermore, the signal line driving circuit in FIG. 15 operates in the same manner as in FIG. 16 even when the scanning lines of other rows are selected. Refer to. Is shown. Furthermore, the selection period of the scanning line Gi in the i-th row Is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Furthermore, the signal line driving circuit in FIG. 15 operates in the same manner as in FIG. 16 even when the scanning lines of other rows are selected. Divided. Furthermore, the signal line driving circuit in FIG. 15 operates in the same manner as in FIG. 16 even when the scanning lines of other rows are selected. Case.

[0139] Note that the timing chart in Fig. 16 shows the case where the wiring 5621_J in the J column is connected to the signal line Sj-2, the signal line Sj-1, and the signal line Sj via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c.

[0140] Note that the timing chart in Fig. 16 shows the timing when the scanning line Gi in the i-th row is selected, the on / off timing 5703a of the first thin film transistor 5603a, the on / off timing 5703b of the second thin film transistor 5603b, the on / off timing 5703c of the third thin film transistor 5603c, and the signal 5721_J input to the wiring 5621_J in the J column.

[0141] Note that different video signals are input to the wirings 5621_1 to 5621_M during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, respectively. For example, the video signal input to the wiring 5621_J during the first sub-selection period T1 is input to the signal line Sj-2, the video signal input to the wiring 5621_J during the second sub-selection period T2 is input to the signal line Sj-1, and the video signal input to the wiring 5621_J during the third sub-selection period T3 is input to the signal line Sj. Further, let the video signals input to the wiring 5621_J during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 be Data_j-2, Data_j-1, and Data_j, respectively.

[0142] As shown in Fig. 16, during the first sub-selection period T1, the first thin film transistor 5603a ​​​​​​​​​​​​​​​a is turned on, and the second thin-film transistor 5603b and the third thin-film transistor 5603c are turned off. At this time, Data_j-2 input to the wiring 5621_J is input to the signal line Sj-2 via the first thin-film transistor 5603a. During the second sub-selection period T2 the second thin-film transistor 5603b is turned on, and the first thin-film transistor 5603a and the third thin-film transistor 5603c are turned off. At this time, Data_j−1 input to the wiring 5621_J is input to the signal line Sj−1 via the second thin-film transistor 5603b. During the third sub-selection period T3, the third thin-film transistor 5603c is turned on and the first thin-film transistor 5603a and the second thin-film transistor 5603b are turned off . At this time, Data_j input to the wiring 5621_J is input to the signal line Sj via the third thin-film transistor 5603c.

[0143] From the above, the signal line driving circuit in FIG. 15 divides one gate selection period into three, so that a video signal can be input from one wiring 5621 to three signal lines during one gate selection period. Therefore, the signal line driving circuit in FIG. 15 can reduce the number of connections between the substrate on which the driver IC 5601 is formed and the substrate on which the pixel portion is formed to about 1 / 3 compared to the number of signal lines. By reducing the number of connections to about 1 / 3, the signal line driving circuit in FIG. 15 can improve reliability, yield, etc. .

[0144] Note that as shown in FIG. 15, if one gate selection period is divided into a plurality of sub-selection periods, and in each of the plurality of sub-selection periods, a video signal can be input from one wiring to each of a plurality of signal lines, then the arrangement, number, driving method, etc. of the thin-film transistors are not limited. ​

[0145] For example, when inputting video signals from one wiring to three or more signal lines respectively in each of three or more sub-selection periods, thin film transistors and wiring for controlling the thin film transistors may be added. However, if one gate selection period is divided into four or more sub-selection periods, one sub-selection period becomes short. Therefore, it is desirable that one gate selection period be divided into two or three sub-selection periods. As another example, as shown in the timing chart of FIG. 17, one selection period may be divided into a precharge period Tp, a first sub-selection period T1, a second sub-selection period T2, and a third selection period T3. Further, the timing chart of FIG. 17 shows the timing when the scanning line Gi in the i-th row is selected, the on / off timing 5803a of the first thin film transistor 5603a, the on / off timing 5803b of the second thin film transistor 5603b, the on / off timing 5803c of the third thin film transistor 5603c, and the signal 5821_J input to the wiring 5621_J in the J-th column. As shown in FIG. 17, in the precharge period Tp, the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c are turned on. At this time, the precharge voltage Vp input to the wiring 5621_J is input to the signal lines Sj-2, signal line Sj-1, and signal line Sj through the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c, respectively. In the first sub-selection period T1, the first thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor

[0146] Another example is that, as shown in the timing chart of FIG. 17, one selection period can be divided into a precharge period Tp, a first sub-selection period T1, a second sub-selection period T2, and a third selection period T3. Moreover, the timing chart of FIG. 17 shows the timing when the scanning line Gi in the i-th row is selected, the on / off timing 5803a of the first thin film transistor 5603a, the on / off timing 5803b of the second thin film transistor 5603b, the on / off timing 5803c of the third thin film transistor 5603c, and the signal 5821_J input to the wiring 5621_J in the J-th column. As shown in FIG. 17, in the precharge period Tp, the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c are turned on. At this time, the precharge voltage Vp input to the wiring 5621_J is input to the signal lines Sj - 2, signal line Sj−1, and signal line Sj through the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c respectively. In the first sub-selection period T1, the first thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor thin film transistor 5603c are turned off. At this time, the signal input to the signal line Sj−2 is output to the wiring 5621_J through the first thin film transistor 5603a. In the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. At this time, the signal input to the signal line Sj−1 is output to the wiring 5621_J through the second thin film transistor 5603b. In the third selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, the signal input to the signal line Sj is output to the wiring 5621_J through the third thin film transistor 5603c. are turned off. At this time, the signal input to the signal line Sj−2 is output to the wiring 5621_J through the first thin film transistor 5603a. In the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. At this time, the signal input to the signal line Sj−1 is output to the wiring 5621_J through the second thin film transistor 5603b. In the third selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, the signal input to the signal line Sj is output to the wiring 5621_J through the third thin film transistor 5603c. the timing when the scanning line Gi in the i-th row is selected, the on / off timing 5803a of the first thin film transistor 5603a, the on / off timing 5803b of the second thin film transistor 5603b, the on / off timing 5803c of the third thin film transistor 5603c, and the signal 5821_J input to the wiring 5621_J in the J-th column. As shown in FIG. 17, in the precharge period Tp, the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c are turned on. At this time, the precharge voltage Vp input to the wiring 5621_J is input to the signal lines Sj - 2, signal line Sj−1, and signal line Sj through the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c respectively. In the first sub-selection period T1, the first thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c are turned off. At this time, the signal input to the signal line Sj−2 is output to the wiring 5621_J through the first thin film transistor 5603a. In the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. At this time, the signal input to the signal line Sj−1 is output to the wiring 5621_J through the second thin film transistor 5603b. In the third selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, the signal input to the signal line Sj is output to the wiring 5621_J through the third thin film transistor 5603c. thin film transistor 5603c are turned off. At this time, the signal input to the signal line Sj−2 is output to the wiring 5621_J through the first thin film transistor 5603a. In the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. At this time, the signal input to the signal line Sj−1 is output to the wiring 5621_J through the second thin film transistor 5603b. In the third selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, the signal input to the signal line Sj is output to the wiring 5621_J through the third thin film transistor 5603c. As shown in FIG. 17, in the precharge period Tp, the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c are turned on. At this time, the precharge voltage Vp input to the wiring 5621_J is input to the signal lines Sj - 2, signal line Sj−1, and signal line Sj through the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c respectively. In the first sub-selection period T1, the first thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603b and the third thin film transistor 5603c are turned on. At this time, the precharge voltage Vp input to the wiring 5621_J is input to the signal lines Sj - 2, signal line Sj−1, and signal line Sj through the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c respectively. In the first sub-selection period T1, the first thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c are turned off. At this time, the signal input to the signal line Sj−2 is output to the wiring 5621_J through the first thin film transistor 5603a. In the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. At this time, the signal input to the signal line Sj−1 is output to the wiring 5621_J through the second thin film transistor 5603b. In the third selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, the signal input to the signal line Sj is output to the wiring 5621_J through the third thin film transistor 5603c. 5603c are turned off. At this time, the signal input to the signal line Sj−2 is output to the wiring 5621_J through the first thin film transistor 5603a. In the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. At this time, the signal input to the signal line Sj−1 is output to the wiring 5621_J through the second thin film transistor 5603b. In the third selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, the signal input to the signal line Sj is output to the wiring 5621_J through the third thin film transistor 5603c. 5603c are turned off. At this time, the signal input to the signal line Sj−2 is output to the wiring 5621_J through the first thin film transistor 5603a. In the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. At this time, the signal input to the signal line Sj−1 is output to the wiring 5621_J through the second thin film transistor 5603b. In the third selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, the signal input to the signal line Sj is output to the wiring 5621_J through the third thin film transistor 5603c. 5603c are turned off. At this time, the signal input to the signal line Sj−2 is output to the wiring 5621_J through the first thin film transistor 5603a. In the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. At this time, the signal input to the signal line Sj−1 is output to the wiring 5621_J through the second thin film transistor 5603b. In the third selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, the signal input to the signal line Sj is output to the wiring 5621_J through the third thin film transistor 5603c. 5603c are turned off. At this time, the signal input to the signal line Sj−2 is output to the wiring 5621_J through the first thin film transistor 5603a. In the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. At this time, the signal input to the signal line Sj−1 is output to the wiring 5621_J through the second thin film transistor 5603b. In the third selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, the signal input to the signal line Sj is output to the wiring 5621_J through the third thin film transistor 5603c. The thin film transistor 5603c turns off. At this time, Dat input to the wiring 5621_J a_j - 2 is input to the signal line Sj - 2 through the first thin film transistor 5603a . In the second sub - selection period T2, the second thin film transistor 5603b turns on, and the first thin film transistor 5603a and the third thin film transistor 5603c turn off. At this time , Data_j−1 input to the wiring 5621_J is input to the signal line Sj−1 through the second thin film transistor 5603 b. In the third sub - selection period T3, the third thin film transistor 5603c turns on, and the first thin film transistor 5603a and the second thin film transistor 5603 b turn off. At this time, Data_j input to the wiring 5621_J is input to the signal line Sj through the third thin film transistor 5603c .

[0147] From the above, the signal line driving circuit of FIG. 15 to which the timing chart of FIG. 17 is applied provides a pre - charge selection period before the sub - selection period, so that the signal line can be pre - charged , and the video signal can be written to the pixel at high speed. In FIG. 17 , those similar to FIG. 16 are denoted by common reference numerals, and detailed descriptions of the same parts or parts having similar functions are omitted .

[0148] Next, the configuration of the scanning line driving circuit will be described. The scanning line driving circuit has a shift register and a buffer. In some cases, it may also have a level shifter. In the scanning line driving circuit, a selection signal is generated when a clock signal (CLK) and a start pulse signal (SP ) are input to the shift register. The generated selection signal is sent to the buffer is buffer-amplified and supplied to the corresponding scanning line. The scanning line is connected to the gate electrodes of the transistors for one line of pixels. And since the transistors for one line of pixels must be turned on all at once, a buffer capable of passing a large current is used. One form of the shift register used as part of the scanning line driving circuit will be described with reference to FIGS. 18 and 19. Since the transistors for one line of pixels must be turned on all at once, a buffer capable of passing a large current is used. One form of the shift register used as part of the scanning line driving circuit will be described with reference to FIGS. 18 and 19.

[0149] One form of the shift register used as part of the scanning line driving circuit will be described with reference to FIGS. 18 and 19. One form of the shift register used as part of the scanning line driving circuit will be described with reference to FIGS. 18 and 19.

[0150] FIG. 18 shows the circuit configuration of the shift register. The shift register shown in FIG. 18 is composed of a plurality of flip-flops 5701_1 to 5701_n. Also, the first clock signal, the second clock signal, the start pulse signal, and the reset signal are input and it operates. FIG. 18 shows the circuit configuration of the shift register. The shift register shown in FIG. 18 is composed of a plurality of flip-flops 5701_1 to 5701_n. Also, the first clock signal, the second clock signal, the start pulse signal, and the reset signal are input and it operates. The first clock signal, the second clock signal, the start pulse signal, and the reset signal are input and it operates. The first clock signal, the second clock signal, the start pulse signal, and the reset signal are input and it operates.

[0151] The connection relationship of the shift register in FIG. 18 will be described. The first-stage flip-flop 5701_1 is connected to the first wiring 5711, the second wiring 5712, the fourth wiring 5714, the fifth wiring 5715, the seventh wiring 5717_1, and the seventh wiring 5717_2. Also, the second-stage flip-flop 5701_2 is connected to the third wiring 5713, the fourth wiring 5714, the fifth wiring 5715, the seventh wiring 5717_1, the seventh wiring 5717_2, and the seventh wiring 5717_3. The first-stage flip-flop 5701_1 is connected to the first wiring 5711, the second wiring 5712, the fourth wiring 5714, the fifth wiring 5715, the seventh wiring 5717_1, and the seventh wiring 5717_2. Also, the second-stage flip-flop 5701_2 is connected to the third wiring 5713, the fourth wiring 5714, the fifth wiring 5715, the seventh wiring 5717_1, the seventh wiring 5717_2, and the seventh wiring 5717_3. The first-stage flip-flop 5701_1 is connected to the first wiring 5711, the second wiring 5712, the fourth wiring 5714, the fifth wiring 5715, the seventh wiring 5717_1, and the seventh wiring 5717_2. Also, the second-stage flip-flop 5701_2 is connected to the third wiring 5713, the fourth wiring 5714, the fifth wiring 5715, the seventh wiring 5717_1, the seventh wiring 5717_2, and the seventh wiring 5717_3. The second-stage flip-flop 5701_2 is connected to the third wiring 5713, the fourth wiring 5714, the fifth wiring 5715, the seventh wiring 5717_1, the seventh wiring 5717_2, and the seventh wiring 5717_3. The second-stage flip-flop 5701_2 is connected to the third wiring 5713, the fourth wiring 5714, the fifth wiring 5715, the seventh wiring 5717_1, the seventh wiring 5717_2, and the seventh wiring 5717_3. The second-stage flip-flop 5701_2 is connected to the third wiring 5713, the fourth wiring 5714, the fifth wiring 5715, the seventh wiring 5717_1, the seventh wiring 5717_2, and the seventh wiring 5717_3.

[0152] Similarly, the i-th stage flip-flop 5701_i (any one of the flip-flops 5701_1 to 5701_n) is either the second wiring 5712 or the third wiring 5713, the fourth wiring 5714, the fifth wiring 5715, the seventh wiring 5717_i - 1, the seventh wiring 5717_i, and the seventh wiring 5717_i + 1. Similarly, the i-th stage flip-flop 5701_i (any one of the flip-flops 5701_1 to 5701_n) is either the second wiring 5712 or the third wiring 5713, the fourth wiring 5714, the fifth wiring 5715, the seventh wiring 5717_i - 1, the seventh wiring 5717_i, and the seventh wiring 5717_i + 1. Similarly, the i-th stage flip-flop 5701_i (any one of the flip-flops 5701_1 to 5701_n) is either the second wiring 5712 or the third wiring 5713, the fourth wiring 5714, the fifth wiring 5715, the seventh wiring 5717_i - 1, the seventh wiring 5717_i, and the seventh wiring 5717_i + 1. 17_i is connected to the seventh wiring 5717_i+1. Here, when i is odd , the flip-flop 5701_i at the i-th stage is connected to the second wiring 5712, and when i is even and in a certain case, the flip-flop 5701_i at the i-th stage is connected to the third wiring 5713 .

[0153] Also, the flip-flop 5701_n at the n-th stage is connected to one of the second wiring 5712 or the third wiring 5 713, the fourth wiring 5714, the fifth wiring 5715, the seventh wiring 5717_n-1 , the seventh wiring 5717_n, and the sixth wiring 5716.

[0154] Incidentally, the first wiring 5711, the second wiring 5712, the third wiring 5713, and the sixth wiring 57 16 may be referred to as the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Further, the fourth wiring 5714 and the fifth wiring 5715 may be referred to as the first power supply line and the second power supply line, respectively.

[0155] Next, the details of the flip-flop shown in FIG. 18 will be described with reference to FIG. 19. FIG. 19 shows a flip-flop having a first thin film transistor 5571, a second thin film transistor 5572, a third thin film transistor 5573, a fourth thin film transistor 5574, a fifth thin film transistor 5575, a sixth thin film transistor 5576, a seventh thin film transistor 5577, and an eighth thin film transistor 5578. Incidentally, the first thin film transistor 5571, the second thin film transistor 5572, the third thin film transistor 5573, the fourth thin film transistor 5574, the fifth thin film transistor 5575, the sixth thin film transistor 5576, the seventh thin film transistor 5577, and the eighth thin film transistor 5578 are n channel type transistors, and it is assumed that they enter the conduction state when the voltage between the gate and the source (Vgs) exceeds the threshold voltage (Vt h).

[0156] Also, the flip-flop shown in FIG. 19 includes a first wiring 5501, a second wiring 5502, a third wiring 5503, a fourth wiring 5504, a fifth wiring 5505, and a sixth wiring 5506 and has.

[0157] Here, all the thin film transistors are shown as enhancement type n-channel transistors, but are not particularly limited. For example, a depletion type n-channel transistor can also be used to drive the drive circuit.

[0158] Next, the connection configuration of the flip-flop shown in FIG. 18 is shown below.

[0159] The first electrode (one of the source electrode or the drain electrode) of the first thin film transistor 5571 is connected to the fourth wiring 5504, and the second electrode (the other of the source electrode or the drain electrode) of the first thin film transistor 5571 is connected to the third wiring 5503.

[0160] The first electrode of the second thin film transistor 5572 is connected to the sixth wiring 5506, and the second electrode of the second thin film transistor 5572 is connected to the third wiring 5503.

[0161] The first electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505, and the second electrode of the third thin film transistor 5573 is connected to the gate electrode of the second thin film transistor 5572 is connected, and the gate electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505 is done.

[0162] The first electrode of the fourth thin film transistor 5574 is connected to the sixth wiring 5506, and the fourth The second electrode of the thin film transistor 5574 is connected to the gate electrode of the second thin film transistor 5572 is connected, and the gate electrode of the fourth thin film transistor 5574 is connected to the gate electrode of the first thin film transistor 5 571.

[0163] The first electrode of the fifth thin film transistor 5575 is connected to the fifth wiring 5505, and the fifth The second electrode of the thin film transistor 5575 is connected to the gate electrode of the first thin film transistor 5571 is connected, and the gate electrode of the fifth thin film transistor 5575 is connected to the first wiring 5501 is done.

[0164] The first electrode of the sixth thin film transistor 5576 is connected to the sixth wiring 5506, and the sixth The second electrode of the thin film transistor 5576 is connected to the gate electrode of the first thin film transistor 5571 is connected, and the gate electrode of the sixth thin film transistor 5576 is connected to the gate electrode of the second thin film transistor 5 572.

[0165] The first electrode of the seventh thin film transistor 5577 is connected to the sixth wiring 5506, and the seventh The second electrode of the thin film transistor 5577 is connected to the gate electrode of the first thin film transistor 5571 is connected, and the gate electrode of the seventh thin film transistor 5577 is connected to the second wiring 5502 is done. The first electrode of the eighth thin film transistor 5578 is connected to the sixth wiring 5506 and the second electrode of the eighth thin film transistor 5578 is connected to the gate is connected to the gate electrode of the eighth thin film transistor 5578, and the gate electrode of the first thin film transistor 5571 is connected to the first wiring 550 1.

[0166] Note that the connection points of the gate electrode of the first thin film transistor 5571, the gate electrode of the fourth thin film transistor 5574 , the second electrode of the fifth thin film transistor 5575, the second electrode of the sixth thin film transistor 5576 and the second electrode of the seventh thin film transistor 5577 are set as node 5543. Further, the connection points of the gate electrode of the second thin film transistor 5572, the second electrode of the third thin film transistor 5573 , the second electrode of the fourth thin film transistor 5574, the gate electrode of the sixth thin film transistor 5576 and the second electrode of the eighth thin film transistor 5578 are set as node 5544.

[0167] Note that the first wiring 5501, the second wiring 5502, the third wiring 5503 and the fourth wiring 5 504 may be respectively referred to as the first signal line, the second signal line, the third signal line, and the fourth signal line. Furthermore, the fifth wiring 5505 may be referred to as the first power supply line, and the sixth wiring 5506 may be referred to as the second power supply line.

[0168] In the flip-flop 5701_i in the i-th stage, the first wiring 5501 in FIG. 19 is connected to the seventh wiring 5717_i-1 in FIG. 18. Also, the second wiring 550 2 in FIG. 19 is connected to the seventh wiring 5717_i+1 in FIG. 18. Also, the third wiring 550 3 in FIG. 19 is connected to the seventh wiring 5717_i. Furthermore, the sixth wiring 5 506 in FIG. 19 is connected to the fifth wiring 5715.

[0169] When i is odd, the fourth wiring 5504 in FIG. 19 is connected to the second wiring 5712 in FIG. 18 Continuing, when i is even, it is connected to the third wiring 5713 in FIG. 18. Also, in FIG. 19 the fifth wiring 5505 and the fourth wiring 5714 in FIG. 18 are connected.

[0170] However, in the first-stage flip-flop 5701_1, the first wiring 550 1 in FIG. 19 is connected to the first wiring 5711 in FIG. 18. Also, in the nth-stage flip-flop 57 01_n, the second wiring 5502 in FIG. 19 is connected to the sixth wiring 5716 in FIG. 18 continuing.

[0171] Also, it is also possible to fabricate the signal line driving circuit and the scanning line driving circuit only with the n-channel TFTs shown in Embodiments 1 to 4. Since the n-channel TFTs shown in Embodiments 1 to 4 have a high carrier mobility of the transistor, it is possible to increase the driving frequency of the driving circuit . Also, the n-channel TFTs shown in Embodiments 1 to 4 have a parasitic capacitance reduced by the source region or drain region which is an In-Ga-Zn-O-based non-single crystal film , so they have high frequency characteristics (referred to as f characteristics). For example, the scanning line driving circuit using the n-channel TFTs shown in Embodiments 1 to 4 can be operated at high speed, so it is possible to increase the frame frequency or to realize black screen insertion and so on. It can also be realized.

[0172] Furthermore, by increasing the channel width of the transistors of the scanning line driving circuit or by arranging a plurality of scanning line driving circuits, a higher frame frequency can be realized . When arranging a plurality of scanning line driving circuits, for driving the scanning lines of even rows, the scanning line driving Place the circuit on one side and place the scanning line driving circuit for driving the scanning lines in the odd rows on the opposite side, so that it is possible to increase the frame frequency. Also, when outputting signals to the same scanning line by a plurality of scanning line driving circuits, it is advantageous for reducing the size of the display device.

[0173] In addition, when manufacturing an active matrix light-emitting display device which is an example of a semiconductor device, since a plurality of thin film transistors are arranged in at least one pixel, it is preferable to arrange a plurality of scanning line driving circuits. An example of a block diagram of an active matrix light-emitting display device is shown in FIG. 1 4(B).

[0174] The light-emitting display device shown in FIG. 14(B) has a pixel portion 5401 having a plurality of pixels each including a display element on a substrate 5400, a first scanning line driving circuit 5402 and a second scanning line driving circuit 5404 for selecting each pixel, and a signal line driving circuit 5 403 for controlling the input of a video signal to the selected pixel.

[0175] When the video signal input to the pixel of the light-emitting display device shown in FIG. 14(B) is in digital format, the pixel becomes a light-emitting or non-light-emitting state by switching the transistor on and off. Therefore, grayscale display can be performed using the area grayscale method or the time grayscale method. The area grayscale method is a driving method for performing grayscale display by dividing one pixel into a plurality of sub-pixels and driving each sub-pixel independently based on a video signal. Also, the time grayscale method is a driving method for performing grayscale display by controlling the period during which the pixel emits light. Since the light-emitting element has a higher response speed than a liquid crystal element or the like, it is more suitable for the time grayscale method than the liquid crystal element.

[0176] ​​​Specifically, when displaying using the time gray scale method, one frame period is divided into multiple subframes. Then, the light emitting element of the pixel is divided into sub-frame periods according to the video signal. By dividing the period into multiple subframes, The total length of time that pixels actually emit light during one frame is controlled by the video signal. It is possible to control the brightness and display gradation.

[0177] In the light-emitting display device shown in FIG. 14B, two switching TFTs are provided for one pixel. When the first scanning line, which is the gate wiring of one of the switching TFTs, is used as the first scanning line, The signal to be outputted is generated by the first scanning line driver circuit 5402 and is applied to the gate of the other switching TFT. A signal input to the second scanning line, which is a wiring, is generated by a second scanning line driver circuit 5404. In this example, the signal input to the first scanning line and the signal input to the second scanning line are Both of these may be generated by a single scanning line driving circuit. The number of switching TFTs in a pixel determines the operation of the switching element. A plurality of scanning lines may be used for each pixel. The signals input to the scanning line driver circuit may all be generated by one scanning line driver circuit, or may be generated by a plurality of scanning line drivers. It may be generated by an automatic circuit.

[0178] In addition, in the light-emitting display device, the driver circuit may be configured with n-channel TFTs. A part of the driver circuit can be formed on the same substrate as the thin film transistor of the pixel portion. In addition, the signal line driver circuit and the scanning line driver circuit may be the same as those shown in any one of the n-channel MOSFETs in Embodiments 1 to 4. It is also possible to fabricate the device using only channel TFTs.

[0179] In addition, the drive circuit described above is not limited to liquid crystal display devices and light-emitting display devices, and may also be used for electronic paper that drives electronic ink using a switching element and an element electrically connected thereto. Electronic paper, which is also called an electrophoretic display device (electrophoretic display), has advantages such as being as easy to read as paper, having lower power consumption compared to other display devices, and being able to be made thin and light. readability, low power consumption compared to other display devices, and the ability to be made thin and light.

[0180] Although various forms of electrophoretic displays are conceivable, a microcapsule containing a first particle having a positive charge and a second particle having a negative charge is dispersed in a solvent or solute, and by applying an electric field to the microcapsule, the particles in the microcapsule are moved in opposite directions to each other and only the color of the particles aggregated on one side is displayed. Note that the first particle or the second particle contains a dye and does not move in the absence of an electric field. Also, the color of the first particle and the color of the second particle are different (including colorless).

[0181] Thus, an electrophoretic display is a display that utilizes the so-called dielectrophoretic effect in which a substance with a high dielectric constant moves to a high electric field region.

[0182] The above microcapsules dispersed in a solvent are called electronic ink, and this electronic ink can be printed on the surfaces of glass, plastic, cloth, paper, etc. Also, color display is possible by using particles having color filters or dyes.

[0183] In addition, the above microcapsules are appropriately sandwiched between two electrodes on an active matrix substrate. ​​​​​​​​​​​If a plurality of local capsules are arranged, an active matrix type display device is completed, and display can be performed by applying an electric field to the microcapsules. For example, the active matrix substrate obtained by the thin film transistors of Embodiments 1 to 4 can be used. For example, the active matrix substrate obtained by the thin film transistors of Embodiments 1 to 4 can be used. For example, the active matrix substrate obtained by the thin film transistors of Embodiments 1 to 4 can be used.

[0184] In addition, the first particles and the second particles in the microcapsules may be made of a material selected from a conductor material, an insulator material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, or a composite material thereof. In addition, the first particles and the second particles in the microcapsules may be made of a material selected from a conductor material, an insulator material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, or a composite material thereof. In addition, the first particles and the second particles in the microcapsules may be made of a material selected from a conductor material, an insulator material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, or a composite material thereof.

[0185] By the above steps, a highly reliable display device can be manufactured as a semiconductor device.

[0186] Note that the configurations shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0187] (Embodiment 6) Manufacture the thin film transistors shown in Embodiments 1 to 4, and use the thin film transistors in a pixel portion and further in a driving circuit to manufacture a semiconductor device (also referred to as a display device) having a display function. Further, a part or all of the driving circuit using the thin film transistors shown in Embodiments 1 to 4 can be integrally formed on the same substrate as the pixel portion to form a system on panel. Manufacture the thin film transistors shown in Embodiments 1 to 4, and use the thin film transistors in a pixel portion and further in a driving circuit to manufacture a semiconductor device (also referred to as a display device) having a display function. Further, a part or all of the driving circuit using the thin film transistors shown in Embodiments 1 to 4 can be integrally formed on the same substrate as the pixel portion to form a system on panel. Manufacture the thin film transistors shown in Embodiments 1 to 4, and use the thin film transistors in a pixel portion and further in a driving circuit to manufacture a semiconductor device (also referred to as a display device) having a display function. Further, a part or all of the driving circuit using the thin film transistors shown in Embodiments 1 to 4 can be integrally formed on the same substrate as the pixel portion to form a system on panel. Manufacture the thin film transistors shown in Embodiments 1 to 4, and use the thin film transistors in a pixel portion and further in a driving circuit to manufacture a semiconductor device (also referred to as a display device) having a display function. Further, a part or all of the driving circuit using the thin film transistors shown in Embodiments 1 to 4 can be integrally formed on the same substrate as the pixel portion to form a system on panel.

[0188] The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light emitting element (also referred to as a light emitting display element) can be used. The light emitting element can emit light by current or voltage. The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light emitting element (also referred to as a light emitting display element) can be used. The light emitting element can emit light by current or voltage. ​​​​This category includes elements whose brightness is controlled by a specific factor, such as inorganic EL (Electroluminescent) devices. Also, electronic inks and other electronic devices A display medium in which the contrast changes due to thermal effects can also be applied.

[0189] The display device includes a panel in which a display element is sealed, and a controller for the panel. and a module in which an IC or the like including the above is mounted. In the process, the element substrate corresponds to one form before the display element is completed, and the element substrate is The element substrate is provided with a means for supplying a current to the display element in each of the plurality of pixels. The display element may be in a state where only the pixel electrodes of the display element are formed, or a conductive film that becomes the pixel electrodes may be formed. may be in a state after the formation of a film and before etching to form a pixel electrode, All forms apply.

[0190] In this specification, the term "display device" refers to an image display device, a display device, or an optical Also refers to connectors, such as FPC (Flexible Printed Circuit). inted circuit) or TAB (Tape Automated Bon ding tape or TCP (Tape Carrier Package) is used. Modules with printed wiring boards attached to the ends of TAB tape or TCP or the display element is mounted with an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which a display circuit (or other circuit) is directly mounted.

[0191] In this embodiment mode, the appearance and cross section of a liquid crystal display panel, which is one mode of a semiconductor device, will be described. Next, it will be described with reference to FIG. 22. FIGS. 22(A1) and (A2) show the In-Ga-Zn-O based non-single crystal films shown in Embodiments 1 to 4 formed on the first substrate 4001 and included as an oxide semiconductor layer in highly reliable thin film transistors 4010, 4011, and a liquid crystal element 4013, which are sealed with a sealing material 4005 between the second substrate 4006. It is a top view of the panel, and FIG. 22(B) corresponds to a cross-sectional view taken along M-N in FIGS. 22(A1) and (A2).

[0192] The sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004. Also, the second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with the liquid crystal layer 4008 by the first substrate 4001, the sealing material 4005, and the second substrate 4006. Further, a signal line driving circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted on a separately prepared substrate in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. Note that the connection method of the separately formed driving circuit is not particularly limited, and a COG method, a wire bonding method, or a TAB method can be used. FIG. 22(A1) is an example in which the signal line driving circuit 4003 is mounted by the COG method, and FIG. 22(A2) is an example in which the signal line driving circuit 4003 is mounted by the TAB method.

[0193]

[0194] Also, the pixel portion 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004 It has a plurality of thin film transistors. In FIG. 22(B), the thin films included in the pixel portion 4002 include the thin film transistor 4010 and the thin film transistor 4011 included in the scanning line driving circuit 4004 are exemplified. Insulating layers 4020 and 402 1 are provided on the thin film transistors 4010 and 4011.

[0195] The thin film transistors 4010 and 4011 are highly reliable thin film transistors including an In- Ga-Zn-O based non-single crystal film as an oxide semiconductor layer as shown in Embodiments 1 to 4 can be applied. In this embodiment, the thin film transistors 4010 and 4011 are n-channel type thin film transistors.

[0196] Also, the pixel electrode layer 4030 of the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. And the counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 40 06. The portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap corresponds to the liquid crystal element 4013. Note that insulating layers 4032 and 4033 that function as alignment films are provided on the pixel electrode layer 4030 and the counter electrode layer 4031, respectively, and the liquid crystal layer 4008 is sandwiched via the insulating layers 4032 and 4033. Note that as the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless steel), ceramics, or plastic can be used. As the plastic,

[0197] for example, an FRP (Fiberglass-Reinforced Plastics) plate, a PV F (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. As the plastic, for example, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. Rum can be used. Also, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film can also be used.

[0198] Also, 4035 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. Note that a spherical spacer may be used. Also, the counter electrode layer 4031 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. Using a common connection portion, the counter electrode layer 40 31 and the common potential line can be electrically connected via conductive particles disposed between a pair of substrates. Note that the conductive particles are contained in the sealing material 40 05.

[0199] Also, a liquid crystal showing a blue phase that does not use an alignment film may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the cholesteric liquid crystal transitions from the cholesteric phase to the isotropic phase when the temperature is raised. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition in which 5 wt% or more of a chiral agent is mixed is used for the liquid crystal layer 4008 in order to improve the temperature range. The liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a response speed as short as 10 μs to 100 μs, is optically isotropic, does not require an alignment process, and has little viewing angle dependence. 100 μs, is optically isotropic, does not require an alignment process, and has little viewing angle dependence.

[0200] Note that this embodiment is an example of a transmissive liquid crystal display device, but it can also be applied to a reflective liquid crystal display device or a transflective liquid crystal display device.

[0201] Also, in the liquid crystal display device of this embodiment, a polarizing plate is provided on the outside (viewing side) of the substrate, and on the inside ​​​An example is shown in which the layers are provided in the order of a colored layer and an electrode layer used for a display element. The polarizing plate may be provided inside the substrate. Also, the laminated structure of the polarizing plate and the colored layer is not limited to the present embodiment, and may be appropriately set according to the materials and manufacturing process conditions of the polarizing plate and the colored layer. Further, a light-shielding film functioning as a black matrix may be provided.

[0202] Also, in the present embodiment, in order to reduce the surface unevenness of the thin film transistor and improve the reliability of the thin film transistor, the thin film transistors obtained in Embodiments 1 to 4 are used as a protective film or an insulating layer (insulating layer 4020, insulating layer 4021 ) that functions as a planarizing insulating film. The protective film is for preventing the intrusion of contaminating impurities such as organic substances, metal substances, and water vapor floating in the air, and a dense film is preferable. The protective film may be formed as a single layer or a laminate of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film using a sputtering method. In the present embodiment, an example of forming the protective film by a sputtering method is shown, but it is not particularly limited and may be formed by various methods.

[0203] Here, an insulating layer 4020 having a laminated structure is formed as the protective film. Here, a silicon oxide film is formed as the first layer of the insulating layer 402 0 using a sputtering method. When a silicon oxide film is used as the protective film, it is effective in preventing the hillock of the aluminum film used as the source electrode layer and the drain electrode layer.

[0204] Also, an insulating layer is formed as the second layer of the protective film. Here, an insulating layer is formed as the second layer of the insulating layer 4020 ​​​​​​​​​​​Then, a silicon nitride film is formed using a sputtering method. The silicon nitride film is used as a protective film. When a silicon nitride film is used, it is possible to suppress the intrusion of mobile ions such as sodium into the semiconductor region and the change in the electrical characteristics of the TFT.

[0205] Further, after forming the protective film, annealing (300°C to 400°C) of the oxide semiconductor layer may be performed.

[0206] Also, an insulating layer 4021 is formed as a planarization insulating film. As the insulating layer 4021, heat-resistant organic materials such as polyimide, acrylic, benzocyclobutene, polyamide, and epoxy can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane-based resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used. Note that the insulating layer 4021 may be formed by laminating a plurality of insulating films formed of these materials.

[0207] The siloxane-based resin corresponds to a resin containing a Si-O-Si bond formed using a siloxane-based material as a starting material. The siloxane-based resin may use an organic group (e.g., an alkyl group or an aryl group) or a fluoro group as a substituent. Also, the organic group may have a fluoro group.

[0208] The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, a sputtering method, a SOG method, spin coating, dipping, spray coating, droplet discharge method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. can be used. When the insulating layer 4021 is formed using a material solution, ​​​​​​​​​At the same time as the step of baking, annealing of the oxide semiconductor layer (300°C to 400°C) may be performed. Yes. By combining the firing step of the insulating layer 4021 and the annealing of the oxide semiconductor layer, it becomes possible to efficiently fabricate a semiconductor device.

[0209] The pixel electrode layer 4030 and the counter electrode layer 4031 can be made of a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, etc.

[0210] Further, the pixel electrode layer 4030 and the counter electrode layer 4031 can be formed using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). The pixel electrode formed using the conductive composition preferably has a sheet resistance of 10,000 Ω / sq or less and a light transmittance of 70% or more at a wavelength of 550 nm. Also, the resistivity of the conductive polymer contained in the conductive composition is preferably 0.1 Ω·cm or less.

[0211] As the conductive polymer, so-called π-electron conjugated conductive polymers can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers of two or more of these can be mentioned.

[0212] In addition, various signals and potentials given to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004 or the pixel portion 4002 are supplied from the FPC 4018.

[0213] In this embodiment, the connection terminal electrode 4015 is formed of the same conductive film as the pixel electrode layer 40 30 included in the liquid crystal element 4013, and the terminal electrode 4016 is formed of the same conductive film as the source electrode layer and the drain electrode layer of the thin film transistors 4010, 40 11.

[0214] The connection terminal electrode 4015 is electrically connected to the terminal included in the FPC 4018 via the anisotropic conductive film 4019.

[0215] In addition, FIG. 22 shows an example in which the signal line driving circuit 4003 is separately formed and mounted on the first substrate 4001, but the present embodiment is not limited to this configuration. The scanning line driving circuit may be separately formed and mounted, or a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted.

[0216] FIG. 23 shows an example of configuring a liquid crystal display module as a semiconductor device using the TFT substrate 2600 manufactured by applying the TFTs shown in Embodiments 1 to 4.

[0217] FIG. 23 is an example of a liquid crystal display module, in which the TFT substrate 2600 and the counter substrate 2601 are fixed by a sealing material 2602, and a pixel portion 2603 including a TFT or the like, a display element 2604 including a liquid crystal layer, and a coloring layer 2605 are provided therebetween to form a display region. The coloring layer 2605 is necessary when performing color display. In the case of the RGB system, coloring layers corresponding to red, green, and blue colors are provided corresponding to each pixel. On the outside of the TFT substrate 2600 and the counter substrate 2601, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are disposed. The light source is composed of a cold cathode tube 2610 and a reflector 2611, and the circuit board 2612 is a flexible wiring board. It is connected to the wiring circuit portion 2608 of the TFT substrate 2600 by the wiring substrate 2609, and external circuits such as a control circuit and a power supply circuit are incorporated. Further, it may be laminated in a state having a retardation plate between the polarizing plate and the liquid crystal layer.

[0218] The liquid crystal display module may use a TN (Twisted Nematic) mode, an IPS (I n-Plane-Switching) mode, an FFS (Fringe Field S witching) mode, an MVA (Multi-domain Vertical A lignment) mode, a PVA (Patterned Vertical Alig nment) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated B irefringence) mode, an FLC (Ferroelectric Liqui d Crystal) mode, an AFLC (AntiFerroelectric Liq uid Crystal) mode, etc.

[0219] Through the above steps, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device.

[0220] Note that the configuration shown in this embodiment can be used by appropriately combining the configurations shown in other embodiments.

[0221] (Embodiment 7) In this embodiment, an example of electronic paper is shown as a semiconductor device to which the thin film transistors shown in Embodiments 1 to 4 are applied.

[0222] ​​​​FIG. 13 shows an active matrix type electronic paper as an example of a semiconductor device. The semiconductor thin film transistors 581 used in the device can be the thin film transistors shown in Embodiments 1 to 4.

[0223] The electronic paper in FIG. 13 is an example of a display device using a twist ball display method. The twist ball display method is a method of performing display by arranging spherical particles painted white and black between a first electrode layer and a second electrode layer that are used as display elements, and causing a potential difference between the first electrode layer and the second electrode layer to control the orientation of the spherical particles.

[0224] The thin film transistor 581 sealed between the substrate 580 and the substrate 596 is a thin film transistor with a bottom gate structure, and is in contact with and electrically connected to the first electrode layer 58 7 through openings formed in the source electrode layer or the drain electrode layer and the insulating layers 583, 584, 585. Between the first electrode layer 587 and the second electrode layer 588, there are provided spherical particles 589 having black regions 590a and white regions 5 90b and including a cavity 594 filled with a liquid around them, and the periphery of the spherical particles 589 is filled with a filler 595 such as resin (see FIG. 13). In this embodiment, the first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. The second electrode layer 588 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 581. Using a common connection portion, the second electrode layer 588 and the common potential line can be electrically connected via conductive particles disposed between the pair of substrates.

[0225] ​​​​​​​​​Also, it is possible to use an electrophoretic element instead of the twist ball. A transparent liquid is filled with positively charged white fine particles and negatively charged black fine particles, and microcapsules with a diameter of about 10 μm to 20 0 μm are used. The microcapsules provided between the first electrode layer and the second electrode layer will cause the white fine particles and the black fine particles to move in opposite directions when an electric field is applied by the first electrode layer and the second electrode layer, and can display white or black. The display element applying this principle is an electrophoretic display element, which is generally called electronic paper. Since the electrophoretic display element has a higher reflectance than a liquid crystal display element, an auxiliary light is not required and the power consumption is small, and it is possible to recognize the display portion even in a dim place. Also even when power is not supplied to the display portion, it is possible to hold the image once displayed. Therefore, even when the semiconductor device with a display function (also simply called a display device or a semiconductor device equipped with a display device) is moved away from the radio wave transmission source it is possible to save the displayed image.

[0226] Through the above steps, a highly reliable electronic paper can be manufactured as a semiconductor device.

[0227] Note that the configuration shown in this embodiment can be used by appropriately combining the configurations shown in other embodiments.

[0228] (Embodiment 8) In this embodiment, an example of a light-emitting display device is shown as a semiconductor device to which the thin film transistors shown in Embodiments 1 to 4 are applied. As the display element of the display device, here it is shown using a light-emitting element that utilizes electroluminescence. Electroluminescence ​ The light-emitting elements using are classified according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter is called an inorganic EL element.

[0229] In an organic EL element, when a voltage is applied to the light-emitting element, electrons and holes are injected from a pair of electrodes into a layer containing a light-emitting organic compound, respectively, and a current flows. Then, when these carriers (electrons and holes) recombine, the light-emitting organic compound forms an excited state, and light is emitted when the excited state returns to the ground state. From such a mechanism, such a light-emitting element is called a current-excited type light-emitting element.

[0230] Inorganic EL elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements according to their element structures. A dispersed inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light-emitting mechanism is donor-acceptor recombination type light emission that utilizes donor levels and acceptor levels. A thin-film inorganic EL element has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light-emitting mechanism is localized light emission that utilizes inner-shell electron transitions of metal ions. Here, an organic EL element is used as the light-emitting element for explanation.

[0231] FIG. 20 is a diagram showing an example of a pixel configuration applicable to digital time-graded driving as an example of a semiconductor device to which an aspect of the present invention is applied.

[0232] The configuration of a pixel applicable to digital time-graded driving and the operation of the pixel will be described. Here, the oxide semiconductor layer (In-Ga-Zn-O system) shown in Embodiments 1 to 4 An n-channel transistor using a non-single crystal film) in the channel formation region is provided in one pixel. An example of using two is shown.

[0233] Pixel 6400 includes a switching transistor 6401, a driving transistor 6402, a light emitting element 6404, and a capacitive element 6403. The switching transistor 64 01 has its gate connected to the scanning line 6406, and a first electrode (either the source electrode or the drain electrode) is connected to the signal line 6405, and a second electrode (the other of the source electrode and the drain electrode) is connected to the gate of the driving transistor 6402. The driving transistor 6402 has its gate connected to the power supply line 6407 via the capacitive element 6403, a first electrode connected to the power supply line 640 7, and a second electrode connected to the first electrode (pixel electrode) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate, and the connection portion is used as a common connection portion. It may have the structure shown in FIG. 1(A), FIG. 2(A), or FIG. 3(A).

[0234] Note that a low power supply potential is set for the second electrode (common electrode 6408) of the light emitting element 6404. Note that the low power supply potential is a potential lower than the high power supply potential set on the power supply line 6407, and the low power supply potential < a potential that satisfies the high power supply potential, and for example, GND, 0V, etc. may be set as the low power supply potential. A potential difference between this high power supply potential and the low power supply potential is applied to the light emitting element 6404 to cause a current to flow through the light emitting element 6404 and make the light emitting element 6404 emit light. Therefore, the potential difference between the high power supply potential and the low power supply potential is set so as to be equal to or higher than the forward threshold voltage of the light emitting element 6404. Each potential is set accordingly.

[0235] Incidentally, the capacitive element 6403 can be omitted by substituting the gate capacitance of the driving transistor 6402. Regarding the gate capacitance of the driving transistor 6402, a capacitance may be formed between the channel region and the gate electrode.

[0236] Here, in the case of the voltage input voltage drive method, a video signal is input to the gate of the driving transistor 6402 such that the driving transistor 6402 is in one of two states: fully on or fully off. That is, the driving transistor 6402 operates in the linear region. To operate the driving transistor 6402 in the linear region, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the driving transistor 6402. Incidentally, a voltage equal to or higher than (the power supply line voltage + the Vth of the driving transistor 6402) is applied to the signal line 6405. Since the driving transistor 6402 operates in the linear region, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the driving transistor 6402. Incidentally, a voltage equal to or higher than (the power supply line voltage + the Vth of the driving transistor 6402) is applied to the signal line 6405. Since the driving transistor 6402 operates in the linear region, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the driving transistor 6402. Incidentally, a voltage equal to or higher than (the power supply line voltage + the Vth of the driving transistor 6402) is applied to the signal line 6405. (Power supply line voltage + Vth of the driving transistor 6402) or higher voltage is applied.

[0237] Also, when performing analog gradation driving instead of digital time gradation driving, the same pixel configuration as in FIG. 20 can be used by changing the signal input. Also, when performing analog gradation driving instead of digital time gradation driving, the same pixel configuration as in FIG. 20 can be used by changing the signal input.

[0238] When performing analog gradation driving, a voltage equal to or higher than the forward voltage of the light emitting element 6404 + the Vth of the driving transistor 6402 is applied to the gate of the driving transistor 6402. The forward voltage of the light emitting element 64 04 refers to the voltage for a desired luminance and includes at least the forward threshold voltage. Incidentally, a video signal is input such that the driving transistor 6402 operates in the saturation region, thereby allowing current to flow through the light emitting element 6404. To operate the driving transistor 6402 in the saturation region, the potential of the power supply line 6407 is 04 refers to the voltage for a desired luminance and includes at least the forward threshold voltage. Incidentally, a video signal is input such that the driving transistor 6402 operates in the saturation region, thereby allowing current to flow through the light emitting element 6404. To operate the driving transistor 6402 in the saturation region, the potential of the power supply line 6407 is 04 refers to the voltage for a desired luminance and includes at least the forward threshold voltage. Incidentally, a video signal is input such that the driving transistor 6402 operates in the saturation region, thereby allowing current to flow through the light emitting element 6404. To operate the driving transistor 6402 in the saturation region, the potential of the power supply line 6407 is 04 refers to the voltage for a desired luminance and includes at least the forward threshold voltage. Incidentally, a video signal is input such that the driving transistor 6402 operates in the saturation region, thereby allowing current to flow through the light emitting element 6404. To operate the driving transistor 6402 in the saturation region, the potential of the power supply line 6407 is such that the driving transistor 6402 operates in the saturation region. To operate the driving transistor 6402 in the saturation region, the potential of the power supply line 6407 is Make it higher than the gate potential of the terminal 6402. By using an analog video signal, a current corresponding to the video signal can be passed through the light-emitting element 6404, and analog gradation driving can be performed.

[0239] Note that the pixel configuration shown in FIG. 20 is not limited to this. For example, a new switch, resistor element, capacitor element, transistor, or logic circuit may be added to the pixel shown in FIG. 20.

[0240] Next, the configuration of the light-emitting element will be described with reference to FIG. 21. Here, the case where the driving TFT is of the n type will be taken as an example to describe the cross-sectional structure of the pixel. In FIGS. 21(A), (B), and (C), the driving TFTs TFT7001, 7011, and 7021 used in the semiconductor device can be manufactured in the same manner as the thin-film transistors shown in Embodiments 1 to 4, and are highly reliable thin-film transistors including an In-Ga-Z n-O-based non-single crystal film as an oxide semiconductor layer. For the light-emitting element, at least one of the anode and the cathode may be transparent in order to extract light. Thus, a thin-film transistor and a light-emitting element are formed on the substrate, and top emission that extracts light from the surface opposite to the substrate, bottom emission that extracts light from the surface on the substrate side, or a light-emitting element having a double-sided emission structure that extracts light from the surface on the substrate side and the surface opposite to the substrate. The pixel configuration according to one aspect of the present invention can be applied to any light-emitting element having an emission structure.

[0241] The light-emitting element may have at least one of the anode and the cathode transparent in order to extract light. Thus, a thin-film transistor and a light-emitting element are formed on the substrate, and top emission that extracts light from the surface opposite to the substrate, bottom emission that extracts light from the surface on the substrate side, or a light-emitting element having a double-sided emission structure that extracts light from the surface on the substrate side and the surface opposite to the substrate. The pixel configuration according to one aspect of the present invention can be applied to any light-emitting element having an emission structure. Then, a thin-film transistor and a light-emitting element are formed on the substrate, and top emission that extracts light from the surface opposite to the substrate, bottom emission that extracts light from the surface on the substrate side, or a light-emitting element having a double-sided emission structure that extracts light from the surface on the substrate side and the surface opposite to the substrate. The pixel configuration according to one aspect of the present invention can be applied to any light-emitting element having an emission structure. There are top emission, bottom emission, and double-sided emission structures for extracting light from the surface opposite to the substrate, the surface on the substrate side, and the surface on the substrate side and the surface opposite to the substrate, respectively. The pixel configuration according to one aspect of the present invention can be applied to any light-emitting element having an emission structure. There are top emission, bottom emission, and double-sided emission structures for extracting light from the surface opposite to the substrate, the surface on the substrate side, and the surface on the substrate side and the surface opposite to the substrate, respectively. The pixel configuration according to one aspect of the present invention can be applied to any light-emitting element having an emission structure. The light-emitting element having a top emission structure will be described with reference to FIG. 21(A).

[0242] The light-emitting element having a top emission structure will be described with reference to FIG. 21(A).

[0243] FIG. 21(A) shows a cross-sectional view of a pixel when the driving TFT, TFT7001, is of the n-type and the light emitted from the light-emitting element 7002 escapes to the anode 7005 side. In FIG. 21(A), a cross-sectional view of the pixel is shown when the driving TFT, TFT7001, is of the n-type and the light emitted from the light-emitting element 7002 escapes to the anode 7005 side. The cathode 7003 of the light-emitting element 7002 and the driving TFT 7001 are electrically connected. On the cathode 7003, a light-emitting layer 7004 and an anode 7005 are sequentially laminated. The cathode 7003 can be made of various materials as long as it is a conductive film with a low work function and that reflects light. For example, Ca, Al, MgAg, AlLi, etc. are desirable. And the light-emitting layer 7 004 may be composed of a single layer or may be configured such that a plurality of layers are laminated. When it is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are laminated in this order on the cathode 7003. Note that it is not necessary to provide all of these layers. The anode 7005 is formed using a conductive material having light-transmitting properties that transmit light, for example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, or a conductive film having light-transmitting properties such as indium tin oxide added with silicon oxide may be used.

[0244] The region sandwiching the light-emitting layer 7004 between the cathode 7003 and the anode 7005 corresponds to the light-emitting element 7002. In the case of the pixel shown in Fig. 21(A), the light emitted from the light-emitting element 7002 is emitted toward the anode 7005 side as indicated by the arrow.

[0245] Next, a light-emitting element with a bottom emission structure will be described with reference to Fig. 21(B). When the driving TFT 7 011 is n-type and the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013 side, a cross-sectional view of the pixel is shown. In Fig. 21(B), the driving TFT 7011 is electrically connected to On a conductive film 7017 having translucency, a cathode 7013 of a light-emitting element 7012 is formed , and a light-emitting layer 7014 and an anode 7015 are sequentially laminated on the cathode 7013. When the anode 7 015 has translucency, a shielding film 7016 for reflecting or shielding light may be formed so as to cover the anode . The cathode 7013 can be made of various materials as long as they are conductive materials with a low work function, similar to the case of Fig. 21(A). However, the film thickness should be such that light can pass through it (preferably about 5 nm to 30 nm). For example, an aluminum film with a film thickness of 20 nm can be used as the cathode 7013. And the light-emitting layer 7 014 may be composed of a single layer or may be configured such that a plurality of layers are laminated, similar to Fig. 21(A). The anode 7015 does not necessarily need to transmit light, but it can be formed using a translucent conductive material, similar to Fig 21(A). And the shielding film 7016 can be made of, for example, a metal that reflects light, etc., but is not limited to a metal film . For example, a resin added with a black pigment can also be used. . The region where the cathode 7013 and the anode 7015 sandwich the light-emitting layer 7014 corresponds to the light-emitting element 7012 . In the case of the pixel shown in Fig. 21(B), the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013 side as indicated by the arrow .

[0246]

[0247] Next, a light-emitting element with a double-sided emission structure will be described with reference to Fig. 21(C). In Fig. 21(C) , on a conductive film 7027 having translucency and electrically connected to a driving TFT 7021, a cathode 7023 of a light-emitting element 7022 is formed, and a light-emitting layer 7024 is formed on the cathode 7023 , The anodes 7025 are stacked in order. The cathode 7023 can be made of various conductive materials as long as the work function is small. However, the film thickness should be such that light can pass through. For example, Al with a film thickness of 20 nm can be used as the cathode 7023. And the light-emitting layer 7024 can be composed of a single layer or multiple stacked layers, just like in Fig. 21(A). The anode 7025 can be formed using a conductive material with light-transmitting properties, similar to Fig. 21(A). Any material can be used as long as it is a conductive material with a small work function. However, the film thickness should be such that light can pass through. For example, Al with a film thickness of 20 nm can be used as the cathode 7023. And the light-emitting layer 7024 can be composed of a single layer or multiple stacked layers, just like in Fig. 21(A). The anode 7025 can be formed using a conductive material with light-transmitting properties, similar to Fig. 21(A). Any material can be used as long as it is a conductive material with a small work function. However, the film thickness should be such that light can pass through. For example, Al with a film thickness of 20 nm can be used as the cathode 7023. And the light-emitting layer 7024 can be composed of a single layer or multiple stacked layers, just like in Fig. 21(A). The anode 7025 can be formed using a conductive material with light-transmitting properties, similar to Fig. 21(A). Any material can be used as long as it is a conductive material with a small work function. However, the film thickness should be such that light can pass through. For example, Al with a film thickness of 20 nm can be used as the cathode 7023. And the light-emitting layer 7024 can be composed of a single layer or multiple stacked layers, just like in Fig. 21(A). The anode 7025 can be formed using a conductive material with light-transmitting properties, similar to Fig. 21(A). Any material can be used as long as it is a conductive material with a small work function. However, the film thickness should be such that light can pass through. For example, Al with a film thickness of 20 nm can be used as the cathode 7023. And the light-emitting layer 7024 can be composed of a single layer or multiple stacked layers, just like in Fig. 21(A). The anode 7025 can be formed using a conductive material with light-transmitting properties, similar to Fig. 21(A). Any material can be used as long as it is a conductive material with a small work function. However, the film thickness should be such that light can pass through. For example, Al with a film thickness of 20 nm can be used as the cathode 7023. And the light-emitting layer 7024 can be composed of a single layer or multiple stacked layers, just like in Fig. 21(A). The anode 7025 can be formed using a conductive material with light-transmitting properties, similar to Fig. 21(A). Any material can be used as long as it is a conductive material with a small work function. However, the film thickness should be such that light can pass through. For example, Al with a film thickness of 20 nm can be used as the cathode 7023. And the light-emitting layer 7024 can be composed of a single layer or multiple stacked layers, just like in Fig. 21(A). The anode 7025 can be formed using a conductive material with light-transmitting properties, similar to Fig. 21(A).

[0248] The overlapping part of the cathode 7023, the light-emitting layer 7024, and the anode 7025 corresponds to the light-emitting element 7022. In the case of the pixel shown in Fig. 21(C), the light emitted from the light-emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as indicated by the arrows. The overlapping part of the cathode 7023, the light-emitting layer 7024, and the anode 7025 corresponds to the light-emitting element 7022. In the case of the pixel shown in Fig. 21(C), the light emitted from the light-emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as indicated by the arrows. The overlapping part of the cathode 7023, the light-emitting layer 7024, and the anode 7025 corresponds to the light-emitting element 7022. In the case of the pixel shown in Fig. 21(C), the light emitted from the light-emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as indicated by the arrows.

[0249] Here, although the light-emitting element is described as an organic EL element, it is also possible to provide an inorganic EL element as the light-emitting element. Here, although the light-emitting element is described as an organic EL element, it is also possible to provide an inorganic EL element as the light-emitting element.

[0250] In this embodiment, an example where a thin-film transistor (driving TFT) for controlling the driving of the light-emitting element is electrically connected to the light-emitting element is shown. However, a configuration in which a current control TFT is connected between the driving TFT and the light-emitting element may also be used. In this embodiment, an example where a thin-film transistor (driving TFT) for controlling the driving of the light-emitting element is electrically connected to the light-emitting element is shown. However, a configuration in which a current control TFT is connected between the driving TFT and the light-emitting element may also be used. In this embodiment, an example where a thin-film transistor (driving TFT) for controlling the driving of the light-emitting element is electrically connected to the light-emitting element is shown. However, a configuration in which a current control TFT is connected between the driving TFT and the light-emitting element may also be used.

[0251] The semiconductor device shown in this embodiment is not limited to the configuration shown in Fig. 21, and various modifications based on the technical idea of the present invention are possible. The semiconductor device shown in this embodiment is not limited to the configuration shown in Fig. 21, and various modifications based on the technical idea of the present invention are possible.

[0252] Next, an example of a semiconductor device to which the thin-film transistors shown in Embodiments 1 to 4 are applied Regarding the appearance and cross-section of a light-emitting display panel (also referred to as a light-emitting panel) corresponding to the form, refer to FIG. 24 for explanation. FIG. 24(A) is a top view of the panel in which thin-film transistors and light-emitting elements formed on the first substrate are sealed with a sealing material between the second substrate, and FIG. 2 4(B) corresponds to the cross-sectional view at H-I in FIG. 24(A).

[0253] A sealing material 4505 is provided so as to surround the pixel portion 4502, signal line driving circuits 4503a, 450 3b, and scanning line driving circuits 4504a, 4504b provided on the first substrate 4501. Further, a second substrate 4506 is provided on the pixel portion 4502, signal line driving circuits 4503a, 4503b, and scanning line driving circuits 4504a, 4504b. Thus, the pixel portion 4502, signal line driving circuits 4503a, 4503b, and scanning line driving circuits 45 04a, 4504b are sealed together with the filling material 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506. In this way, it has high airtightness so as not to be exposed to the outside air, and it is preferable to package (encase) it with a protective film (bonding film, ultraviolet curable resin film, etc.) with little outgassing or a cover material.

[0254] Also, the pixel portion 4502, signal line driving circuits 4503a, 4 503b, and scanning line driving circuits 4504a, 4504b provided on the first substrate 4501 have a plurality of thin-film transistors. In FIG. 24(B), the thin-film transistor 4510 included in the pixel portion 4502 and the thin-film transistor 4509 included in the signal line driving circuit 4503a are illustrated.

[0255] The thin-film transistors 4509, 4510 are those shown in Embodiments 1 to 4, In-​​​​​​​​ A highly reliable thin film transistor including a Ga-Zn-O based non-single crystal film as an oxide semiconductor layer can be applied. In this embodiment, the thin film transistors 4509 and 4510 are n-channel type thin film transistors.

[0256] Also, 4511 corresponds to a light emitting element, and the first electrode layer 4517, which is a pixel electrode of the light emitting element 4511, is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. Note that the configuration of the light emitting element 4511 has a laminated structure of the first electrode layer 4517, the electroluminescent layer 4512, and the second electrode layer 4513, but is not limited to the configuration shown in this embodiment. The configuration of the light emitting element 4511 can be appropriately changed according to the direction of the light extracted from the light emitting element 4511 and the like. The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. Particularly, it is preferable to use a photosensitive material to form an opening on the first electrode layer 4517 and form it so that the side wall of the opening becomes an inclined surface formed with a continuous curvature.

[0257] The electroluminescent layer 4512 may be composed of a single layer or may be configured such that a plurality of layers are laminated.

[0258]

[0259] Either way is acceptable.

[0259] A protective film may be formed on the second electrode layer 4513 and the partition wall 4520 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light emitting element 4511. As the protective film, a silicon nitride film, a silicon oxynitride film, a DLC film, etc. can be formed.

[0260] Also, the signal line drive circuits 4503a and 4503b, and the scan line drive circuits 4504a and 4504b Moreover, various signals and potentials supplied to the pixel portion 4502 are supplied from the FPCs 4518a and 4518 b.

[0261] In the present embodiment, the connection terminal electrode 4515 is formed of the same conductive film as the first electrode layer 4 517 of the light-emitting element 4511, and the terminal electrode 4516 is formed of the same conductive film as the source electrode layer and the drain electrode layer of the thin-film transistors 4509 and 4 510.

[0262] The connection terminal electrode 4515 is electrically connected to the terminal of the FPC 4518a through the anisotropic conductive film 4519 .

[0263] The second substrate 4506 positioned in the light extraction direction of the light from the light-emitting element 4511 must be translucent . In that case, a translucent material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used.

[0264] Moreover, as the filling material 4507, in addition to inert gases such as nitrogen and argon, an ultraviolet-curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EV A (ethylene vinyl acetate) can be used. In the present embodiment, nitrogen is used as the filling material 4507 .

[0265] Moreover, if necessary, an optical film such as a polarizing plate, a circularly polarizing plate (including an elliptically polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), or a color filter may be appropriately provided on the light-emitting surface of the light-emitting element . Further, an antireflection film may be provided on the polarizing plate or the circularly polarizing plate. For example, due to surface irregularities It is possible to perform an anti-glare process that can diffuse reflected light and reduce reflections.

[0266] The signal line drive circuits 4503a, 4503b, and the scan line drive circuits 4504a, 4504b may be implemented by drive circuits formed of a single-crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate. Also, only the signal line drive circuit, or a part thereof, or only the scan line drive circuit, or a part thereof may be separately formed and implemented, and the present embodiment is not limited to the configuration of FIG. 24. By the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device. By the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device. It should be noted that the configurations shown in the present embodiment can be used by appropriately combining the configurations shown in other embodiments.

[0267] By the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device. It can be manufactured.

[0268] Note that the configurations shown in the present embodiment can be used by appropriately combining the configurations shown in other embodiments. It shall be possible to use them.

[0269] (Embodiment 9) A semiconductor device to which the thin film transistors shown in Embodiments 1 to 4 are applied can be applied as an electronic paper. The electronic paper can be used for electronic devices in any field as long as it can display information. For example, it can be applied to electronic books, posters, in-vehicle advertisements in vehicles such as trains, and displays on various cards such as credit cards. An example of an electronic device is shown in FIGS. 25 and 26. An electronic paper can be used for electronic devices in any field as long as it can display information. For example, using an electronic paper, it can be applied to electronic books, posters, in-vehicle advertisements in vehicles such as trains, and displays on various cards such as credit cards. For example, using an electronic paper, it can be applied to electronic books, posters, in-vehicle advertisements in vehicles such as trains, and displays on various cards such as credit cards. An example of an electronic device is shown in FIGS. 25 and 26. shown.

[0270] FIG. 25(A) shows a poster 2631 made of electronic paper. When the advertising medium is a paper print, the advertisement is replaced manually, but if an electronic paper is used, When the advertising medium is a paper print, the advertisement is replaced manually, but if an electronic paper is used, It is possible to change the display of the advertisement in a short time. Also, a stable image can be obtained without the display being disrupted. Note that the poster may be configured to wirelessly transmit and receive information. In addition, when the advertisement medium is a paper print, the advertisement is exchanged manually, but if electronic paper is used,

[0271] Fig. 25(B) shows an in-vehicle advertisement 2632 in a vehicle such as a train. the display of the advertisement can be changed in a short time without much manual labor. Also, a stable image can be obtained without the display being disrupted. Note that the in-vehicle advertisement may be configured to wirelessly transmit and receive information. In addition, Fig. 26 shows an example of an electronic book 2700. For example, the electronic book 2700 is composed of two housings, a housing 2701 and a housing 2703. The housing 2701 and the housing 2703 are integrated by a shaft portion 2711, and can be opened and closed around the shaft portion 2711.

[0272] With such a configuration, it is possible to perform operations similar to those of a paper book. The housing 2701 incorporates a display unit 2705, and the housing 2703 incorporates a display unit 2707. The display unit 2705 and the display unit 2707 may be configured to display consecutive screens, or may be configured to display different screens. With a configuration to display different screens, for example, text can be displayed on the right display unit (display unit 2705 in Fig. 26), and an image can be displayed on the left display unit

[0273] (display unit 2707 in Fig. 26). In addition, Fig. 26 shows an example in which the housing 2701 is provided with an operation unit and the like. For example, the housing 2 In addition, Fig. 26 shows an example in which the housing 2701 is provided with an operation unit and the like. For example, the housing 2 In addition, Fig. 26 shows an example in which the housing 2701 is provided with an operation unit and the like. For example, the housing 2 (display unit 2707 in Fig. 26).

[0274] In addition, Fig. 26 shows an example in which the housing 2701 is provided with an operation unit and the like. For example, the housing 2 In 701, it is equipped with a power supply 2721, operation keys 2723, a speaker 2725, etc. . Pages can be sent by the operation keys 2723. Note that keys boards, pointing devices, etc. may also be provided on the same surface as the display part of the housing. Also, on the back surface or side surface of the housing, external connection terminals (such as earphone terminals, USB terminals, or terminals connectable to various cables such as an AC adapter and a USB cable), a recording medium insertion part, etc. may be provided. Furthermore, the e - book 2700 may be configured to have a function as an electronic dictionary.

[0275] Also, the e - book 2700 may be configured to be able to wirelessly transmit and receive information. By wireless means, it is possible to purchase and download desired book data, etc. from an e - book server.

[0276] Note that the configurations shown in this embodiment can be used by appropriately combining the configurations shown in other embodiments.

[0277] (Embodiment 10) The semiconductor device using the thin - film transistor shown in Embodiments 1 to 4 can be applied to various electronic devices (including gaming machines). Examples of electronic devices include, for example, a tele vision device (also called a television or a television receiver), monitors for computers, etc., a digital camera, a digital video camera, a digital photo frame, a mobile phone ( also called a cellular phone or a mobile phone device), a portable game machine, a portable information terminal, an audio playback device, a p achinko machine and other large - scale game machines, etc.

[0278] FIG. 27(A) shows an example of a television apparatus 9600. The television apparatus 96 00 has a display unit 9603 incorporated in a housing 9601. The display unit 9603 can display images. Here, a configuration is shown in which the housing 9601 is supported by a stand 9605.

[0279] The operation of the television apparatus 9600 can be performed by operation switches provided in the housing 9601 or by a separate remote controller 9610. Channel and volume operations can be performed by operation keys 9609 provided on the remote controller 9610, and the video displayed on the display unit 9603 can be operated. Further, the remote controller 9610 may be configured to include a

[0280] display unit 9607 for displaying information output from the remote controller 9610. Note that the television apparatus 9600 is configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts, and by connecting to a communication network via a modem, either wired or wirelessly, one-way (from sender to receiver) or two-way

[0281] (between sender and receiver, or between receivers, etc.) information communication is also possible. FIG. 27(B) shows an example of a digital photo frame 9700. For example, the digital photo frame 9700 has a display unit 9703 incorporated in a housing 9701. The display unit 9703 can display various images, and for example, by displaying image data

[0282] taken by a digital camera or the like, it can function in the same way as a normal photo frame.Note that the digital photo frame 9700 includes an operation unit, external connection terminals (such as USB terminals, various terminals connectable to various cables such as USB cables), a recording medium insertion part, etc., and has a configuration including these. These components may be incorporated on the same surface as the display unit, but it is preferable to provide them on the side or back surface because the design will be improved. For example, an image data memory storing image data captured by a digital camera can be inserted into the recording medium insertion part of the digital photo frame to capture the image data and display the captured image data on the display unit 9703. A terminal (such as a terminal connectable to various cables such as a USB cable), etc. These components may be incorporated on the same surface as the display unit, but it is preferable to provide them on the side or back surface because the design will be improved. For example, an image data memory storing image data captured by a digital camera can be inserted into the recording medium insertion part of the digital photo frame to capture the image data and display the captured image data on the display unit 9703. A memory storing image data captured by a digital camera can be inserted into the recording medium insertion part of the digital photo frame to capture the image data and display the captured image data on the display unit 9703. The captured image data can be displayed on the display unit 9703.

[0283] Also, the digital photo frame 9700 may be configured to be able to wirelessly transmit and receive information. It can also be configured to capture and display desired image data wirelessly.

[0284] Figure 28(A) shows a portable gaming machine, which is composed of two housings, a housing 9881 and a housing 9891, and is connected so as to be openable and closable by a connecting part 9893. A display unit 9882 is incorporated in the housing 9881, and a display unit 9883 is incorporated in the housing 9891. Also, the portable gaming machine shown in Figure 28(A) further includes a speaker unit 9884, a recording medium insertion part 9886, an LED lamp 9890, input means (operation keys 9885, connection terminals 9887, a sensor 9888 (including functions for measuring force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9889), etc. Of course, the configuration of the portable gaming machine is not limited to the above, and it may be a configuration including at least a semiconductor device according to one aspect of the present invention, and other accessory equipment may be appropriately provided. A display unit 9882 is incorporated in the housing 9881, and a display unit 9883 is incorporated in the housing 9891. Also, the portable gaming machine shown in Figure 28(A) further includes a speaker unit 9884, a recording medium insertion part 9886, an LED lamp 9890, input means (operation keys 9885, connection terminals 9887, a sensor 9888 (including functions for measuring force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9889), etc. A display unit 9882 is incorporated in the housing 9881, and a display unit 9883 is incorporated in the housing 9891. Also, the portable gaming machine shown in Figure 28(A) further includes a speaker unit 9884, a recording medium insertion part 9886, an LED lamp 9890, input means (operation keys 9885, connection terminals 9887, a sensor 9888 (including functions for measuring force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9889), etc. 888 (including functions for measuring force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays) Of course, the configuration of the portable gaming machine is not limited to the above, and it may be a configuration including at least a semiconductor device according to one aspect of the present invention, and other accessory equipment may be appropriately provided. Including functions for measuring force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays Of course, the configuration of the portable gaming machine is not limited to the above, and it may be a configuration including at least a semiconductor device according to one aspect of the present invention, and other accessory equipment may be appropriately provided. It may be a configuration including at least a semiconductor device according to one aspect of the present invention, and other accessory equipment may be appropriately provided. It can be achieved. The portable gaming machine shown in FIG. 28(A) has a function of reading programs or data recorded on a recording medium and displaying them on a display unit, and a function of sharing information by performing wireless communication with other portable gaming machines. Note that the functions of the portable gaming machine shown in FIG. 28(A) are not limited to this, and it can have various functions. A function of reading programs or data recorded on a recording medium and displaying them on a display unit, and a function of sharing information by performing wireless communication with other portable gaming machines. Note that the functions of the portable gaming machine shown in FIG. 28(A) are not limited to this, and it can have various functions. Note that the functions of the portable gaming machine shown in FIG. 28(A) are not limited to this, and it can have various functions.

[0285] FIG. 28(B) shows an example of a large gaming machine, a slot machine 9900. The slot machine 9900 has a display unit 9903 incorporated in a housing 9901. In addition, the slot machine 9900 is provided with operating means such as a start lever and a stop switch, a coin insertion slot, a speaker, and the like. Of course, the configuration of the slot machine 9900 is not limited to the above, and it may be a configuration including at least a semiconductor device according to one aspect of the present invention, and other accessory equipment may be appropriately provided. The slot machine 9900 has a display unit 9903 incorporated in a housing 9901. In addition, the slot machine 9900 is provided with operating means such as a start lever and a stop switch, a coin insertion slot, a speaker, and the like. Of course, the configuration of the slot machine 9900 is not limited to the above, and it may be a configuration including at least a semiconductor device according to one aspect of the present invention, and other accessory equipment may be appropriately provided. Of course, the configuration of the slot machine 9900 is not limited to the above, and it may be a configuration including at least a semiconductor device according to one aspect of the present invention, and other accessory equipment may be appropriately provided. Of course, the configuration of the slot machine 9900 is not limited to the above, and it may be a configuration including at least a semiconductor device according to one aspect of the present invention, and other accessory equipment may be appropriately provided.

[0286] FIG. 29(A) shows an example of a mobile phone 1000. The mobile phone 1000 includes an operating button 1003, an external connection port 1004, a speaker 1005, a microphone 1006, etc., in addition to a display unit 1002 incorporated in a housing 1001. The mobile phone 1000 includes an operating button 1003, an external connection port 1004, a speaker 1005, a microphone 1006, etc., in addition to a display unit 1002 incorporated in a housing 1001. The mobile phone 1000 includes an operating button 1003, an external connection port 1004, a speaker 1005, a microphone 1006, etc., in addition to a display unit 1002 incorporated in a housing 1001.

[0287] The mobile phone 1000 shown in FIG. 29(A) can input information by touching the display unit 1002 with a finger or the like. Also, operations such as making a call or sending an email can be performed by touching the display unit 1002 with a finger or the like. The mobile phone 1000 shown in FIG. 29(A) can input information by touching the display unit 1002 with a finger or the like. Also, operations such as making a call or sending an email can be performed by touching the display unit 1002 with a finger or the like. The mobile phone 1000 shown in FIG. 29(A) can input information by touching the display unit 1002 with a finger or the like. Also, operations such as making a call or sending an email can be performed by touching the display unit 1002 with a finger or the like.

[0288] The screen of the display unit 1002 mainly has three modes. The first is a display mode mainly for displaying images, the second is an input mode mainly for inputting information such as characters, and the third is a display The screen of the display unit 1002 mainly has three modes. The first is a display mode mainly for displaying images, the second is an input mode mainly for inputting information such as characters, and the third is a display This is a display + input mode in which two modes, namely a mode and an input mode, are mixed.

[0289] For example, when making a phone call or creating an email, the display unit 1002 may be set as the main character input mode, and an input operation on the characters displayed on the screen may be performed. In this case it is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002.

[0290] In addition, by providing a detection device having sensors such as a gyro and an acceleration sensor inside the mobile phone 1000, the orientation (portrait or landscape) of the mobile phone 1000 can be determined, and the screen display of the display unit 1002 can be automatically switched.

[0291] In addition, the switching of the screen mode is performed by touching the display unit 1002 or operating the operation button 1003 of the housing 1001. It can also be switched according to the type of image displayed on the display unit 1002. For example, if the image signal displayed on the display unit is video data, it is switched to the display mode, and if it is text data, it is switched to the input mode.

[0292] In addition, in the input mode, the signal detected by the optical sensor of the display unit 1002 is detected, and when there is no input by touch operation on the display unit 1002 for a certain period, the screen mode may be controlled to be switched from the input mode to the display mode.

[0293] The display unit 1002 can also function as an image sensor. For example, by touching the palm or finger on the display unit 10 02, palm prints, fingerprints, etc. can be imaged to perform personal authentication. ​​​​It can be cut. Also, if a backlight that emits near-infrared light or a light source for a sensor that emits near-infrared light is used in the display unit, it is also possible to image finger veins, palm veins, etc. Using a light source for imaging finger veins, palm veins, etc., it is also possible to image finger veins, palm veins, etc.

[0294] FIG. 29(B) is also an example of a mobile phone. The mobile phone in FIG. 29(B) includes a display device 9410 including a housing 9411, a display unit 9412, and operation buttons 9413, and a communication device 9400 including operation buttons 9402, an external input terminal 9403, a microphone 9404, a speaker 9405, and a light emitting unit 9406 that emits light when receiving an incoming call in a housing 9401. The display device 9410 having a display function is detachable in two directions of the arrow from the communication device 9400 having a telephone function. Therefore, it is possible to attach the short axes of the display device 9410 and the communication device 9400 to each other, or to attach the long axes of the display device 9410 and the communication device 9400 to each other. Also, when only the display function is required, the display device 9410 can be removed from the communication device 9400 and the display device 9410 can be used alone. The communication device 9400 and the display device 9410 can exchange images or input information by wireless communication or wired communication, and each has a rechargeable battery. a display unit 9412, and an operation button 9413, and a communication device 9400 including an operation button 9402, an external input terminal 9403, a microphone 9404, a speaker 9405, and a light emitting unit 9406 that emits light when receiving an incoming call in a housing 9401. The display device 9410 having a display function is detachable in two directions of the arrow from the communication device 9400 having a telephone function. Therefore, it is possible to attach the short axes of the display device 9410 and the communication device 9400 to each other, or to attach the long axes of the display device 9410 and the communication device 9400 to each other. Also, when only the display function is required, the display device 9410 can be removed from the communication device 9400 and the display device 9410 can be used alone. The communication device 9400 and the display device 9410 can exchange images or input information by wireless communication or wired communication, and each has a rechargeable battery. operation buttons 9402, an external input terminal 9403, a microphone 9404, a speaker 9405, and a light emitting unit 9406 that emits light when receiving an incoming call in a housing 9401. The display device 9410 having a display function is detachable in two directions of the arrow from the communication device 9400 having a telephone function. Therefore, it is possible to attach the short axes of the display device 9410 and the communication device 9400 to each other, or to attach the long axes of the display device 9410 and the communication device 9400 to each other. Also, when only the display function is required, the display device 9410 can be removed from the communication device 9400 and the display device 9410 can be used alone. The communication device 9400 and the display device 9410 can exchange images or input information by wireless communication or wired communication, and each has a rechargeable battery. a light emitting unit 9406 that emits light when receiving an incoming call in a housing 9401. The display device 9410 having a display function is detachable in two directions of the arrow from the communication device 9400 having a telephone function. Therefore, it is possible to attach the short axes of the display device 9410 and the communication device 9400 to each other, or to attach the long axes of the display device 9410 and the communication device 9400 to each other. Also, when only the display function is required, the display device 9410 can be removed from the communication device 9400 and the display device 9410 can be used alone. The communication device 9400 and the display device 9410 can exchange images or input information by wireless communication or wired communication, and each has a rechargeable battery. a display device 9410 having a display function is detachable in two directions of the arrow from the communication device 9400 having a telephone function. Therefore, it is possible to attach the short axes of the display device 9410 and the communication device 9400 to each other, or to attach the long axes of the display device 9410 and the communication device 9400 to each other. Also, when only the display function is required, the display device 9410 can be removed from the communication device 9400 and the display device 9410 can be used alone. The communication device 9400 and the display device 9410 can exchange images or input information by wireless communication or wired communication, and each has a rechargeable battery. Therefore, it is possible to attach the short axes of the display device 9410 and the communication device 9400 to each other, or to attach the long axes of the display device 9410 and the communication device 9400 to each other. Also, when only the display function is required, the display device 9410 can be removed from the communication device 9400 and the display device 9410 can be used alone. The communication device 9400 and the display device 9410 can exchange images or input information by wireless communication or wired communication, and each has a rechargeable battery. a display device 9410 and the communication device 9400 to each other, or to attach the long axes of the display device 9410 and the communication device 9400 to each other. Also, when only the display function is required, the display device 9410 can be removed from the communication device 9400 and the display device 9410 can be used alone. The communication device 9400 and the display device 9410 can exchange images or input information by wireless communication or wired communication, and each has a rechargeable battery. When only the display function is required, the display device 9410 can be removed from the communication device 9400 and the display device 9410 can be used alone. The communication device 9400 and the display device 9410 can exchange images or input information by wireless communication or wired communication, and each has a rechargeable battery. When only the display function is required, the display device 9410 can be removed from the communication device 9400 and the display device 9410 can be used alone. The communication device 9400 and the display device 9410 can exchange images or input information by wireless communication or wired communication, and each has a rechargeable battery. The communication device 9400 and the display device 9410 can exchange images or input information by wireless communication or wired communication, and each has a rechargeable battery. a rechargeable battery.

[0295] Note that the configurations shown in this embodiment can be used by appropriately combining the configurations shown in other embodiments. It is assumed that they can be used by appropriately combining the configurations shown in other embodiments.

Example

[0296] In this example, the results of examining the ratio dependence of the conductivity of the oxide semiconductor film on the oxygen gas flow rate ratio during film formation will be described. will be described.

[0297] In this example, an In-Ga-Zn-O-based polycrystalline film was formed using a sputtering method, and the formed The conductivity of the obtained In-Ga-Zn-O based non-single crystal film was measured. The ratio of the oxygen gas flow rate during film formation Samples were prepared under the condition that the ratio was from 0% by volume to 100% by volume, and for each ratio of the oxygen gas flow rate The conductivity of the In-Ga-Zn-O based non-single crystal film was measured. For the measurement of the conductivity, Ag Semiconductor Parameter Analyzer HP4155C manufactured by Agilent Technologies was used.

[0298] In the sputtering film formation of the In-Ga-Zn-O based non-single crystal film, In2 O3:Ga2O3:ZnO = 1:1:1 (In:Ga:Zn = 1:1:0.5) was used as a target A disk-shaped oxide semiconductor target with a diameter of 8 inches mixed in this ratio was used. Other film formation conditions were The distance between the substrate and the target was 170 mm, the film formation gas pressure was 0.4 Pa, and the direct current (DC) power supply was 0.5 kW, and the film formation temperature was room temperature.

[0299] As the film formation gas, argon gas and oxygen gas were used. Film formation was carried out under the condition that the flow rate ratio of oxygen gas to argon gas and oxygen gas was from 0% by volume to 100% by volume, and the conductivity of the In-Ga-Zn -O based non-single crystal film was measured. In addition, in order to perform atomic-level rearrangement of the In-Ga-Zn-O based non-single crystal film, after the film formation of the In-Ga-Zn-O based non-single crystal film, heat treatment was carried out at 350 °C for 1 hour in a nitrogen atmosphere The conductivity of the In-Ga-Zn-O based non-single crystal film with respect to each ratio of the oxygen gas flow rate was as shown in Fig. 12 In Fig. 12, the horizontal axis is the ratio (% by volume) of the oxygen gas flow rate to the argon gas flow rate and the oxygen gas flow rate, and the vertical axis is the conductivity (S / cm) of the In-Ga-Zn-O based non-single crystal film. Also, the flow rate (sccm) of the argon gas corresponding to Fig. 12, the flow of the oxygen gas

[0300] The conductivity of the In-Ga-Zn-O based non-single crystal film with respect to each ratio of the oxygen gas flow rate was as shown in Fig. 12 In Fig. 12, the horizontal axis is the ratio (% by volume) of the oxygen gas flow rate to the argon gas flow rate and the oxygen gas flow rate, and the vertical axis is the conductivity (S / cm) of the In-Ga-Zn-O based non-single crystal film. Also, the flow rate (sccm) of the argon gas corresponding to Fig. 12, the flow of the oxygen gas cm) of the In-Ga-Zn-O based non-single crystal film. Also, the flow rate (sccm) of the argon gas corresponding to Fig. 12, the flow of the oxygen gas Amount (sccm), oxygen gas flow rate (volume %) and In-Ga-Zn-O non-single crystal film The electrical conductivity (S / cm) is shown in Table 1.

[0301] [Table 1]

[0302] From the results of FIG. 12 and Table 1, it can be seen that the conductor The conductivity drops sharply, and when the oxygen gas flow rate is between 11.1% by volume and 40% by volume, the conductivity The rate is 1.0 x 10 -5 ~1.0×10 -4 The oxygen gas flow rate is about S / cm. When the oxygen content exceeds 40% by volume, the electrical conductivity tends to decrease gradually. When the gas flow rate is between 60% and 70% by volume, the decrease in conductivity becomes somewhat steeper. Here, the maximum conductivity is obtained when the oxygen gas flow rate is 0% by volume, that is, when the deposition gas is Al. The conductivity is 6.44 S / cm under the condition of only Gongas, and the minimum value is the ratio of oxygen gas flow rate is 100% by volume, that is, the deposition gas is oxygen gas only, the deposition gas is 4.19 × 10 -11 S / cm It is.

[0303] In the graph of Figure 12, the gradient of the conductivity becomes slightly steeper when the oxygen gas flow rate is around 70 volume percent. A first oxide semiconductor region that functions as an active layer and a second oxide semiconductor region that has a higher conductivity than the first oxide semiconductor region are disposed on the boundary of the first oxide semiconductor region. The condition of the oxygen gas flow rate between the second oxide semiconductor region, which functions as a protective layer for the active layer, is set to be low. By dividing the electrodes, the difference in electrical conductivity can be increased. In the fourth embodiment, the first oxide semiconductor region 103 is made of an In—Ga—Zn—O-based When forming a non-single crystal film, the ratio of the oxygen gas flow rate should be less than 70% by volume so that the conductivity is greater than 1. 0×10 -8 S / cm. Also, for the In-Ga-Zn-O-based non-single crystal film used for the second oxide semiconductor region 104 with a lower conductivity than the first oxide semiconductor region, when forming the film, the ratio of the oxygen gas flow rate should be 70% by volume or more so that the conductivity is 1.0× 10 -8 S / cm or less. Further, for the buffer layers 301a and 301b shown in Embodiment 3, since it is preferable that the conductivity is higher than that of the first oxide semiconductor region 103, the ratio of the oxygen gas flow rate should be less than 10% by volume so that the conductivity is greater than 1.0×10 -3 S / cm.

Explanation of Reference Numerals

[0304] 100 Substrate 101 Gate electrode layer 102 Gate insulating layer 103 First oxide semiconductor region 104 Second oxide semiconductor region 105a Source electrode layer or drain electrode layer 105b Source electrode layer or drain electrode layer 107 Protection insulating layer 108 Capacitance wiring 110 Pixel electrode layer 112 First conductive film 112a First conductive film 113 Second conductive film 113a Second conductive film 114 Third conductive film 114a Third conductive film 120 Connection electrode 121 Terminal 122 Terminal 125 Contact hole 126 Contact hole 127 Contact Hole 128 Transparent Conductive Film 129 Transparent Conductive Film 150 Terminal 151 Terminal 152 Gate Insulating Layer 153 Connection Electrode 154 Protection Insulating Film 155 Transparent Conductive Film 156 Electrode 170 Thin Film Transistor 301a Buffer Layer 302 Oxide Semiconductor Film 302a Oxide Semiconductor Film 403a Oxide Film 404a Sidewall Insulating Layer 580 Substrate 596 Substrate 581 Thin Film Transistor 583 Insulating Layer 585 Insulating Layer 587 Electrode Layer 588 Electrode Layer 589 Spherical Particle 590a Black Region 590b White Region 594 Cavity 595 Filling Material 1000 Mobile Phone 1001 Housing 1002 Display Unit 1003 Operation Button 1004 External Connection Port 1005 Speaker 1006 Microphone 2600 TFT Substrate 2601 Opposite Substrate 2602 Sealing Material 2603 Pixel Section 2604 Display Element 2605 Coloring Layer 2606 Polarizing Plate 2607 Polarizing Plate 2608 Wiring Circuit Section 2609 Flexible Wiring Substrate 2610 Cold Cathode Tube 2611 Reflector 2612 Circuit board 2613 Diffuser 2631 Poster 2632 In-vehicle advertisement 2700 E-book 2701 Housing 2703 Housing 2705 Display unit 2707 Display unit 2711 Shaft part 2721 Power supply 2723 Operation key 2725 Speaker 4001 Substrate 4002 Pixel part 4003 Signal line drive circuit 4004 Scanning line drive circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Thin film transistor 4011 Thin film transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 Insulating layer 4021 Insulating layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulating layer 4501 Substrate 4502 Pixel part 4503a Signal line drive circuit 4504a Scanning line drive circuit 4505 Sealing material 4506 Substrate 4507 Filling material 4509 Thin film transistor 4510 Thin film transistor 4511 Light emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4518a FPC 4519 Anisotropic conductive film 4520 Partition wall 5300 Substrate 5301 Pixel section 5302 Scanning line drive circuit 5303 Signal line drive circuit 5400 Substrate 5401 Pixel section 5402 Scanning line drive circuit 5403 Signal line drive circuit 5404 Scanning line drive circuit 5501 Wiring 5502 Wiring 5503 Wiring 5504 Wiring 5505 Wiring 5506 Wiring 5543 Node 5544 Node 5571 Thin film transistor 5572 Thin film transistor 5573 Thin film transistor 5574 Thin film transistor 5575 Thin film transistor 5576 Thin film transistor 5577 Thin film transistor 5578 Thin film transistor 5601 Driver IC 5602 Switch group 5603a Thin film transistor 5603b Thin film transistor 5603c Thin film transistor 5611 Wiring 5612 Wiring 5613 Wiring 5621 Wiring 5701 Flip-flop 5703a Timing 5703b Timing 5703c Timing 5711 Wiring 5712 Wiring 5713 Wiring 5714 Wiring 5715 Wiring 5716 Wiring 5717 Wiring 5721 Signal 5803a Timing 5803b Timing 5803c Timing 5821 Signal 6400 Pixel 6401 Switching Transistor 6402 Driving Transistor 6403 Capacitive Element 6404 Light-Emitting Element 6405 Signal Line 6406 Scanning Line 6407 Power Supply Line 6408 Common Electrode 7001 TFT 7002 Light-Emitting Element 7003 Cathode 7004 Light-Emitting Layer 7005 Anode 7011 Driving TFT 7012 Light-Emitting Element 7013 Cathode 7014 Light-Emitting Layer 7015 Anode 7016 Masking Film 7017 Conductive Film 7021 Driving TFT 7022 Light-Emitting Element 7023 Cathode 7024 Light-Emitting Layer 7025 Anode 7027 Conductive Film 9400 Communication Device 9401 Housing 9402 Operation Button 9403 External Input Terminal 9404 Microphone 9405 Speaker 9406 Light-emitting part 9410 Display device 9411 Housing 9412 Display part 9413 Operation button 9600 Television device 9601 Housing 9603 Display part 9605 Stand 9607 Display part 9609 Operation key 9610 Remote control unit 9700 Digital photo frame 9701 Housing 9703 Display part 9881 Housing 9882 Display part 9883 Display part 9884 Speaker part 9885 Input means (operation key 9886 Recording medium insertion part 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED lamp 9891 Housing 9893 Connecting part 9900 Slot machine 9901 Housing 9903 Display part

Claims

【Claim 1】 a gate electrode layer, a gate insulating layer on the gate electrode layer, a source electrode layer and a drain electrode layer on the gate insulating layer, and an oxide semiconductor layer on the gate insulating layer, the source electrode layer, and the drain electrode layer, wherein the oxide semiconductor layer has a first oxide semiconductor region and a second oxide semiconductor region on the first oxide semiconductor region, the first oxide semiconductor region is in contact with the gate insulating layer, side surfaces of the source electrode layer, and side surfaces of the drain electrode layer, and a conductivity of the second oxide semiconductor region is smaller than a conductivity of the first oxide semiconductor region.

Images