Semiconductor device

Abstract

To provide a semiconductor device with improved performance.SOLUTION: A semiconductor device includes: a substrate; a wall structure which is disposed on the substrate, extends in a first direction, and includes first and second side surfaces facing each other in a second direction intersecting a first direction; a first lower active pattern which is disposed on the first surface and includes a first lower bridge pattern spaced apart from the substrate; a first upper active pattern which is disposed on the first side surface, and includes a first upper bridge pattern spaced further apart from the substrate than the first lower active pattern; a first gate structure which is disposed on the first side surface and intersects the first lower active pattern and the first upper active pattern; a second lower active pattern which is disposed on the second side surface, and includes a second lower bridge pattern spaced apart from the substrate; a second upper active pattern which is disposed on the second side surface, and includes the second upper bridge pattern spaced further apart from the substrate the second lower active pattern; and a second gate structure which is disposed on the second side surface, and intersects the second lower active pattern and the second upper active pattern. Therein a width in the second direction of the wall structure increases away from the substrate.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a stacked multi-gate transistor.

Background Art

[0002] As one of the scaling techniques for increasing the density of integrated circuit devices, a multi-gate transistor has been proposed in which a silicon body in the shape of a fin or a nanowire is formed on a substrate, and a gate is formed on the surface of the silicon body.

[0003] Since such a multi-gate transistor uses a three-dimensional channel, it is easy to scale. In addition, the current control ability can be improved without increasing the gate length of the multi-gate transistor. Moreover, the short channel effect (SCE) in which the potential of the channel region is affected by the drain voltage can be effectively suppressed. Therefore, the development of semiconductor devices using multi-gate transistors has become an issue.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention has been made in view of the problems in the above-described conventional semiconductor devices, and an object of the present invention is to provide a semiconductor device with improved performance.

Means for Solving the Problems

[0005] To achieve the above object, a semiconductor device according to the present invention includes a substrate, a wall structure extending in a first direction on the substrate, the wall structure including a first side surface and a second side surface facing each other in a second direction intersecting the first direction, a first lower active pattern including at least one first lower bridge pattern spaced apart from the substrate on the first side surface, a first upper active pattern including at least one first upper bridge pattern spaced apart from the substrate more than the first lower active pattern on the first side surface, a first gate structure intersecting the first lower active pattern and the first upper active pattern on the first side surface, a second lower active pattern including at least one second lower bridge pattern spaced apart from the substrate on the second side surface, a second upper active pattern including at least one second upper bridge pattern spaced apart from the substrate more than the second lower active pattern on the second side surface, and a second gate structure intersecting the second lower active pattern and the second upper active pattern on the second side surface, and in the second direction, the width of the wall structure increases as it moves away from the substrate.

[0006] Also, a semiconductor device according to the present invention made to achieve the above object includes a substrate, a wall structure extending in a first direction on the substrate, the wall structure including a first side surface and a second side surface facing each other in a second direction intersecting the first direction, a first lower active pattern including at least one first lower bridge pattern spaced apart from the substrate on the first side surface, a first upper active pattern including at least one first upper bridge pattern spaced apart from the substrate more than the first lower active pattern on the first side surface, a first gate structure intersecting the first lower active pattern and the first upper active pattern on the first side surface, a second lower active pattern including at least one second lower bridge pattern spaced apart from the substrate on the second side surface, a second upper active pattern including at least one second upper bridge pattern spaced apart from the substrate more than the second lower active pattern on the second side surface, and a second gate structure intersecting the second lower active pattern and the second upper active pattern on the second side surface. In the second direction, the width of the at least one first upper bridge pattern is smaller than the width of the at least one first lower bridge pattern, and in a third direction intersecting the first direction and the second direction, the thickness of the at least one first upper bridge pattern is larger than the thickness of the at least one first lower bridge pattern.

[0007] Also, a semiconductor device according to the present invention made to achieve the above object includes a substrate, a wall structure extending in a first direction on the substrate, the wall structure including a first side surface and a second side surface facing each other in a second direction intersecting the first direction, a first lower active pattern including at least one first lower bridge pattern separated from the substrate on the first side surface, a first upper active pattern including at least one first upper bridge pattern separated from the substrate more than the first lower active pattern on the first side surface, a first gate structure intersecting the first lower active pattern and the first upper active pattern on the first side surface, a second lower active pattern including at least one second lower bridge pattern separated from the substrate on the second side surface, a second upper active pattern including at least one second upper bridge pattern separated from the substrate more than the second lower active pattern on the second side surface, and a second gate structure intersecting the second lower active pattern and the second upper active pattern on the second side surface, and in the second direction, a width of the at least one first upper bridge pattern is smaller than a width of the at least one first lower bridge pattern, and a number of the at least one first upper bridge pattern is larger than a number of the at least one first lower bridge pattern.

[0008] Also, a semiconductor device according to an embodiment of the present invention includes a substrate including a first region and a second region, a first lower active pattern including at least one first lower bridge pattern separated from the substrate on the first region, a first upper active pattern including at least one first upper bridge pattern separated from the substrate more than the first lower active pattern on the first region, a second lower active pattern including at least one second lower bridge pattern separated from the substrate on the second region, a second upper active pattern including at least one second upper bridge pattern separated from the substrate more than the second lower active pattern on the second region, a wall structure extending in the first direction between the first region and the second region, separating the first lower active pattern and the second lower active pattern, and separating the first upper active pattern and the second upper active pattern, a first gate structure intersecting the first lower active pattern and the first upper active pattern on the first region, a first lower source / drain pattern connected to the first lower active pattern in the first direction on a side surface of the first gate structure, a first upper source / drain pattern connected to the first upper active pattern in the first direction on a side surface of the first gate structure, a second gate structure intersecting the second lower active pattern and the second upper active pattern on the second region, a second lower source / drain pattern connected to the second lower active pattern in the first direction on a side surface of the second gate structure, and a second upper source / drain pattern connected to the second upper active pattern in the first direction on a side surface of the second gate structure. In a second direction intersecting the first direction, a width of the wall structure increases as it moves away from the substrate, and a thickness of the at least one first upper bridge pattern is greater than a thickness of the at least one first lower bridge pattern, or a number of the at least one first upper bridge pattern is greater than a number of the at least one first lower bridge pattern.

[0009] Also, a method of manufacturing a semiconductor device according to an embodiment of the present invention includes providing a substrate including a first region and a second region; forming a first lower active pattern including at least one first lower bridge pattern spaced apart from the substrate on the first region; forming a first upper active pattern including at least one first upper bridge pattern spaced apart from the substrate more than the first lower active pattern on the first region; forming a second lower active pattern including at least one second lower bridge pattern spaced apart from the substrate on the second region; forming a second upper active pattern including at least one second upper bridge pattern spaced apart from the substrate more than the second lower active pattern on the second region; forming a wall structure extending in the first direction between the first region and the second region, separating the first lower active pattern and the second lower active pattern, and separating the first upper active pattern and the second upper active pattern; forming a first gate structure intersecting the first lower active pattern and the first upper active pattern on the first region; and forming a second gate structure intersecting the second lower active pattern and the second upper active pattern on the second region, wherein in a second direction intersecting the first direction, a width of the wall structure increases as it moves away from the substrate.

Advantages of the Invention

[0010] According to the semiconductor device of the present invention, by controlling a channel area of a lower multi-gate transistor and / or an upper multi-gate transistor, a characteristic difference between the lower multi-gate transistor and the upper multi-gate transistor can be minimized.

Brief Description of the Drawings

[0011]

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Embodiments for Carrying Out the Invention

[0012] Next, a specific example of an embodiment for implementing the semiconductor device according to the present invention will be described with reference to the drawings.

[0013] In this specification, first, second, etc. are used to describe various elements and components. Of course, these elements and components are not limited by these terms. These terms are merely used to distinguish one element or component from another. Therefore, the first element or component mentioned below can of course be the second element or component within the technical idea of the present invention. In addition, in this specification, "identical" means not only completely identical but also including minute differences that may occur due to process margins and the like.

[0014] Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 15. FIG. 1 is a layout diagram for explaining a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1, FIGS. 3 and 4 are various enlarged views for explaining the R1 region of FIG. 2, FIG. 5 is a cross-sectional view taken along line B-B of FIG. 1, and FIG. 6 is a cross-sectional view taken along line C-C of FIG. 1.

[0015] Referring to FIGS. 1 to 6, a semiconductor device according to an embodiment of the present invention includes a substrate 100, a first lower active pattern AP11, a first upper active pattern AP12, a second lower active pattern AP21, a second upper active pattern AP22, a wall structure 102, a first base insulating film 104, a second base insulating film 204, a first intermediate insulating film 105, a second intermediate insulating film 205, a field insulating film 106, a first gate structure GS1, a second gate structure GS2, a first gate spacer 140, a second gate spacer 240, a first lower source / drain pattern 160A, a first upper source / drain pattern 160B, a second lower source / drain pattern 260A, a second upper source / drain pattern 260B, an interlayer insulating film 180, a first gate contact CB1, and a second gate contact CB2.

[0016] The substrate 100 can be bulk silicon or SOI (silicon-on-insulator). Alternatively, the substrate 100 can be a silicon substrate or can contain other substances such as silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the substrate 100 can be one in which an epitaxial layer is formed on a base substrate. For convenience of explanation, in the following description, the case where the substrate 100 is a silicon substrate will be described.

[0017] The substrate 100 includes a first region I and a second region II. The first region I and the second region II are regions separated from each other with the wall structure 102 as the center. For example, the wall structure 102 extends in a first direction X parallel to the upper surface of the substrate 100. Also, the wall structure 102 is parallel to the upper surface of the substrate 100 and includes a first side surface 102a and a second side surface 102b that face each other in a second direction Y intersecting the first direction X. The first region I is a region of the substrate 100 defined on the first side surface 102a of the wall structure 102, and the second region II is a region of the substrate 100 defined on the second side surface 102b of the wall structure 102. The wall structure 102, for example, is a wall having a first side surface 102a, a second side surface 102b, an upper surface, and a lower surface that face each other when viewed from the first direction X. In one embodiment, transistors of different conductivity types are formed in the first region I and the second region II. As an example, the first region I is an NFET region, and the second region II is a PFET region. As another example, the first region I is a PFET region, and the second region II is an NFET region. However, the technical idea of the present invention is not limited thereto, and transistors of the same conductivity type can also be formed in the first region I and the second region II.

[0018] The first lower active pattern AP11 is formed on the first region I of the substrate 100. The first lower active pattern AP11 extends in the first direction X. The first lower active pattern AP11 includes at least one first lower bridge pattern (111 to 114) separated from the substrate 100. For example, at least one first lower bridge pattern (111 to 114) includes a first lower sheet pattern 111, a second lower sheet pattern 112, a third lower sheet pattern 113, and a fourth lower sheet pattern 114 that are sequentially stacked on the upper surface of the substrate 100. The first lower sheet pattern 111, the second lower sheet pattern 112, the third lower sheet pattern 113, and the fourth lower sheet pattern 114 are spaced apart from each other and each extend in the first direction X. Such a first lower active pattern AP11 can be provided as a channel region of an MBCFET (registered trademark) including a multi-bridge channel. The number of bridge patterns included in the first lower active pattern AP11 is an example and is not limited to that shown in the figure.

[0019] The first upper active pattern AP12 is formed on the first lower active pattern AP11. The first upper active pattern AP12 extends in the first direction X. The first upper active pattern AP12 includes at least one first upper bridge pattern (115 to 118) that is spaced apart from the first lower active pattern AP11 from the substrate 100. For example, at least one first upper bridge pattern (115 to 118) includes a first upper sheet pattern 115, a second upper sheet pattern 116, a third upper sheet pattern 117, and a fourth upper sheet pattern 118 that are sequentially stacked on the upper surface of the first lower active pattern AP11. The first upper sheet pattern 115, the second upper sheet pattern 116, the third upper sheet pattern 117, and the fourth upper sheet pattern 118 are spaced apart from each other and each extend in the first direction X. Such a first upper active pattern AP12 can be provided as a channel region of an MBCFET (registered trademark) including a multi-bridge channel.

[0020] In one embodiment, a first fin pattern 110 is formed between a substrate 100 and a first lower active pattern AP11. The first fin pattern 110 protrudes from the upper surface of the first region I of the substrate 100 and extends in the first direction X. The first fin pattern 110 may be formed by etching a part of the substrate 100, or may be an epitaxial layer grown from the substrate 100. The first lower active pattern AP11 and the first upper active pattern AP12 are sequentially arranged on the first fin pattern 110 in a vertical direction (for example, the third direction Z intersecting the first direction X and the second direction Y) intersecting the upper surface of the substrate 100.

[0021] A second lower active pattern AP21 is formed on the second region II of the substrate 100. The second lower active pattern AP21 extends in the first direction X. The second lower active pattern AP21 includes at least one second lower bridge pattern (211 to 214) spaced apart from the substrate 100. For example, the at least one second lower bridge pattern (211 to 214) includes a fifth lower sheet pattern 211, a sixth lower sheet pattern 212, a seventh lower sheet pattern 213, and an eighth lower sheet pattern 214 sequentially stacked on the upper surface of the substrate 100. The fifth lower sheet pattern 211, the sixth lower sheet pattern 212, the seventh lower sheet pattern 213, and the eighth lower sheet pattern 214 are spaced apart from each other and extend in the first direction X respectively. Such a second lower active pattern AP21 may be provided as a channel region of an MBCFET (registered trademark) including a multi-bridge channel. The number of bridge patterns included in the second lower active pattern AP21 is an example and is not limited to that shown in the figure.

[0022] A second upper active pattern AP22 is formed on the second lower active pattern AP21. The second upper active pattern AP22 extends in the first direction X. The second upper active pattern AP22 includes at least one second upper bridge pattern (215-218) spaced apart from the second lower active pattern AP21 from the substrate 100. For example, at least one second upper bridge pattern (215-218) includes a fifth upper sheet pattern 215, a sixth upper sheet pattern 216, a seventh upper sheet pattern 217, and an eighth upper sheet pattern 218 sequentially stacked on the upper surface of the second lower active pattern AP21. The fifth upper sheet pattern 215, the sixth upper sheet pattern 216, the seventh upper sheet pattern 217, and the eighth upper sheet pattern 218 are spaced apart from each other and extend in the first direction X respectively. Such a second upper active pattern AP22 can be provided as a channel region of an MBCFET (registered trademark) including a multi-bridge channel.

[0023] In one embodiment, a second fin pattern 210 is formed between the substrate 100 and the second lower active pattern AP21. The second fin pattern 210 protrudes from the upper surface of the second region II of the substrate 100 and extends in the first direction X. The second fin pattern 210 may be formed by etching a part of the substrate 100, or may also be an epitaxial layer grown from the substrate 100. The second lower active pattern AP21 and the second upper active pattern AP22 are sequentially arranged on the second fin pattern 210 in the third direction Z.

[0024] The active patterns (AP11, AP12, AP21, AP22) each include silicon (Si) or germanium (Ge) which are elemental semiconductor materials. Alternatively, the active patterns (AP11, AP12, AP21, AP22) can each include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor. IV-IV group compound semiconductors can be, for example, binary compounds, ternary compounds containing at least two or more of carbon (C), silicon (Si), germanium (Ge), tin (Sn), or compounds doped with group IV elements. III-V group compound semiconductors can be, for example, one of binary compounds, ternary compounds, or quaternary compounds formed by bonding at least one of group III elements aluminum (Al), gallium (Ga), and indium (In) and at least one of group V elements phosphorus (P), arsenic (As), and antimony (Sb). For the sake of convenience in explanation, in the following description, the case where the active patterns (AP11, AP12, AP21, AP22) are silicon (Si) patterns will be described.

[0025] In one embodiment, the first lower active pattern AP11 and the second lower active pattern AP21 are arranged at the same level with respect to each other, and the first upper active pattern AP12 and the second upper active pattern AP22 are arranged at the same level with respect to each other. Here, being arranged at the same level means being arranged at the same height with respect to each other based on the upper surface of the substrate 100. For example, as shown in the figure, the first lower bridge patterns (111 to 114) and the second lower bridge patterns (211 to 214) are arranged at the same height with respect to each other, and the first upper bridge patterns (115 to 118) and the second upper bridge patterns (215 to 218) are arranged at the same height with respect to each other.

[0026] In one embodiment, the first lower active pattern AP11 and the second lower active pattern AP21 are formed at the same level with respect to each other, and the first upper active pattern AP12 and the second upper active pattern AP22 are formed at the same level with respect to each other. In this specification, being formed at the same level means being formed by the same manufacturing process. For example, the first lower active pattern AP11 and the second lower active pattern AP21 are made of the same substance and / or the same substance composition as each other, and the first upper active pattern AP12 and the second upper active pattern AP22 are made of the same substance and / or the same substance composition as each other.

[0027] The first base insulating film 104 is interposed between the substrate 100 and the first lower active pattern AP11. The first base insulating film 104 electrically isolates the substrate 100 from the first lower active pattern AP11. For example, the first base insulating film 104 is interposed between the first fin pattern 110 and the first lower sheet pattern 111. In one embodiment, the first base insulating film 104 conformally extends along the upper surface of the substrate 100, one side surface of the first fin pattern 110, and the profile of the upper surface. The second base insulating film 204 is interposed between the substrate 100 and the second lower active pattern AP21. The second base insulating film 204 electrically isolates the substrate 100 from the second lower active pattern AP21. For example, the second base insulating film 204 is interposed between the second fin pattern 210 and the fifth lower sheet pattern 211. In one embodiment, the second base insulating film 204 conformally extends along the upper surface of the substrate 100, one side surface of the second fin pattern 210, and the profile of the upper surface.

[0028] The first base insulating film 104 and the second base insulating film 204 may each include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, but are not limited thereto. As an example, the first base insulating film 104 and the second base insulating film 204 each include a silicon nitride film. In one embodiment, the first base insulating film 104 and the second base insulating film 204 are disposed at the same level as each other. In one embodiment, the first base insulating film 104 and the second base insulating film 204 are formed at the same level as each other.

[0029] The first intermediate insulating film 105 is interposed between the first lower active pattern AP11 and the first upper active pattern AP12. The first intermediate insulating film 105 electrically separates the first lower active pattern AP11 and the first upper active pattern AP12. For example, the first intermediate insulating film 105 is interposed between the fourth lower sheet pattern 114 and the first upper sheet pattern 115. The second intermediate insulating film 205 is interposed between the second lower active pattern AP21 and the second upper active pattern AP22. The second intermediate insulating film 205 electrically separates the second lower active pattern AP21 and the second upper active pattern AP22. For example, the second intermediate insulating film 205 is interposed between the eighth lower sheet pattern 214 and the fifth upper sheet pattern 215.

[0030] The first intermediate insulating film 105 and the second intermediate insulating film 205 may each include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, but are not limited thereto. As an example, the first intermediate insulating film 105 and the second intermediate insulating film 205 each include a silicon nitride film. In one embodiment, the first intermediate insulating film 105 and the second intermediate insulating film 205 are arranged at the same level as each other. In one embodiment, the first intermediate insulating film 105 and the second intermediate insulating film 205 are formed at the same level as each other.

[0031] The field insulating film 106 is formed on the substrate 100. For example, the field insulating film 106 is formed on the first base insulating film 104 and the second base insulating film 204. The field insulating film 106 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, but is not limited thereto. As an example, the field insulating film 106 includes a silicon oxide film. In one embodiment, the field insulating film 106 fills at least a part of the region on the side surface of the first fin pattern 110 and at least a part of the region on the side surface of the second fin pattern 210. In FIG. 2, only the case where the upper surface of the field insulating film 106 is arranged coplanarly with the upper surfaces of the first base insulating film 104 and the second base insulating film 204 is shown, but this is merely an example. As another example, the upper surface of the field insulating film 106 can be formed lower than the upper surfaces of the first base insulating film 104 and the second base insulating film 204, or can be formed higher than the upper surfaces of the first base insulating film 104 and the second base insulating film 204.

[0032] The wall structure 102 extends in the first direction X between the first region I and the second region II. The wall structure 102 separates the first lower active pattern AP11 and the second lower active pattern AP21, and separates the first upper active pattern AP12 and the second upper active pattern AP22. For example, the first lower active pattern AP11 and the first upper active pattern AP12 are in contact with the first side surface 102a of the wall structure 102, and the second lower active pattern AP21 and the second upper active pattern AP22 are in contact with the second side surface 102b of the wall structure 102. Such active patterns (AP11, AP12, AP21, AP22) are each provided as a channel region of a fork sheet field effect transistor (forksheet FET).

[0033] The wall structure 102 may include an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, but is not limited thereto. As an example, the wall structure 102 includes a silicon nitride film. The wall structure 102 is provided as a dielectric wall of a so-called DWS (Dielectric Wall Scheme) forksheet field effect transistor (forksheet FET) structure. The wall structure 102 has a tapered shape. Specifically, in the second direction Y, the width of the wall structure 102 increases as it moves away from the substrate 100. This is due to, but not limited to, the characteristics of the etching process (or patterning process) for forming the wall structure 102. Only the case where the lower surface of the wall structure 102 is arranged coplanarly with the upper surface of the substrate 100 is shown, but this is merely an example. As another example, the lower surface of the wall structure 102 can be formed lower than the upper surface of the substrate 100, or can be formed higher than the upper surface of the substrate 100.

[0034] In one embodiment, the wall structure 102 separates the first base insulating film 104 and the second base insulating film 204. For example, the lower surface of the wall structure 102 is formed lower than the lower surface of the first base insulating film 104 and the lower surface of the second base insulating film 204. Also, the wall structure 102 separates the first intermediate insulating film 105 and the second intermediate insulating film 205. Due to the wall structure 102 having a tapered shape, the widths of the active patterns (AP11, AP12, AP21, AP22) decrease as they move away from the substrate 100 respectively. Also, the width of the first upper active pattern AP12 is smaller than the width of the first lower active pattern AP11, and the width of the second upper active pattern AP22 is smaller than the width of the second lower active pattern AP21. Here, the width means the width in the second direction Y. For example, as shown in FIG. 3, the width W12 of the fourth lower sheet pattern 114 is smaller than the width W11 of the first lower sheet pattern 111, and the width W22 of the fourth upper sheet pattern 118 is smaller than the width W21 of the first upper sheet pattern 115. In addition, the width W21 of the first upper sheet pattern 115 is smaller than the width W12 of the fourth lower sheet pattern 114. The width of each sheet pattern in the second direction Y means the maximum width of each sheet pattern in the second direction Y.

[0035] In addition, since the wall structure 102 has a tapered shape, the side surfaces of the active patterns (AP11, AP12, AP21, AP22) facing the wall structure 102 are inclined with respect to the upper surface of the substrate 100, respectively. For example, as shown in FIG. 3, one side surface of the first lower sheet pattern 111 facing the wall structure 102 forms a first acute angle θ1 with the lower surface of the first lower sheet pattern 111. In one embodiment, the thickness of at least one first upper bridge pattern (115-118) is greater than the thickness of at least one first lower bridge pattern (111-114). Here, the thickness means the thickness in the third direction Z. For example, as shown in FIG. 3, the thickness T2 of the first upper sheet pattern 115 is greater than the thickness T1 of the first lower sheet pattern 111. In one embodiment, the plurality of first lower bridge patterns (111-114) have the same thickness (for example, T1) with each other. In one embodiment, the plurality of first upper bridge patterns (115-118) have the same thickness (for example, T2) with each other. In one embodiment, the number of at least one first upper bridge pattern (115-118) is the same as the number of at least one first lower bridge pattern (111-114). For example, as shown in the figure, the number of the first lower bridge patterns (111-114) and the number of the first upper bridge patterns (115-118) are four in total.

[0036] In one embodiment, the cross-sectional area of the first upper active pattern AP12 is the same as the cross-sectional area of the first lower active pattern AP11. Here, the cross-sectional area means the cross-sectional area in a cross-section intersecting the first direction X. For example, the thickness (e.g., T2) of at least one first upper bridge pattern (115-118) is controlled such that the cross-sectional area of at least one first upper bridge pattern (115-118) is the same as the cross-sectional area of at least one first lower bridge pattern (111-114). In one embodiment, the distance by which a plurality of first upper bridge patterns (115-118) are separated from each other is smaller than the distance by which a plurality of first lower bridge patterns (111-114) are separated from each other. For example, as shown in FIG. 3, the separation distance D2 between the first upper sheet pattern 115 and the second upper sheet pattern 116 is smaller than the separation distance D1 between the first lower sheet pattern 111 and the second lower sheet pattern 112.

[0037] In one embodiment, the sides of the active patterns (AP11, AP12, AP21, AP22) facing the wall structure 102 also have an inclination with respect to the upper surface of the substrate 100, respectively. For example, as shown in FIG. 3, the other side surface of the first lower sheet pattern 111 facing the wall structure 102 forms a second acute angle θ2 with the lower surface of the first lower sheet pattern 111. This is due to, but not limited to, the characteristics of the etching process (or patterning process) for forming the active patterns (AP11, AP12, AP21, AP22). In one embodiment, as shown in FIG. 3, the second acute angle θ2 is the same as the first acute angle θ1. Alternatively, in one embodiment, as shown in FIG. 4, the second acute angle θ2 is different from the first acute angle θ1. In one embodiment, the first acute angle θ1 is smaller than the second acute angle θ2.

[0038] The first gate structure GS1 is formed on the first region I of the substrate 100. The first gate structure GS1 intersects the first lower active pattern AP11 and the first upper active pattern AP12. For example, the first gate structure GS1 extends in the second direction Y on the first side surface 102a of the wall structure 102. At least one first lower bridge pattern (111 to 114) and at least one first upper bridge pattern (115 to 118) extend in the first direction X and penetrate the first gate structure GS1, respectively. Therefore, the first gate structure GS1 surrounds the periphery of each of the first lower bridge patterns (111 to 114) and the periphery of each of the first upper bridge patterns (115 to 118).

[0039] The second gate structure GS2 is formed on the second region II of the substrate 100. The second gate structure GS2 intersects the second lower active pattern AP21 and the second upper active pattern AP22. For example, the second gate structure GS2 extends in the second direction Y on the second side surface 102b of the wall structure 102. At least one second lower bridge pattern (211 to 214) and at least one second upper bridge pattern (215 to 218) extend in the first direction X and penetrate the second gate structure GS2, respectively. Therefore, the second gate structure GS2 surrounds the periphery of each of the second lower bridge patterns (211 to 214) and the periphery of each of the second upper bridge patterns (215 to 218). The first gate structure GS1 may include a first gate dielectric film 120 and a first gate electrode 130, and the second gate structure GS2 may include a second gate dielectric film 220 and a second gate electrode 230.

[0040] The first gate dielectric film 120 is laminated on the first lower active pattern AP11 and the first upper active pattern AP12. The first gate dielectric film 120 extends conformally. The first gate dielectric film 120 is interposed between the first lower active pattern AP11 and the first gate electrode 130, and between the first upper active pattern AP12 and the first gate electrode 130. The first gate dielectric film 120 further extends along the upper surface of the first base insulating film 104 and / or the upper surface of the field insulating film 106. Further, the first gate dielectric film 120 extends further along the side surface of the first intermediate insulating film 105. In one embodiment, a part of the first gate dielectric film 120 is interposed between the wall structure 102 and the first gate electrode 130. For example, the first gate dielectric film 120 extends further along the first side surface 102a of the wall structure 102.

[0041] The second gate dielectric film 220 is laminated on the second lower active pattern AP21 and the second upper active pattern AP22. The second gate dielectric film 220 extends conformally. The second gate dielectric film 220 is interposed between the second lower active pattern AP21 and the second gate electrode 230, and between the second upper active pattern AP22 and the second gate electrode 230. The second gate dielectric film 220 extends further along the upper surface of the second base insulating film 204 and / or the upper surface of the field insulating film 106. Further, the second gate dielectric film 220 extends further along the side surface of the second intermediate insulating film 205. In one embodiment, a part of the second gate dielectric film 220 is interposed between the wall structure 102 and the second gate electrode 230. For example, the second gate dielectric film 220 extends further along the second side surface 102b of the wall structure 102.

[0042] The first gate dielectric film 120 and the second gate dielectric film 220 may each contain at least one of, for example, silicon oxide, silicon oxynitride, silicon nitride, or a high-k material having a dielectric constant greater than that of silicon oxide. Examples of high-k materials include hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), strontium titanate (SrTiO3), lanthanum aluminate (LaAlO3), yttrium oxide (Y2O3), hafnium oxynitride (HfO x N y )、zirconium oxynitride (ZrOx N y ) nitride of lanthanum (La2O x N y ) nitride of aluminum (Al2O x N y ) nitride of titanium (TiO x N y ) nitride of strontium titanate (SrTiO x N y ) nitride of lanthanum aluminate (LaAlO x N y ) nitride of yttrium (Y2O x N y ) and may include at least one of combinations thereof, but is not limited thereto.

[0043] The semiconductor device according to an embodiment of the present invention includes an NC (Negative Capacitance) FET using a Negative Capacitor. For example, the first gate dielectric film 120 and / or the second gate dielectric film 220 includes a ferroelectric material film having ferroelectric characteristics and a dielectric material film having dielectric characteristics. The ferroelectric material film has a negative capacitance, and the dielectric material film has a positive capacitance. For example, when two or more capacitors are connected in series and the capacitance of each capacitor has a positive value, the overall capacitance decreases from the capacitance of each individual capacitor. On the contrary, when at least one of the capacitances of two or more capacitors connected in series has a negative value, the overall capacitance has a positive value and is greater than the absolute value of each individual capacitance. When a ferroelectric material film having a negative capacitance and a dielectric material film having a positive capacitance are connected in series, the overall capacitance value of the ferroelectric material film and the dielectric material film connected in series increases. By using the increase in the overall capacitance value, a transistor including a ferroelectric material film can have a subthreshold swing (SS) of less than about 60 mV / decade at room temperature.

[0044] The ferroelectric material film has ferroelectric properties. The ferroelectric material film can include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide can be a substance in which hafnium oxide is doped with zirconium (Zr). As another example, hafnium zirconium oxide can also be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0045] The ferroelectric material film further includes a doped dopant. For example, the dopant can include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). Depending on which ferroelectric material the ferroelectric material film contains, the type of dopant included in the ferroelectric material film can vary. When the ferroelectric material film contains hafnium oxide, the dopant contained in the ferroelectric material film may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0046] When the dopant is aluminum (Al), the ferroelectric material film may contain about 3 at% to about 8 at% (atomic%) of aluminum. Here, the ratio of the dopant may be the ratio of aluminum to the total of hafnium and aluminum. When the dopant is silicon (Si), the ferroelectric material film may contain about 2 at% to about 10 at% of silicon. When the dopant is yttrium (Y), the ferroelectric material film may contain 2 at% to 10 at% of yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may contain 1 at% to 7 at% of gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may contain 50 at% to 80 at% of zirconium.

[0047] The paraelectric material film has the characteristics of a paraelectric. The paraelectric material film may include, for example, at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide contained in the paraelectric material film may include, for example, but is not limited to, at least one of hafnium oxide, zirconium oxide, and aluminum oxide. The ferroelectric material film and the paraelectric material film may contain the same substance. The ferroelectric material film has the characteristics of a ferroelectric, but the paraelectric material film does not necessarily have the characteristics of a ferroelectric. For example, when the ferroelectric material film and the paraelectric material film contain hafnium oxide, the crystal structure of the hafnium oxide contained in the ferroelectric material film is different from the crystal structure of the hafnium oxide contained in the paraelectric material film.

[0048] The ferroelectric material film has a thickness having ferroelectric characteristics. The thickness of the ferroelectric material film is, for example, 0.5 nm to 10 nm, but is not limited thereto. Since the critical thickness showing the characteristics of the ferroelectric may vary for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material. As an example, the first gate dielectric film 120 and / or the second gate dielectric film 220 includes one ferroelectric material film. As another example, the first gate dielectric film 120 and / or the second gate dielectric film 220 may include a plurality of ferroelectric material films separated from each other. The first gate dielectric film 120 and / or the second gate dielectric film 220 has a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0049] The first gate electrode 130 is stacked on the first gate dielectric film 120. In one embodiment, the first gate electrode 130 is formed by stacking a plurality of conductive films. For example, the first gate electrode 130 includes a first work function adjustment film 132 that adjusts the work function and a first filling conductive film 134 that fills the space formed by the first work function adjustment film 132. The second gate electrode 230 is stacked on the second gate dielectric film 220. In one embodiment, the second gate electrode 230 is formed by stacking a plurality of conductive films. For example, the second gate electrode 230 includes a second work function adjustment film 232 that adjusts the work function and a second filling conductive film 234 that fills the space formed by the second work function adjustment film 232.

[0050] The first work function adjustment film 132 and the second work function adjustment film 232 are shown only when they have the same thickness as each other, but this is just an example. Of course, the first work function adjustment film 132 and the second work function adjustment film 232 can also have different thicknesses from each other. The first work function adjustment film 132 and the second work function adjustment film 232 may each include, for example, at least one of TiN, TaN, TiC, TaC, TiAlC, and combinations thereof, but are not limited thereto. The first filling conductive film 134 and the second filling conductive film 234 may each include, for example, W or Al, but are not limited thereto. In one embodiment, the wall structure 102 extends in the first direction X and separates the first gate structure GS1 and the second gate structure GS2. For example, the upper surface of the wall structure 102 is formed higher than the upper surfaces of the first gate structure GS1 and the second gate structure GS2.

[0051] The first gate spacer 140 extends along the side surface of the first gate structure GS1. In one embodiment, a part of the first gate dielectric film 120 is interposed between the first gate electrode 130 and the first gate spacer 140. For example, as shown in FIG. 5, the first gate dielectric film 120 further extends along at least a part of the inner surface of the first gate spacer 140. Such a first gate dielectric film 120 is formed by a replacement process, but is not limited thereto. The second gate spacer 240 extends along the side surface of the second gate structure GS2. In one embodiment, a part of the second gate dielectric film 220 is interposed between the second gate electrode 230 and the second gate spacer 240. For example, as shown in FIG. 6, the second gate dielectric film 220 further extends along at least a part of the inner surface of the second gate spacer 240. Such a second gate dielectric film 220 is formed by a replacement process, but is not limited thereto.

[0052] The first gate spacer 140 and the second gate spacer 240 may each include, for example, at least one of silicon nitride, silicon oxynitride, silicon oxycarbide, boron silicon nitride, boron silicon carbonitride, silicon oxycarbonitride, and combinations thereof, but are not limited thereto. As an example, the first gate spacer 140 and the second gate spacer 240 each include a silicon nitride film.

[0053] The first lower source / drain pattern 160A and the first upper source / drain pattern 160B are formed on at least one side surface (e.g., both side surfaces) of the first gate structure GS1. The first lower source / drain pattern 160A is connected to the first lower active pattern AP11 in the first direction X, and the first upper source / drain pattern 160B is connected to the first upper active pattern AP12 in the first direction X. For example, at least one first lower bridge pattern (111 to 114) penetrates the first gate structure GS1 and the first gate spacer 140 and is connected to the first lower source / drain pattern 160A. Also, at least one first upper bridge pattern (115 to 118) penetrates the first gate structure GS1 and the first gate spacer 140 and is connected to the first upper source / drain pattern 160B. The first lower source / drain pattern 160A and the first upper source / drain pattern 160B are electrically separated from the first gate electrode 130 by the first gate spacer 140 and / or the first gate dielectric film 120.

[0054] In one embodiment, the first lower source / drain pattern 160A and the first upper source / drain pattern 160B each include an epitaxial layer. For example, the first lower source / drain pattern 160A is formed from the first lower active pattern AP11 by an epitaxial growth method, and the first upper source / drain pattern 160B is formed from the first upper active pattern AP12 by an epitaxial growth method. When the first region I is an NFET region, the first lower source / drain pattern 160A and the first upper source / drain pattern 160B each contain an n-type impurity (e.g., phosphorus (P), antimony (Sb), or arsenic (As)) or an impurity for preventing the diffusion of the n-type impurity. When the first region I is an NFET region, the first lower source / drain pattern 160A and the first upper source / drain pattern 160B can each further contain a tensile stress substance. As an example, when the first lower active pattern AP11 and the first upper active pattern AP12 are each a silicon (Si) pattern, the first lower source / drain pattern 160A and the first upper source / drain pattern 160B can each contain a substance having a lattice constant smaller than that of silicon (Si) (e.g., silicon carbide (SiC)).

[0055] In one embodiment, the first lower source / drain pattern 160A and the first upper source / drain pattern 160B are electrically separated. For example, as shown in FIG. 5, a first isolation insulating film 108 is formed between the first lower source / drain pattern 160A and the first upper source / drain pattern 160B. The thickness of the first isolation insulating film 108 is shown only when it is the same as the thickness of the first intermediate insulating film 105, but this is an example, and of course, the thickness of the first isolation insulating film 108 may be different from the thickness of the first intermediate insulating film 105. The second lower source / drain pattern 260A and the second upper source / drain pattern 260B are formed on at least one side surface (e.g., both side surfaces) of the second gate structure GS2.

[0056] The second lower source / drain pattern 260A is connected to the second lower active pattern AP21 in the first direction X, and the second upper source / drain pattern 260B is connected to the second upper active pattern AP22 in the first direction X. For example, at least one second lower bridge pattern (211 - 214) penetrates through the second gate structure GS2 and the second gate spacer 240 and is connected to the second lower source / drain pattern 260A. Also, at least one second upper bridge pattern (215 - 218) penetrates through the second gate structure GS2 and the second gate spacer 240 and is connected to the second upper source / drain pattern 260B. The second lower source / drain pattern 260A and the second upper source / drain pattern 260B are electrically separated from the second gate electrode 230 by the second gate spacer 240 and / or the second gate dielectric film 220.

[0057] In one embodiment, the second lower source / drain pattern 260A and the second upper source / drain pattern 260B each include an epitaxial layer. For example, the second lower source / drain pattern 260A is formed from the second lower active pattern AP21 by an epitaxial growth method, and the second upper source / drain pattern 260B is formed from the second upper active pattern AP22 by an epitaxial growth method. When the second region II is a PFET region, the second lower source / drain pattern 260A and the second upper source / drain pattern 260B each contain a p-type impurity (e.g., boron (B), indium (In), gallium (Ga), or aluminum (Al)) or an impurity for preventing the diffusion of p-type impurities. When the second region II is a PFET region, the second lower source / drain pattern 260A and the second upper source / drain pattern 260B can each further contain a compressive stress material.

[0058] As an example, when the second lower active pattern AP21 and the second upper active pattern AP22 are each a silicon (Si) pattern, the second lower source / drain pattern 260A and the second upper source / drain pattern 260B may each contain a material with a lattice constant larger than that of silicon (Si) (for example, silicon germanium (SiGe)). In one embodiment, the second lower source / drain pattern 260A and the second upper source / drain pattern 260B are electrically separated. For example, as shown in FIG. 6, a second separation insulating film 208 is formed between the second lower source / drain pattern 260A and the second upper source / drain pattern 260B. The thickness of the second separation insulating film 208 is shown only when it is the same as the thickness of the second intermediate insulating film 205, but this is just an example. Of course, the thickness of the second separation insulating film 208 may be different from the thickness of the second intermediate insulating film 205.

[0059] The interlayer insulating film 180 is formed on the wall structure 102, the gate structures (GS1, GS2), and the source / drain patterns (160A, 160B, 260A, 260B). The interlayer insulating film 180 covers the wall structure 102, the gate structures (GS1, GS2), and the source / drain patterns (160A, 160B, 260A, 260B). The interlayer insulating film 180 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, boron silicon nitride, boron silicon carbonitride, silicon oxycarbonitride, and a low-k material having a dielectric constant smaller than that of silicon oxide, but is not limited thereto.

[0060] The low dielectric constant material may include, for example, but is not limited to, at least one of FOX (Flowable Oxide), TOSZ (Torene SilaZene), USG (Undoped Silica Glass), BSG (Borosilica Glass), PSG (PhosphoSilica Glass), BPSG (BoroPhosphoSilica Glass), PTEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate), FSG (Fluoride Silicate Glass), CDO (Carbon Doped silicon Oxide), Xerogel, Aerogel, Amorphous Fluorinated Carbon, OSG (Organo Silicate Glass), Parylene, BCB (bis-benzocyclobutenes), SiLK, polyimide, porous polymeric material, and combinations thereof.

[0061] The first gate contact CB1 is electrically connected to the first gate structure GS1. For example, the first gate contact CB1 extends in the third direction Z, penetrates the interlayer insulating film 180, and is connected to the upper surface of the first gate electrode 130. The second gate contact CB2 is electrically connected to the second gate structure GS2. For example, the second gate contact CB2 extends in the third direction Z, penetrates the interlayer insulating film 180, and is connected to the upper surface of the second gate electrode 230. The first gate contact CB1 and the second gate contact CB2 may each include a conductive material, for example, a metallic material such as cobalt (Co), titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), or cobalt tungsten phosphorous (CoWP), but is not limited thereto.

[0062] As semiconductor devices become more highly integrated, research on semiconductor devices using multi-gate transistors stacked to realize more semiconductor devices in the same area is underway. Such a semiconductor device includes a lower multi-gate transistor on a substrate and an upper multi-gate transistor stacked on the lower multi-gate transistor. In addition, in a DWS (Dielectric Wall Scheme) forksheet FET (forksheet field effect transistor) structure including stacked multi-gate transistors, the wall structure 102 provided as a dielectric wall has a tapered shape that becomes narrower downward. In such a case, the channel width of the upper multi-gate transistor becomes smaller than the channel width of the lower multi-gate transistor, and a characteristic difference occurs between the lower multi-gate transistor and the upper multi-gate transistor.

[0063] A semiconductor device according to an embodiment can minimize the characteristic difference between the lower multi-gate transistor and the upper multi-gate transistor by controlling the channel area of the lower multi-gate transistor and / or the upper multi-gate transistor. For example, as described above, the thickness (e.g., T2) of at least one first upper bridge pattern (115 to 118) is greater than the thickness (e.g., T1) of at least one first lower bridge pattern (111 to 114). Also, in one embodiment, the thickness (e.g., T2) of at least one first upper bridge pattern (115 to 118) is controlled such that the cross-sectional area of at least one first upper bridge pattern (115 to 118) is the same as the cross-sectional area of at least one first lower bridge pattern (111 to 114).

[0064] For example, a specific group of bridge patterns (e.g., sheet patterns) together form a channel region between the source and drain regions of the transistor. The bridge pattern includes all sheet patterns for the corresponding transistor and is described as a multi-sheet channel pattern. In one embodiment, the multi-sheet channel pattern of the upper transistor (e.g., the first upper bridge pattern (115 - 118)) has the same cross-sectional area as the multi-sheet channel pattern of the lower transistor (e.g., the first lower bridge pattern (111 - 114)) when viewed from the first direction X. In one embodiment, the cross-sectional area of the first lower active pattern AP11 can be within a specific percentage difference (e.g., 0% - 5% difference) from the cross-sectional area of the first upper active pattern AP12. Similar differences occur between other upper and lower active patterns. Accordingly, by minimizing the characteristic differences between the lower multi-gate transistor and the upper multi-gate transistor, a semiconductor device with improved performance can be provided.

[0065] FIG. 7 is a cross-sectional view for explaining the schematic configuration of a semiconductor device according to an embodiment of the present invention. For convenience of explanation, parts overlapping with the content described above with reference to FIGS. 1 - 6 will be briefly explained or omitted. Referring to FIG. 7, in a semiconductor device according to an embodiment of the present invention, the first gate electrode 130 includes a first lower work function adjustment film 132a and a first upper work function adjustment film 132b, and the second gate electrode 230 includes a second lower work function adjustment film 232a and a second upper work function adjustment film 232b.

[0066] The first lower work function adjustment film 132a intersects the first lower active pattern AP11. The first upper work function adjustment film 132b intersects the first upper active pattern AP12. The second lower work function adjustment film 232a intersects the second lower active pattern AP21. The second upper work function adjustment film 232b intersects the second upper active pattern AP22. The first lower work function adjustment film 132a, the first upper work function adjustment film 132b, the second lower work function adjustment film 232a, and the second upper work function adjustment film 232b may each include at least one of, for example, TiN, TaN, TiC, TaC, TiAlC, and combinations thereof, but are not limited thereto.

[0067] In one embodiment, the first lower work function adjustment film 132a and the first upper work function adjustment film 132b are work function adjustment films of different conductivity types, and the second lower work function adjustment film 232a and the second upper work function adjustment film 232b are work function adjustment films of different conductivity types. As an example, the first lower work function adjustment film 132a and the second lower work function adjustment film 232a are work function adjustment films of NFETs, and the first upper work function adjustment film 132b and the second upper work function adjustment film 232b are work function adjustment films of PFETs. As another example, the first lower work function adjustment film 132a and the second lower work function adjustment film 232a may be work function adjustment films of PFETs, and the first upper work function adjustment film 132b and the second upper work function adjustment film 232b may be work function adjustment films of NFETs. As still another example, the first lower work function adjustment film 132a and the second upper work function adjustment film 232b may be work function adjustment films of NFETs, and the first upper work function adjustment film 132b and the second lower work function adjustment film 232a may be work function adjustment films of PFETs.

[0068] FIG. 8 is a cross-sectional view for explaining a schematic configuration of a semiconductor device according to an embodiment of the present invention, and FIG. 9 is an enlarged view for explaining the R2 region of FIG. 8. For convenience of explanation, parts overlapping with the above-described content using FIGS. 1 to 6 will be briefly explained or omitted. Referring to FIGS. 8 and 9, in the semiconductor device according to the embodiment of the present invention, the number of at least one first upper bridge pattern (115 to 119) is larger than the number of at least one first lower bridge pattern (111 to 114).

[0069] For example, the first upper bridge pattern (115 to 119) further includes the fifth upper sheet pattern 119. That is, the number of the first lower bridge patterns (111 to 114) is four, and the number of the first upper bridge patterns (115 to 119) is five, which is more than that. In one embodiment, the thickness of at least one first upper bridge pattern (115 to 119) is the same as the thickness of at least one first lower bridge pattern (111 to 114). For example, as shown in FIG. 9, the thickness T2 of the first upper sheet pattern 115 is the same as the thickness T1 of the first lower sheet pattern 111. In one embodiment, the plurality of first lower bridge patterns (111 to 114) have the same thickness (for example, T1) with each other. In one embodiment, the plurality of first upper bridge patterns (115 to 119) have the same thickness (for example, T2) with each other.

[0070] In one embodiment, the cross-sectional area of the first upper active pattern AP12 is the same as the cross-sectional area of the first lower active pattern AP11. For example, the number of at least one first upper bridge pattern (115 to 119) is controlled such that the cross-sectional area of at least one first upper bridge pattern (115 to 119) is the same as the cross-sectional area of at least one first lower bridge pattern (111 to 114). Thereby, by minimizing the characteristic difference between the lower multi-gate transistor and the upper multi-gate transistor, a semiconductor device with improved performance can be provided. In one embodiment, the distance by which the plurality of first upper bridge patterns (115 to 119) are separated from each other is smaller than the distance by which the plurality of first lower bridge patterns (111 to 114) are separated from each other. For example, as shown in FIG. 9, the separation distance D2 between the first upper sheet pattern 115 and the second upper sheet pattern 116 is smaller than the separation distance D1 between the first lower sheet pattern 111 and the second lower sheet pattern 112.

[0071] FIG. 10 is a cross-sectional view for explaining the schematic configuration of a semiconductor device according to an embodiment of the present invention, and FIG. 11 is an enlarged view for explaining the R3 region of FIG. 10. For the sake of convenience of explanation, parts that overlap with the content described above with reference to FIGS. 1 to 6 will be briefly explained or omitted. Referring to FIGS. 10 and 11, in a semiconductor device according to an embodiment of the present invention, some of the plurality of first upper bridge patterns (115 to 118) have a thickness different from that of some of the other plurality of first upper bridge patterns (115 to 118).

[0072] For example, the thicknesses T21 of the first upper sheet pattern 115, the second upper sheet pattern 116, and the third upper sheet pattern 117 are the same as the thickness (for example, T1) of at least one of the first lower bridge patterns (111 to 114). The thickness T22 of the fourth upper sheet pattern 118 is greater than the thickness (for example, T1) of at least one of the first lower bridge patterns (111 to 114). In one embodiment, the cross-sectional area of the first upper active pattern AP12 is the same as the cross-sectional area of the first lower active pattern AP11. For example, the thickness T22 of the fourth upper sheet pattern 118 is controlled such that the cross-sectional area of at least one of the first upper bridge patterns (115 to 118) is the same as the cross-sectional area of at least one of the first lower bridge patterns (111 to 114). In one embodiment, the distance at which the plurality of first upper bridge patterns (115 to 118) are separated from each other is smaller than the distance at which the plurality of first lower bridge patterns (111 to 114) are separated from each other. For example, as shown in FIG. 9, the separation distance D21 between the first upper sheet pattern 115 and the second upper sheet pattern 116 and / or the separation distance D22 between the third upper sheet pattern 117 and the fourth upper sheet pattern 118 is smaller than the separation distance D1 between the first lower sheet pattern 111 and the second lower sheet pattern 112.

[0073] FIGS. 12 to 15 are various cross-sectional views for explaining the schematic configuration of the semiconductor device according to an embodiment of the present invention. For convenience of explanation, parts overlapping with the content described above with reference to FIGS. 1 to 6 will be briefly described or omitted. Referring to FIGS. 12 to 15, the semiconductor device according to an embodiment of the present invention further includes a third upper active pattern AP13, a fourth upper active pattern AP23, a third intermediate insulating film 305, and a fourth intermediate insulating film 405.

[0074] The third upper active pattern AP13 is formed on the first upper active pattern AP12. The third upper active pattern AP13 is separated from the substrate 100 by a greater distance than the first upper active pattern AP12. The first gate structure GS1 intersects the third upper active pattern AP13. The fourth upper active pattern AP23 is formed on the second upper active pattern AP22. The fourth upper active pattern AP23 is separated from the substrate 100 by a greater distance than the second upper active pattern AP22. The second gate structure GS2 intersects the fourth upper active pattern AP23. The third intermediate insulating film 305 is interposed between the first upper active pattern AP12 and the third upper active pattern AP13. The third intermediate insulating film 305 electrically separates the first upper active pattern AP12 and the third upper active pattern AP13. The fourth intermediate insulating film 405 is interposed between the second upper active pattern AP22 and the fourth upper active pattern AP23. The fourth intermediate insulating film 405 electrically separates the second upper active pattern AP22 and the fourth upper active pattern AP23.

[0075] Referring to FIGS. 12 and 13, in the semiconductor device according to an embodiment of the present invention, the third upper active pattern AP13 includes at least one third upper bridge pattern (311 to 314), and the fourth upper active pattern AP23 includes at least one fourth upper bridge pattern (411 to 414). Referring to FIG. 12, in the semiconductor device according to an embodiment of the present invention, the thickness of at least one first upper bridge pattern (115 to 118) is greater than the thickness of at least one first lower bridge pattern (111 to 114). Also, the thickness of at least one third upper bridge pattern (311 to 314) is greater than the thickness of at least one first upper bridge pattern (115 to 118). In one embodiment, the cross-sectional area of the third upper active pattern AP13 is the same as the cross-sectional area of the first upper active pattern AP12.

[0076] Referring to FIG. 13, in the semiconductor device according to an embodiment of the present invention, the number of at least one first upper bridge pattern (115 to 119) is greater than the number of at least one first lower bridge pattern (111 to 114). Also, the thickness of at least one third upper bridge pattern (311 to 314) is greater than the thickness of at least one first lower bridge pattern (111 to 114) and / or the thickness of at least one first upper bridge pattern (115 to 119). In one embodiment, the cross-sectional area of the third upper active pattern AP13 is the same as the cross-sectional area of the first upper active pattern AP12.

[0077] Referring to FIGS. 14 and 15, in the semiconductor device according to an embodiment of the present invention, the third upper active pattern AP13 includes at least one third upper bridge pattern (311 to 316), and the fourth upper active pattern AP23 includes at least one fourth upper bridge pattern 411 to 416. Referring to FIG. 14, in a semiconductor device according to an embodiment of the present invention, the thickness of at least one first upper bridge pattern (115-118) is greater than the thickness of at least one first lower bridge pattern (111-114). Also, the number of at least one third upper bridge pattern (311-316) is greater than the number of at least one first upper bridge pattern (115-118). In one embodiment, the cross-sectional area of the third upper active pattern AP13 is the same as the cross-sectional area of the first upper active pattern AP12.

[0078] Referring to FIG. 15, in a semiconductor device according to an embodiment of the present invention, the number of at least one first upper bridge pattern (115-119) is greater than the number of at least one first lower bridge pattern (111-114). Also, the number of at least one third upper bridge pattern (311-316) is greater than the number of at least one first upper bridge pattern (115-119). In one embodiment, the cross-sectional area of the third upper active pattern AP13 is the same as the cross-sectional area of the first upper active pattern AP12.

[0079] Hereinafter, with reference to FIGS. 1 to 43, a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention will be described. FIGS. 16 to 41 are intermediate stage diagrams for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. For convenience of explanation, parts overlapping with the above-described content using FIGS. 1 to 15 will be briefly described or omitted.

[0080] Referring to FIGS. 16 and 17, a base sacrificial film 504, a first active film pAP1, a first sacrificial film 530A, an intermediate sacrificial film 505, a second active film pAP2, a second sacrificial film 530B, and at least one protective film (592, 594) are formed on a substrate 100. For reference, FIG. 17 is a cross-sectional view taken along the line A-A of FIG. 16. The base sacrificial film 504 is formed on the substrate 100. The first active film pAP1 and the first sacrificial film 530A are alternately laminated on the base sacrificial film 504. For example, the first active film pAP1 includes at least one lower active film (511 - 514) sequentially laminated on the base sacrificial film 504.

[0081] The first sacrificial film 530A is interposed between the lower active films (511 - 514) and separates the lower active films (511 - 514) from each other in the vertical direction (e.g., the third direction Z). The intermediate sacrificial film 505 is formed on the first active film pAP1 and the first sacrificial film 530A. The second active film pAP2 and the second sacrificial film 530B are alternately laminated on the intermediate sacrificial film 505. For example, the second active film pAP2 includes at least one upper active film (515 - 518) sequentially laminated on the intermediate sacrificial film 505. The second sacrificial film 530B is interposed between the upper active films (515 - 518) and separates the upper active films (515 - 518) from each other in the vertical direction (e.g., the third direction Z).

[0082] In one embodiment, the thickness of at least one upper active film (515 - 518) is greater than the thickness of at least one lower active film (511 - 514). The first sacrificial film 530A and the second sacrificial film 530B have an etching selectivity with respect to the first active film pAP1 and the second active film pAP2. As an example, the first active film pAP1 and the second active film pAP2 each include a silicon (Si) film, and the first sacrificial film 530A and the second sacrificial film 530B each include a silicon germanium (SiGe) film. The base sacrificial film 504 and the intermediate sacrificial film 505 have an etching selectivity with respect to the substrate 100, the first active film pAP1, the first sacrificial film 530A, the second active film pAP2, and the second sacrificial film 530B.

[0083] As an example, the first sacrificial film 530A and the second sacrificial film 530B each include a silicon germanium (SiGe) film containing germanium (Ge) at a first concentration, and the base sacrificial film 504 and the intermediate sacrificial film 505 each include a silicon germanium (SiGe) film containing germanium (Ge) at a second concentration greater than the first concentration. At least one protective film (592, 594) is formed on the second active film pAP2 and the second sacrificial film 530B. In a subsequent process, at least one protective film (592, 594) may include various substances that protect the first active film pAP1, the first sacrificial film 530A, the second active film pAP2, and / or the second sacrificial film 530B. As an example, a first protective film 592 containing silicon oxide (SiO) and a second protective film 594 containing amorphous silicon (a-Si) are sequentially stacked on the second active film pAP2 and the second sacrificial film 530B.

[0084] Referring to FIGS. 18 and 19, a first base sacrificial pattern 104S, a second base sacrificial pattern 204S, a first lower active pattern AP11, a first lower sacrificial pattern 531A, a second lower active pattern AP21, a second lower sacrificial pattern 532A, a first intermediate sacrificial pattern 105S, a second intermediate sacrificial pattern 205S, a first upper active pattern AP12, a first upper sacrificial pattern 531B, a second upper active pattern AP22, and a second upper sacrificial pattern 532B are formed on a substrate 100. For reference, FIG. 19 is a cross-sectional view taken along line A-A of FIG. 18.

[0085] The first base sacrificial pattern 104S, the second base sacrificial pattern 204S, the first lower active pattern AP11, the first lower sacrificial pattern 531A, the second lower active pattern AP21, the second lower sacrificial pattern 532A, the first intermediate sacrificial pattern 105S, the second intermediate sacrificial pattern 205S, the first upper active pattern AP12, the first upper sacrificial pattern 531B, the second upper active pattern AP22, and the second upper sacrificial pattern 532B each extend in a first direction X. For example, a patterning process is performed to pattern the base sacrificial film 504, the first active film pAP1, the first sacrificial film 530A, the intermediate sacrificial film 505, the second active film pAP2, the second sacrificial film 530B, and at least one protective film (592, 594) shown in FIGS. 16 and 17. In one embodiment, in the process of etching the base sacrificial film 504, a part of the substrate 100 is etched to form the first fin pattern 110 on the first region I and the second fin pattern 210 on the second region II.

[0086] Referring to FIG. 20, a first filling insulating film 602 is formed. The first filling insulating film 602 fills the regions between the first lower active pattern AP11 and the second lower active pattern AP21 and between the first upper active pattern AP12 and the second upper active pattern AP22. For example, the first filling insulating film 602 covers the result of FIG. 19. The first filling insulating film 602 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, but is not limited thereto. As an example, the first filling insulating film 602 includes a silicon nitride film.

[0087] Referring to FIG. 21, the first base sacrificial pattern 104S, the second base sacrificial pattern 204S, the first intermediate sacrificial pattern 105S, and the second intermediate sacrificial pattern 205S are exposed. For example, a part of the first filling insulating film 602 is removed to expose the side surfaces of the first base sacrificial pattern 104S, the second base sacrificial pattern 204S, the first intermediate sacrificial pattern 105S, and the second intermediate sacrificial pattern 205S. In one embodiment, the first filling insulating film 602 that fills the regions between the first lower active pattern AP11 and the second lower active pattern AP21 and between the first upper active pattern AP12 and the second upper active pattern AP22 may not be removed.

[0088] Referring to FIG. 22, the first base sacrificial pattern 104S, the second base sacrificial pattern 204S, the first intermediate sacrificial pattern 105S, and the second intermediate sacrificial pattern 205S are removed. Since the first base sacrificial pattern 104S, the second base sacrificial pattern 204S, the first intermediate sacrificial pattern 105S, and the second intermediate sacrificial pattern 205S have an etching selectivity with respect to the substrate 100, the active patterns (AP11, AP12, AP21, AP22), and the sacrificial patterns (531A, 532A, 531B, 532B), they can be selectively removed.

[0089] Referring to FIG. 23, the second filling insulating film 604 is formed. The second filling insulating film 604 fills the regions where the first base sacrificial pattern 104S, the second base sacrificial pattern 204S, the first intermediate sacrificial pattern 105S, and the second intermediate sacrificial pattern 205S have been removed. For example, the second filling insulating film 604 covers the result of FIG. 22. The second filling insulating film 604 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, but is not limited thereto. As an example, the second filling insulating film 604 includes a silicon nitride film.

[0090] Referring to FIG. 24, the wall structure 102, the first base insulating film 104, the second base insulating film 204, the first intermediate insulating film 105, and the second intermediate insulating film 205 are formed. For example, a field insulating film 106 is formed on the second filling insulating film 604. The field insulating film 106 exposes the active patterns (AP11, AP12, AP21, AP22) and the sacrificial patterns (531A, 532A, 531B, 532B). For example, the upper surface of the field insulating film 106 is formed lower than the lower surface of the first lower sheet pattern 111.

[0091] Next, a recess process for the second filling insulating film 604 is performed. As a result, a first base insulating film 104 is formed between the substrate 100 and the first lower active pattern AP11, and a second base insulating film 204 is formed between the substrate 100 and the second lower active pattern AP21. Next, the first filling insulating film 602 on at least one of the protective films (592, 594) is removed. Next, at least one of the protective films (592, 594) is removed. As a result, a wall structure 102 is formed that separates the first lower active pattern AP11 and the second lower active pattern AP21, and separates the first upper active pattern AP12 and the second upper active pattern AP22.

[0092] Referring to FIGS. 25 and 26, a first mask pattern MP1 is formed on the second region II of the substrate 100. For reference, FIG. 26 is a cross-sectional view taken along line A-A of FIG. 25. The first mask pattern MP1 covers the second region II of the substrate 100. For example, the first mask pattern MP1 covers the second lower active pattern AP21, the second lower sacrificial pattern 532A, the second upper active pattern AP22, and the second upper sacrificial pattern 532B. The first mask pattern MP1 can also cover at least a part of the wall structure 102, but is not limited thereto.

[0093] Referring to FIGS. 27 to 29, a dummy gate structure DG1 and a first gate spacer 140 are formed on the first region I of the substrate 100. For reference, FIG. 28 is a cross-sectional view taken along line A-A of FIG. 27, and FIG. 29 is a cross-sectional view taken along line B-B of FIG. 27. The dummy gate structure DG1 intersects the first lower active pattern AP11, the first lower sacrificial pattern 531A, the first upper active pattern AP12, and the first upper sacrificial pattern 531B. For example, the dummy gate structure DG1 extends in the second direction Y on the first side surface 102a of the wall structure 102.

[0094] In one embodiment, the dummy gate structure DG1 includes a dummy gate dielectric film 520 and a dummy gate electrode 530. For example, a dielectric film and an electrode film that are sequentially stacked are formed on the first region I of the substrate 100. Next, a gate mask 550 extending in the second direction Y is formed on the electrode film on the first region I. Next, a patterning process is performed to pattern the dielectric film and the electrode film using the gate mask 550 as an etching mask. The patterned dielectric film forms the dummy gate dielectric film 520, and the patterned electrode film forms the dummy gate electrode 530.

[0095] The dummy gate structure DG1 has an etching selectivity with respect to the first lower active pattern AP11, the first lower sacrificial pattern 531A, the first upper active pattern AP12, and the first upper sacrificial pattern 531B. As an example, the dummy gate electrode 530 includes a polysilicon (poly Si) film. Next, a first gate spacer 140 is formed on the side surface of the dummy gate structure DG1. The first gate spacer 140 extends along the side surface of the dummy gate structure DG1. The first gate spacer 140 may include, for example, at least one of silicon nitride, silicon oxynitride, silicon oxycarbide, boron silicon nitride, boron silicon carbonitride, silicon oxycarbonitride, and combinations thereof, but is not limited thereto.

[0096] Referring to FIG. 30, an etching process is performed on the first lower active pattern AP11, the first lower sacrificial pattern 531A, the first upper active pattern AP12, and the first upper sacrificial pattern 531B. The etching process uses, for example, the dummy gate structure DG1 and the first gate spacer 140 as etching masks. By performing the etching process, a first recess 110r is formed outside the dummy gate structure DG1. In one embodiment, the first recess 110r is defined on the upper surface of the first base insulating film 104.

[0097] Referring to FIG. 31, a first lower source / drain pattern 160A, a first upper source / drain pattern 160B, and an interlayer insulating film 180 are formed. The first lower source / drain pattern 160A fills the lower part of the first recess 110r. For example, an epitaxial growth process is performed using the first lower active pattern AP11 as a seed layer. Thereby, the first lower source / drain pattern 160A connected to the first lower active pattern AP11 is formed. The first upper source / drain pattern 160B fills the upper part of the first recess 110r.

[0098] For example, a first isolation insulating film 108 that covers the first lower source / drain pattern 160A and exposes the first upper active pattern AP12 is formed. Next, an epitaxial growth process is performed using the first upper active pattern AP12 as a seed layer. Thereby, the first upper source / drain pattern 160B connected to the first upper active pattern AP12 is formed. Next, an interlayer insulating film 180 that covers the first upper source / drain pattern 160B is formed. The interlayer insulating film 180 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, boron silicon nitride, boron silicon carbonitride, silicon oxycarbonitride, and a low dielectric constant material having a dielectric constant smaller than that of silicon oxide, but is not limited thereto.

[0099] Referring to FIG. 32, the dummy gate structure DG1 is removed. Since the dummy gate structure DG1 has an etching selectivity with respect to the first lower active pattern AP11, the first lower sacrificial pattern 531A, the first upper active pattern AP12, and the first upper sacrificial pattern 531B, it can be selectively removed. By removing the dummy gate structure DG1, the first lower active pattern AP11, the first lower sacrificial pattern 531A, the first upper active pattern AP12, and the first upper sacrificial pattern 531B disposed inside the first gate spacer 140 are exposed.

[0100] Referring to FIG. 33, the first lower sacrificial pattern 531A and the first upper sacrificial pattern 531B are removed. Since the first lower sacrificial pattern 531A and the first upper sacrificial pattern 531B have an etching selectivity with respect to the first lower active pattern AP11 and the first upper active pattern AP12, they can be selectively removed.

[0101] Referring to FIGS. 34 to 36, the first gate structure GS1 is formed. For reference, FIG. 35 is a cross-sectional view taken along line A-A of FIG. 34, and FIG. 36 is a cross-sectional view taken along line B-B of FIG. 34. For example, the first gate dielectric film 120 and the first gate electrode 130 are sequentially stacked on the first lower active pattern AP11 and the first upper active pattern AP12. Next, a patterning process for the first gate dielectric film 120 and the first gate electrode 130 is performed. Thereby, the first gate structure GS1 surrounding at least one of the first lower bridge patterns (111 to 114) and at least one of the first upper bridge patterns (115 to 118) is formed.

[0102] Referring to FIGS. 37 and 38, the second mask pattern MP2 is formed on the first region I of the substrate 100. For reference, FIG. 38 is a cross-sectional view taken along line A-A of FIG. 37. The second mask pattern MP2 covers the first region I of the substrate 100. For example, the second mask pattern MP2 covers the first lower active pattern AP11, the first upper active pattern AP12, the first lower source / drain pattern 160A, the first upper source / drain pattern 160B, and the first gate structure GS1. The second mask pattern MP2 can also cover at least a part of the wall structure 102, but is not limited thereto.

[0103] Referring to FIGS. 39 to 41, a second lower source / drain pattern 260A, a second upper source / drain pattern 260B, and a second gate structure GS2 are formed on the second region II of the substrate 100. For reference, FIG. 40 is a cross-sectional view taken along line A-A of FIG. 39, and FIG. 41 is a cross-sectional view taken along line B-B of FIG. 39. Except for being formed on the second region II of the substrate 100, forming the second lower source / drain pattern 260A, the second upper source / drain pattern 260B, and the second gate structure GS2 is the same as forming the first lower source / drain pattern 160A, the first upper source / drain pattern 160B, and the first gate structure GS1, so detailed description will be omitted below.

[0104] Next, referring to FIGS. 1 to 6, a first gate contact CB1 connected to the first gate structure GS1 and a second gate contact CB2 connected to the second gate structure GS2 are formed. Thereby, the semiconductor device described above with reference to FIGS. 1 to 6 is manufactured.

[0105] FIG. 42 is an intermediate stage diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. For convenience of explanation, parts overlapping with the content described above with reference to FIGS. 1 to 41 will be briefly described or omitted. Referring to FIG. 42, the second active film pAP2 includes at least one upper active film (515 to 519) sequentially stacked on the intermediate sacrificial film 505. For reference, FIG. 42 is another cross-sectional view taken along line A-A of FIG. 16. In one embodiment, the number of at least one upper active film (515 to 519) is larger than the number of at least one lower active film (511 to 514). Next, the steps described above are performed using FIGS. 18 to 41. Thereby, the semiconductor device described above using FIGS. 8 and 9 can be manufactured.

[0106] FIG. 43 is an intermediate stage diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. For convenience of explanation, parts overlapping with the content described above using FIGS. 1 to 41 will be briefly explained or omitted. Referring to FIG. 43, the second active film pAP2 includes at least one upper active film (515 to 518) sequentially laminated on the intermediate sacrificial film 505. For reference, FIG. 43 is another cross-sectional view taken along the line A-A of FIG. 16. In one embodiment, a part of the plurality of upper active films (515 to 518) has a thickness different from that of another part of the plurality of upper active films (515 to 518). Next, the steps described above are performed using FIGS. 18 to 41. Thereby, the semiconductor device described above using FIGS. 10 and 11 can be manufactured.

[0107] Note that the present invention is not limited to the above-described embodiments. Various modifications can be made without departing from the technical scope of the present invention.

Description of Reference Numerals

[0108] 100 Substrate 102 Wall structure 102a First side surface 102b Second side surface 104 First base insulating film 106 Field insulating film 110 First fin pattern 111 to 114 (First lower bridge pattern) (First to fourth) lower sheet patterns 115 to 119 (First upper bridge pattern) (First to fifth) upper sheet patterns 120 First gate dielectric film 130 First gate electrode 132 First work function adjustment film 132a First lower work function adjustment film 132b First upper work function adjustment film 134 First filling conductive film 140 First gate spacer 160A First lower source / drain pattern 160B First upper source / drain pattern 180 Interlayer insulating film 204 Second base insulating film 205 Second intermediate insulating film 208 Second separation insulating film 210 Second fin pattern 211~214 (Second lower bridge pattern)(Fifth~Eighth) lower sheet pattern 215~219 (Second upper bridge pattern)(Fifth~Ninth) upper sheet pattern 220 Second gate dielectric film 230 Second gate electrode 232 Second work function adjustment film 232a Second lower work function adjustment film 232b Second upper work function adjustment film 234 Second filling conductive film 240 Second gate spacer 260A Second lower source / drain pattern 260B Second upper source / drain pattern AP11 First lower active pattern AP12 First upper active pattern AP21 Second lower active pattern AP22 Second upper active pattern CB1, CB2 (First, Second) gate contact GS1, GS2 (First, Second) gate structure

Claims

1. A substrate, on the substrate, a wall structure extending in a first direction, the wall structure including a first side surface and a second side surface facing each other in a second direction intersecting the first direction, on the first side surface, a first lower active pattern including at least one first lower bridge pattern spaced apart from the substrate, on the first side surface, a first upper active pattern including at least one first upper bridge pattern spaced apart from the substrate more than the first lower active pattern, on the first side surface, a first gate structure intersecting the first lower active pattern and the first upper active pattern, on the second side surface, a second lower active pattern including at least one second lower bridge pattern spaced apart from the substrate, on the second side surface, a second upper active pattern including at least one second upper bridge pattern spaced apart from the substrate more than the second lower active pattern, on the second side surface, a second gate structure intersecting the second lower active pattern and the second upper active pattern, and having, in the second direction, a semiconductor device characterized in that a width of the wall structure increases as it moves away from the substrate.

2. The semiconductor device according to claim 1, characterized in that in the second direction, a width of the at least one first upper bridge pattern is smaller than a width of the at least one first lower bridge pattern.

3. The semiconductor device according to claim 1, characterized in that in a third direction intersecting the first direction and the second direction, a thickness of the at least one first upper bridge pattern is larger than a thickness of the at least one first lower bridge pattern.

4. The semiconductor device according to claim 1, characterized in that a number of the at least one first upper bridge patterns is larger than a number of the at least one first lower bridge patterns.

5. The semiconductor device according to claim 1, further comprising a base insulating film electrically separating the substrate and the first lower active pattern between the substrate and the first lower active pattern.

6. The semiconductor device according to claim 1, further comprising an intermediate insulating film electrically separating the first lower active pattern and the first upper active pattern between the first lower active pattern and the first upper active pattern.

7. The first gate structure includes a gate dielectric film and a gate electrode that are sequentially stacked on the first lower active pattern and the first upper active pattern. The semiconductor device according to claim 1, wherein a part of the gate dielectric film is interposed between the wall structure and the gate electrode.

8. On a side surface of the first gate structure, a first lower source / drain pattern connected to the first lower active pattern in the first direction, On a side surface of the first gate structure, a first upper source / drain pattern connected to the first upper active pattern in the first direction, On a side surface of the second gate structure, a second lower source / drain pattern connected to the second lower active pattern in the first direction, The semiconductor device according to claim 1, further comprising, on a side surface of the second gate structure, a second upper source / drain pattern connected to the second upper active pattern in the first direction.

9. The first lower source / drain pattern and the first upper source / drain pattern each contain impurities of a first conductivity type. The semiconductor device according to claim 8, wherein the second lower source / drain pattern and the second upper source / drain pattern each contain impurities of a second conductivity type different from the first conductivity type.

10. The first lower source / drain pattern and the second lower source / drain pattern each contain impurities of a first conductivity type. The semiconductor device according to claim 8, wherein the first upper source / drain pattern and the second upper source / drain pattern each contain impurities of a second conductivity type different from the first conductivity type.

11. A substrate, On the substrate, a wall structure extending in a first direction, the wall structure including a first side surface and a second side surface facing each other in a second direction intersecting the first direction, On the first side surface, a first lower active pattern including at least one first lower bridge pattern separated from the substrate, On the first side surface, a first upper active pattern including at least one first upper bridge pattern separated from the substrate more than the first lower active pattern, On the first side surface, a first gate structure intersecting the first lower active pattern and the first upper active pattern On the second side surface, a second lower active pattern including at least one second lower bridge pattern separated from the substrate; On the second side surface, a second upper active pattern including at least one second upper bridge pattern separated from the substrate more than the second lower active pattern; On the second side surface, a second gate structure intersecting the second lower active pattern and the second upper active pattern; and it has, In the second direction, the width of the at least one first upper bridge pattern is smaller than the width of the at least one first lower bridge pattern, In a third direction intersecting the first direction and the second direction, a semiconductor device characterized in that the thickness of the at least one first upper bridge pattern is larger than the thickness of the at least one first lower bridge pattern.

12. The semiconductor device according to claim 11, characterized in that in the second direction, the width of the wall structure increases as it moves away from the substrate.

13. The semiconductor device according to claim 11, characterized in that in the third direction, the thickness of the at least one second upper bridge pattern is larger than the thickness of the at least one second lower bridge pattern.

14. The at least one first lower bridge pattern includes a first lower sheet pattern and a second lower sheet pattern that are sequentially stacked on the substrate and are separated from each other, The at least one first upper bridge pattern includes a first upper sheet pattern and a second upper sheet pattern that are sequentially stacked on the first lower active pattern and are separated from each other, The semiconductor device according to claim 11, characterized in that the distance between the first upper sheet pattern and the second upper sheet pattern is smaller than the distance between the first lower sheet pattern and the second lower sheet pattern.

15. The semiconductor device according to claim 11, characterized in that in a cross-section intersecting the first direction, the cross-sectional area of the first upper active pattern is the same as the cross-sectional area of the first lower active pattern.

16. A substrate, On the substrate, a wall structure extending in a first direction, the wall structure including a first side surface and a second side surface facing each other in a second direction intersecting the first direction; On the first side surface, a first lower active pattern including at least one first lower bridge pattern separated from the substrate; On the first side surface, a first upper active pattern including at least one first upper bridge pattern separated from the substrate by the first lower active pattern; On the first side surface, a first gate structure intersecting the first lower active pattern and the first upper active pattern; On the second side surface, a second lower active pattern including at least one second lower bridge pattern separated from the substrate; On the second side surface, a second upper active pattern including at least one second upper bridge pattern separated from the substrate by the second lower active pattern; On the second side surface, a second gate structure intersecting the second lower active pattern and the second upper active pattern, and having: In the second direction, the width of the at least one first upper bridge pattern is smaller than the width of the at least one first lower bridge pattern; A semiconductor device, wherein the number of the at least one first upper bridge patterns is larger than the number of the at least one first lower bridge patterns.

17. The semiconductor device according to claim 16, wherein in the second direction, the width of the wall structure increases as it moves away from the substrate.

18. The semiconductor device according to claim 16, wherein the number of the at least one second upper bridge patterns is larger than the number of the at least one second lower bridge patterns.

19. The at least one first lower bridge pattern includes a first lower sheet pattern and a second lower sheet pattern that are sequentially stacked on the substrate and spaced apart from each other; The at least one first upper bridge pattern includes a first upper sheet pattern and a second upper sheet pattern that are sequentially stacked on the first lower active pattern and spaced apart from each other; The semiconductor device according to claim 16, wherein the distance between the first upper sheet pattern and the second upper sheet pattern is smaller than the distance between the first lower sheet pattern and the second lower sheet pattern.

20. The semiconductor device according to claim 16, wherein in a cross section intersecting the first direction, the cross-sectional area of the first upper active pattern is the same as the cross-sectional area of the first lower active pattern.

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