Method for manufacturing ceramic thin film metalization substrate, method for manufacturing chip-on-submount, and method for manufacturing semiconductor module

Abstract

To manufacture a ceramic thin film metalization substrate improved in cost performance.SOLUTION: A method for manufacturing a substrate in which a thin film metalization 4 consists of an adhesive layer, a barrier layer and a surface layer and a ceramic substrate 5 is an aluminum nitride substrate includes the steps of: coating the ceramic substrate with an ultraviolet curable resist 7; performing prebake at a temperature of 60°C or higher to 90°C or lower and for a time of 70 sec or longer to 120 sec or shorter; performing primary exposure with an integrated irradiation amount of 10 mJ / cm2 or more to 50 mJ / cm2 or less; performing inversion bake at a temperature of 110°C or higher to 140°C or lower and for a time of 40 sec or longer to 90 sec or shorter; performing secondary exposure with an integrated irradiation amount of 260 mJ / cm2 or more to 350 mJ / cm2 or less; performing development with a developer; forming the thin film metalization; and peeling the resist with a peeling solution and forming a pattern circuit.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] Embodiments generally relate to a method for manufacturing a ceramic thin film metallized substrate, a method for manufacturing a chip-on-sub mount, and a method for manufacturing a semiconductor module.

Background Art

[0002] In recent years, high-performance light-emitting semiconductor devices such as laser diodes (LDs), high-power LEDs for general lighting to headlamps, and deep ultraviolet LEDs (sterilization lamps, resin curing lamps) with strong requirements for high heat dissipation have been developing. Along with the development of these light semiconductor devices, the demand for ceramic substrates having both heat dissipation and electrical insulation properties has been increasing year by year. In particular, as the heat generation of the light semiconductor device increases with high performance, the ceramic substrate tends to be smaller and thinner in order to efficiently dissipate heat. Among ceramic substrates, an aluminum nitride substrate (AlN) with high heat dissipation has an insulating support member made of an aluminum nitride sintered body, and a metal layer in which a titanium (Ti) layer, a platinum (Pt) layer, and an (Au) layer are sequentially deposited on the lower surface and the upper surface is formed for a light semiconductor device package component (Patent Document 1). According to Patent Document 1, the thermal conductivity of the aluminum nitride sintered body is 55 to 250 W / m·K, and the heat generated by the light semiconductor device during driving is dissipated to the outside through the insulating support member and the metal substrate. As a result, compared with an aluminum oxide sintered body having a thermal conductivity of about 20 W / m·K, the light semiconductor device can always be kept at an appropriate temperature and driven normally and stably for a long period of time.

[0003]

[0004] ​​​​​​​​In order to reduce the manufacturing cost of a ceramic substrate having both heat dissipation and electrical insulation properties, , manufacturing in a large shape has been carried out. As one of the manufacturing methods for dividing a large-sized aluminum nitride substrate into submounts for semiconductor laser elements, a manufacturing method of cutting from a substrate having a thermal conductivity of 200 W / m· K, a thickness of 0.5 mm, and a 2-inch substrate into 1 mm square is disclosed (Patent Document 2).

[0005] The metal layer formed on these insulating substrates is subjected to pattern circuit formation on the conductive layer portion and the insulating portion without the metal layer as necessary. For the formation of the pattern circuit, an etching method or a lift-off method is disclosed (Patent Document 3). According to Patent Document 3, after forming a thin film material on a substrate, a photoresist material is applied, primary exposure using ultraviolet light is performed, a protective film layer having resistance to etching of any photoresist is formed, and unnecessary portions are selectively removed to form a pattern circuit.

[0006] In order to reduce the manufacturing cost, it is advantageous to process from a larger substrate. On the other hand, with the miniaturization and high performance of the semiconductor module into which the cut product is incorporated, the product size becomes smaller and the pattern circuit becomes finer (more delicate). However, as the substrate increases in size, it is necessary to uniformly manufacture the non-circuit (substrate portion) that insulates the circuit portions composed of the conductive layers of the products divided into individual pieces and the circuits on the entire surface of the substrate, and the manufacturing method becomes difficult as the size of the substrate before cutting increases.

[0007] As a method for forming a circuit pattern on the surface of a ceramic substrate, there is a lithography process in which a resist is applied, a pattern is formed by exposure, and development is performed. To manufacture the product uniformly ​​​​​​​To do so, it is necessary to uniformly perform the process from resist coating to development in the lithography process. There is.

[0008] That is, as the substrate becomes larger, the number of products to be cut increases, the working efficiency improves, and the manufacturing cost is reduced. However, differences occur in the resist coated with the pattern between the central part and the peripheral part of the product, and defects caused by the resist are likely to occur. Therefore, in order to uniformly form a fine pattern on a large substrate, it has been found that control of the lithography process from resist coating to development is necessary. has been found.

Prior Art Documents

Patent Documents

[0009]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0010] In recent years, with the development of high-performance light semiconductor devices such as laser diodes and LEDs, the demand for ceramic circuit boards having both heat dissipation, electrical insulation, and circuit conductivity has been increasing year by year. In particular, with the miniaturization and high-performance of the devices, the heat generation of the devices increases, and the high reliability of the ceramic circuit board is required. Therefore, a ceramic thin film metallized substrate (sub mount) having both heat dissipation and electrical insulation and forming a conductive circuit without impairing the high reliability is required. mount) having both heat dissipation and electrical insulation and forming a conductive circuit is required.

[0011] ​​​​The embodiment solves such problems and enables efficient production of small substrates from large ceramic thin film metallized substrates, with excellent cost performance. It relates to a method for manufacturing a ceramic thin film metallized substrate.

Means for Solving the Problems

[0012] The method for manufacturing a ceramic thin film metallized substrate according to the embodiment is such that in the lithography process, after resist coating, the pre-bake temperature is 60°C or higher and 100°C or lower, and the time is 70 seconds or more and 120 seconds or less, the integrated exposure dose after pre-bake is 10 mJ / cm 2 or more and 50 m J / cm 2 or less, the temperature of the post-first-exposure reversal bake is 110°C or higher and 140°C or lower, and the time is 40 seconds or more and 90 seconds or less, the integrated exposure dose after the post-reversal bake second exposure is 260 mJ / cm 2 or more and 350 mJ / cm 2 or less, and after development after the second exposure, a pattern circuit is formed by thin film metallization. This is a manufacturing method.

Brief Description of the Drawings

[0013]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

[0014] Hereinafter, a method for manufacturing a ceramic thin-film metallized substrate, a chip-on Detailed description of embodiments of the method for manufacturing a submount and the method for manufacturing a semiconductor module will explain.

[0015] The pattern circuit provided on the ceramic thin film metallized substrate according to the embodiment is a ceramic The conductive and insulating parts are shown by thin-film metallization on the surface of the mixed circuit board, and are divided according to product size. This refers to both the circuit before and after division (hereafter referred to as "pattern circuit"). The formation of a circuit is a process in which conductive and insulating parts are formed on the surface of a ceramic substrate by thin-film metallization. This refers to the pattern circuit that is formed before dividing the ceramic substrate. (hereinafter referred to as "pattern circuit formation").

[0016] The method for forming a pattern circuit of a ceramic thin film metallized substrate according to the embodiment is as follows: In the lithography process, the pre-bake temperature after resist application is between 60℃ and 100℃. The lower part shows the time from 70 seconds to 120 seconds, and the first exposure (pattern exposure) area after pre-baking The calculated dose is 10 mJ / cm 2 More than 50mJ / cm 2 The following is an inversion base image after the first exposure. The baking temperature is 110℃ to 140℃, the baking time is 40 seconds to 90 seconds, and the baking time is 110℃ to 140℃. The cumulative dose of the second exposure (full exposure) was 260 mJ / cm 2 More than 350mJ / cm 2It is as follows , after performing development after the second exposure, a pattern circuit is formed. Hereinafter, the embodiments related to the manufacturing method of the ceramic thin film metallized substrate, the manufacturing method of the chip on submount, and the manufacturing method of the semiconductor module will be described in detail.

[0017] FIG. 1 shows a top view of an example before cutting of the ceramic thin film metallized substrate according to the embodiment . 1 is the ceramic thin film metallized substrate before cutting, 2 is the ceramic thin film metallized substrate, and 3 is the ceramic thin film metallized substrate after cutting. Note that the ceramic thin film meta lized substrate includes a large-sized ceramic thin film metallized substrate 2 from which a plurality of ceramic thin film metallized substrates 3 can be obtained by cutting (dividing). In FIG. 1, the ceramic thin film meta lized substrate 3 is substantially rectangular in plan view, but may be substantially polygonal.

[0018] FIG. 2 shows an example of a top view of the ceramic thin film metallized substrate 3 according to the embodiment. 4 is the thin film metallization, and 5 is the ceramic substrate. When the ceramic substrate 5 is an aluminum nitride substrate, the thermal conductivity can be 160 W / m·K or more, and further 240 W / m·K or more, with a high thermal conductivity. Other ceramic substrates 5 include aluminum oxide , beryllium oxide, etc. These ceramic substrates 5 may be single plates, or may have a three-dimensional structure such as a multi layer structure.

[0019] FIG. 3 is a side view of the ceramic thin film metallized substrate of FIG. 2. 6 is the thin film metallization . FIG. 4 is a bottom view of the thin film metallized substrate of FIG. 2. In FIG. 4, the thin film metallization is formed on the entire bottom surface of the ceramic substrate, but a circuit may be formed in the same manner as on the top surface, or a thin film ​​ It is acceptable to use a ceramic substrate without metallization. In the case of a heat sink, it is joined to the heat sink by brazing or soldering, and a thin metallization is formed. If not, it is joined to the heat sink with an adhesive such as resin.

[0020] FIG. 5 shows one of the steps of manufacturing a pattern circuit of a ceramic thin film metallized substrate according to an embodiment. 1A is a cross-sectional view of a ceramic substrate 5 before processing, and FIG. The surface of the ceramic substrate 5 is coated with a resist 7. (C) shows the state after pre-baking. The ceramic substrate 5 is subjected to a first exposure through a mask 8. (D) shows the state where the unexposed portion of the resist 9 is irradiated with ultraviolet light. The resist 9 is exposed on the ceramic substrate. After that, a second exposure is performed. (E) shows the exposed resist by etching the resist surface. 9 is formed on the surface of the ceramic substrate 5. (F) shows the exposed resist 9 and FIG. 1(G) shows the state in which a thin metallization film 10 is formed on the surface of the ceramic substrate 5. The resist 9 is then removed (lifted off) to leave a thin film metal film on the surface of the ceramic substrate 5. This is the state in which the talize 4 has been formed.

[0021] The process for manufacturing a ceramic thin film metallized substrate is as follows: After applying resist to the laminated substrate, the pre-bake temperature is 60℃ or higher and 100℃ or lower. The pre-bake time is between 70 and 120 seconds. The purpose of pre-bake is to dry the resist uniformly. However, if the temperature is lower than 60°C and the time is shorter than 70 seconds, the resist will Some areas become liquid or semi-dried, and the pattern cannot be exposed by the first exposure. Conversely, if the temperature exceeds 100°C and the time exceeds 120 seconds, the resist will be overheated. Bridges occur, and the pattern cannot be exposed. The temperature is preferably 70° C. or higher and 90° C. or lower, and the time is preferably 80 seconds or higher and 110 seconds or lower.

[0022] For the first exposure after pre-baking, the cumulative exposure dose was 10 mJ / cm 2 More than 50mJ / cm 2 Below The purpose of the first exposure is to expose the resist through a mask and to expose the resist in the exposed area. The change in the quality of the ceramic substrate causes the pattern shape to be exposed to light. Irradiance is 10mJ / cm 2 If it is smaller, there will be areas where the pattern shape cannot be fully exposed. On the other hand, the cumulative irradiation dose is 50 mJ / cm 2 If it is larger than this, the inside of the mask will be exposed to light, This is because there are areas where the pattern accuracy is poor. The cumulative dose is 20 mJ / cm 2 More than 40mJ / cm 2 It is preferable that:

[0023] For the reversal bake after the first exposure, the temperature should be 110℃ or higher and 140℃ or lower, and the time should be 40 seconds or less. In the reverse bake, the resist exposed to the first exposure is preferentially crosslinked (crosslinked). When the temperature drops below 110°C and the time is shorter than 40 seconds, the heat is released. The bridge does not advance, and the pattern shape and precision are not uniform. If the temperature exceeds 140°C and the time exceeds 90 seconds, crosslinking will progress to the non-exposed areas. This is because there are portions where the pattern shape and accuracy are not uniform. Furthermore, for the reverse bake the temperature of the bake is preferably 120°C or higher and 130°C or lower, and the time is preferably 50 seconds or longer and 80 seconds or shorter.

[0024] Regarding the post-reverse bake secondary exposure, the integrated exposure dose is 260 mJ / cm 2 or more and 350 mJ / cm 2 or less. The purpose of the secondary exposure is to expose the uncrosslinked portions that have been primary exposed and undergone reverse bake. If the integrated exposure dose is less than 260 mJ / cm 2 there may be portions where the resist cannot be removed during the subsequent development process. If the integrated exposure dose is greater than 350 mJ / cm 2 crosslinking progresses and the pattern accuracy deteriorates. Furthermore, the integrated exposure dose of the secondary exposure after reverse bake is preferably 270 mJ / cm or more and 340 mJ / cm 2 or less. 2 It is preferred that be the case.

[0025] After the secondary exposure, development is performed, and the exposed portions of the resist that have been exposed on the ceramic substrate remain (E). After ashing the ceramic substrate with the remaining resist exposed portions, a thin film metallization film is formed on the surface (F). Methods for forming the thin film metallization include vapor deposition methods and sputtering methods. The metal for forming the thin film metallization is, for example, a three-layer structure such as an adhesion layer, a barrier layer, and a surface layer. The adhesion layer is a metal layer formed to bond the metal to the surface of the ceramic substrate, and examples include titanium (Ti). The barrier layer is located between the adhesion layer and the surface layer and is a metal layer formed to prevent the mutual diffusion of metals, and examples include platinum (Pt) and palladium (Pd). The surface layer is a metal layer formed for bonding to other components, and examples include gold (Au). diffusion of metals, and examples include platinum (Pt) and palladium (Pd). The surface layer is a metal layer formed for bonding to other components, and examples include gold (Au). diffusion of metals, and examples include platinum (Pt) and palladium (Pd). The surface layer is a metal layer formed for bonding to other components, and examples include gold (Au). diffusion of metals, and examples include platinum (Pt) and palladium (Pd). The surface layer is a metal layer formed for bonding to other components, and examples include gold (Au). , nickel (Ni), copper (Cu), etc. After thin film metallization, the resist is peeled off. A thin film metallization pattern circuit is formed by lifting off (G).

[0026] When thin-film metallization is to be performed on the back side of the pattern circuit, ashing is then performed in the same manner as for the front side. When forming a bonding layer on the surface of the thin metallization, a solder is used. The bonding layer is formed by, for example, gold-tin (Au-Sn) solder. After forming the pattern circuit using these thin film metallization and bonding layers, the product size is cut. The cutting is performed using a dicer or the like. The substrate 3 is a chip-on-sub-mount substrate characterized in that a semiconductor element is mounted via a bonding layer. It is suitable for case 11.

[0027] FIG. 6 shows an example of a chip-on-submount according to an embodiment. In FIG. 6, 5 is a ceramic substrate. The reference numeral 6 denotes a thin film metallization, 12 denotes solder, and 13 denotes a semiconductor element. The submount 11 is mounted on a heat sink via a bonding layer. This is suitable for the semiconductor module 14 characterized by the above.

[0028] FIG. 7 shows an example of a semiconductor module (semiconductor device) according to the embodiment. In FIG. Wire bonding, 16 is a semiconductor device that bonds the chip-on-submount and the heat sink Reference numeral 17 denotes a lead frame. Reference numeral 18 denotes a heat sink.

[0029] In FIG. 7, the chip-on-submount 11 is mounted on the heat sink 18 via the bonding layer 16. The semiconductor element 13 and the thin film metallization 4 are electrically connected by wire bonding 15. is also provided. In addition to the semiconductor element 13, the thin film metallization 6 and the lead frame 17 are joined by wire bonding 15. The wire bonding 15 and the lead frame 17, and the chip on submount 11 connected by the bonding layer 16 and the heat sink 18 are used as the semiconductor module 14. The semiconductor module 14 is not limited to such a structure. For example, either the wire bonding 15 or the lead frame 17 may be used. In addition, a plurality of semiconductor elements 13, wire bondings 15, and lead frames 17 may be provided in the semiconductor module 14, respectively.

[0030] In addition, the bonding layers 12 and 16 for bonding the semiconductor element 13 and the heat sink 18 include solder, brazing material, etc. Solder is preferably lead-free solder. Also, the solder has a melting point of 4 50 °C or lower. The brazing material has a melting point exceeding 450 °C. Also, those with a melting point of 5 00 °C or higher are called high-temperature brazing materials. High-temperature brazing materials include those mainly composed of silver (Ag).

[0031] While the semiconductor element 13 is being miniaturized, the amount of heat generated from the chip is steadily increasing. Therefore, in the ceramic thin film metallization substrate 3 on which the semiconductor element 13 is mounted, improving heat dissipation is important. In addition, for the high performance of the semiconductor module 14, a plurality of semiconductor elements 13 are mounted in the semiconductor module 14. If even one semiconductor element 1 3 exceeds the true temperature of the element, the resistance changes to a negative temperature coefficient on the minus side. Along with this, thermal runaway occurs where electric power flows concentratedly and it is instantaneously destroyed. This phenomenon occurs. Therefore, improving heat dissipation is effective. Also, the semiconductor module 14 can be used for laser diodes, high-power LEDs for headlamps from general lighting LEDs, and deep ultraviolet LEDs (sterilization lamps, resin curing lamps) that require strong high heat dissipation. etc. Lasers and LEDs are advancing in high output, and improving the reliability of the semiconductor module 14 directly leads to improving the reliability of laser devices and LED lighting.

[0032] Next, a method for forming a pattern circuit of thin film metallization of the aluminum nitride substrate among the ceramic thin film metallization substrates 3 according to the embodiment will be described. The pattern circuit formation of the aluminum nitride substrate is not particularly limited as long as it has the above-described configuration, but the following methods can be mentioned as methods for obtaining a good yield. First, an aluminum nitride substrate is prepared. In particular, considering the heat dissipation of the entire ceramic thin film metallization substrate 3 generated from the aluminum nitride substrate, the thermal conductivity of the aluminum nitride substrate is preferably 170 W / m·K or more. Also, when conducting electrical connection between the thin film metallization side and the opposite side of the thin film metallization side where the pattern circuit is formed, an aluminum nitride substrate having a through hole by a through hole or via hole is prepared. When providing a through hole in the aluminum nitride substrate, the through hole may be provided at the preform stage. Also, a step of providing a through hole in the aluminum nitride substrate may be performed. The step of providing a through hole is performed by laser processing, cutting processing such as drilling, etc.

[0033] First, prepare an aluminum nitride substrate. In particular, considering the heat dissipation of the entire ceramic thin film metallization substrate 3 generated from the aluminum nitride substrate, the thermal conductivity of the aluminum nitride substrate is preferably 170 W / m·K or more. Also, when conducting electrical connection between the thin film metallization side and the opposite side of the thin film metallization side where the pattern circuit is formed, an aluminum nitride substrate having a through hole by a through hole or via hole is prepared. When providing a through hole in the aluminum nitride substrate, the through hole may be provided at the preform stage. Also, a step of providing a through hole in the aluminum nitride substrate may be performed. The step of providing a through hole is performed by laser processing, cutting processing such as drilling, etc. is preferably 170 W / m·K or more. Also, when conducting electrical connection between the thin film metallization side and the opposite side of the thin film metallization side where the pattern circuit is formed, an aluminum nitride substrate having a through hole by a through hole or via hole is prepared. When providing a through hole in the aluminum nitride substrate, the through hole may be provided at the preform stage. Also, a step of providing a through hole in the aluminum nitride substrate may be performed. The step of providing a through hole is performed by laser processing, cutting processing such as drilling, etc. is preferably 170 W / m·K or more. Also, when conducting electrical connection between the thin film metallization side and the opposite side of the thin film metallization side where the pattern circuit is formed, an aluminum nitride substrate having a through hole by a through hole or via hole is prepared. When providing a through hole in the aluminum nitride substrate, the through hole may be provided at the preform stage. Also, a step of providing a through hole in the aluminum nitride substrate may be performed. The step of providing a through hole is performed by laser processing, cutting processing such as drilling, etc.

[0034] Apply resist 7 to the aluminum nitride substrate. Use a coater or the like for the application. The resist may be a phenolic resin-based photoresist or the like. Next, perform resist application on the aluminum nitride substrate that has been pre-baked. The pre-baking may use a dedicated heating device, and if the coater has a baking function, it may be pre-baked as it is. Cool it after heating at a predetermined temperature and time.

[0035] Next, set the pre-baked aluminum nitride substrate in an exposure device and perform primary exposure. The primary exposure irradiates ultraviolet light or the like through a mask 8 with a pattern formed to expose the unmasked portion. Next, perform reversal baking on the aluminum nitride substrate that has undergone primary exposure. The reversal baking may use a dedicated heating device or the heating device of the coater. The reversal baking is held at a predetermined heating temperature and time and then cooled.

[0036] Next, set the reversally baked aluminum nitride substrate in an exposure device and perform secondary exposure. The secondary exposure exposes the entire surface of the substrate without using the mask 8. Next, remove the resist 7 other than the exposed resist 9 by development processing. Perform thin film metallization 10 on the aluminum nitride substrate with the exposed resist 9. There are methods such as evaporation method and sputtering method for thin film metallization. Peel off (lift off) the exposed resist 9 from the aluminum nitride substrate on which thin film metallization 10 has been performed to form a pattern circuit by thin film metallization 4.

[0037] When forming a bonding layer 12 such as solder on the surface of the thin film metallization by lithography, similar to the case of forming a thin film, perform resist application, exposure, development, solder film formation, and peeling (lift off). It is formed in the process. Examples of solder include Au-Sn, Au-Si (silicon), etc. In addition to forming a bonding layer by lithography, it is also possible to plate the entire surface to improve the bondability. Examples of plating include nickel (Ni)-based Au plating with palladium (Pd) as an underlayer, etc.

[0038] Next, a step of cutting the aluminum nitride substrate into the product size is performed. The aluminum nitride substrate with the pattern circuit formed thereon is cut into the product shape. The cutting is performed by a dicing saw or the like. Next, a step of bonding the semiconductor element 13, etc. is performed. A bonding layer is provided at the location where the semiconductor element 13 is to be bonded. The bonding layer is preferably solder or brazing material. After providing the bonding layer, the semiconductor element 13 is provided thereon.

[0039] Next, a step of bonding the aluminum nitride substrate with the semiconductor element 13 bonded thereto to the semiconductor module is performed. It is bonded to the heat sink 18 through the bonding layer. Also, if necessary, the pattern circuit formed by the thin film metallization 4 and the lead frame 17 are bonded by wire bonding 15. Also, the semiconductor element 13 and the pattern circuit formed by the thin film metallization 4 are bonded by wire bonding 15. Also, the semiconductor element 13, the lead frame 17, and the wire bonding 15 are provided in necessary numbers.

[0040] In the above, it has been described as being manufactured by bonding to the heat sink 18 through a bonding layer such as solder in a state where the thin film metallization 6 is formed on the back surface of the pattern circuit of the aluminum nitride substrate, but it is not limited to that case. For example, on the back surface of the pattern circuit, a thin film meta ​​​​​​​​​​​​When there is no rise 6 and the substrate is in the state of an aluminum nitride substrate, it may be joined to the heat sink 18 with any adhesive.

[0041] (Examples 1 - 9, Comparative Examples 1 - 8) For the ceramic thin - film metallized substrate, an aluminum nitride substrate with a diameter of 100 mm and a thickness of 0.32 mm (thermal conductivity 200 W / m·K) was prepared. Using a spin coater on the aluminum nitride substrate, the rotation speed and time were set at 200 rpm for 10 seconds, 1000 rpm for 15 seconds, 2000 rpm for 15 seconds, and 200 rpm for 2 seconds. A resist of 3 cm was dropped to coat the entire surface of the substrate with an ultraviolet - curable resist. 3

[0042] After resist coating, pre - baking was performed at the temperature and time shown in Table 1 using a spin coater. Next, as shown in FIGS. 1 and 2, a circuit pattern with two conductor parts of 0.6 mm × 0.3 mm spaced 0.1 mm apart was formed on a product size of 0.9 mm × 0.9 mm after cutting, and a glass mask with a diameter of 100 mm was prepared. An exposure machine (parallel light mask aligner) was set with the aluminum nitride substrate and the glass mask, and the exposure operation was performed under the conditions shown in Table 1. Next, the aluminum nitride substrate was set in a spin coater and reverse - baking was performed under the conditions shown in Table 1. Next, the aluminum nitride substrate was set in the exposure machine and secondary exposure was performed under the conditions shown in Table 1.

[0043]

Table 1

[0044] As can be seen from Table 1, in Examples 1 - 9, the pre - baking temperature, pre - baking time, primary exposure The values of the integrated exposure dose, reverse bake temperature, reverse bake time, and secondary exposure integrated exposure dose were within the preferable ranges. On the other hand, in Comparative Examples 1 to 8, those values were outside the preferable ranges.

[0045] Next, after the secondary exposure, the aluminum nitride substrate was set in a solvent-resistant cassette and developed by oscillating in the developing solution in a constant temperature bath at 25°C for 150 seconds. The developing solution used was a lithography developing solution obtained by adding a nonionic surfactant to tetramethylammonium hydroxide. The developed aluminum nitride substrate was washed with pure water and then dried by rotating at 3000 rpm for 3 minutes in a spin dryer.

[0046]

[0046] Next, the aluminum nitride substrate was ashed in an asher device. The ashing conditions were performed at an RF power of 400 W for 1 minute. Next, titanium (Ti) 0.1 μm, platinum (Pt) 0.2 μm, and gold (Au) 0.3 μm were sequentially deposited on the aluminum nitride substrate in an electron beam evaporation device. Next, the aluminum nitride substrate was set in a solvent-resistant cassette and the resist was peeled off by oscillating in the resist stripping solution in a constant temperature bath at 50°C for 45 minutes. The resist stripping solution used was an alkaline resist stripping solution based on N-methyl-2-pyrrolidone. The aluminum nitride substrate after resist stripping was washed with pure water. Next, the aluminum nitride substrate was cut by a dicing saw.

[0047] Regarding the products cut by the dicing saw, the pattern shape and peeling state were confirmed with a stereomicroscope. Products with unevenness at the edge of the pattern and a product shape that did not meet the dimensional specifications were counted as pattern accuracy defects, and products with peeling defects in the pattern due to pattern circuit formation were counted as peeling defects.

[0048] Also, for each of the aluminum nitride thin film metallized substrates 100 after cutting according to the examples and comparative examples One semiconductor element, a laser diode element, was joined to one circuit pattern by Au - Sn solder for each to fabricate a chip - on - submount.

[0049] The heat - sink portion of a copper stem component having a heat - sink portion and two lead - terminal portions was soldered to the chip - on - submount. Next, the laser diode element, the pattern circuit, and the lead terminals were joined by wire bonding. Next, a window cap was joined to fabricate a semiconductor module for a laser device.

[0050] The semiconductor module was subjected to a high - temperature continuous power - on test at 100 °C for 200 hours to confirm the laser characteristics of the semiconductor module. For the modules whose laser characteristics decreased after 200 hours, the causes were investigated. The defects of the modules were two types of defects: power - on failure and thermal runaway failure. The power - on failure was a defect in which the semiconductor was damaged due to an electrical short between the pattern circuits. The thermal runaway failure was a defect in which the heat generated by the semiconductor was not sufficiently transferred to the substrate side, resulting in semiconductor damage or a decrease in performance. These two defects were counted as module defects.

[0051] The substrate defect occurrence rates and module defect rates of the examples and comparative examples are shown in Table 2.

[0052]

Table 2

[0053] As can be seen from the substrate defects in Table 2, the aluminum nitride thin film metallized substrates , pattern accuracy defects did not occur or the defect rate was low. This is because the resist was properly dried by pre-baking, and the pattern shape could be exposed by the first exposure. Also, , the resist that was photosensitized by the reverse bake was preferentially crosslinked, and the uncrosslinked portions by the reverse bake were properly exposed by the second exposure. This is because the resist that was photosensitized by the reverse bake was preferentially crosslinked, and the uncrosslinked portions by the reverse bake were properly exposed by the second exposure. This is because the resist that was photosensitized by the reverse bake was preferentially crosslinked, and the uncrosslinked portions by the reverse bake were properly exposed by the second exposure.

[0054] In contrast, in the comparative example, many pattern accuracy defects occurred. When the pre-bake condition was weak, the drying state was not sufficient. When it was strong, the resist underwent thermal crosslinking, so the photosensitivity of the pattern could not be properly achieved. When the first exposure condition was weak, the pattern could not be sufficiently photosensitized. When it was strong, the exposure advanced to the inner part of the mask, so the predetermined pattern shape and accuracy could not be sufficiently controlled. When the reverse bake condition was weak, the crosslinking did not proceed sufficiently. When it was strong, the crosslinking advanced to the unexposed portions, so the predetermined pattern shape and accuracy could not be sufficiently controlled. When the condition of the second exposure was weak, the resist was difficult to be removed during development. When it was strong, the crosslinking advanced, so the predetermined pattern shape and accuracy could not be sufficiently controlled. When the pre-bake condition was weak, the drying state was not sufficient. When it was strong, the resist underwent thermal crosslinking, so the photosensitivity of the pattern could not be properly achieved. When the first exposure condition was weak, the pattern could not be sufficiently photosensitized. When it was strong, the exposure advanced to the inner part of the mask, so the predetermined pattern shape and accuracy could not be sufficiently controlled. When the first exposure condition was weak, the pattern could not be sufficiently photosensitized. When it was strong, the exposure advanced to the inner part of the mask, so the predetermined pattern shape and accuracy could not be sufficiently controlled. When the reverse bake condition was weak, the crosslinking did not proceed sufficiently. When it was strong, the crosslinking advanced to the unexposed portions, so the predetermined pattern shape and accuracy could not be sufficiently controlled. When the reverse bake condition was weak, the crosslinking did not proceed sufficiently. When it was strong, the crosslinking advanced to the unexposed portions, so the predetermined pattern shape and accuracy could not be sufficiently controlled. When the condition of the second exposure was weak, the resist was difficult to be removed during development. When it was strong, the crosslinking advanced, so the predetermined pattern shape and accuracy could not be sufficiently controlled. When the condition of the second exposure was weak, the resist was difficult to be removed during development. When it was strong, the crosslinking advanced, so the predetermined pattern shape and accuracy could not be sufficiently controlled. This is because when the condition of the second exposure was weak, the resist was difficult to be removed during development. When it was strong, the crosslinking advanced, so the predetermined pattern shape and accuracy could not be sufficiently controlled.

[0055] Also, as can be seen from the substrate defects in Table 2, for the aluminum nitride thin film metallized substrate according to the example, peeling defects did not occur or the defect rate was low. This is because the resist was properly dried by pre-baking, and the exposed portions were properly altered by the first exposure. Also, , the resist that was photosensitized by the reverse bake was preferentially crosslinked, and the uncrosslinked portions by the reverse bake were properly exposed and the exposed portions were properly altered by the second exposure. , the resist that was photosensitized by the reverse bake was preferentially crosslinked, and the uncrosslinked portions by the reverse bake were properly exposed and the exposed portions were properly altered by the second exposure. , the resist that was photosensitized by the reverse bake was preferentially crosslinked, and the uncrosslinked portions by the reverse bake were properly exposed and the exposed portions were properly altered by the second exposure. , the uncrosslinked portions by the reverse bake were properly exposed and the exposed portions were properly altered by the second exposure. This is because the resist that was photosensitized by the reverse bake was preferentially crosslinked, and the uncrosslinked portions by the reverse bake were properly exposed and the exposed portions were properly altered by the second exposure.

[0056] On the other hand, in the comparative example, many peeling defects occurred. Especially when the pre-baking conditions were weak the drying state was not sufficient, so the resist could not be properly exposed in the subsequent processes, and peeling during lift-off was likely to occur.

[0057] Also, as can be seen from the module defects in Table 2, for the aluminum nitride thin film metal rise substrate according to the example, no conduction failure occurred. Since the processes from pre-baking to secondary exposure were appropriate conditions, there were few pattern accuracy defects, the distance between patterns was ensured, and the insulation state was properly maintained.

[0058] On the other hand, in the comparative example, a conduction failure occurred. This can be attributed to the poor pattern accuracy . Other reasons include that even if the pattern dimensions are within the tolerance, unevenness occurs in the pattern shape and current leaks from the convex part, and a part of the thin film metallization penetrates into the insulating part between the patterns because the resist layer is not sufficiently crosslinked.

[0059] Also, as can be seen from the module defects in Table 2, for the aluminum nitride thin film metal rise substrate according to the example, no thermal runaway failure occurred. Since the processes from pre-baking to secondary exposure were appropriate conditions, heat could be dissipated well to the semiconductor element, solder, thin film metallization, and aluminum nitride substrate, and there was no influence on the operation due to the heat generated by the semiconductor element .

[0060] On the other hand, in the comparative example, a thermal runaway failure occurred. When observing the defective substrate, no abnormality was found in the solder joint layer between the semiconductor element and the thin film metallization, but voids were observed between the thin film metallization and the aluminum nitride substrate. The thermal runaway failure occurred due to the generated voids This is because sufficient heat dissipation could not be achieved. The cause of this pore generation is the pre-baking condition being weak, so the resist remained on the aluminum nitride substrate without being sufficiently dried, inhibiting the bonding between the thin film metallization and the aluminum nitride substrate and resulting in this situation

[0061] As mentioned above, several embodiments of the present invention have been illustrated. However, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, changes, etc. can be made without departing from the gist of the invention These embodiments and their modifications are included in the scope and gist of the invention, as well as in the scope of the invention described in the claims and its equivalents Moreover, the above-described embodiments can be implemented in combination with each other

Description of Reference Numerals

[0062] 1... Ceramic thin film metallization substrate before cutting 2... Ceramic thin film metallization substrate 3... Ceramic thin film metallization substrate after cutting 4, 6... Thin film metallization (pattern circuit) 5... Ceramic substrate 7... Resist 8... Mask 9... Exposed resist 10... Thin film metallization 11... Chip on submount 12, 16... Bonding layer 13... Semiconductor element 14... Semiconductor module 15... Wire bonding 17... Lead frame 18... Heat sink

Claims

1. A pattern circuit having a conductive portion and an insulating portion formed by a thin film is formed on a ceramic substrate In a method for manufacturing a ceramic thin film metallized substrate, The ceramic substrate is an aluminum nitride substrate, The thin film metallization is formed from an adhesion layer, a barrier layer, and a surface layer, A step of applying an ultraviolet curable resist to the ceramic substrate, A step of performing a pre-bake at a temperature of 60°C or higher and 90°C or lower and a time of 70 seconds or longer and 120 seconds or shorter And, Integrated exposure dose of 10 mJ / cm ２ or more and 50 mJ / cm or less ２ a step of performing a first exposure within the above range, A step of performing an inversion bake at a temperature of 110°C or higher and 140°C or lower and a time of 40 seconds or longer and 90 seconds or shorter Process and, The integrated exposure dose is 260 mJ / cm ２ or more and 350 mJ / cm ２ or less, and a step of performing secondary exposure A step of developing with a developer, A step of forming the thin film metallization, A step of peeling the resist with a stripping solution to form a pattern circuit, A method for manufacturing a ceramic thin film metallized substrate, comprising the steps of:

2. The aluminum nitride substrate in the method for manufacturing a ceramic thin film metallized substrate has a diameter of 100 mm or more and a thermal conductivity of 160 W / m·K or more. The method for manufacturing a ceramic thin film metallized substrate according to claim 1, characterized in that Diameter 100mm or more, thermal conductivity 160W / m・K or more, characterized in that the claim 1. The method for manufacturing a ceramic thin film metallized substrate according to claim 1.

3. In the method for manufacturing a ceramic thin film metallized substrate, the thin film metallization has an adhesion layer of Titanium, the barrier layer is a platinum, and the surface layer is a laminated film of gold. The method for manufacturing a ceramic thin film metallized substrate according to claim 1 or claim 2. The method for manufacturing a ceramic thin film metallized substrate according to claim 2.

4. The developer in the method for manufacturing a ceramic thin film metallized substrate is a developer obtained by adding a nonionic surfactant to tetramethylammonium Hydroxide. The method for manufacturing a ceramic thin film metallized substrate according to claim 1 or claim 2. The method for manufacturing a ceramic thin film metallized substrate according to claim 2.

5. In a method for manufacturing a chip on substrate having a bonding layer on a pattern circuit of a ceramic thin film metallized substrate, a step of forming a bonding layer on the ceramic thin film metallized substrate obtained by the manufacturing method according to any one of claims 1 to 3 is performed. A method for manufacturing a chip on substrate, characterized in that In the method for manufacturing a chip on substrate, the bonding layer is a gold-tin solder. The method for manufacturing a chip on substrate according to claim 5, characterized in that The method for manufacturing a chip on substrate according to claim 5, characterized in that The method for manufacturing a chip on substrate according to claim 5, characterized in that

6. The bonding layer in the method for manufacturing a chip on substrate is a gold-tin solder. The method for manufacturing a chip on substrate according to claim 5, characterized in that The method for manufacturing a chip on substrate according to claim 5, characterized in that

7. In a method for manufacturing a semiconductor module in which a semiconductor element is mounted on a chip on substrate, a semiconductor element is mounted on the chip on substrate obtained by the manufacturing method according to claim 5 or claim 6. The semiconductor module manufacturing method according to claim 5 or claim 6, characterized in that the semiconductor element is mounted on the chip on substrate obtained by the manufacturing method according to claim 5 or claim 6. A method for manufacturing a semiconductor module, characterized by performing a step of mounting a conductive element.

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