Semiconductor device

Abstract

To provide a semiconductor device that can improve reliability.SOLUTION: A semiconductor device according to the present disclosure includes an insulating sheet 4 on which one die pad 5 is arranged, an insulating sheet 8 on which multiple die pads 9 are arranged, a semiconductor switch 6 and a rectifier diode 7 arranged on the die pad 5, a semiconductor switch 10 and a rectifier diode 11 arranged on each die pad 9, and a heat sink 15 joined to the insulating sheet 4 and the insulating sheet 8.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] Conventionally, a semiconductor device including a converter circuit, a brake circuit, and an inverter circuit has been disclosed (see, for example, Patent Document 1). In the semiconductor device disclosed in Patent Document 1, an insulating sheet made of resin is provided on one surface of a heat sink, a frame is provided on the insulating sheet, and a semiconductor chip and wires are bonded on the frame. Then, the insulating sheet, the frame, the semiconductor chip, and the wires are sealed with a molding resin.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Mechanical properties differ between a metal member and a resin member. Therefore, internal stresses associated with shrinkage and expansion of different types of members are generated due to environmental stresses such as temperature and humidity. This internal stress causes the insulating sheet to peel off from the heat sink, affecting the reliability of the semiconductor device. In the semiconductor device disclosed in Patent Document 1, stress tends to concentrate at corners of the insulating sheet, etc., which makes the insulating sheet likely to peel off. Thus, there has been room for improvement in improving the reliability of conventional semiconductor devices.

[0005] The present disclosure has been made to solve such problems, and an object thereof is to provide a semiconductor device capable of improving reliability.

Means for Solving the Problems

[0006] To solve the above problems, a semiconductor device according to the present disclosure includes a first insulating material on which one first die pad is disposed, a second insulating material on which a plurality of second die pads are disposed, a first semiconductor element disposed on the first die pad, a second semiconductor element disposed on each second die pad, and a heat sink bonded to the first insulating material and the second insulating material.

Effect of the Invention

[0007] According to the present disclosure, it becomes possible to improve reliability.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Modes for Carrying Out the Invention

[0009] <Embodiment 1> FIG. 1 is a plan view showing an example of the configuration of a semiconductor device according to Embodiment 1. FIG. 2 is a cross-sectional view showing an example of the configuration of the semiconductor device according to Embodiment 1.

[0010] The semiconductor device according to Embodiment 1 includes an inverter circuit and a converter circuit 3. The inverter circuit is composed of an inverter P-side circuit 1 on the high side and an inverter N-side circuit 2 on the low side.

[0011] In the inverter P-side circuit 1, one die pad 5 (first die pad) is disposed on one insulating sheet 4 (first insulating material). On the die pad 5, three pairs of a semiconductor switch 6 and a rectifying diode 7, that is, a total of six semiconductor elements (first semiconductor elements) are disposed. The semiconductor switch 6 is, for example, an IGBT (Insulated Gate Bipolar Transistor) or the like. The die pad 5 is composed of, for example, copper or the like and is a part of a frame constituting the semiconductor device.

[0012] In the inverter N-side circuit 2, three die pads 9 (second die pads) are disposed on one insulating sheet 8 (second insulating material). On one die pad 9, one pair of a semiconductor switch 10 and a rectifying diode 11, that is, a total of two semiconductor elements (second semiconductor elements) are disposed. Thus, in the inverter N-side circuit 2, a total of six semiconductor elements are disposed in a region where one insulating sheet 8 is disposed, similar to the inverter P-side circuit 1. Each die pad 9 corresponds to the U phase, the V phase, and the W phase. By disposing the three die pads 9 together on the insulating sheet 8, cost reduction can be achieved.

[0013] In the converter circuit 3, four die pads 13 (third die pads) are arranged on one insulating sheet 12 (third insulating material). On one of the four die pads 13 (P-side converter), three rectifier diodes 14 are arranged. On the remaining three die pads 13 (N-side converter), one rectifier diode 14 (corresponding to U-phase, V-phase, or W-phase) is arranged respectively. Thus, in the converter circuit 3, similar to the inverter P-side circuit 1 and the inverter N-side circuit 2, a total of six semiconductor elements are arranged in the region where one insulating sheet 12 is arranged. In the converter circuit 3, it can be miniaturized by the amount of the absence of semiconductor switches, and the size of the converter circuit 3 alone can be made substantially the same as that of the inverter P-side circuit 1 and the inverter N-side circuit 2. By arranging the four die pads 13 together on the insulating sheet 12, cost reduction can be achieved.

[0014] The insulating sheets 4, 8, and 12 are joined to the heat sink 15. The heat sink 15 functions to release the heat generated in each of the inverter P-side circuit 1, the inverter N-side circuit 2, and the converter circuit 3 to the outside. The heat sink 15 may be configured using a metal material such as aluminum to improve heat dissipation.

[0015] The mold resin 16 (sealing resin) seals the insulating sheets 4, 8, 12, the die pads 5, 9, 13, the semiconductor switches 6, 10, and the rectifier diodes 7, 11, 13. The mold resin 16 has insulating properties and may be configured of, for example, an epoxy resin.

[0016] Note that in a plan view, it is desirable that the area of the insulating sheet 4 in the inverter P-side circuit 1 is 90% or more and 110% or less of the area of the insulating sheet 8 in the inverter N-side circuit 2. By making the area of the insulating sheet 4 and the area of the insulating sheet 8 substantially the same, the surface properties of the insulating sheet 4 and the insulating sheet 8 become substantially the same. Thereby, the internal stress of the semiconductor device can be made uniform, and a semiconductor device resistant to environmental stress can be realized.

[0017] In a plan view, the area of the insulating sheet 12 in the converter circuit 3 is desirably 90% or more and 110% or less of the area of the insulating sheet 4 in the inverter P-side circuit 1 or the area of the insulating sheet 8 in the inverter N-side circuit 2. By making the area of the insulating sheet 4 and the area of the insulating sheet 12 substantially the same, the surface properties of the insulating sheet 4 and the insulating sheet 12 become substantially the same. Thereby, the internal stress of the semiconductor device can be made uniform, and a semiconductor device that is resistant to environmental stress can be realized.

[0018] Although not shown, in the inverter P-side circuit 1, the inverter N-side circuit 2, and the converter circuit 3, the circuit is configured by wiring with an arbitrary material such as a wire and an electrode.

[0019] Although not shown, each of the inverter P-side circuit 1, the inverter N-side circuit 2, and the converter circuit 3 has an external terminal for electrically connecting to the outside. The mold resin 16 seals the inverter P-side circuit 1, the inverter N-side circuit 2, and the converter circuit 3 so that the external terminals are exposed to the outside. Each of the inverter P-side circuit 1, the inverter N-side circuit 2, and the converter circuit 3 outputs a current or a control signal to the outside of the mold resin 16 via the external terminal.

[0020] Although not shown, the semiconductor device according to Embodiment 1 may be configured to further include a brake circuit. In this case, the semiconductor device may include one pair of a semiconductor switch and a rectifying diode that constitute the brake circuit. The brake circuit may be configured on any of the insulating sheet 4 in the inverter P-side circuit 1, the insulating sheet 8 in the inverter N-side circuit 2, and the insulating sheet 12 in the converter circuit 3, but it is desirable to configure it on the insulating sheet 12 in the converter circuit 3.

[0021] Between the die pads 5 in the inverter P-side circuit 1, the die pads 9 in the inverter N-side circuit 2, and the die pads 13 in the converter circuit 3, and the heat sink 15, insulating sheets 4, insulating sheets 8, and insulating sheets 12 are respectively in close contact without gaps, and a heat dissipation path with low thermal resistance in the vertical direction in FIG. 2 is ensured (the wavy arrow in FIG. 2). Here, the die pads 5, the die pads 9, and the die pads 13 are also called concentrated heat dissipation die pads. The concentrated heat dissipation die pads may be arranged at intervals so as not to interfere with each other thermally.

[0022] According to each of the concentrated heat dissipation die pads, the insulating sheets 4, 8, and 12 are arranged separately. By making the width of the region where the insulating sheets 4, 8, and 12 are divided narrower than the distance between the concentrated heat dissipation die pads, an insulation distance between the concentrated heat dissipation die pads and the heat sink 15 is ensured.

[0023] When the semiconductor device operates, heat is generated mainly in the inverter P-side circuit 1, the inverter N-side circuit 2, and the converter circuit 3. The semiconductor elements belonging to these respective circuits have approximately the same heat generation amount because they have similar operations individually. However, since the operations of the semiconductor elements are different for each circuit, the heat generation amounts in each circuit are different. Therefore, thermal interference can occur between each circuit that is a heat source. For example, heat is transmitted from the inverter P-side circuit 1 to the inverter N-side circuit 2 and the converter circuit 3 via the heat sink 15. Also, the reverse can occur.

[0024] In order to efficiently release the heat generated by the semiconductor device to the outside, it is ideal to transfer heat in the vertical direction without interfering with the adjacent die pad as much as possible. In the semiconductor device according to Embodiment 1, heat generated in each of the inverter P-side circuit 1, the inverter N-side circuit 2, and the converter circuit 3 is reduced from interfering with each other, and a heat dissipation route is ensured to be transmitted to the heat sink 15 via the insulating sheet directly below the die pad. Thereby, the non-uniformity of the temperature distribution in the insulating sheet due to the non-uniform heat generation of the semiconductor elements can be suppressed.

[0025] Since the coefficient of linear expansion of each material constituting the semiconductor device is non-uniform, it is inevitable that the semiconductor device will warp due to environmental stress. Environmental stress includes a temperature gradient due to heat generation of the semiconductor elements constituting the semiconductor device, an external temperature change, and moisture. When the semiconductor device is subjected to environmental stress, internal stress is generated because relative positional fluctuations occur between the die pads 5, 9, 13, the insulating sheets 4, 8, 12, the heat sink 15, and the mold resin 16. In particular, when stress is generated at the bonding interface between the insulating sheets 4, 8, 12 and the heat sink 15 and at the bonding interface between the insulating sheets 4, 8, 12 and the die pads 5, 9, 13, the insulating sheets 4, 8, 12 will peel off, and this peeling will gradually expand and eventually lead to complete peeling.

[0026] FIG. 3 is a cross-sectional view for explaining the internal stress in a semiconductor device according to the prior art. Further, FIG. 4 is a plan view for explaining the internal stress in a semiconductor device according to the prior art. In FIG. 3, the illustration of the semiconductor element is omitted. In a semiconductor device according to the prior art, one insulating sheet 17 is disposed on the heat sink 15. In FIG. 3, the white arrows indicate the direction of stress, and the black arrows indicate the strength of the internal stress.

[0027] As shown in FIGS. 3 and 4, since stress tends to concentrate at the ends such as the corners and sides rather than the center of the insulating sheet 17, such ends often become the peeling starting points 18. The larger the size of the semiconductor device, the more likely it is to warp, and the internal stress also increases.

[0028] On the one hand, in the semiconductor device according to Embodiment 1, as shown in FIG. 5, the internal stress due to the overall warpage is locally applied to each of the insulating sheets 4 in the inverter P-side circuit 1, the insulating sheet 8 in the inverter N-side circuit 2, and the insulating sheet 12 in the converter circuit 3. However, in the semiconductor device according to Embodiment 1, compared with the single insulating sheet 17 provided in the semiconductor device according to the prior art (see FIGS. 3 and 4), since the insulating sheets 4, 8, and 12 do not pull against each other, the stress at the ends of the insulating sheets 4, 8, 12 and the gap portion between the die pads 5, 9, and 13 is relaxed. As a result, it is possible to prevent the peeling of the insulating sheets 4, 8, and 12 without breaking the bonding interface between the heat sink 15 and the insulating sheets 4, 8, and 12. Note that in FIG. 5, the illustration of the semiconductor element is omitted.

[0029] A method of increasing the bonding strength by using a resin component with high adhesion for the insulating sheet can be considered, but in many cases, it is accompanied by an increase in cost or sacrifices other characteristics, so it is technically difficult. According to Embodiment 1, it is possible to realize a highly reliable semiconductor device by reusing existing materials.

[0030] <Embodiment 2> FIG. 6 is a cross-sectional view showing an example of the configuration of the semiconductor device according to Embodiment 2.

[0031] As shown in FIG. 6, the semiconductor device according to Embodiment 2 is characterized in that it is divided into three heat sinks 19, 20, and 21 in the region between the insulating sheets 4, 8, and 12. Note that in FIG. 6, the illustration of the semiconductor element is omitted, which is the same as in Embodiment 1 (see FIGS. 1 and 2).

[0032] Specifically, the heat sinks 19 and 20 are divided in the region between the insulating sheets 4 and 12. Also, the heat sinks 20 and 21 are divided in the region between the insulating sheets 4 and 8.

[0033] FIG. 7 is a cross-sectional view for explaining internal stress in the semiconductor device according to Embodiment 2. Note that in FIG. 7, illustration of the semiconductor element is omitted, which is the same as in Embodiment 1 (see FIGS. 1 and 2). In FIG. 7, the white arrow indicates the direction of stress, and the black arrow indicates the strength of the internal stress.

[0034] During operation of the semiconductor device, the molding resin 16 swells by absorbing moisture from the environment, while the heat sink 15 hardly swells. In the semiconductor device according to Embodiment 2, since it is divided into three heat sinks 19, 20, and 21, even when the molding resin 16 swells and the semiconductor device warps, the divided heat sinks 19, 20, and 21 can easily follow the swelling direction of the molding resin 16, and the stress applied to the insulating sheets 4, 8, and 12 is relaxed. As a result, it is possible to prevent peeling of the insulating sheets 4, 8, and 12 without breaking the bonding interface between the insulating sheets 4, 8, and 12 and the heat sinks 19, 20, and 21.

[0035] <Embodiment 3> FIG. 8 is a cross-sectional view showing an example of the configuration of the semiconductor device according to Embodiment 3.

[0036] As shown in FIG. 8, the semiconductor device according to Embodiment 3 is characterized in that the heat sink 22 has a comb shape. Note that in FIG. 8, illustration of the semiconductor element is omitted, which is the same as in Embodiment 1 (see FIGS. 1 and 2). In FIG. 8, the black arrow indicates the strength of the internal stress.

[0037] Specifically, the heat sink 22 has depressions (grooves) in the regions between the insulating sheet 4 and the insulating sheet 8, and between the insulating sheet 4 and the insulating sheet 12. This depression is provided on the surface side where the insulating sheets 4, 8, and 12 of the heat sink 22 are joined.

[0038] By adopting such a configuration, like the semiconductor device according to Embodiment 2, the heat sink 22 can easily follow the warping of the semiconductor device due to temperature changes or moisture absorption, and since the heat sink 22 is connected by a single metal plate, it is possible to contribute to the simplification of the assembly process without increasing the number of components.

[0039] <Embodiment 4> FIG. 9 is a cross-sectional view showing an example of the configuration of the semiconductor device according to Embodiment 4.

[0040] As shown in FIG. 9, the semiconductor device according to Embodiment 4 is characterized in that the heat sink 23 is comb-shaped. In FIG. 9, the illustration of the semiconductor element is omitted, but it is the same as in Embodiment 1 (see FIGS. 1 and 2).

[0041] Specifically, the heat sink 23 has a depression (groove) on the surface side facing the surface to which the insulating sheet 17 is joined.

[0042] In the semiconductor device according to the related art shown in FIG. 3, when the mold resin 16 absorbs moisture and expands, the heat sink 15 resists it, so stress is applied to the insulating sheet 17.

[0043] On the other hand, in the semiconductor device according to Embodiment 4, as shown in FIG. 10, by providing a depression in the heat sink 23, the heat sink 23 is likely to warp along the expansion direction of the mold resin 16, so an effect of relaxing the internal stress of the semiconductor device can be obtained. In FIG. 10, the white arrows indicate the direction of stress. In FIG. 10, the illustration of the semiconductor element and the die pad is omitted, but it is the same as in Embodiment 1 (see FIGS. 1 and 2).

[0044] Note that, like the semiconductor device according to Embodiment 1, the semiconductor device according to Embodiment 4 may divide the insulating sheet 17 into insulating sheets 4, 8, and 12. Specifically, the heat sink 23 has depressions (grooves) in the regions between the insulating sheet 4 and the insulating sheet 8, and between the insulating sheet 4 and the insulating sheet 12. These depressions are provided on the surface side facing the surfaces of the insulating sheets 4, 8, and 12 to which the heat sink 23 is joined. In this case, internal stress can be further relaxed. However, the same effect can be expected even when a single insulating sheet 17 is used. When the insulating sheet 17 is divided into insulating sheets 4, 8, and 12, the dividing positions of the insulating sheets 4, 8, and 12 do not necessarily have to coincide with the positions of the depressions in the heat sink. The heat sink 23 may have two or more depressions.

[0045] <Modifications of Embodiments 1 to 4> In Embodiments 1 to 4, the case where an insulating sheet is used as a member for insulating each of the inverter P-side circuit 1, the inverter N-side circuit 2, and the converter circuit 3 from the outside has been described. However, as long as it can be insulated from the outside, it is not limited to an insulating sheet. For example, an insulating substrate made of ceramic may be used as a member for insulating from the outside.

[0046] Note that within the scope of the present disclosure, it is possible to freely combine the embodiments or appropriately modify or omit each embodiment.

[0047] <Supplementary Note> Hereinafter, various aspects of the present disclosure will be summarized and described as supplementary notes.

[0048] (Supplementary Note 1) A first insulating material in which one first die pad is disposed, A second insulating material in which a plurality of second die pads are disposed, A first semiconductor element disposed on the first die pad, A second semiconductor element disposed on each of the second die pads, A heat sink joined to the first insulating material and the second insulating material, A semiconductor device comprising (Appendix 2) The semiconductor device according to Appendix 1, wherein at least three of the second die pads are arranged in the second insulating material. (Appendix 3) The semiconductor device according to Appendix 1 or 2, wherein in a plan view, the area of the first insulating material is 90% or more and 110% or less of the area of the second insulating material. (Appendix 4) Further comprising a third insulating material in which a plurality of third die pads are arranged, The semiconductor device according to any one of Appendices 1 to 3, wherein the heat sink is joined to the third insulating material. (Appendix 5) The semiconductor device according to Appendix 4, wherein at least four of the third die pads are arranged in the third insulating material. (Appendix 6) The semiconductor device according to Appendix 4 or 5, wherein in a plan view, the area of the third insulating material is 90% or more and 110% or less of the area of the first insulating material or the second insulating material. (Appendix 7) The semiconductor device according to any one of Appendices 1 to 6, wherein the heat sink has a depression in a region between the first insulating material and the second insulating material. (Appendix 8) The semiconductor device according to Appendix 7, wherein the depression is provided on a surface side of the heat sink where the first insulating material and the second insulating material are joined. (Appendix 9) The semiconductor device according to Appendix 7, wherein the depression is provided on a surface side of the heat sink facing the surface where the first insulating material and the second insulating material are joined. (Appendix 10) Further comprising an insulating encapsulation resin that encapsulates the first insulating material, the second insulating material, the third insulating material, the first die pad, the second die pad, the third die pad, the first semiconductor element, and the second semiconductor element, the semiconductor device according to any one of Appendices 4 to 6.

Explanation of Reference Numerals

[0049] 1 Inverter P-side circuit, 2 Inverter N-side circuit, 3 Converter circuit, 4 Insulating sheet, 5 Die pad, 6 Semiconductor switch, 7 Rectifier diode, 8 Insulating sheet, 9 Die pad, 10 Semiconductor switch, 11 Rectifier diode, 12 Insulating sheet, 13 Die pad, 14 Rectifier diode, 15 Heat sink, 16 Mold resin, 17 Insulating sheet, 18 Peeling starting point, 19 Heat sink, 20 Heat sink, 21 Heat sink, 22 Heat sink, 23 Heat sink.

Claims

1. a first insulating material on which one first die pad is disposed; a second insulating material on which a plurality of second die pads are disposed; a first semiconductor element disposed on the first die pad; a second semiconductor element disposed on each of the second die pads; a heat sink bonded to the first insulating material and the second insulating material; A semiconductor device comprising the above.

2. The semiconductor device according to claim 1, wherein at least three of the second die pads are disposed on the second insulating material.

3. The semiconductor device according to claim 1, wherein in a plan view, the area of the first insulating material is 90% or more and 110% or less of the area of the second insulating material.

4. further comprising a third insulating material on which a plurality of third die pads are disposed, The semiconductor device according to claim 1 or 2, wherein the heat sink is bonded to the third insulating material.

5. The semiconductor device according to claim 4, wherein at least four of the third die pads are disposed on the third insulating material.

6. The semiconductor device according to claim 4, wherein in a plan view, the area of the third insulating material is 90% or more and 110% or less of the area of the first insulating material or the second insulating material.

7. The semiconductor device according to any one of claims 1 to 3, wherein the heat sink has a recess in a region between the first insulating material and the second insulating material.

8. The semiconductor device according to claim 7, wherein the recess is provided on a surface side of the heat sink where the first insulating material and the second insulating material are bonded.

9. The semiconductor device according to claim 7, wherein the recess is provided on a surface side of the heat sink facing the surface where the first insulating material and the second insulating material are bonded.

10. The semiconductor device according to claim 4, further comprising an insulating encapsulating resin that encapsulates the first insulating material, the second insulating material, the third insulating material, the first die pad, the second die pad, the third die pad, the first semiconductor element, and the second semiconductor element.

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