Semiconductor device

Abstract

To improve area efficiency while improving noise resistance.SOLUTION: A semiconductor device includes a first substrate having a first pad and signal wiring, a semiconductor chip joined to the first substrate at the first pad, and a conductive member arranged to cover at least a portion of the signal wiring.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] An imaging device has been proposed that improves the area efficiency of a substrate by laminating a sensor element and a logic chip (see Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the imaging device disclosed in Patent Document 1, a pad portion for bonding a logic chip is provided on the back side of the sensor element, and a wiring layer that conducts to a vertical signal line is disposed in the vicinity of the pad portion. In this case, a change in the voltage level in the wiring layer of the logic chip is transmitted to the sensor element via the pad as noise, which may fluctuate the voltage level of the vertical signal line of the sensor element. However, Patent Document 1 does not recognize the need to suppress noise from the logic chip, nor is any countermeasure described.

[0005] Therefore, the present disclosure provides a semiconductor device that improves noise resistance while improving area efficiency.

Means for Solving the Problems

[0006] In order to solve the above problems, according to the present disclosure, a first substrate having a first pad and a signal wiring, a semiconductor chip bonded to the first substrate at the first pad, A semiconductor device is provided, which includes a conductive member arranged to cover at least a part of the signal wiring.

[0007] The conductive member may be arranged at a height different from that of the first pad.

[0008] The conductive member may be arranged on the first substrate.

[0009] The first substrate has a second pad to which a bonding wire is connected. The conductive member may be arranged at the same height as the second pad.

[0010] The first substrate may be arranged at the same height as the conductive member and have a dummy wiring layer with an indeterminate voltage level.

[0011] The thickness of the conductive member may be greater than the thickness of the signal wiring.

[0012] The conductive member may be arranged on the semiconductor chip.

[0013] The semiconductor chip may have a wiring layer arranged such that at least a part of it overlaps with the conductive member in plan view.

[0014] The semiconductor chip has a plurality of stacked wiring layers. The conductive member may be arranged to cover at least a part of the wiring layer closest to the first substrate among the plurality of wiring layers.

[0015] The conductive member may be set to a predetermined voltage level.

[0016] The first substrate has a plurality of pixels. Each of the plurality of pixels has a photoelectric conversion element and a pixel circuit that generates a pixel signal photoelectrically converted by the photoelectric conversion element. The signal wiring at least partially covered by the conductive member may transmit the pixel signal.

[0017] The semiconductor chip is bonded to the first substrate via a plurality of the first pads. A plurality of the signal wirings may be arranged between two of the first pads adjacent to each other in a predetermined direction in plan view.

[0018] Two or more of the first pads are arranged in a first direction and a second direction intersecting each other. The signal wiring includes a plurality of first signal wirings arranged along the second direction between two or more of the first pads arranged in the first direction in plan view, and a plurality of second signal wirings arranged along the first direction and connecting the plurality of first signal wirings and the two or more of the first pads. The conductive member may be arranged to cover at least a part of the plurality of first signal wirings and the plurality of second signal wirings.

[0019] An insulating layer is provided to cover the first pad, the signal wiring, and the plurality of pixels. The thickness of the insulating layer may be different for each location of the first pad, the signal wiring, and the pixel.

[0020] The insulating layer may have a thickness in a region overlapping the plurality of pixels in plan view that is thicker than the thickness in a region overlapping the signal wiring.

[0021] The insulating layer may have a thickness in a region overlapping the plurality of pixels in plan view that is thicker than the thickness in a region overlapping the first pad.

[0022] The insulating layer may have a thickness in a region overlapping the first pad in plan view that is thicker than the thickness in a region overlapping the signal wiring.

[0023] The insulating layer may be a laminated insulating layer formed by laminating a plurality of insulating films each containing a different insulating material.

[0024] The conductive member may be disposed so as to face the signal wiring with the insulating layer interposed therebetween.

[0025] A second substrate laminated on the side of the first substrate opposite to the bonding surface of the semiconductor chip, and a logic circuit disposed on at least one of the semiconductor chip and the second substrate.

Brief Description of the Drawings

[0026]

Figure 1

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Figure 10B

Figure 10C

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Figure 10E

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Embodiments for Carrying Out the Invention

[0027] Hereinafter, embodiments of a semiconductor device will be described with reference to the drawings. Hereinafter, the description will focus on the main components of the semiconductor device, but the semiconductor device may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0028] FIG. 1 is a block diagram showing a schematic configuration of a semiconductor device 1 according to the present disclosure. The semiconductor device 1 shown in FIG. 1 shows a schematic configuration of an image sensor. Note that the semiconductor device 1 according to the present disclosure is not necessarily limited to an image sensor that acquires gradation information photoelectrically converted by each pixel to generate a captured image, and can also be applied to an EVS (Event-Based Vision Sensor) that detects event information by each pixel to generate an event image. In this specification, an example in which the semiconductor device 1 according to the present disclosure is applied to a light detection device such as an image sensor or an EVS will be mainly described, but the semiconductor device 1 according to the present disclosure can also be applied to various electronic devices other than the light detection device.

[0029] As shown in FIG. 1, the semiconductor device 1 in FIG. 1 includes a pixel array unit 2a and a peripheral circuit unit 2b. The peripheral circuit unit 2b includes, for example, a vertical drive unit 3, a column processing unit 4, a horizontal drive unit 5, a system control unit 6, a signal processing unit 7, and a data storage unit 8, and can be roughly classified into a control circuit and a logic circuit as will be described later. The signal processing unit 7 and the data storage unit 8 may be mounted on the same substrate as the pixel array unit 2a, the vertical drive unit 3, etc., or may be arranged on a separate substrate. Each process of the signal processing unit 7 and the data storage unit 8 may be executed by an external signal processing unit provided in a semiconductor chip 50 different from the semiconductor device 1, for example, a DSP (Digital Signal Processor) circuit or the like.

[0030] The pixel array unit 2a has a configuration in which unit pixels px each having a photoelectric conversion unit that generates and accumulates charges according to the amount of received light are two-dimensionally arranged in a matrix in a first direction (for example, row direction) X and a second direction (for example, column direction) Y. Here, the row direction refers to the pixel row of the pixel array unit 2a, that is, the arrangement direction in the row direction, and the column direction refers to the pixel column of the pixel array unit 2a, that is, the arrangement direction in the column direction. The specific circuit configuration of the unit pixel px will be described later. Hereinafter, the unit pixel px may be abbreviated as pixel px.

[0031] In the pixel array section 2a, pixel drive wirings L as row signal lines are wired along the row direction for each pixel row, and vertical signal lines VSL as column signal lines are wired along the column direction for each pixel column. The pixel drive wiring L transmits a drive signal for driving when reading a signal from the pixel px. In FIG. 1, each individual pixel drive wiring L is illustrated as a single wiring, but it is not limited to one. One end of the pixel drive wiring L is connected to the output end corresponding to each row of the vertical drive section 3.

[0032] The vertical drive section 3 is composed of a shift register, an address decoder, etc., and drives each pixel px of the pixel array section 2a all at once or by row units. The vertical drive section 3, together with the system control section 6, constitutes a drive section for controlling the operation of each pixel px of the pixel array section 2a. Although the specific configuration of the vertical drive section 3 is omitted from the illustration, generally, it has two scanning systems: a readout scanning system and a blanking scanning system.

[0033] The readout scanning system sequentially selects and scans the pixels px of the pixel array section 2a by row units in order to read a signal from the pixel px. The signal read from the pixel px is an analog signal. The blanking scanning system performs blanking scanning for the readout row where readout scanning is performed by the readout scanning system, with a lead time of the exposure time compared to that readout scanning.

[0034] By the blanking scanning by this blanking scanning system, unnecessary charges are swept out from the photoelectric conversion section of the pixels px in the readout row, thereby resetting the photoelectric conversion section of each pixel px. And by sweeping out (resetting) the unnecessary charges by this blanking scanning system, a so-called electronic shutter operation is performed. Here, the electronic shutter operation refers to an operation of discarding the charges in the photoelectric conversion section and newly starting exposure (starting charge accumulation).

[0035] The signal read out by the readout scanning system during the readout operation corresponds to the amount of light received after the immediately preceding readout operation or electronic shutter operation. Then, the period from the readout timing by the immediately preceding readout operation or the sweep timing by the electronic shutter operation to the readout timing by the current readout operation becomes the exposure period for the pixel px.

[0036] The signals output from each pixel px of the pixel row selectively scanned by the vertical drive unit 3 are input to the column processing unit 4 through each of the vertical signal lines VSL for each pixel column. The column processing unit 4 performs predetermined signal processing on the signals output from each pixel px of the selected row through the vertical signal line VSL for each unit pixel column of the pixel array unit 2a, and temporarily holds the pixel signals after the signal processing.

[0037] Specifically, the column processing unit 4 performs at least noise removal processing, such as CDS (Correlated Double Sampling) processing or DDS (Double Data Sampling) processing, as the signal processing. For example, by the CDS processing, pixel-specific fixed pattern noises such as reset noise and threshold variations of the amplification transistors within the unit pixel are removed. In addition to the noise removal processing, the column processing unit 4 has, for example, an AD (analog-digital) conversion function, and converts the analog pixel signal into a digital signal and outputs it.

[0038] The horizontal drive unit 5 is composed of a shift register, an address decoder, etc., and sequentially selects the unit circuits corresponding to the pixel columns of the column processing unit 4. By the selective scanning by the horizontal drive unit 5, the pixel signals signal-processed for each unit circuit in the column processing unit 4 are sequentially output.

[0039] The system control unit 6 is composed of a timing generator that generates various timing signals, etc., and performs drive control of the vertical drive unit 3, the column processing unit 4, the horizontal drive unit 5, etc. based on the various timings generated by the timing generator.

[0040] The signal processing unit 7 has at least an arithmetic processing function, and performs various signal processes such as arithmetic processing on the pixel signals output from the column processing unit 4. The data storage unit 8 temporarily stores the data necessary for the processing when performing signal processing in the signal processing unit 7. The pixel signals signal-processed in the signal processing unit 7 are converted into a predetermined format and output from the output unit 9 to the outside of the semiconductor device 1.

[0041] FIG. 2 is a diagram showing a cross-sectional configuration (FIG. 2A) and a planar configuration (FIG. 2B) of the semiconductor device 1 according to an embodiment of the present disclosure. The semiconductor device 1 according to an embodiment is, for example, a back-illuminated (back-illuminated) CMOS (Complementary Metal Oxide Semiconductor) image sensor. More specifically, the semiconductor device 1 according to an embodiment is a stacked image sensor in which a semiconductor chip 50 having various signal processing circuits for performing signal processing is flip-chip mounted on a sensor element 10 (first semiconductor element) mounted on a silicon substrate (first substrate) 11. Hereinafter, the semiconductor chip 50 may be referred to as a logic chip or a second substrate. Note that FIG. 2A shows a cross-sectional configuration taken along line A-A shown in FIG. 2B.

[0042] (Sensor element) The sensor element 10 has a light-receiving region 100A in which a plurality of photoelectric conversion units 12 are two-dimensionally arranged on a silicon substrate 11 (first substrate), and a peripheral region 100B provided around the light-receiving region 100A. The pixel array unit 2a of FIG. 1 is arranged in the light-receiving region 100A. At least a part of the peripheral circuit unit 2b of FIG. 1 is arranged in the peripheral region 100B. Each of the plurality of pixels px arranged in the pixel array unit 2a has a photoelectric conversion unit 12.

[0043] The sensor element 10 has a back surface (surface SF1) of the silicon substrate 11 as a light incident surface, and a multilayer wiring layer 20 is provided on the front surface (surface SF2, other surfaces) of the silicon substrate 11. The semiconductor chip 50 is bonded to the silicon substrate 11 by flip-chip mounting via a pad portion 34 (first pad) provided on the back surface (surface SF1) side of the silicon substrate 11 in the peripheral region 100B of the sensor element 10.

[0044] In the semiconductor device 1 of the present embodiment, in the peripheral region 100B of the sensor element 10, a pad portion 36 (second pad) used for connection to an external substrate (not shown) is further provided on the back surface (surface SF1) side of the silicon substrate 11. The pad portion 34 and the pad portion 36 are electrically connected by, for example, a wiring layer 33 provided on the surface SF1 of the silicon substrate 11, a through-via 13 penetrating the silicon substrate 11, and a multilayer wiring layer 20 provided on the front surface (surface SF2) side of the silicon substrate 11.

[0045] (Light-receiving region) In the light-receiving region 100A, a photoelectric conversion unit 12 that selectively detects light in different wavelength ranges for each pixel px and performs photoelectric conversion is provided. The photoelectric conversion unit 12 is, for example, an n-type semiconductor region formed in the thickness direction (Z-axis direction in FIG. 2) of the silicon substrate 11, and is constituted by a pn junction type photodiode (PD) with a p-type semiconductor region provided on the surface SF2 of the silicon substrate 11. For example, it is embedded and formed in the silicon substrate 11 for each pixel px.

[0046] On the silicon substrate 11, further, in the vicinity of the plane SF2, a charge storage section for storing the signal charges generated in the photoelectric conversion section 12 and a transfer transistor (TG) for transferring the signal charges to the charge storage section are provided. In the vicinity of the plane SF2 of the silicon substrate 11, together with the transfer transistor (TG), for example, a reset transistor (RST), an amplification transistor (Amp), a selection transistor (SEL), etc. are provided. Such transistors are, for example, MOSEFT (Metal Oxide Semiconductor Field Effect Transistor), and constitute a pixel circuit provided for each pixel px. Each pixel circuit may be, for example, a three-transistor configuration including a transfer transistor (TG), a reset transistor (RST), and an amplification transistor (Amp), or alternatively, a four-transistor configuration with a selection transistor (SEL) added thereto. Transistors other than the transfer transistor (TG) can also be shared between pixels.

[0047] In the light-receiving region 100A, on the light-receiving surface (plane SF1) side of the silicon substrate 11, for example, an interlayer insulating layer 31, an inner lens 37L, a planarization layer 38, a protective layer 40, a color filter 41, and an on-chip lens 42L are provided in this order. The inner lens 37L, the color filter 41, and the on-chip lens 42L are each arranged, for example, so as to face the photoelectric conversion section 12 of each pixel px.

[0048] The interlayer insulating layer 31, the inner lens 37L, the planarization layer 38, the protective layer 40, the color filter 41, and the on-chip lens 42L are each constituted of, for example, a material having light transmissivity. Specifically, for example, any one of silicon nitride (SiN) and silicon oxynitride (SiON), or a laminated film thereof.

[0049] Also, between each pixel px, pixel isolation sections 35, 39 are laminated. The pixel isolation section 35 is provided in a part of the interlayer insulating layer 31, and the pixel isolation section 39 is provided in a part of the planarization layer 38, respectively. The pixel isolation sections 35, 39 are constituted of, for example, a light-shielding material such as tungsten (W).

[0050] (Peripheral area) In the peripheral area 100B, for example, on the SF1 side of the silicon substrate 11, for example, an interlayer insulating layer 31, a stacked insulating layer 17, a planarization layer 38, a protective layer 40, and an on-chip lens layer 42 are stacked in this order. The stacked insulating layer 17 and the on-chip lens layer 42 respectively extend from an inner lens 37L and an on-chip lens 42L provided in the light receiving area 100A.

[0051] In the peripheral area 100B, for example, four pad portions 34 (two of which are shown in FIG. 2A) for mounting the semiconductor chip 50 on the sensor element 10 and, for example, a plurality of pad portions 36 used for connection to an external substrate are respectively provided. In the interlayer insulating layer 31, for example, a wiring layer 33 for electrically connecting the pad portion 34 and the pad portion 36 is provided. Further, in the interlayer insulating layer 31, for example, between the light receiving area 100A and the peripheral area 100B, a light shielding film 32 made of a conductive material having light shielding properties such as tungsten (W) is provided.

[0052] In the silicon substrate 11, for example, a through via 13 penetrating between the surface SF1 and the surface SF2 is provided. The through via 13 is provided for each of the pad portions 34 and 36, for example.

[0053] (Multilayer wiring layer) On the SF2 surface of the silicon substrate 11, a plurality of insulating layers 21 are stacked, and wiring layers 22 are arranged in at least some of the insulating layers 21. The wiring layers 22 are stacked, and each wiring layer 22 is connected by, for example, a via or a contact.

[0054] The through-via 13 penetrating the silicon substrate 11 is connected on one side to the wiring layer 33 connected to the pad portion 34 or the pad portion 36 provided on the surface SF1 side of the silicon substrate 11, and on the other side to the wiring layer 22 provided on the surface SF2 side of the silicon substrate 11. The pad portion 34 and the pad portion 36 are electrically connected via each wiring layer 33 including the through-via 13. The wiring layer 33 is disposed in the interlayer insulating layer 31. The wiring layer 33 may be laminated on the interlayer insulating layer 31. The wiring layer 33 includes a plurality of vertical signal lines VSL. These vertical signal lines VSL are electrically connected to a plurality of vertical signal lines VSL extending in the column direction in the pixel array portion 2.

[0055] (Pad portion) The pad portion 34 is a so-called land electrode for flip-chip mounting a semiconductor chip 50 on the sensor element 10, and is provided, for example, in an opening H1 provided to expose a part of the wiring layer 33 provided in the interlayer insulating layer 31. The pad portion 34 has, for example, a laminated structure of a plurality of metal layers. For example, the pad portion 34 has a laminated structure in which metal films 34a, 34b, and 34c are laminated in this order from the side of the silicon substrate 11. As the material of the pad portion 34, for example, conductive materials such as tantalum (Ta), tantalum nitride (TaN), and copper (Cu) can be used. Among these, for the metal film 34a in direct contact with the wiring layer 33, for example, tantalum (Ta) is used, for the metal film 34b provided between the metal film 34a and the metal film 34c, for example, tantalum nitride (TaN) is used, and for the metal film 34c connected to the semiconductor chip 50 via the bump 52, for example, copper (Cu) is preferably used. An opening H1 for exposing the pad portion 34 is provided in the laminated insulating layer 17, the planarization layer 38, the protective layer 40, and the on-chip lens layer 42 on the pad portion 34.

[0056] A bonding wire (not shown) is connected to the pad portion 36. The pad portion 36 is used for connection to an external substrate via a bonding wire and is provided, for example, on the interlayer insulating layer 31. The pad portion 36 is made of a material such as a single layer film of aluminum (Al) or a laminated film with a barrier metal. An opening H2 that exposes the pad portion 36 is provided in the laminated insulating layer 17, the planarizing layer 38, the protective layer 40, and the on-chip lens layer 42 above the pad portion 36.

[0057] Furthermore, it is desirable that the pad portion 36 be provided at approximately the same height as the pad portion 34. Here, approximately the same does not necessarily mean that they are the same height. For example, the difference in height between the bottom surfaces of the pad portion 34 and the pad portion 36 is equal to or less than the thickness of the insulating layer on which one of the pad portion 34 and the pad portion 36 is provided. This makes it easier to process the pad portion 34 and the pad portion 36.

[0058] The shield member 14 and the dummy wiring layer 15 are arranged at the same height (layer) as the pad portion 36. The pad portion 36, the shield member 14, and the dummy wiring layer 15 are made of the same conductive material (e.g., aluminum (Al)), and therefore can be formed in the same manufacturing process. The shield member 14 is set to a predetermined reference voltage (e.g., power supply voltage). On the other hand, the voltage level of the dummy wiring layer 15 is in an indefinite (floating) state. The shield member 14 may be arranged at a different height from the pad portion 34.

[0059] The shielding member 14 is disposed so as to cover at least a portion of the vertical signal line VSL or the wiring layer 33 connected to the vertical signal line VSL. More specifically, the shielding member 14 is disposed opposite the vertical signal line VSL or the wiring layer 33 connected to the vertical signal line VSL via the insulating layer 17. The shielding member 14 is provided mainly for the purpose of preventing noise generated in the semiconductor chip 50 from being transmitted to the vertical signal line VSL. In this specification, the shielding member 14 may be referred to as a conductive member. The shape and location of the shielding member 14 will be described later.

[0060] The dummy wiring layer 15 is provided for the purpose of improving the stability of processing by adjusting the aperture ratio of the mask during dry etching. In addition, since there is a risk of steps being formed if there are too few structures in the planarization process, providing the dummy wiring layer 15 can improve the flatness during film formation.

[0061] The semiconductor chip 50 flip-chip mounted on the silicon substrate (first substrate) 11 of the sensor element 10 is a logic chip on which various signal processing circuits for performing signal processing are formed. Pad sections 51 made of aluminum (Al) or the like are arranged on the surface of the semiconductor chip 50 facing the sensor element 10. The pad sections 51 of the semiconductor chip 50 and the pad sections 34 of the sensor element 10 are joined via solder bumps 52. In this way, the semiconductor chip 50 is flip-chip mounted on the light-irradiated surface (back surface) of the sensor element 10.

[0062] Fig. 3 is a planar layout diagram of the shielding member 14, and Fig. 4 is a cross-sectional view taken along line AA in Fig. 3. Fig. 3 shows a planar layout of a portion of the silicon substrate 11. On the silicon substrate 11, a plurality of pad portions 34 for bonding a semiconductor chip 50 to be flip-chip mounted on the sensor element 10 are arranged in a first direction (e.g., row direction) X and a second direction (e.g., column direction) Y. A plurality of vertical signal lines VSL (first signal wiring) extending in the second direction Y are arranged between two pad portions 34 adjacent to each other in the first direction X. The plurality of vertical signal lines VSL are connected to the respective pad portions 34 via lead-out wiring (second signal wiring) 18.

[0063] 3 shows an example in which the shielding member 14 covers the entire area of the silicon substrate (first substrate) 11 except for a plurality of rectangular regions surrounding each of the plurality of pad portions 34. As shown in FIGS. 3 and 4, the shielding member 14 is arranged so as to cover the area other than the areas where the plurality of pad portions 34 are arranged. Note that the present disclosure is not limited to such an arrangement of the shielding member 14, and it is sufficient that the shielding member 14 covers at least a portion of the first signal wiring 17. Here, "covering at least a portion" means that the shielding member 14 overlaps at least a portion of the first signal wiring 17 in a plan view.

[0064] FIG. 5 is a diagram showing the planar shape of the shield member 14. As shown in FIG. 5, the shield member 14 is arranged, for example, in a lattice pattern so as to surround the pad portion 34. FIG. 5 is only an example of the planar shape of the shield member 14. Various modifications are conceivable for the planar shape of the shield member 14.

[0065] FIG. 6 is a diagram showing typical modified examples of the planar shape of the shield member 14. FIG. 6A shows an example in which the opening of the pad portion 34 has a rhombus shape, FIG. 6B shows an example in which the opening H1 of the pad portion 34 has an octagon shape, and FIG. 6C shows an example in which the opening of the pad portion 34 has a circular shape. In any of FIGS. 6A to 6C, except for the opening in the sensor element 10, the shield member 14 covers it.

[0066] As shown in FIG. 3, it is desirable to cover at least a part of the lead wiring 18 extending from the vertical signal line VSL to the pad portion 34 with the shield member 14. In order to cover the lead wiring 18 with the shield member 14, it is desirable to make the planar shape of the shield member 14 the octagon shape shown in FIG. 6B that matches the outer shape of the pad portion 34. Note that FIGS. 5 and 6 show typical planar shapes of the shield member 14, and planar shapes other than those shown may be adopted.

[0067] FIG. 7 is a diagram showing the planar shape of the dummy wiring layer 15. FIG. 7 shows an example in which the planar shape of the dummy wiring layer 15 is rectangular. The interval between two adjacent dummy wiring layers 15 in the first direction (for example, the row direction) X and the second direction (for example, the column direction) Y is arbitrary and does not necessarily have to be constant.

[0068] Various modifications can be considered for the planar shape of the dummy wiring layer 15. FIG. 8 is a diagram showing representative examples of the planar shape of the dummy wiring layer 15. FIG. 8A shows an example in which the planar shape of the dummy wiring layer 15 is circular or elliptical. FIG. 8B shows an example in which the planar shape of the dummy wiring layer 15 is polygonal. FIG. 8C shows an example in which the planar shape of the dummy wiring layer 15 has a plurality of concavities and convexities. FIG. 8D shows an example in which the planar shape of the dummy wiring layer 15 is rectangular. FIGS. 8A to 8D show representative examples of the planar shape of the dummy wiring, and other planar shapes than those shown may also be used.

[0069] (Manufacturing process of the imaging device) FIG. 9 is a flowchart of the manufacturing process of the imaging device according to the present embodiment. FIGS. 10A to 10H are cross-sectional views of each manufacturing process of the imaging device according to the present embodiment. Hereinafter, the manufacturing process of the imaging device according to the present embodiment will be described in order with reference to these drawings.

[0070] First, a manufacturing process of FEOL (Front End Of Line) is performed (step S1). In FEOL, after forming the photoelectric conversion unit 12 on the silicon substrate 11, gates (not shown) of various transistors such as a charge storage unit and a transfer transistor (TG) are formed on the surface (surface SF2) of the silicon substrate 11.

[0071] Subsequently, a manufacturing process of BEOL (Back End Of Line) is performed (step S2). In BEOL, as shown in FIG. 10A, a multilayer wiring layer 20 in which a plurality of wiring layers 22 are laminated is formed on at least a part of the plurality of insulating layers 21 to be laminated on the surface SF2 of the silicon substrate 11. Wiring layers 22 having different layers are joined by vias or contacts. Next, a support substrate (not shown) is bonded to the surface SF2 of the silicon substrate 11 and turned upside down (step S3). FIG. 10A shows a cross-sectional view after being turned upside down. A support substrate (not shown) is disposed below the multilayer wiring layer 20 in FIG. 10A.

[0072] Next, as shown in FIG. 10B, an interlayer insulating layer 31 and a light-shielding film 32 are formed on the silicon substrate 11 (step S4). The interlayer insulating layer 31 has an insulating layer 31a made of, for example, silicon oxide (SiO2) and a light-shielding film 32 made of, for example, tungsten (W). An optical black region is formed around the pixel array portion 2 by the light-shielding film 32. Subsequently, the insulating layer 31a and the silicon substrate 11 are processed at a predetermined position of the interlayer insulating layer 31, for example, by dry etching, to form, for example, annular openings H1a and H2a. Next, after forming Ta as a barrier metal, for example, on the side surfaces of the openings H1a and H2a, Cu is plated, for example, in the openings H1a and H2a to form through vias 13 (step S5).

[0073] Next, a wiring layer 33 and a pad portion 34 are formed (step S6). In step S6, as shown in FIG. 10C, after forming, for example, a SiO2 film on the through vias 13 and the insulating layer 31a, a groove is formed at a predetermined position (specifically, at the position where the wiring layer 33 is to be formed), and copper (Cu) is plated. Subsequently, the Cu formed other than in the groove is removed, for example, by CMP to form the wiring layer 33. Next, after forming, for example, a SiO2 film on the insulating layer 31a and the wiring layer 33, an opening is formed at a predetermined position, for example, by etching to expose the wiring layer 33. In this opening, a pad portion 34 made of, for example, Ta (metal film 34a) / TaN (metal film 34b) / Cu (metal film 34c) is formed, for example, by plating, and then the surface is planarized, for example, by CMP, and the metal films 34a, 34b, and 34c formed other than the pad portion 34 are removed.

[0074] Subsequently, as shown in FIG. 10C, vias 16 extending upward from the wiring layer 33 are formed (step S7). Next, as shown in FIG. 10D, a laminated film, which is the material of the shield member 14, the pad portion 36, and the dummy wiring layer 15, is formed (step S8).

[0075] In steps S7 and S8, as shown in FIGS. 10C and 10D, as a part of the interlayer insulating layer 31, for example, a SiCN / SiO2 laminated film is formed, and then the SiCN / SiO2 laminated film is patterned by, for example, dry etching. Next, after forming a SiO2 film as a part of the interlayer insulating layer 31, an opening is formed on the wiring layer 33 by, for example, photolithography or the like, and tungsten (W) or aluminum (Al) is embedded in the opening to form via 16. Also, the pixel isolation portion 35 is formed together. Next, after forming a TaN / Ta (barrier metal) and Al film on the interlayer insulating layer 31, for example, by photolithography or the like, patterning is performed to form a shield member 14, a pad portion 36, and a dummy wiring layer 15 at predetermined positions on the interlayer insulating layer 31 including via 16.

[0076] Subsequently, an inner lens 37L is formed (step S9). In step S10, as shown in FIG. 10E, after forming a SiON / SiN laminated insulating layer 17 on the interlayer insulating layer 31, the pad portions 34 and 36, the shield member 14, and the dummy wiring layer 15, a resist is formed on the SiON / SiN laminated insulating layer 17 in a region corresponding to the light receiving region 100A using photolithography and reflow. Next, by etch-back, a lens shape is transferred to the SiON / SiN laminated insulating layer 17 to form a SiON / SiN laminated insulating layer (also referred to as an inner lens layer) 17 provided with the inner lens 37L in the light receiving region 100A. Subsequently, a SiO2 film is formed on the SiON / SiN laminated insulating layer 17. Next, after forming a pixel isolation portion 39 between each pixel px in the light receiving region 100A using the same method as the pixel isolation portion 35, for example, the surface of the SiO2 film is planarized using a CMP (Chemical Mechanical Polishing) method to form a planarization layer 38.

[0077] Subsequently, a color filter 41 and an on-chip lens 42L are formed (step S10). In step S10, as shown in FIG. 10F, for example, after a resin is applied onto the planarization layer 38 by a coater or the like to form a protective layer 40, a color filter 41 having a predetermined color is formed at a position corresponding to each pixel px in the light-receiving region 100A. Next, after applying a lens material onto the protective layer 40 and the color filter 41, a resist is formed on the lens material in a region corresponding to the light-receiving region 100A using photolithography and reflow. Next, by etching back, the lens shape is transferred to the lens material to form an on-chip lens layer 42 provided with the on-chip lens 42L in the light-receiving region 100A.

[0078] Subsequently, openings H1 and H2 for the pad portions 34 and 36 are formed (step S11). In step S11, as shown in FIG. 10G, for example, at a position corresponding to the pad portion 36, the on-chip lens layer 42, the protective layer 40, the planarization layer 38, and the stacked insulating layer 17 are processed, for example, by dry etching to form a rectangular opening H2 to expose the pad portion 36.

[0079] Next, for example, at a position corresponding to the pad portion 34, the on-chip lens layer 42, the protective layer 40, the planarization layer 38, the stacked insulating layer 17, and the stacked insulating layer 17 are processed, for example, by dry etching to form a circular opening H1 to expose the pad portion 34, thereby completing the sensor element 10.

[0080] Next, a semiconductor chip 50 is bonded by CoW (Chip on Wafer) (step S12). In step S12, the semiconductor chip 50 is mounted onto the pad portion 34 via bumps 52. Thus, the semiconductor device 1 shown in FIG. 2 is completed.

[0081] (Film thickness of the SiON / SiN stacked insulating layer) As shown in FIG. 10E, a SiON / SiN laminated insulating layer 17 is formed on the pad portions 34 and 36, the shield member 14, the dummy wiring layer 15, and the pixel array portion 2. FIG. 11 is a cross-sectional view showing the film thickness difference of the SiON / SiN laminated insulating layer 17 according to the present embodiment, and FIG. 12 is a cross-sectional view showing the film thickness difference of the laminated insulating layer 17 according to a comparative example. The comparative example is a semiconductor device 1 without the shield member 14. In FIGS. 11 and 12, for simplicity, the laminated insulating layer 17 is illustrated as one layer, but actually, for example, it has a three-layer structure of SiON / SiN / SiON.

[0082] As shown in FIG. 11, in the present embodiment, the thickness of the laminated insulating layer 17 above the pad portion 36, the shield member 14, and the dummy wiring layer 15, the thickness of the laminated insulating layer 17 above the pad portion 34, and the thickness of the laminated insulating layer 17 above the pixel array portion 2 are made different from each other, thereby reducing the step of the laminated insulating layer 17. On the other hand, in the comparative example, the shield member 14 is not provided, and the thickness of the laminated insulating layer 17 above the pad portion 36 and the dummy wiring layer 15, the thickness of the laminated insulating layer 17 above the pad portion 34, and the thickness of the laminated insulating layer 17 above the pixel array portion 2 are made the same. Therefore, in the comparative example, the step of the laminated insulating layer 17 becomes large between the pixel array portion 2 and the region other than the pixel array portion 2.

[0083] In the semiconductor device 1 according to the present embodiment, since the planarization process is performed after forming the laminated insulating layer 17 as shown in FIG. 10E, as shown in FIG. 11, the smaller the step, the easier the planarization process can be performed, and the flatness can be improved. In the case of the comparative example, in the planarization process, an additional process of thinning the laminated insulating layer 17 in the region other than the pixel array portion 2 is required, which takes time and deteriorates the flatness.

[0084] Further, in the present embodiment, since the thick laminated insulating layer 17 is formed on the pixel array portion 2, hydrogen can be supplied to the pixel array portion 2 through the SiN film in the laminated insulating layer 17, so that the dark current can be further suppressed. Also, by increasing the thickness of the laminated insulating layer 17, the moisture resistance of the pixel array portion 2 can be further improved.

[0085] FIG. 13 is a cross-sectional view showing details of the film thickness of the stacked insulating layer 17 of SiON 17a / SiN 17b / SiON 17c that covers the pad portion 34 and the shield member 14. As shown in FIG. 13, the film thickness of the stacked insulating layer 17 varies depending on the location. More specifically, the film thickness of the stacked insulating layer 17 on the pad portion 34 is thicker than the film thickness of the stacked insulating layer 17 on the shield member 14 and thinner than the film thickness of the stacked insulating layer 17 between the pad portion 34 and the shield member 14. In this way, by making the film thickness of the stacked insulating layer 17 on the pad portion 34 thicker than the film thickness of the stacked insulating layer 17 on the shield member 14, the flatness can be improved.

[0086] FIG. 14 is a cross-sectional view showing how the film thickness of the stacked insulating layer 17 changes depending on the intervals between structures 19 such as the shield member 14, the dummy wiring layer 15, and the pad portions 34 and 36. FIG. 14A shows the case where there are no other structures 19 around the structure 19, more specifically, the case where the distance from an adjacent structure 19 is more than 10 μm. FIG. 14B shows the case where the interval between two adjacent structures 19 is wide, more specifically, the case where the distance from an adjacent structure 19 is more than 3 μm and less than 10 μm. FIG. 14C shows the case where the interval between two adjacent structures 19 is slightly narrow, more specifically, the case where the distance from an adjacent structure 19 is about 3 μm. FIG. 14D shows the case where the interval between two adjacent structures 19 is narrow, more specifically, the case where the distance from an adjacent structure 19 is less than 2 μm.

[0087] In the case of FIG. 14A, the film thickness of the stacked insulating layer 17 is substantially the same between the upper surface of the structure 19 and the region where the structure 19 does not exist. In FIG. 14A, the film thickness of the stacked insulating layer 17 in the region where the structure 19 does not exist is denoted as A, and the film thickness of the stacked insulating layer 17 on the upper surface of the structure 19 is denoted as B.

[0088] In the case of FIG. 14B, the film thickness C of the stacked insulating layer 17 between two adjacent structures 19 is substantially equal to the film thickness D of the stacked insulating layer 17 on the upper surface of the structure 19. The film thicknesses C and D are the same as the film thickness A or slightly thinner than the film thickness A.

[0089] In the case of FIG. 14C, the film thickness E of the stacked insulating layer 17 between two adjacent structures 19 is thinner than the film thickness F of the stacked insulating layer 17 on the upper surface of the structure 19. The film thickness F is thinner than the film thicknesses C and D.

[0090] In the case of FIG. 14D, the film thickness G of the stacked insulating layer 17 between two adjacent structures 19 is thicker than the film thickness H of the stacked insulating layer 17 on the upper surface of the structure 19. The film thickness H is about the same as the film thickness F. Also, the film thickness G is thicker than the film thickness A.

[0091] (Arranging the shield member 14 on the semiconductor chip 50) In FIG. 2, an example of arranging the shield member 14 in the peripheral circuit portion 2b of the silicon substrate (first substrate) 11 having the pixel array portion 2 is shown, but the shield member 14 may be arranged on the semiconductor chip 50.

[0092] FIG. 15 is a cross-sectional view showing an example of arranging the shield member 14 on the semiconductor chip 50. There are a plurality of candidates for the arrangement location of the shield member 14 in the semiconductor chip 50. FIG. 15A is a cross-sectional view showing a first example of the arrangement location of the shield member 14, and FIG. 15B is a cross-sectional view showing a second example of the arrangement location of the shield member 14. Although omitted in FIGS. 15A and 15B, a predetermined reference voltage (for example, a power supply voltage) is applied to the shield member 14 provided in the semiconductor chip 50 by a wiring layer, via, contact, etc. not shown. At least a part of the shield member 14 is arranged so as to overlap at least one wiring layer 53 in the semiconductor chip 50 in a plan view.

[0093] The shield member 14 in FIG. 15A is arranged along the lowermost surface of the semiconductor chip 50. A pad portion 51 is arranged in the same layer as the shield member 14, and the shield member 14 is formed using the same material (for example, aluminum (Al)) in the same manufacturing process as the pad portion 51. This pad portion 51 is joined to the pad portion 34 of the silicon substrate (first substrate) 11 by bumps 52. Above the shield member 14, a plurality of wiring layers 53 are arranged. By providing the shield member 14, noise from the wiring layer 53 is prevented from being transmitted to the silicon substrate (first substrate) 11 side.

[0094] The shield member 14 in FIG. 15B is arranged above the pad portion 51, that is, inside the semiconductor chip 50. At the same height as the shield member 14, a wiring layer 53 is arranged and is formed of the same material as the material of the wiring layer 53 (for example, copper (Cu)). Above the shield member 14, a wiring layer 53 or a pad portion 51 or the like is arranged, and the shield member 14 can prevent noise from the wiring layer 53 from being transmitted to the silicon substrate (first substrate) 11.

[0095] FIG. 16 is a diagram for explaining the thickness and width of the pad portion 34, the shield member 14, and the like. The thicknesses of the shield member 14, the dummy wiring layer 15, and the pad portion 36 are about 500 to 750 nm, while the thicknesses of the pad portion 34 for bump connection, the vertical signal line VSL, and the wiring layer 33 are about 100 to 250 nm. Thus, the thickness of the shield member 14 is thicker than the thicknesses of the vertical signal line VSL and the wiring layer 33.

[0096] The shield member 14 is arranged so as to cover at least a part of the vertical signal line VSL. Specifically, it is desirable that the width of the shield member 14 is equal to or greater than the combined width of the plurality of vertical signal lines VSL.

[0097] FIG. 17 is a cross-sectional view showing an example of the layer structure of a structure 19 such as a shield member 14 or a dummy wiring layer 15. The structure 19 in FIG. 17 has a three-layer structure, and the lowermost layer is a laminate 19a composed of TaN / Ta / TaN / Ta. An AlCu layer 19b is laminated on the laminate 19a, and a Ta layer 19c is disposed on the AlCu layer 19b. The thickness of the lowermost laminate 19a is, for example, about 3000 nm, the thickness of the AlCu layer 19b is, for example, about 750 nm, and the thickness of the uppermost Ta layer is, for example, about 25 nm.

[0098] FIG. 18 is a cross-sectional view showing an example of the layer structure of the pad portions 34 and 36. The layer structure of the pad portions 34 and 36 is the same as the layer structure of the structure 19 in FIG. 17, but a part of the uppermost Ta layer 19c is removed to expose the AlCu layer 19b.

[0099] As described above, the semiconductor device 1 according to the present embodiment has a CoW structure in which a semiconductor chip 50 is bonded via bumps on a silicon substrate (first substrate) 11 on which a pixel array portion 2 is disposed, and a shield member 14 is disposed so as to cover at least a part of the vertical signal lines VSL. Therefore, noise from the semiconductor chip 50 can be blocked by the shield member 14, the voltage level of the vertical signal lines VSL does not fluctuate due to noise from the logic circuit of the semiconductor chip 50, and the electrical characteristics of the semiconductor device 1 can be improved.

[0100] In addition, since the upper surfaces of the shield member 14 and the pixel array portion 2 are covered with a laminated insulating layer 17 containing SiN, the moisture resistance can be improved. Further, the film thickness of the laminated insulating layer 17 is changed depending on the location, and the SiN layer in the pixel array portion 2 is made thicker, so that the dark current can be suppressed while improving the moisture resistance. Furthermore, since the laminated insulating layer 17 in the pad portions 34 and 36 is made thicker than the laminated insulating layer 17 in the shield member 14 and the dummy wiring layer 15, the flatness can be improved and the planarization process can be simplified.

[0101] In FIG. 2, an example of flip-chip mounting a semiconductor chip (logic chip) 50 on a silicon substrate 11 on which a sensor element 10 is mounted is shown. However, separately from the semiconductor chip 50, another silicon substrate 54 on which a logic circuit or the like is mounted may be bonded to the silicon substrate 11.

[0102] FIG. 19 is a cross-sectional view of a semiconductor device 1a in which a silicon substrate 54 is bonded to a silicon substrate 11. On the silicon substrate 54, a logic circuit including at least a part of a peripheral circuit portion of an image sensor and the like is mainly mounted.

[0103] The silicon substrate 54 is bonded to the outermost surface SF3 side of the wiring layer 20 of the silicon substrate 11. The silicon substrate 54 and the silicon substrate 11 are joined, for example, by CCC (Couper to Couper Connection). Alternatively, these two substrates 11 and 54 may be joined by vias or bumps. On the silicon substrate 54, a laminated wiring layer 23 and an insulating layer 24 are laminated, and a Cu wiring layer 25 provided in the insulating layer 21 of the silicon substrate 11 and a Cu wiring layer 26 provided in the insulating layer 24 of the silicon substrate 54 are directly joined.

[0104] Thus, in the present embodiment, when the semiconductor chip 50 is flip-chip mounted on the silicon substrate 11 on which the sensor element 10 is mounted by CoW, at least one of the silicon substrate 11 or the semiconductor chip 50 is provided with a shield member 14 so that noise from the wiring layer 53 of the semiconductor chip 50 is not transmitted to the wiring layer 33 (particularly the vertical signal line VSL) on the silicon substrate 11. Thereby, noise from the wiring layer 53 of the semiconductor chip 50 is not superimposed on the vertical signal line VSL, and the electrical characteristics of the semiconductor device 1 such as improvement in the image quality of the captured image can be improved.

[0105] Since the shield member 14 is arranged in the same layer as the pad portion 36 for bonding wire connection and the dummy wiring layer 15, it can be formed in an existing manufacturing process.

[0106] By making the thickness of the shield member 14 thicker than the thickness of the pad portion 34 for flip-chip mounting the semiconductor chip 50 and making the thickness of the pad portion 34 higher than the upper surface of the interlayer insulating layer 31 in the pixel array portion 2, the step of the laminated insulating layer 17 can be reduced, and the flatness of the planarization layer 38 disposed on the laminated insulating layer 17 can be improved.

[0107] <Application Examples to Mobile Objects> The technology according to the present disclosure (this technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile object such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, a robot, etc.

[0108] FIG. 20 is a block diagram showing a schematic configuration example of a vehicle control system which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0109] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in FIG. 20, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an out-of-vehicle information detection unit 12030, an in-vehicle information detection unit 12040, and an integrated control unit 12050. Further, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053 are illustrated.

[0110] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device such as a driving force generation device for generating a driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0111] The body control unit 12020 controls the operations of various devices installed in the vehicle according to various programs. For example, the body control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as a headlamp, a backlamp, a brake lamp, a turn signal, or a fog lamp. In this case, radio waves transmitted from a portable device that replaces a key or signals from various switches can be input to the body control unit 12020. The body control unit 12020 receives these inputs of radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0112] The vehicle exterior information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the outside of the vehicle and receives the captured image. The vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing on objects such as people, vehicles, obstacles, signs, or characters on the road surface based on the received image.

[0113] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. Also, the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared light.

[0114] The vehicle interior information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the vehicle interior information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that images the driver, and the vehicle interior information detection unit 12040 may calculate the degree of driver fatigue or concentration based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0115] Based on the information inside and outside the vehicle acquired by the out-vehicle information detection unit 12030 or the in-vehicle information detection unit 12040, the microcomputer 12051 can calculate the control target values of the driving force generator, the steering mechanism, or the braking device, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control for realizing functions of an ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation of the vehicle, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, collision warning of the vehicle, or lane departure warning of the vehicle.

[0116] In addition, based on the information around the vehicle acquired by the out-vehicle information detection unit 12030 or the in-vehicle information detection unit 12040, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, etc., which runs autonomously regardless of the driver's operation, by controlling the driving force generator, the steering mechanism, the braking device, etc.

[0117] Also, based on the out-vehicle information acquired by the out-vehicle information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, the microcomputer 12051 can perform cooperative control for the purpose of anti-glare, such as controlling the headlamp according to the position of the preceding vehicle or the oncoming vehicle detected by the out-vehicle information detection unit 12030 and switching the high beam to the low beam.

[0118] The audio-visual output unit 12052 transmits at least one of an audio output signal and a video output signal to an output device capable of notifying information visually or auditorily to the vehicle occupants or outside the vehicle. In the example of FIG. 20, as the output device, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0119] FIG. 21 is a diagram showing an example of the installation position of the imaging unit 12031.

[0120] In FIG. 21, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0121] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirror, rear bumper, back door, and the upper part of the windshield inside the vehicle cabin of the vehicle 12100, for example. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin mainly acquire images in front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images on the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or the back door mainly acquires images behind the vehicle 12100. The imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin is mainly used for detecting a preceding vehicle or pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0122] Note that FIG. 21 shows an example of the imaging ranges of the imaging units 12101 to 12104. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided at the front nose, and the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided at the side mirrors, respectively. The imaging range 12114 indicates the imaging range of the imaging unit 12104 provided at the rear bumper or the back door. For example, by overlapping the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0123] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0124] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 determines the distance to each solid object within the imaging ranges 12111 to 12114 and the temporal change of this distance (relative speed with respect to the vehicle 12100). In particular, it can extract, as the leading vehicle, the solid object that is closest to the traveling path of the vehicle 12100 and travels in substantially the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more). Further, the microcomputer 12051 can set the inter-vehicle distance to be secured in advance in front of the leading vehicle and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control), etc. Thus, cooperative control for the purpose of automatic driving, etc., which autonomously travels without relying on the driver's operation, can be performed.

[0125] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 classifies and extracts solid object data regarding solid objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other solid objects, and can use it for automatic avoidance of obstacles. For example, the microcomputer 12051 discriminates between obstacles around the vehicle 12100 as obstacles visible to the driver of the vehicle 12100 and obstacles difficult to visually recognize. Then, the microcomputer 12051 determines a collision risk indicating the degree of risk of collision with each obstacle. When the collision risk is equal to or higher than a set value and there is a possibility of collision, it can output an alarm to the driver via the audio speaker 12061 or the display unit 12062, or perform forced deceleration or avoidance steering via the drive system control unit 12010 to provide driving support for collision avoidance.

[0126] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian exists in the captured images of the imaging units 12101 to 12104. Such recognition of a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras and a procedure of performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio-visual output unit 12052 controls the display unit 12062 to superimpose and display a rectangular contour line for emphasis on the recognized pedestrian. Further, the audio-visual output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0127] As described above, an example of a vehicle control system to which the technology according to the present disclosure can be applied has been described. The technology according to the present disclosure can be applied to, for example, the imaging unit 12031 or the like among the configurations described above. Specifically, the semiconductor devices 1 and 1a according to the present disclosure can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031 or the like, a more visible high-quality captured image can be obtained, so that it becomes possible to reduce the driver's fatigue. Note that the present technology can adopt the following configurations. (1) A first substrate having a first pad and a signal wiring, A semiconductor chip bonded to the first substrate at the first pad, A conductive member disposed so as to cover at least a part of the signal wiring, and A semiconductor device. (2) The semiconductor device according to (1), wherein the conductive member is disposed at a height different from that of the first pad. (1) The semiconductor device according to (1). (3) The semiconductor device according to (1) or (2), wherein the conductive member is disposed on the first substrate. (1) or (2) The semiconductor device according to (1) or (2). (4) the first substrate has a second pad to which a bonding wire is connected; The conductive member is disposed at the same height as the second pad. The semiconductor device according to (3). (5) The first substrate has a dummy wiring layer that is disposed at the same height as the conductive member and has an indefinite voltage level. The semiconductor device according to (3) or (4). (6) The thickness of the conductive member is greater than the thickness of the signal wiring. The semiconductor device according to any one of (1) to (5). (7) The conductive member is disposed on the semiconductor chip. The semiconductor device according to (1) or (2). (8) The semiconductor chip has a wiring layer that is arranged so as to at least partially overlap the conductive member in a plan view. The semiconductor device according to (7). (9) The semiconductor chip has a plurality of stacked wiring layers, the conductive member is disposed so as to cover at least a portion of the wiring layer closest to the first substrate, among the plurality of wiring layers. (8) The semiconductor device according to (8). (10) The conductive member is set to a predetermined voltage level. The semiconductor device according to any one of (1) to (9). (11) The first substrate has a plurality of pixels, Each of the plurality of pixels is a photoelectric conversion element; a pixel circuit for generating a pixel signal photoelectrically converted by the photoelectric conversion element, the signal wiring, at least a portion of which is covered with the conductive member, transmits the pixel signal; The semiconductor device according to any one of (1) to (10). (12) The semiconductor chip is bonded to the first substrate via a plurality of the first pads, a plurality of the signal wirings are arranged between two of the first pads that are adjacent to each other in a predetermined direction in a plan view; The semiconductor device described in (11). (13) The two or more of the first pads are arranged in a first direction and a second direction that intersect each other, The signal wiring, A plurality of first signal wirings arranged along the second direction between the two or more first pads arranged in the first direction in a plan view, A plurality of second signal wirings arranged along the first direction and connecting the plurality of first signal wirings and the two or more first pads, The conductive member is arranged so as to cover at least a part of the plurality of first signal wirings and the plurality of second signal wirings, (12) The semiconductor device described in (12). (14) An insulating layer is provided so as to cover the first pad, the signal wiring, and the plurality of pixels, The thickness of the insulating layer is different for each location of the first pad, the signal wiring, and the pixel, (11) to (13) Any one of the semiconductor devices. (15) In the insulating layer, the thickness of the region overlapping the plurality of pixels in a plan view is thicker than the thickness of the region overlapping the signal wiring, (14) The semiconductor device described in (14). (16) In the insulating layer, the thickness of the region overlapping the plurality of pixels in a plan view is thicker than the thickness of the region overlapping the first pad, (14) The semiconductor device described in (14). (17) In the insulating layer, the thickness of the region overlapping the first pad in a plan view is thicker than the thickness of the region overlapping the signal wiring, (14) The semiconductor device described in (14). (18) The insulating layer is a laminated insulating layer formed by laminating a plurality of insulating films containing different insulating materials, (14) to (17) Any one of the semiconductor devices described in any one of the above items. (19) The conductive member is arranged so as to face the signal wiring with the insulating layer interposed therebetween, (14) to (18) Any one of the semiconductor devices described in any one of the above items. (20) A second substrate is laminated on the first substrate on the side opposite to the bonding surface of the semiconductor chip; a logic circuit disposed on at least one of the semiconductor chip and the second substrate, (The semiconductor device according to any one of 1 to 19.

[0128] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and intent of the present disclosure, which is derived from the contents defined in the claims and their equivalents. [Explanation of symbols]

[0129] REFERENCE SIGNS LIST 1 semiconductor device, 1a semiconductor device, 2 pixel array section, 2a pixel array section, 2b peripheral circuit section, 3 vertical drive section, 4 column processing section, 5 horizontal drive section, 6 system control section, 7 signal processing section, 8 data storage section, 9 output section, 10 sensor element, 11 silicon substrate, H1, H2, H1a, H2a openings, 12 photoelectric conversion section, 13 through via, 14 shielding member, 15 dummy wiring layer, 16 via, 17 laminated insulating layer, 18 wiring (second signal wiring), 18 wiring, 19 structure, 19a laminated body, 19b AlCu layer, 19c Ta layer, 20 multilayer wiring layer, 21 insulating layer, 22 wiring layer, 23 laminated wiring layer, 24 insulating layer, 25 Cu wiring layer, 26 Cu wiring layer, 31 interlayer insulating layer, 31a insulating layer, 32 light-shielding film, 33 Wiring layer, 34 pad portion, 34a metal film, 34b metal film, 34c metal film, 35 pixel separation portion, 36 pad portion, 37L inner lens, 38 planarization layer, 39 pixel separation portion, 40 protective layer, 41 color filter, 42 on-chip lens layer, 42L on-chip lens, 50 semiconductor chip, 51 pad portion, 52 solder bump, 53 wiring layer, 54 silicon substrate, 100A light receiving area, 100B peripheral area

Claims

1. A first substrate having a first pad and a signal wiring, A semiconductor chip bonded to the first substrate at the first pad, A conductive member disposed so as to cover at least a part of the signal wiring, and comprising: A semiconductor device.

2. The conductive member is disposed at a height different from that of the first pad, The semiconductor device according to claim 1.

3. The conductive member is disposed on the first substrate, The semiconductor device according to claim 1.

4. The first substrate has a second pad to which a bonding wire is connected, The conductive member is disposed at the same height as the second pad, The semiconductor device according to claim 3.

5. The first substrate is disposed at the same height as the conductive member and has a dummy wiring layer with an indeterminate voltage level, The semiconductor device according to claim 3.

6. The thickness of the conductive member is thicker than the thickness of the signal wiring, The semiconductor device according to claim 1.

7. The conductive member is disposed on the semiconductor chip, The semiconductor device according to claim 1.

8. The semiconductor chip has a wiring layer disposed so as to overlap at least a part of the conductive member in plan view, The semiconductor device according to claim 7.

9. The semiconductor chip has a plurality of stacked wiring layers, The conductive member is disposed so as to cover at least a part of the wiring layer closest to the first substrate among the plurality of wiring layers, The semiconductor device according to claim 8.

10. The conductive member is set to a predetermined voltage level, The semiconductor device according to claim 1.

11. The first substrate has a plurality of pixels, Each of the plurality of pixels, A photoelectric conversion element, A pixel circuit that generates a pixel signal photoelectrically converted by the photoelectric conversion element, and having, The signal wiring at least partially covered by the conductive member transmits the pixel signal, The semiconductor device according to claim 1.

12. The semiconductor chip is bonded to the first substrate via a plurality of the first pads, A plurality of the signal wirings are disposed between two of the first pads adjacent to each other in a predetermined direction in plan view, The semiconductor device according to claim 11.

13. Two or more of the first pads are arranged in a first direction and a second direction intersecting each other, The signal wiring is, A plurality of first signal wirings disposed along the second direction between the two or more first pads arranged in the first direction in plan view, A plurality of second signal wirings that are arranged along the first direction and connect the plurality of first signal wirings and the two or more first pads. The conductive member is arranged so as to cover at least a part of the plurality of first signal wirings and the plurality of second signal wirings. The semiconductor device according to claim 12.

14. An insulating layer that is arranged so as to cover the first pad, the signal wiring, and the plurality of pixels. The thickness of the insulating layer is different for each location of the first pad, the signal wiring, and the pixel. The semiconductor device according to claim 11.

15. In the insulating layer, the thickness of the region overlapping the plurality of pixels in plan view is thicker than the thickness of the region overlapping the signal wiring. The semiconductor device according to claim 14.

16. In the insulating layer, the thickness of the region overlapping the plurality of pixels in plan view is thicker than the thickness of the region overlapping the first pad. The semiconductor device according to claim 14.

17. In the insulating layer, the thickness of the region overlapping the first pad in plan view is thicker than the thickness of the region overlapping the signal wiring. The semiconductor device according to claim 14.

18. The insulating layer is a laminated insulating layer formed by laminating a plurality of insulating films containing different insulating materials. The semiconductor device according to claim 14.

19. The conductive member is arranged so as to face the signal wiring with the insulating layer interposed therebetween. The semiconductor device according to claim 14.

20. A second substrate laminated on the side of the first substrate opposite to the bonding surface of the semiconductor chip. A logic circuit arranged on at least one of the semiconductor chip and the second substrate. The semiconductor device according to claim 1.

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