Semiconductor device

Abstract

To provide a semiconductor device with parasitic capacitance reduced.SOLUTION: A transistor 10 includes a substrate 100, an insulating layer 110 on the substrate, an oxide insulating layer 121 on the insulating layer, an oxide semiconductor layer 122 on the oxide insulating layer, an oxide insulating layer 123 on the insulating layer and the oxide semiconductor layer, a gate insulating layer 150 on the oxide insulating layer, a gate electrode layer 160 on the gate insulating layer, a side wall insulating layer 176 on the oxide insulating layer, an insulating layer 180 on the oxide insulating layer, a conductive layer 190 on low-resistance regions 125 and 127, and a conductive layer 195 on the conductive layer. The oxide semiconductor layer and the oxide insulating layer include the low-resistance region 125 or the low-resistance region 127. The side wall insulating layer is provided on the oxide insulating layer and includes a region in contact with a side surface of the gate insulating layer and the gate electrode layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine, relating to the manufacture or composition of matter, especially The present invention relates to, for example, a semiconductor device, a display device, a light-emitting device, a power storage device, an imaging device, and In particular, one embodiment of the present invention relates to a semiconductor device or a driving method thereof. or a method for producing the same.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term generally refers to a semiconductor device. A transistor and a semiconductor circuit are examples of a semiconductor device. Display devices and electronic devices may include semiconductor devices. [Background technology]

[0003] The technology of constructing a transistor using a semiconductor film formed on a substrate with an insulating surface is attracting attention. The transistor is used in devices such as integrated circuits (ICs) and image display devices (display devices). Silicon is widely used as a semiconductor thin film that can be applied to transistors. Silicon-based semiconductor materials are widely known, but oxide semiconductors are also attracting attention. There are.

[0004] For example, indium (In), gallium (Ga), and A transistor using an amorphous oxide semiconductor containing zinc (Zn) is disclosed in Patent Document 1. There are.

[0005] In addition, a conductive layer may be formed over an oxide semiconductor layer and then subjected to heat treatment. A method for manufacturing a transistor with reduced layer resistance is disclosed in Patent Document 2 and non-patent documents. Yes.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Non-Patent Documents

[0007]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] In manufacturing a semiconductor device with highly integrated transistors, miniaturization of the transistors is essential. However, in the miniaturization of transistors, an increase in the parasitic capacitance of the transistors becomes a problem. In transistor operation, when there is parasitic capacitance in the vicinity of the channel (for example, between the source electrode and the drain electrode), time is required for charging the parasitic capacitance, which reduces the responsiveness of the transistor and, consequently, the responsiveness of the semiconductor device. Yes.

[0009] In addition, in various processes for forming transistors (especially film formation, processing, etc.), as miniaturization progresses, the controllability becomes more difficult, and variations in the manufacturing process have a great impact on transistor characteristics and, further, on reliability. Yes. Yes.

[0010] Yes. Yes. Yes.

[0011] Therefore, one aspect of the present invention aims to reduce the parasitic capacitance near the transistor. Or, one of the aims is to provide a semiconductor device capable of high-speed operation. Also One of the aims is to provide a semiconductor device with good electrical characteristics. Or, one of the aims is to provide a highly reliable semiconductor device. Or, one of the aims is to reduce the variation in characteristics of a transistor or a semiconductor device due to the manufacturing process. A semiconductor device having an oxide semiconductor with less oxygen deficiency is provided. Or, one of the aims is to provide a semiconductor device that can be formed by a simple process. Also Or, one of the aims is to provide a semiconductor device configured to be able to reduce the interface state density near the oxide semiconductor. Or, one of the aims is to provide a low-power consumption semiconductor device. Or, one of the aims is to provide a novel semiconductor device or the like. Or, one of the aims is to provide a method for manufacturing the above semiconductor device. Or, one of the aims is to provide a novel semiconductor device or the like. Or, one of the aims is to provide a method for manufacturing the above semiconductor device.

[0012] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention is not required to solve all of these problems. Note that other problems will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc. will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc.

Means for Solving the Problems

[0013] (1) One aspect of the present invention forms a first insulating layer on a substrate, and on the first insulating layer, a first oxide insulating layer, and a first oxide semiconductor layer are sequentially formed, the first oxide insulating layer, and the first oxide semiconductor layer are etched into an island shape using a first mask to form a second oxide insulating layer and a second oxide semiconductor layer, a third oxide insulating layer is formed on the second oxide semiconductor layer and the first insulating layer is formed, a second insulating layer is formed on the third oxide insulating layer, and a first conductive layer is formed on the second insulating layer and the first conductive layer and the second insulating layer are selectively etched using a second mask to form a gate electrode layer and a gate insulating layer, and a first low-resistance region is formed by adding a first ion to the second oxide semiconductor layer using the gate electrode layer as a mask A third insulating layer is formed on the gate electrode layer, the third oxide insulating layer, and the first insulating layer A sidewall insulating layer is formed by performing dry etching on the third insulating layer, and a second conductive layer is formed on the gate electrode layer, the sidewall insulating layer, the third oxide insulating layer, and the first insulating layer A region alloyed in the second oxide semiconductor layer is formed by performing a heat treatment, which is a method for manufacturing a semiconductor device characterized by doing so

[0014] (2) Another aspect of the present invention is to form a first insulating layer on a substrate, and on the first insulating layer, a first oxide insulating layer and a first oxide semiconductor layer are sequentially formed, and the stack of the first oxide insulating layer and the first oxide semiconductor layer is etched into an island shape using a first mask to form a second oxide insulating layer and a second oxide semiconductor layer, a third oxide insulating layer is formed on the second oxide semiconductor layer and the first insulating layer is formed, a second insulating layer is formed on the third oxide insulating layer, a first conductive layer is formed on the second insulating layer and the first conductive layer and the second insulating layer are selectively etched using a second mask ​​By etching, a gate electrode layer and a gate insulating layer are formed, and the gate electrode layer is masked. and a first ion is added to the second oxide semiconductor layer to form a first low-temperature oxide semiconductor layer. forming a resistive region, a gate electrode layer, a third oxide insulating layer, and a third insulating layer on the first insulating layer; and then dry etching the third insulating layer to form a sidewall insulating layer. , the gate electrode layer, and the sidewall insulating layer are used as a mask to perform a process on the second oxide semiconductor layer. and forming a second low resistance region by adding a second ion. A method for fabricating the device.

[0015] (3) In the method for manufacturing a semiconductor device described above, the second conductive layer is made of molybdenum, titanium, tantalum, It is preferable that the material is a metal or nitride containing at least one of tungsten and tungsten.

[0016] (4) In the method for manufacturing a semiconductor device described above, the first ions added are fluorine ions. , phosphorus, argon, or xenon, and the dose of the first ions is 1× 10 13 ions / cm 2 5x10 or more 16 ions / cm 2 It is preferable to .

[0017] (5) In the method for manufacturing the semiconductor device described above, the second ions in the addition of the second ions are titanium ions. It is preferable that the metal is one or more of indium, molybdenum, tantalum, and tungsten. It's nice.

[0018] (6) Another aspect of the present invention is a method for manufacturing a semiconductor device comprising: forming a first oxide insulating layer on a first insulating layer; a second oxide insulating layer on the oxide semiconductor layer; and a gate insulating layer on the second oxide insulating layer. a gate electrode layer on the gate insulating layer; and a sidewall insulating layer on the oxide semiconductor layer; The lower surface of the oxide semiconductor layer is higher than the lower surface of the gate electrode layer in the cross section in the channel width direction. The oxide semiconductor layer is located at a position lower than the gate electrode layer, and the oxide semiconductor layer has a top surface and a side surface facing the gate electrode layer. the sidewall insulating layer has a region in contact with a side surface of the gate insulating layer, and the oxide semiconductor layer has The first region has a region overlapping with a gate electrode layer, and the second region has a region overlapping with a gate electrode layer. has a region between the first region and the third region and overlaps with the sidewall insulating layer, and The region has a region of lower resistance compared to the first region, and a third region of higher resistance compared to the second region. a lower region having a first element, a second region having a first element, and a third region having a first element and a second element The semiconductor device is characterized by having a region having the following:

[0019] (7) In the semiconductor device described above, a first conductive layer is provided below the oxide semiconductor layer, and the first conductive layer It is preferable that the insulating film has a region overlapping with the oxide semiconductor layer.

[0020] (8) In the semiconductor device described above, the first element is any one of fluorine, phosphorus, argon, and xenon. The second element is one or more of titanium, indium, molybdenum, tungsten, tantalum, It is preferable that the above formula is one or more of the formulas.

[0021] (9) In the above-described semiconductor device, the third region preferably includes a region containing an alloy.

[0022] (10) Another embodiment of the present invention is a semiconductor device including the above-described semiconductor device, a housing, and a speaker. It is an electronic device. [Effects of the Invention]

[0023] Therefore, by using one embodiment of the present invention, it is possible to reduce parasitic capacitance near a transistor. As a result, a semiconductor device capable of high-speed operation can be provided. Alternatively, a semiconductor device with high reliability can be provided. Alternatively, the characteristics of a transistor or semiconductor device caused by the manufacturing process can be improved. The semiconductor device including the oxide semiconductor with few oxygen vacancies can be manufactured. Alternatively, a semiconductor device that can be formed by a simple process can be provided. Alternatively, the interface state density in the vicinity of the oxide semiconductor layer can be reduced. Alternatively, a semiconductor device with low power consumption can be provided. Alternatively, a novel semiconductor device or the like can be provided. A method for fabricating the device can be provided.

[0024] The description of these effects does not preclude the existence of other effects. The embodiment does not necessarily have to have all of these effects. , the specification, drawings, claims, etc., and It is possible to extract other effects from the claims and other descriptions. [Brief explanation of the drawings]

[0025]

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Mode for Carrying Out the Invention

[0026] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are commonly used for the same parts or parts having the same functions in different drawings, and the repeated description may be omitted. Note that the matching of the same elements constituting the drawings may be appropriately omitted or changed between different drawings. be, and it can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are commonly used for the same parts or parts having the same functions in different drawings, and the repeated description may be omitted. Note that the matching of the same elements constituting the drawings may be appropriately omitted or changed between different drawings. It should not be construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are commonly used for the same parts or parts having the same functions in different drawings, and the repeated description may be omitted. Note that the matching of the same elements constituting the drawings may be appropriately omitted or changed between different drawings. In the configuration of the invention described below, the same reference numerals are commonly used for the same parts or parts having the same functions in different drawings, and the repeated description may be omitted. Note that the matching of the same elements constituting the drawings may be appropriately omitted or changed between different drawings. For example, in this specification and the like, when it is explicitly described that X and Y are connected, it is assumed that X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected as disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text, and those other than the connection relationship shown in the figure or the text are also regarded as being described in the figure or the text.

[0027] For example, in this specification and the like, when it is explicitly described that X and Y are connected, it is assumed that X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected as disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text, and those other than the connection relationship shown in the figure or the text are also regarded as being described in the figure or the text. be. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text, and those other than the connection relationship shown in the figure or the text are also regarded as being described in the figure or the text. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text, and those other than the connection relationship shown in the figure or the text are also regarded as being described in the figure or the text. For example, in this specification and the like, when it is explicitly described that X and Y are connected, it is assumed that X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected as disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text, and those other than the connection relationship shown in the figure or the text are also regarded as being described in the figure or the text.

[0028] Here, let X and Y be objects (e.g., devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers , etc.).

[0029] As an example of the case where X and Y are directly connected, an element (e.g., a switch, transistor, capacitor, inductor, resistor, diode , display element, light-emitting element, load, etc.) that enables electrical connection between X and Y is not connected between X and Y, and X and Y are connected without an element (e.g., a switch, transistor, capacitor , inductor, resistor, diode, display element, light-emitting element, load, etc.) that enables electrical connection between X and Y. That is, it is a case where X and Y are connected without passing through such an element.

[0030] As an example of the case where X and Y are electrically connected, one or more elements (e.g., a switch, transistor, capacitor , inductor, resistor, diode, display element, light-emitting element, load, etc.) that enable electrical connection between X and Y can be connected between X and Y. Note that a switch has a function of controlling on / off. That is, a switch can be in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether to allow current to flow or not. Or, a switch has a function of selecting and switching a path through which current flows. When X and Y are electrically connected, it shall include the case where X and Y are directly connected.

[0031] As an example of the case where X and Y are functionally connected, a circuit (e.g., a logic circuit (inverter, NAND circuit, NOR circuit, etc.), signal conversion circuit, etc.) that enables functional connection between X and Y Conversion circuits (such as DA conversion circuits, AD conversion circuits, gamma correction circuits), potential level conversion circuits (power source circuits (such as boost circuits, buck circuits), level shifter circuits that change the potential level of signals, etc.) , voltage sources, current sources, switching circuits, amplification circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplification circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected by one or more between X and Y. Note that, as an example, even if another circuit is sandwiched between X and Y, when the signal output from X is transmitted to Y, X and Y shall be regarded as functionally connected. Note that when X and Y are functionally connected, it shall include the case where X and Y are directly connected and the case where X and Y are electrically connected.

[0032] Note that when it is explicitly stated that X and Y are electrically connected, the case where X and Y are electrically connected (that is, connected with another element or another circuit sandwiched between X and Y ), the case where X and Y are functionally connected (that is, functionally connected with another circuit sandwiched between X and Y ), and the case where X and Y are directly connected (that is, connected without another element or another circuit sandwiched between X and Y ) are disclosed in this specification and the like. That is, when it is explicitly stated that they are electrically connected, it is disclosed in this specification and the like that the same content as the case where it is only explicitly stated that they are connected. That is, when it is explicitly stated that they are electrically connected, the same content as the case where it is only explicitly stated that they are connected is disclosed in this specification and the like.

[0033] Note that, for example, the source (or the first terminal, etc.) of a transistor is connected via Z1 (or via not), is electrically connected to X, and the drain (or the second terminal, etc.) of the transistor is Z When it is electrically connected to Y via (or without) 2, or the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, and another part of Z1 is directly connected to X connected, and the drain (or the second terminal, etc.) of the transistor is directly connected to a part of Z2 connected, and another part of Z2 is directly connected to Y, it can be expressed as follows can be done.

[0034] For example, it can be expressed as "X, Y, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor are electrically connected to each other, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as "The source (or the first terminal, etc.) of the transistor is electrically connected to X, the drain (or the second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as "X is electrically connected to Y via the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are provided in this connection order." Using the same expression method as these examples, by stipulating the connection order in the circuit configuration, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor can be distinguished ". etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are provided in this connection order." It can be expressed as such. By using the same expression method as these examples, by stipulating the connection order in the circuit configuration, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor can be distinguished Using a similar expression method to stipulate the connection order in the circuit configuration, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor can be distinguished from each other, between the source (or the first terminal, etc.) of the transistor and the drain (or the second terminal, etc.) Thus, the technical scope can be determined.

[0035] Or, as another expression method, for example, "the source of the transistor (or the first terminal, etc.) is electrically connected to X via at least the first connection path, and the first connection path does not have a second connection path, and the second connection path is the path between the source (or the first terminal, etc.) of the transistor and the drain (or the second terminal, etc.) of the transistor via the transistor, and the first connection path is the path via Z1, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y via at least the third connection path, and the third connection path does not have the second connection path, and the third connection path is the path via Z2." It can be expressed like this. Or, "the source (or the first terminal, etc.) of the transistor is electrically connected to X via Z1 by at least the first connection path, and the first connection path does not have a second connection path, and the second connection path has a connection path via the transistor, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y via Z2 by at least the third connection path, and the third connection path does not have the second connection path." It can be expressed like this. Or, "the source (or the first terminal, etc.) of the transistor is electrically connected to X via Z1 by at least the first electrical path, and the first electrical path does not have a second electrical path, and the second electrical path is the electrical path from the source (or the first terminal, etc.) of the transistor to the drain (or the second terminal, etc.) of the transistor, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y via at least the third electrical path, and the third electrical path does not have the second electrical path." It can be expressed like this. Or, "the source (or the first terminal, etc.) of the transistor is electrically connected to X via Z1 by at least the first electrical path, and the first electrical path does not have a second electrical path, and the second electrical path is the electrical path from the source (or the first terminal, etc.) of the transistor to the drain (or the second terminal, etc.) of the transistor, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y via at least the third electrical path, and the first electrical path does not have a second electrical path, and the second electrical path is the electrical path from the source (or the first terminal, etc.) of the transistor to the drain (or the second terminal, etc.) of the transistor, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y via at least the third electrical path, and the third electrical path does not have the second electrical path." It can be expressed like this. Or, "the source (or the first terminal, etc.) of the transistor is electrically connected to X via Z1 by at least the first electrical path, and the first electrical is electrically connected to Y via Z2 by the electrical path of, and the third electrical path does not have a fourth electrical path, and the fourth electrical path is from the drain (or the second terminal, etc.) of the transistor to the source (or the first terminal, etc.) of the transistor is an electrical path. It can be expressed as ". By using an expression method similar to these examples, by defining the connection path in the circuit configuration, the source (or the first terminal etc.) of the transistor and the drain (or the second terminal, etc.) of the transistor can be distinguished to determine the technical scope.

[0036] Note that these expression methods are just examples and are not limited to these expression methods. Here, X , Y, Z1, and Z2 are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0037] Note that even when components that are independent on the circuit diagram are shown as being electrically connected to each other , there may be a case where one component has the functions of a plurality of components combined. For example, when a part of the wiring also functions as an electrode, one conductive film has the functions of both the wiring function and the electrode function. Therefore, the electrical connection in this specification includes such a case where one conductive film has the functions of a plurality of components combined within its scope.

[0038] <Supplementary Note Regarding the Description of the Drawings> In this specification, phrases indicating arrangements such as "above" and "below" are used for convenience in explaining the positional relationship between components with reference to the drawings. Also, the positional relationship between components is It changes appropriately according to the direction of depicting the configuration. Therefore, it is not limited to the terms described in the specification and can be appropriately rephrased according to the situation. It is not limited and can be appropriately rephrased according to the situation.

[0039] Also, the terms "upper" and "lower" do not limit the positional relationship of the components to be directly above or below and in direct contact. For example, in the expression "electrode B on insulating layer A", it is not necessary for electrode B to be formed in direct contact on insulating layer A, and those including other components between insulating layer A and electrode B are not excluded.

[0040] In this specification, "parallel" means a state where two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, "substantially parallel" means a state where two straight lines are arranged at an angle of -30° or more and 30° or less. Also, "perpendicular" means a state where two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Also, "substantially perpendicular" means a state where two straight lines are arranged at an angle of 60° or more and 120° or less.

[0041] Also, in this specification, when the crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

[0042] Also, in the drawings, the size, layer thickness, or area are shown in an arbitrary size for the convenience of explanation. Therefore, it is not necessarily limited to that scale. Note that the drawings are shown schematically for clarity and are not limited to the shapes or values shown in the drawings.

[0043] Also, in the drawings, in the top view (also called the plan view or layout view) and perspective view, etc., For the sake of clarity of the drawings, descriptions of some components may be omitted.

[0044] Also, "identical" may have the same area or the same shape. Also, due to the relationship of the manufacturing process, it is assumed that it may not have exactly the same shape, so it can be rephrased as substantially identical and still be considered identical. Since it is assumed that it may not have exactly the same shape due to the relationship of the manufacturing process, it can be rephrased as substantially identical and still be considered identical. and can be rephrased as being identical.

[0045] <Supplementary Note Regarding Rephrasable Descriptions> In this specification and the like, when explaining the connection relationship of a transistor, one of the source and the drain is expressed as "one of the source or the drain" (or the first electrode, or the first terminal), and the other of the source and the drain is expressed as "the other of the source or the drain" (or the second electrode, or the second terminal). This is because the source and the drain of a transistor change depending on the structure or operating conditions of the transistor. Regarding the naming of the source and the drain of a transistor, it can be appropriately rephrased according to the situation, such as the source (drain) terminal or the source (drain) electrode. This is because the source and the drain of a transistor change depending on the structure or operating conditions of the transistor. Regarding the naming of the source and the drain of a transistor, it can be appropriately rephrased according to the situation, such as the source (drain) terminal or the source (drain) electrode. it can be appropriately rephrased according to the situation, such as the source (drain) terminal or the source (drain) electrode. and can be appropriately rephrased according to the situation.

[0046] Also, in this specification and the like, the terms "electrode" and "wiring" do not functionally define these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed. and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed. and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed.

[0047] Also, in this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. And the drain (drain terminal, drain electrode) There is a channel region between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and current can flow through the drain, the channel region and the source.

[0048] Here, since the source and the drain change depending on the structure or operating conditions of the transistor, etc., it is difficult to limit which one is the source or the drain. Therefore, the part that functions as the source and the part that functions as the drain are not called the source or the drain, and in some cases, one of the source and the drain is denoted as the first electrode, and the other of the source and the drain is denoted as the second electrode.

[0049] It should be noted that the ordinal numbers "first", "second", "third", etc. used in this specification are added to avoid confusion of components, and it is noted that they are not numerically limiting.

[0050] In addition, in this specification, etc., a display device may refer to a device in which, for example, an FPC (Flexible Printed Circuits) or a TCP (Tape Carrier Package) is attached to the substrate of the display panel, or a device in which an IC (integrated circuit) is directly mounted by the COG (Chip On Glass) method.

[0051] Also, the term "film" and the term "layer" can be interchanged with each other in some cases or depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer".

[0052] ​​​​​​​​​​​​ <Supplementary Note on the Definition of Clauses> Hereinafter, the definition of clauses in this specification and the like will be described.

[0053] <Regarding Connection> In this specification, "A and B are connected" means that A and B are directly connected, and in addition, it includes those that are electrically connected. Here, "A and B are electrically connected" means that when there is an object having some electrical action between A and B, it enables the transfer of electrical signals between A and B.

[0054] Note that the content described in one embodiment (even some content) can be applied to, combined with, or replaced with the content described in another embodiment (even some content) described in that embodiment, and / or the content described in one or more other embodiments (even some content).

[0055] Note that the content described in the embodiments refers to the content described using various figures in each embodiment, or the content described using the text described in the specification.

[0056] Note that the figure (even a part) described in one embodiment can be combined with another part of that figure, another figure (even a part) described in that embodiment, and / or the figure (even a part) described in one or more other embodiments to form more figures.

[0057] (Embodiment 1) In this embodiment, a semiconductor device according to one aspect of the present invention and a method for manufacturing the same will be described with reference to the drawings.

[0058] <Structure of Transistor 10> FIG. 1(A), FIG. 1(B), and FIG. 1(C) are top views and cross-sectional views of transistor 10 according to one aspect of the present invention. FIG. 1(A) is a top view, FIG. 1(B) is a cross-sectional view taken along the dashed line A1 - A2 shown in FIG. 1(A), FIG. 1(C) is a cross-sectional view taken along the line A3 - A4 shown in FIG. 1(A). Note that in FIG. 1(A), some elements are enlarged, reduced, or omitted for clarity of the drawing. (A), some elements are enlarged, reduced, or omitted for clarity of the drawing. Also, the direction of the dashed line A1 - A2 may be referred to as the channel length direction, and the direction of the dashed line A3 - A4 may be referred to as the channel width direction.

[0059] Transistor 10 includes a substrate 100, an insulating layer 110, an oxide insulating layer 121, an oxide semiconductor layer 122, an oxide insulating layer 123, a low-resistance region 125, a low-resistance region 127, a gate insulating layer 150, a gate electrode layer 160, sidewall insulating layers 176, an insulating layer 180, a conductive layer 190, and a conductive layer 195.

[0060] Insulating layer 110 is provided on substrate 100.

[0061] Oxide insulating layer 121 is provided on insulating layer 110.

[0062] Oxide semiconductor layer 122 is provided on oxide insulating layer 121.

[0063] Oxide insulating layer 123 is provided on insulating layer 110 and oxide semiconductor layer 122. Also, oxide insulating layer 123 may have a region in contact with the side surface of oxide semiconductor layer 122. Thereby, the side ends of oxide semiconductor layer 122 can be protected, and the electrical characteristics of the transistor can be stabilized.

[0064] The oxide semiconductor layer 122 and the oxide insulating layer 123 have a low-resistance region 125 and a low-resistance region 1 27. The low-resistance region 125 contains any one or more of hydrogen, nitrogen, fluorine, helium, neon, argon , krypton, xenon, boron, and phosphorus. Further, the low-resistance region 1 27 contains, in addition to the materials shown in the low-resistance region 125, any one or more of titanium, molybdenum, tungsten, chromium , vanadium, niobium, tantalum, zirconium, and hafnium . The low-resistance region 125 and the low-resistance region 127 function as a source or a drain .

[0065] Also, in the low-resistance region 127, the materials shown above, the oxide semiconductor layer 122, and the oxide insulating layer 123 may form an alloy. By forming an alloy, the resistance can be reduced .

[0066] The low-resistance region 125 and the low-resistance region 127 in the oxide semiconductor layer 122 and the oxide insulating layer 123 can be referred to as an oxide conductive layer .

[0067] Note that a structure in which neither the low-resistance region 125 nor the low-resistance region 127 is present may also be used .

[0068] In the oxide semiconductor layer 122 and the oxide insulating layer 123, the channel region overlapping the gate electrode layer 160 is defined as the first region, the region overlapping the sidewall insulating layer 176 is defined as the second region, and the region where the gate electrode layer 160 and the sidewall insulating layer 176 do not overlap is defined as the third region. In this case, the low-resistance region 125 can be provided in the second region and the third region. The low-resistance region 127 can be provided in the third region. Note that the low-resistance region 125 may extend into the first region, and the low-resistance region 127 may also extend into the first region . can be provided in the third region. Note that the low-resistance region 125 may spread into the first region, and the low-resistance region 127 may also spread into the first region may spread to the second region. When compared with the third region, this second region can be referred to as an LDD (Lightly Doped Drain) region. Also, the low-resistance regions 125 and 127 may extend across the oxide insulating layer 121.

[0069] Also, in the above, the second region has a region with lower resistance than the first region, and the third region can be said to have a region with lower resistance than the second region. Resistance can be expressed by resistance value measurement ( for example, sheet resistance) or impurity concentration.

[0070] Also, in the third region, there is a region where the concentration of the above-described elements is 1×10 18 atoms / cm 3 or more and 1×10 22 atoms / cm 3 or less.

[0071] The gate insulating layer 150 is provided on the oxide insulating layer 123.

[0072] The gate electrode layer 160 is provided on the gate insulating layer 150. Note that the gate electrode layer 160 and the gate insulating layer 150, the oxide insulating layer 123, and the oxide semiconductor layer 122 are provided in a stacked manner.

[0073] The sidewall insulating layer 176 is provided on the oxide insulating layer 123 and has a region in contact with the side surfaces of the gate insulating layer 150 and the gate electrode layer 160.

[0074] The insulating layer 180 is provided on the oxide insulating layer 123.

[0075] The conductive layer 190 is provided on the low-resistance region 125 or the low-resistance region 127. The conductive layer 1 90 and the low-resistance region 125 or the low-resistance region 127 have regions that are electrically connected. .

[0076] The conductive layer 195 is provided on the conductive layer 190.

[0077] With the above structure, the parasitic capacitance between the gate and the source or between the gate and the drain can be reduced. As a result, the cut-off frequency characteristics of the transistor 10 are improved, and the transistor can operate at high speed.

[0078] In addition, since the transistor 10 can form the gate, source, and drain in a self-aligned manner, the alignment accuracy is relaxed, and a fine transistor can be easily fabricated.

[0079] In addition, as shown in the cross-sectional view taken along line A3 - A4 in FIG. 1(C), the transistor 10 has a region where the gate electrode layer 160 faces the side surfaces of the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 via the gate insulating layer 150 in the channel width direction. That is, when a voltage is applied to the gate electrode layer 160, the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 are surrounded by the electric field of the gate electrode layer 160 in the channel width direction. The structure of the transistor in which the semiconductor is surrounded by the electric field of the gate electrode layer 160 is called a surrounded channel (s-channel) structure. Also, in the S-channel structure, the lower surface of the oxide semiconductor layer 122 is provided at a position higher than the lower surface of the gate electrode layer 160.

[0080] Here, the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 together When using a certain oxide, in transistor 10, in the on state, since a channel is formed throughout the entire (bulk) of the oxide semiconductor layer 122, the on-current increases. On the other hand, in the off state case, since the entire channel region formed in the oxide semiconductor layer 122 is depleted, the off-current can be made even smaller.

[0081] <Regarding the oxide insulating layer> Note that the oxide insulating layer (for example, oxide insulating layer 121, oxide insulating layer 123) basically has insulating properties and refers to a layer in which current can flow near the interface with the semiconductor when the gate electric field or drain electric field becomes strong.

[0082] <Regarding the channel length> Note that the channel length in a transistor refers to, for example, in the top view of the transistor, the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the semiconductor (or the part where current flows in the semiconductor when the transistor is in the on state) overlaps with the gate electrode, or in the region where the channel is formed. Note that in one transistor, the channel length does not necessarily take the same value in all regions. That is, the channel length of one transistor may not be determined by a single value. Therefore, in this specification, the channel length is taken as any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.

[0083] <Regarding the channel width> The channel width refers to, for example, the length of the region where the semiconductor (or the part where current flows in the semiconductor when the transistor is in the on state) overlaps with the gate electrode. Note that in one transistor, In the case of a transistor, the channel width does not necessarily take the same value in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.

[0084] Note that depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter referred to as the effective channel width) may differ from the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may increase. In that case, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view.

[0085] By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0086] <Regarding SCW> Therefore, in this specification, in the top view of the transistor, where the semiconductor and the gate electrode overlap, ​​​​​​​​​​​The apparent channel width in the region may be referred to as the "surrounded channel width (SCW)". Also, in this specification, when simply described as the channel width, it may refer to the surrounded channel width or the apparent channel width. Or, in this specification, when simply described as the channel width, it may refer to the effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, surrounded channel width, etc. can be determined by obtaining a cross-sectional TEM image, etc. and analyzing the image. In addition, when calculating the field-effect mobility of a transistor, the current value per channel width, etc., the surrounded channel width may be used for calculation. In that case, the value may be different from the case of calculating using the effective channel width. <Improvement of characteristics in miniaturization> To highly integrate a semiconductor device, miniaturization of transistors is essential. On the other hand, it is known that the electrical characteristics of transistors deteriorate due to miniaturization of transistors, and when the channel width is reduced, the on-current decreases. For example, in the transistor of one aspect of the present invention shown in FIG. 1, as described above, an oxide insulating layer 123 is formed so as to cover the oxide semiconductor layer 122 in which the channel is formed, and the channel formation region and the gate insulating layer are not in contact with each other. Therefore, scattering of carriers generated at the interface between the channel formation region and the gate insulating layer can be suppressed, and the on-current of the transistor can be increased.

[0087]

[0088]

[0089]

[0090] ​​​​​​​​​​​​​​ Also, in the transistor according to one aspect of the present invention, since the gate electrode layer 160 is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 122 serving as a channel, in addition to the gate electric field from the vertical direction, a gate electric field from the side surface direction is applied to the oxide semiconductor layer 122. Further, the lower surface of the oxide semiconductor layer 122 is positioned higher than the lower surface of the gate electrode layer 160, and a gate electric field is also applied to the lower surface of the oxide semiconductor layer 122. That is, a gate electric field is applied to the entire oxide semiconductor layer 122, and current flows through the entire oxide semiconductor layer 122, so that the on-current can be further increased. Also, in the transistor according to one aspect of the present invention, since the gate electrode layer 160 is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 122 serving as a channel, in addition to the gate electric field from the vertical direction, a gate electric field from the side surface direction is applied to the oxide semiconductor layer 122. Further, the lower surface of the oxide semiconductor layer 122 is positioned higher than the lower surface of the gate electrode layer 160, and a gate electric field is also applied to the lower surface of the oxide semiconductor layer 122. That is, a gate electric field is applied to the entire oxide semiconductor layer 122, and current flows through the entire oxide semiconductor layer 122, so that the on-current can be further increased. Also, in the transistor according to one aspect of the present invention, since the gate electrode layer 160 is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 122 serving as a channel, in addition to the gate electric field from the vertical direction, a gate electric field from the side surface direction is applied to the oxide semiconductor layer 122. Further, the lower surface of the oxide semiconductor layer 122 is positioned higher than the lower surface of the gate electrode layer 160, and a gate electric field is also applied to the lower surface of the oxide semiconductor layer 122. That is, a gate electric field is applied to the entire oxide semiconductor layer 122, and current flows through the entire oxide semiconductor layer 122, so that the on-current can be further increased. Also, in the transistor according to one aspect of the present invention, since the gate electrode layer 160 is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 122 serving as a channel, in addition to the gate electric field from the vertical direction, a gate electric field from the side surface direction is applied to the oxide semiconductor layer 122. Further, the lower surface of the oxide semiconductor layer 122 is positioned higher than the lower surface of the gate electrode layer 160, and a gate electric field is also applied to the lower surface of the oxide semiconductor layer 122. That is, a gate electric field is applied to the entire oxide semiconductor layer 122, and current flows through the entire oxide semiconductor layer \alpha, so that the on-current can be further increased. Also, in the transistor according to one aspect of the present invention, since the gate electrode layer 160 is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 122 serving as a channel, in addition to the gate electric field from the vertical direction, a gate electric field from the side surface direction is applied to the oxide semiconductor layer 122. Further, the lower surface of the oxide semiconductor layer 1\alpha is positioned higher than the lower surface of the gate electrode layer 160, and a gate electric field is also applied to the lower surface of the oxide semiconductor layer 122. That is, a gate electric field is applied to the entire oxide semiconductor layer 122, and current flows through the entire oxide semiconductor layer 122, so that the on-current can be further increased. Also, in the transistor according to one aspect of the present invention, since the gate electrode layer 160 is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 122 serving as a channel, in addition to the gate electric field from the vertical direction, a gate electric field from the side surface direction is applied to the oxide semiconductor layer 122. Further, the lower surface of the oxide semiconductor layer 122 is positioned higher than the lower surface of the gate electrode layer 160, and a gate electric field is also applied to the lower surface of the oxide semiconductor layer 122. That is, a gate electric field is applied to the entire oxide semiconductor layer 122, and current flows through the entire oxide semiconductor layer 122, so that the on-current can be further increased. Also, in the transistor according to one aspect of the present invention, since the gate electrode layer 160 is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 122 serving as a channel, in addition to the gate electric field from the vertical direction, a gate electric field from the side surface direction is applied to the oxide semiconductor layer 122. Further, the lower surface of the oxide semiconductor layer 122 is positioned higher than the lower surface of the gate electrode layer 160, and a gate electric field is also applied to the lower surface of the oxide semiconductor layer 122. That is, a gate electric field is applied to the entire oxide semiconductor layer 122, and current flows through the entire oxide semiconductor layer 122, so that the on-current can be further increased.

[0091] Also, the transistor according to one aspect of the present invention has effects such as making it difficult to form interface states by forming the oxide insulating layer 123 on the oxide insulating layer 121 and the oxide semiconductor layer 122, and eliminating the influence of impurity mixing from above and below by making the oxide semiconductor layer 122 an intermediate layer. Therefore, in addition to the improvement of the on-current of the transistor described above, the threshold voltage can be stabilized and the S value (subthreshold value) can be reduced. Consequently, Icut (current when the gate voltage VG is 0V) can be lowered, and power consumption can be reduced. Further, since the threshold voltage of the transistor is stabilized, the long-term reliability of the semiconductor device can be improved. Also, the transistor according to one aspect of the present invention has effects such as making it difficult to form interface states by forming the oxide insulating layer 123 on the oxide insulating layer 121 and the oxide semiconductor layer 122, and eliminating the influence of impurity mixing from above and below by making the oxide semiconductor layer 122 an intermediate layer. Therefore, in addition to the improvement of the on-current of the transistor described above, the threshold voltage can be stabilized and the S value (subthreshold value) can be reduced. Consequently, Icut (current when the gate voltage VG is 0V) can be lowered, and power consumption can be reduced. Further, since the threshold voltage of the transistor is stabilized, the long-term reliability of the semiconductor device can be improved. Also, the transistor according to one aspect of the present invention has effects such as making it difficult to form interface states by forming the oxide insulating layer 123 on the oxide insulating layer 121 and the oxide semiconductor layer 122, and eliminating the influence of impurity mixing from above and below by making the oxide semiconductor layer 122 an intermediate layer. Therefore, in addition to the improvement of the on-current of the transistor described above, the threshold voltage can be stabilized and the S value (subthreshold value) can be reduced. Consequently, Icut (current when the gate voltage VG is 0V) can be lowered, and power consumption can be reduced. Further, since the threshold voltage of the transistor is stabilized, the long-term reliability of the semiconductor device can be improved. Also, the transistor according to one aspect of the present invention has effects such as making it difficult to form interface states by forming the oxide insulating layer \alpha on the oxide insulating layer 121 and the oxide semiconductor layer 122, and eliminating the influence of impurity mixing from above and below by making the oxide semiconductor layer 122 an intermediate layer. Therefore, in addition to the improvement of the on-current of the transistor described above, the threshold voltage can be stabilized and the S value (subthreshold value) can be reduced. Consequently, Icut (current when the gate voltage VG is 0V) can be lowered, and power consumption can be reduced. Further, since the threshold voltage of the transistor is stabilized, the long-term reliability of the semiconductor device can be improved. Also, the transistor according to one aspect of the present invention has effects such as making it difficult to form interface states by forming the oxide insulating layer 123 on the oxide insulating layer 121 and the oxide semiconductor layer 122, and eliminating the influence of impurity mixing from above and below by making the oxide semiconductor layer 122 an intermediate layer. Therefore, in addition to the improvement of the on-current of the transistor described above, the threshold voltage can be stabilized and the S value (subthreshold value) can be reduced. Consequently, Icut (current when the gate voltage VG is 0V) can be lowered, and power consumption can be reduced. Further, since the threshold voltage of the transistor is stabilized, the long-term reliability of the semiconductor device can be improved. Also, the transistor according to one aspect of the present invention has effects such as making it difficult to form interface states by forming the oxide insulating layer 123 on the oxide insulating layer 121 and the oxide semiconductor layer 122, and eliminating the influence of impurity mixing from above and below by making the oxide semiconductor layer 122 an intermediate layer. Therefore, in addition to the improvement of the on-current of the transistor described above, the threshold voltage can be stabilized and the S value (subthreshold value) can be reduced. Consequently, Icut (current when the gate voltage VG is 0V) can be lowered, and power consumption can be reduced. Further, since the threshold voltage of the transistor is stabilized, the long-term reliability of the semiconductor device can be improved. Also, the transistor according to one aspect of the present invention has effects such as making it difficult to form interface states by forming the oxide insulating layer 123 on the oxide insulating layer 121 and the oxide semiconductor layer 122, and eliminating the influence of impurity mixing from above and below by making the oxide semiconductor layer 122 an intermediate layer. Therefore, in addition to the improvement of the on-current of the transistor described above, the threshold voltage can be stabilized and the S value (subthreshold value) can be reduced. Consequently, Icut (current when the gate voltage VG is 0V) can be lowered, and power consumption can be reduced. Further, since the threshold voltage of the transistor is stabilized, the long-term reliability of the semiconductor device can be improved. Also, the transistor according to one aspect of the present invention has effects such as making it difficult to form interface states by forming the oxide insulating layer 123 on the oxide insulating layer 121 and the oxide semiconductor layer 122, and eliminating the influence of impurity mixing from above and below by making the oxide semiconductor layer 122 an intermediate layer. Therefore, in addition to the improvement of the on-current of the transistor described above, the threshold voltage can be stabilized and the S value (subthreshold value) can be reduced. Consequently, Icut (current when the gate voltage VG is 0V) can be lowered, and power consumption can be reduced. Further, since the threshold voltage of the transistor is stabilized, the long-term reliability of the semiconductor device can be improved.

[0092] Also, in the transistor according to one aspect of the present invention, since the gate electrode layer 160 is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 122 serving as a channel, in addition to the gate electric field from the vertical direction, a gate electric field from the side surface direction is applied to the oxide semiconductor layer 122. Also, in the transistor according to one aspect of the present invention, since the gate electrode layer 160 is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 122 serving as a channel, in addition to the gate electric field from the vertical direction, a gate electric field from the side surface direction is applied to the oxide semiconductor layer 122. Also, in the transistor according to one aspect of the present invention, since the gate electrode layer 160 is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 122 serving as a channel, in addition to the gate electric field from the vertical direction, a gate electric field from the side surface direction is applied to the oxide semiconductor layer 122. is applied. That is, a gate electric field is applied to the entire oxide semiconductor layer 122, and it becomes possible to suppress the influence of the drain electric field and significantly suppress the short-channel effect. Therefore, even when miniaturized, good characteristics can be obtained. .

[0093] In addition, the transistor according to one aspect of the present invention has a wide bandgap material in the oxide semiconductor layer 122 serving as the channel, so that it has high source-drain breakdown voltage characteristics and can have stable electrical characteristics in various temperature environments.

[0094] Note that in this embodiment, examples using an oxide semiconductor layer or the like in a channel or the like have been shown, but one aspect of the embodiment of the present invention is not limited thereto. For example, the channel and its vicinity, the source region, the drain region, etc. may, in some cases or according to the situation, be formed of a material having silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor , or the like.

[0095] [[ID=3o]] <Each component of the transistor> Each component of the transistor according to this embodiment is shown below.

[0096] 《Substrate 100》 For the substrate 100, for example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. can be used. Also, a single-crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, SOI (Silico It is also possible to use an (n On Insulator) substrate or the like, and those with semiconductor elements provided thereon may be used. The substrate 100 is not limited to a mere support material, and may be a substrate on which other devices such as other transistors are formed. In this case, one or more of the gate, source, and drain of the transistor may be electrically connected to the above-mentioned other devices.

[0097] Also, a flexible substrate may be used as the substrate 100. As a method of providing a transistor on the flexible substrate, after manufacturing a transistor on a non-flexible substrate, there is also a method of peeling off the transistor and transferring it to the substrate 100 which is a flexible substrate. In that case, it is preferable to provide a peeling layer between the non-flexible substrate and the transistor. Note that, as the substrate 100, a sheet, film, or foil woven with fibers may be used. Also, the substrate 100 may have stretchability. Also, the substrate 100 may have the property of returning to its original shape when bending or pulling is stopped. Or, it may have the property of not returning to its original shape. The thickness of the substrate 100 is, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, more preferably 15 μm or more and 300 μm or less. Making the substrate 100 thinner can reduce the weight of the semiconductor device. Also, by making the substrate 100 thinner, in the case of using glass or the like, there may be a case where it has stretchability, or a property of returning to its original shape when bending or pulling is stopped. Therefore, impacts applied to the semiconductor device on the substrate 100 due to dropping or the like can be alleviated. That is, a robust semiconductor device can be provided.

[0098] As the substrate 100 which is a flexible substrate, for example, metals, alloys, resins, glass, or their fibers and the like can be used. The substrate 100 which is a flexible substrate preferably has a lower coefficient of linear expansion so that deformation due to the environment is suppressed. As the substrate 100 which is a flexible substrate, for example, a material having a coefficient of linear expansion of 1×10 / K or less, 5×10 -3 / K or less, or 1×10 -5 / K or less may be used. Examples of the resin include polyester, polyolefin, -5 polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, polytetrafluoroethylene (PTFE), and the like. In particular, aramid is suitable as the substrate 100 which is a flexible substrate because it has a low coefficient of linear expansion.

[0099] 《Insulating layer 110》 The insulating layer 110 can use an insulating film containing one or more of silicon (Si), nitrogen (N), oxygen (O), fluorine (F), hydrogen (H)), aluminum (Al), gallium (Ga), germanium (Ge), yttrium ( Y), zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (Hf ), and tantalum (Ta).

[0100] In addition to having a role of preventing diffusion of impurities from the substrate 100, the insulating layer 110 can play a role of supplying oxygen to the oxide semiconductor layer 122. Therefore, the insulating layer 110 is preferably an insulating film containing oxygen, and more preferably an insulating film containing more oxygen than the stoichiometric composition. For example, in the TDS method, the oxygen release amount in terms of oxygen atoms is 1.0 ×10 atoms / cm 19 3 or more. Note that the film during the above TDS analysis​​​ The surface temperature is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 500°C or lower. When the substrate 100 is a substrate on which other devices are formed as described above , the insulating layer 110 also functions as an interlayer insulating film. In that case, it is preferable to perform planarization processing by a method such as CMP (Chemical Mechanical Polishing) so that the surface becomes flat.

[0101] In addition, in the insulating layer 110, by having fluorine, fluorine gasified from the insulating layer can stabilize the oxygen deficiency in the oxide semiconductor layer 122.

[0102] 《Oxide insulating layer 121, oxide semiconductor layer 122, oxide insulating layer 123》 The oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 are oxide semiconductor films containing In or Zn , and typically include In-Ga oxide, In-Zn oxide, In -Mg oxide, Zn-Mg oxide, In-M-Zn oxide (M is Al, Ti, Ga, Y, Sn, Zr, La, Ce, Mg, Hf, or Nd).

[0103] The oxides that can be used as the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 preferably contain at least indium (In) or zinc (Zn) . Or it is preferable to contain both In and Zn. In addition, in order to reduce the variation in the electrical characteristics of the transistors using the oxide, it is preferable to include a stabilizer together with them.

[0104] Examples of the stabilizer include gallium (Ga), tin (Sn), hafnium (Hf), aluminum There are aluminum (Al), zirconium (Zr), etc. Also, as other stabilizers there are lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (P r), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium ( Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium ( Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), etc. .

[0105] The contents of indium, gallium, etc. in the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 can be compared by time-of-flight secondary ion mass spectrometry (TOF-SIMS), X-ray photoelectron spectroscopy (XPS), or ICP mass spectrometry (ICP-MS).

[0106] Since the oxide semiconductor layer 122 has an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more, the off-current of the transistor 10 can be reduced.

[0107] The thickness of the oxide semiconductor layer 122 is 3 nm or more and 200 nm or less, preferably 3 nm or more and 10 0 nm or less, and more preferably 3 nm or more and 50 nm or less.

[0108] Note that the thickness of the oxide semiconductor layer 122 may be formed thinner, the same, or thicker than the oxide insulating layer 121. For example, when the oxide semiconductor layer 122 is thickened, the on-current of the transistor can be increased. Also, the oxide insulating layer 12 1 has a thickness such that the effect of suppressing the generation of interface levels in the oxide semiconductor layer 122 is not lost. That's all right. For example, the thickness of the oxide semiconductor layer 122 is greater than 1 times, or 2 times or more, or 4 times or more, or 6 times or more than the thickness of the oxide insulating layer 121. Also, when it is not necessary to increase the on-current of the transistor, the thickness of the oxide insulating layer 12 1 may be equal to or greater than the thickness of the oxide semiconductor layer 122.

[0109] When the compositions of the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 are different, the interface may be observed using a scanning transmission electron microscope STEM (Scanning Tran smission Electron Microscope). It can be done. In some cases.

[0110] Also, the oxide semiconductor layer 122 may have a higher In content than the oxide insulating layer 121 and the oxide insulating layer 123. In oxide semiconductors, mainly the s-orbitals of heavy metals contribute to carrier conduction. By increasing the In content, more s-orbitals overlap, so an oxide with a composition where In is more than M has a higher mobility compared to an oxide with a composition where In is equal to or less than M. Therefore, by using an oxide with a high In content for the oxide semiconductor layer 122, a transistor with high field-effect mobility can be realized. In oxide semiconductors, mainly the s-orbitals of heavy metals contribute to carrier conduction. By increasing the In content, more s-orbitals overlap, so an oxide with a composition where In is more than M has a higher mobility compared to an oxide with a composition where In is equal to or less than M. Therefore, by using an oxide with a high In content for the oxide semiconductor layer 122, a transistor with high field-effect mobility can be realized. In some cases. By using an oxide with a high In content for the oxide semiconductor layer 122, a transistor with high field-effect mobility can be realized.

[0111] Also, when the oxide semiconductor layer 122 is an In-M-Zn oxide (M is Al, Ti, Ga, Y, Sn , Zr, La, Ce, Mg, Hf, or Nd), for example, in the target used to form the oxide semiconductor layer 122 by sputtering, when the atomic ratio of the metal elements is In:M:Zn = x2:y2:z2, x2 / (x2 + y2 + z2) is 1 / 3. In some cases. In some cases. It is preferable to be as described above. Further, x2 / y2 is 1 / 3 or more and 10 or less, more preferably 1 or more and 6 or less, and z2 / y2 is 1 / 3 or more and 10 or less, more preferably 1 or more and 6 or less. Thereby, a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) film is likely to be formed. Representative examples of the atomic ratio of the metal elements of the target include In :M:Zn = 1:1:1, 1:1:1.2, 2:1:1.5, 2:1:2.3, 2:1: 3, 3:1:2, 4:2:3, 4:2:4.1, 5:1:7, etc.

[0112] As the oxide insulating layer 121 and the oxide insulating layer 123, having a function as a stabilizer Al, Ti, Ga, Y, Sn, Zr, La, Ce, Mg, Hf, or Nd, having a higher atomic ratio than In may have the following effects. (1) Increase the energy gap of the oxide insulating layer 12 1 and the oxide insulating layer 123. (2) Decrease the electron affinity of the oxide insulating layer 121 and the oxide insulating layer 123. (3) Shield impurities from the outside. (4) Have higher insulating properties compared to the oxide semiconductor layer 122. (5) Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, Hf, or Nd are metal elements with a strong binding force with oxygen elements. Therefore, by having Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, Hf, or N d at a higher atomic ratio than In, oxygen deficiency is less likely to occur.

[0113] By providing an oxide film less likely to have oxygen deficiency in contact with the upper and lower sides of the oxide semiconductor layer 122 compared to the oxide semiconductor layer 122 oxygen deficiency in the oxide semiconductor layer 122 can be reduced. This is possible. Further, since the oxide semiconductor layer 122 is in contact with the oxide insulating layer 121 containing one or more of the metal elements constituting the oxide semiconductor layer 122 and the oxide insulating layer 123, the interface state density at the interface between the oxide insulating layer 121 and the oxide semiconductor layer 122 and at the interface between the oxide semiconductor layer 122 and the oxide insulating layer 123 is extremely low. Therefore, after adding oxygen to the oxide insulating layer 121, the oxide insulating layer 123, the gate insulating layer 150, the insulating layer 110, or the insulating layer 180, and then performing heat treatment, the oxygen moves through the oxide insulating layer 121 and the oxide insulating layer 123 to the oxide semiconductor layer 122. At this time, the oxygen is trapped at the interface states, and it is possible to efficiently move the oxygen contained in the oxide insulating layer 121 or the oxide insulating layer 123 to the oxide semiconductor layer 122. As a result, it is possible to reduce the oxygen deficiency contained in the oxide semiconductor layer 122. Further, since oxygen is also added to the oxide insulating layer 121 or the oxide insulating layer 123, it is possible to reduce the oxygen deficiency of the oxide insulating layer 121 and the oxide insulating layer 123. That is, at least the local state density of the oxide semiconductor layer 122 can be reduced. When the oxide semiconductor layer 122 is in contact with an insulating film having different constituent elements (for example, a gate insulating layer including a silicon oxide film), interface states are formed, and these interface states may form a channel. In such a case, a second transistor having a different threshold voltage may appear, and the apparent threshold voltage of the transistor may vary. However, since the oxide insulating layer 121 and the oxide insulating layer 123 containing one or more of the metal elements constituting the oxide semiconductor layer 122 are in contact with the oxide semiconductor layer 122, the interface between the oxide insulating layer 121 and the oxide semiconductor layer 122 and the interface between the oxide semiconductor layer 122 and the oxide insulating layer 123 have an extremely low interface state density. Therefore, after adding oxygen to the oxide insulating layer 121, the oxide insulating layer 123, the gate insulating layer 150, the insulating layer 110, or the insulating layer 180, and then performing heat treatment, the oxygen moves through the oxide insulating layer 121 and the oxide insulating layer 123 to the oxide semiconductor layer 122. At this time, the oxygen is trapped at the interface states, and it is possible to efficiently move the oxygen contained in the oxide insulating layer 121 or the oxide insulating layer 123 to the oxide semiconductor layer 122. As a result, it is possible to reduce the oxygen deficiency contained in the oxide semiconductor layer 122. Further, since oxygen is also added to the oxide insulating layer 121 or the oxide insulating layer 123, it is possible to reduce the oxygen deficiency of the oxide insulating layer 121 and the oxide insulating layer 123. That is, at least the local state density of the oxide semiconductor layer 122 can be reduced. After adding oxygen to the oxide insulating layer 121, the oxide insulating layer 123, the gate insulating layer 150, the insulating layer 110, or the insulating layer 180, and then performing heat treatment, the oxygen moves through the oxide insulating layer 121 and the oxide insulating layer 123 to the oxide semiconductor layer 122. At this time, the oxygen is trapped at the interface states, and it is possible to efficiently move the oxygen contained in the oxide insulating layer 121 or the oxide insulating layer 123 to the oxide semiconductor layer 122. As a result, it is possible to reduce the oxygen deficiency contained in the oxide semiconductor layer 122. Further, since oxygen is also added to the oxide insulating layer 121 or the oxide insulating layer 123, it is possible to reduce the oxygen deficiency of the oxide insulating layer 121 and the oxide insulating layer 123. That is, at least the local state density of the oxide semiconductor layer 122 can be reduced. After adding oxygen to the oxide insulating layer 121, the oxide insulating layer 123, the gate insulating layer 150, the insulating layer 110, or the insulating layer 180, and then performing heat treatment, the oxygen moves through the oxide insulating layer 121 and the oxide insulating layer 123 to the oxide semiconductor layer 122. At this time, the oxygen is trapped at the interface states, and it is possible to efficiently move the oxygen contained in the oxide insulating layer 121 or the oxide insulating layer 123 to the oxide semiconductor layer 122. As a result, it is possible to reduce the oxygen deficiency contained in the oxide semiconductor layer 122. Further, since oxygen is also added to the oxide insulating layer 👍 121 or the oxide insulating layer 123, it is possible to reduce the oxygen deficiency of the oxide insulating layer 121 and the oxide insulating layer 123. That is, at least the local state density of the oxide semiconductor layer 122 can be reduced. After adding oxygen to the oxide insulating layer 121, the oxide insulating layer 123, the gate insulating layer 150, the insulating layer 110, or the insulating layer 180, and then performing heat treatment, the oxygen moves through the oxide insulating layer 121 and the oxide insulating layer 123 to the oxide semiconductor layer 122. At this time, the oxygen is trapped at the interface states, and it is possible to efficiently move the oxygen contained in the oxide insulating layer 121 or the oxide insulating layer 123 to the oxide semiconductor layer 122. As a result, it is possible to reduce the oxygen deficiency contained in the oxide semiconductor layer 122. Further, since oxygen is also added to the oxide insulating layer 121 or the oxide insulating layer 123, it is possible to reduce the oxygen deficiency of the oxide insulating layer 121 and the oxide insulating layer 123. That is, at least the local state density of the oxide semiconductor layer 122 can be reduced. After adding oxygen to the oxide insulating layer 121, the oxide insulating layer 123, the gate insulating layer 150, the insulating layer 110, or the insulating layer 180, and then performing heat treatment, the oxygen moves through the oxide insulating layer 121 and the oxide insulating layer 123 to the oxide semiconductor layer 122. At this time, the oxygen is trapped at the interface states, and it is possible to efficiently move the oxygen contained in the oxide insulating layer 121 or the oxide insulating layer 123 to the oxide semiconductor layer 122. As a result, it is possible to reduce the oxygen deficiency contained in the oxide semiconductor layer 122. Further, since oxygen is also added to the oxide insulating layer 121 or the oxide insulating layer 123, it is possible to reduce the oxygen deficiency of the oxide insulating layer 121 and the oxide insulating layer 123. That is, at least the local state density of the oxide semiconductor layer 122 can be reduced. After adding oxygen to the oxide insulating layer 121, the oxide insulating layer 123, the gate insulating layer 150, the insulating layer 110, or the insulating layer 180, and then performing heat treatment, the oxygen moves through the oxide insulating layer 121 and the oxide insulating layer 123 to the oxide semiconductor layer 122. At this time, the oxygen is trapped at the interface states, and it is possible to efficiently move the oxygen contained in the oxide insulating layer 121 or the oxide insulating layer 123 to the oxide semiconductor layer 122. As a result, it is possible to reduce the oxygen deficiency contained in the oxide semiconductor layer 122. Further, since oxygen is also added to the oxide insulating layer 121 or the oxide insulating layer 123, it is possible to reduce the oxygen deficiency of the oxide insulating layer 121 and the oxide insulating layer 123. That is, at least the local state density of the oxide semiconductor layer 122 can be reduced. After adding oxygen to the oxide insulating layer 121, the oxide insulating layer 123, the gate insulating layer 150, the insulating layer 110, or the insulating layer 180, and then performing heat treatment, the oxygen moves through the oxide insulating layer 121 and the oxide insulating layer 123 to the oxide semiconductor layer 122. At this time, the oxygen is trapped at the interface states, and it is possible to efficiently move the oxygen contained in the oxide insulating layer 121 or the oxide insulating layer 123 to the oxide semiconductor layer 122. As a result, it is possible to reduce the oxygen deficiency contained in the oxide semiconductor layer 122. Further, since oxygen is also added to the oxide insulating layer 121 or the oxide insulating layer 123, it is possible to reduce the oxygen deficiency of the oxide insulating layer 121 and the oxide insulating layer 123. That is, at least the local state density of the oxide semiconductor layer 122 can be reduced. After adding oxygen to the oxide insulating layer 121, the oxide insulating layer 123, the gate insulating layer 150, the insulating layer 110, or the insulating layer 180, and then performing heat treatment, the oxygen moves through the oxide insulating layer 121 and the oxide insulating layer 123 to the oxide semiconductor layer 122. At this time, the oxygen is trapped at the interface states, and it is possible to efficiently move the oxygen contained in the oxide insulating layer 121 or the oxide insulating layer 123 to the oxide semiconductor layer 122. As a result, it is possible to reduce the oxygen deficiency contained in the oxide semiconductor layer 122. Further, since oxygen is also added to the oxide insulating layer 121 or the oxide insulating layer 123, it is possible to reduce the oxygen deficiency of the oxide insulating layer 121 and the oxide insulating layer 123. That is, at least the local state density of the oxide semiconductor layer 122 can be reduced. After adding oxygen to the oxide insulating layer 121, the oxide insulating layer

[0114] When the oxide semiconductor layer 122 is in contact with an insulating film having different constituent elements (for example, a gate insulating layer including a silicon oxide film), interface states are formed, and these interface states may form a channel. In such a case, a second transistor having a different threshold voltage may appear, and the apparent threshold voltage of the transistor may vary. However, since the oxide insulating layer 121 and the oxide insulating layer 123 containing one or more of the metal elements constituting the oxide semiconductor layer 122 are in contact with the oxide semiconductor layer 122, the interface between the oxide insulating layer 121 and the oxide semiconductor layer 122 and the interface between the oxide semiconductor layer 122 and the oxide insulating layer 123 have an extremely low interface state density. Therefore, after adding oxygen to the oxide insulating layer 121, the oxide insulating layer 123, the gate insulating layer 150, the insulating layer 110, or the insulating layer 180, and then performing heat treatment, the oxygen moves through the oxide insulating layer 121 and the oxide insulating layer 123 to the oxide semiconductor layer 122. At this time, the oxygen is trapped at the interface states, and it is possible to efficiently move the oxygen contained in the oxide insulating layer 121 or the oxide insulating layer 123 to the oxide semiconductor layer 122. As a result, it is possible to reduce the oxygen deficiency contained in the oxide semiconductor layer 122. Further, since oxygen is also added to the oxide insulating layer 121 or the oxide insulating layer 123, it is possible to reduce the oxygen deficiency of the oxide insulating layer 121 and the oxide insulating layer 123. That is, at least the local state density of the oxide semiconductor layer 122 can be reduced. After adding oxygen to the oxide insulating layer 121, the oxide insulating layer 123, the gate insulating layer 150, the insulating layer 110, or the insulating layer 180, and then performing heat treatment, the oxygen moves through the oxide insulating layer 121 and the oxide insulating layer 123 to the oxide semiconductor layer 122. At this time, the oxygen is trapped at the interface states, and it is possible to efficiently move the oxygen contained in the oxide insulating layer 121 or the oxide insulating layer 123 to the oxide semiconductor layer 122. As a result, it is possible to reduce the oxygen deficiency contained in the oxide semiconductor layer 122. Further, since oxygen is also added to the oxide insulating layer 121 or the oxide insulating layer 123, it is possible to reduce the oxygen deficiency of the oxide insulating layer 121 and the oxide insulating layer 123. That is, at least the local state density of the oxide semiconductor layer 122 can be reduced. After adding oxygen to the oxide insulating layer 121, the oxide insulating layer 123, the gate insulating layer 150, the insulating layer 110, or the insulating layer 180, and then performing heat treatment, the oxygen moves through the oxide insulating layer 121 and the oxide insulating layer 123 to the oxide semiconductor layer 122. At this time, the oxygen is trapped at the interface states, and it is possible to efficiently move the oxygen contained in the oxide insulating layer 121 or the oxide insulating layer 123 to the oxide semiconductor layer 122. As a result, it is possible to reduce the oxygen deficiency contained in the oxide semiconductor layer 122. Further, since oxygen is also added to the oxide insulating layer 121 or the oxide insulating layer 123, it is possible to reduce the oxygen deficiency of the oxide insulating layer 121 and the oxide insulating layer 123. That is, at least the local state density of the oxide semiconductor layer 122 can be reduced. It is difficult to form interface levels at the interface between the interface and the oxide insulating layer 123 and the oxide semiconductor layer 122. It becomes difficult.

[0115] In this embodiment, the oxygen deficiency amount of the oxide semiconductor layer 122, and further the oxygen deficiency amounts of the oxide insulating layer 121 and the oxide insulating layer 123 in contact with the oxide semiconductor layer 122 can be reduced, and the density of localized levels of the oxide semiconductor layer 122 can be reduced. As a result, the transistor 10 shown in this embodiment can have characteristics of little variation in threshold voltage and high reliability. Further, the transistor 10 shown in this embodiment has excellent electrical characteristics to have.

[0116] Further, when the gate insulating layer 150 is in contact with the oxide semiconductor layer 122 and a channel is formed at the interface, interface scattering occurs at the interface, and the field-effect mobility of the transistor becomes low. However, since the oxide insulating layer 12 1 and the oxide insulating layer 123 containing one or more metal elements constituting the oxide semiconductor layer 122 are provided in contact with the oxide semiconductor layer 122, carrier scattering hardly occurs at the interfaces between the oxide semiconductor layer 122 and the oxide insulating layer 121 and the oxide insulating layer 123, and the field-effect mobility of the transistor can be increased.

[0117] The oxide insulating layer 121 and the oxide insulating layer 123 are typically In-Ga oxide, In-Z n oxide, In-Mg oxide, Ga-Zn oxide, Zn-Mg oxide, In-M-Zn acid oxide (M is Al, Ti, Ga, Y, Sn, Zr, La, Ce, Mg, Hf, or Nd) and the energy level of the lower end of the conduction band is closer to the vacuum level than the oxide semiconductor layer 122. ​​​​​​, typically, the energy level at the lower end of the conduction band of the oxide insulating layer 121 and the oxide insulating layer 123 and the energy level at the lower end of the conduction band of the oxide semiconductor layer 122 have a difference of 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.2 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. That is, the difference in electron affinity between the oxide insulating layer 121, the oxide insulating layer 123 and the oxide semiconductor layer 122 is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.2 eV or more, and 2 eV or less , 1 eV or less, 0.5 eV or less, or 0.4 eV or less. Note that the electron affinity indicates the difference between the vacuum level and the energy level at the lower end of the conduction band.

[0118] Also, when the oxide insulating layer 121 and the oxide insulating layer 123 are In-M-Zn oxides (M is Al, T i, Ga, Y, Sn, Zr, La, Ce, Mg, Hf, or Nd), compared with the oxide semiconductor layer 122, the atomic ratio of M (Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, Hf, or Nd) contained in the oxide insulating layer 121 and the oxide insulating layer 123 is high , and since the element represented by the aforementioned M binds more strongly to oxygen than indium, it has a function of suppressing the occurrence of oxygen deficiency in the oxide insulating layer 121 and the oxide insulating layer 123. That is, the oxide insulating layer 121 and the oxide insulating layer 123 are oxide semiconductor films in which oxygen deficiency is less likely to occur than in the oxide semiconductor layer 122 .

[0119] Also, when the oxide insulating layer 121 is an In-M-Zn oxide (M is Al, Ti, Ga, Y, Sn, Zr, La, Ce, Mg, Hf, or Nd), in the target used for forming the oxide insulating layer 121 by sputtering method, the atomic ratio of the metal elements is In:M​ :Assuming Zn = x1:y1:z1, x1 / y1 < z1 / y1, and z1 / y1 is preferably not less than 0.1 and not more than 6, more preferably not less than 0.2 and not more than 3.

[0120] In addition, since the oxide insulating layers 121 and 123 have higher insulating properties than the oxide semiconductor layer 122, they can have the same function as the gate insulating layer.

[0121] In addition, the oxide insulating layer 123 can be replaced with a metal oxide such as aluminum oxide (AlOx), gallium oxide (GaOx), hafnium oxide (HfOx), silicon oxide (SiOx), germanium oxide (GeOx), or zirconia (ZrOx), or the metal oxide can be provided on the oxide insulating layer 123.

[0122] In addition, the oxide insulating layer 123 may have a thickness that does not cause the generation of interface levels in the oxide semiconductor layer 122 to be lost. For example, the thickness may be equal to or less than that of the oxide insulating layer 121. If the oxide insulating layer 123 is thick, there is a risk that the electric field by the gate electrode layer 160 will not easily reach the oxide semiconductor layer 122. Therefore, the oxide insulating layer 123 is preferably formed thin. For example, the oxide insulating layer 123 may be thinner than the thickness of the oxide semiconductor layer 122. Note that the present invention is not limited to this, and the thickness of the oxide insulating layer 123 may be appropriately set according to the voltage for driving the transistor in consideration of the breakdown voltage of the gate insulating layer 150.

[0123] For example, the thickness of the oxide insulating layer 123 is preferably not less than 1 nm and not more than 20 nm, or not less than 3 nm and not more than 10 nm.

[0124] In addition, when the oxide insulating layer 123 is an In-M-Zn oxide (M is Al, Ti, Ga, Y, Sn, Zr, La, Ce, Mg, Hf, or Nd), in the target used for forming the oxide insulating layer 121 and the oxide insulating layer 123 by sputtering, when the atomic ratio of the metal elements is In:M:Zn = x3:y3:z3, x3 / y3 < x2 / y2, and z3 / y3 is preferably 1 / 3 or more and 6 or less, more preferably 1 or more and 6 or less. Note that by setting z3 / y3 to 1 or more and 6 or less, a CAAC-OS film is likely to be formed as the oxide insulating layer 123. Representative examples of the atomic ratio of the metal elements of the target include In:M:Zn = 1:3:2, 1:3:4, 1:3:6, 1:3:8, 1:4:4, 1:4 :5, 1:4:6, 1:4:7, 1:4:8, 1:5:5, 1:5:6, 1:5:7, 1 :5:8, 1:6:8, 1:6:4, 1:9:6, etc. Note that the atomic ratio is not limited to these, and an appropriate atomic ratio may be used according to the required semiconductor characteristics.

[0125] In addition, the atomic ratios of the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 may each include fluctuations of plus or minus 40% of the above atomic ratios as errors.

[0126] For example, when forming an oxide semiconductor film that becomes the oxide semiconductor layer 122, when using a target for film formation with an atomic ratio of metal elements of In:Ga:Zn = 1:1:1 for film formation, the atomic ratio of the metal elements of the oxide semiconductor film becomes about In:Ga:Zn = 1:1:0.6 and the atomic ratio of zinc may be the same or decreased. Therefore, when the atomic ratio is described, the vicinity of the atomic ratio is included.

[0127] ​​​​​​​ <Regarding hydrogen concentration> Hydrogen contained in the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 reacts with oxygen bonded to metal atoms to form water, and oxygen vacancies are formed in the lattice from which oxygen has desorbed (or the part from which oxygen has desorbed). When hydrogen enters the oxygen vacancies, carriers electrons may be generated. In addition, a part of the hydrogen may combine with oxygen bonded to metal atoms to generate carriers, electrons. Therefore, a transistor using an oxide semiconductor layer containing hydrogen tends to have normally-on characteristics. For this reason, at the oxide insulating layer 121, the oxide semiconductor layer 122, the oxide insulating layer 123, and their respective interfaces, it is preferable that hydrogen is reduced as much as possible together with oxygen vacancies. For example, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS: Secondary Ion

[0128] Mass Spectrometry) at the oxide insulating layer 121, the oxide semiconductor layer 122, the oxide insulating layer 123, and their respective interfaces is 1×10 atoms / cm or more and 2×10 atoms / cm or less, preferably 1×10 16 at oms / cm 3 or more and 5×10 20 atoms / cm 3 or less, more preferably 1×10 16 at oms / cm 3 or more and 1×10 19 atoms / cm 3 or less, even more preferably 1×10 16 atoms / cm 3 or more and 5×10 19 atoms / cm 3 or less, and even more preferably 1×1 0 16 atoms / cm 3 or more and 5×10 18 atoms / cm3 It is desirable to do the following. As a result, the transistor 10 can have electrical characteristics (also referred to as normal-off characteristics) in which the threshold voltage is positive.

[0129] <Regarding the carbon and silicon concentrations> In addition, when silicon or carbon, which is one of the Group 14 elements, is contained at the oxide insulating layer 121, the oxide semiconductor layer 122, the oxide insulating layer 123, and their respective interfaces, oxygen deficiency increases in the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123, and an n-type region may be formed. For this reason, it is desirable to reduce the concentrations of silicon and carbon at the oxide insulating layer 121, the oxide semiconductor layer 122, the oxide insulating layer 123, and their respective interfaces. For example, the concentrations of silicon and carbon obtained by SIMS at the oxide insulating layer 121, the oxide semiconductor layer 122, the oxide insulating layer 123, and their respective interfaces are 1×10 atoms / cm or more and 1×10 atoms / cm or less, preferably 1×10 atoms / cm 16 or more and 5×10 3 atoms / cm 19 or less, more preferably 1×10 3 atoms / cm 16 or more and 3 2×10 18 atoms / cm 3 or less. It is desirable to do the following. As a result, the transistor 10 can have electrical characteristics in which the threshold voltage is positive. 16 3 18 cm 3

[0130] <Regarding the concentrations of alkali metals and alkaline earth metals> In addition, when an alkali metal and an alkaline earth metal combine with an oxide semiconductor, carriers may be generated, and the off-current of the transistor may increase. Therefore, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the oxide insulating layer 121, the oxide semiconductor layer 122, the oxide insulating layer 123, and at each interface. For example, at the oxide insulating layer 121, the oxide semiconductor layer 122, the oxide insulating layer 123, and at each interface, the concentration of the alkali metal or alkaline earth metal obtained by secondary ion mass spectrometry is 1×10 atoms / cm or less, preferably 2×10 atoms / cm or less. Thereby, the transistor 10 can have electrical characteristics with a positive threshold voltage. <Regarding nitrogen concentration> In addition, if nitrogen is contained in the oxide insulating layer 121, the oxide semiconductor layer 122, the oxide insulating layer 123, and at each interface, electrons as carriers are generated, the carrier density increases, and an n-type region may be formed. As a result, a transistor using an oxide semiconductor layer containing nitrogen tends to have normally-on characteristics. Therefore, at the oxide insulating layer 121, the oxide semiconductor layer 122, the oxide insulating layer 123, and at each interface, it is preferable that nitrogen is reduced as much as possible. For example, at the oxide insulating layer 121, the oxide semiconductor layer 122, the oxide insulating layer 123, and at each interface, the nitrogen concentration obtained by SIMS is 1×10 18 atoms / cm 3 or more and 5×10 16 atoms / cm or less. 3 Thereby, the transistor 10 can have electrical characteristics with a positive threshold voltage.

[0131] In addition, if nitrogen is contained in the oxide insulating layer 121, the oxide semiconductor layer 122, the oxide insulating layer 123, and at each interface, electrons as carriers are generated, the carrier density increases, and an n-type region may be formed. As a result, a transistor using an oxide semiconductor layer containing nitrogen tends to have normally-on characteristics. Therefore, at the oxide insulating layer 121, the oxide semiconductor layer 122, the oxide insulating layer 123, and at each interface, it is preferable that nitrogen is reduced as much as possible. For example, at the oxide insulating layer 121, the oxide semiconductor layer 122, the oxide insulating layer 123, and at each interface, the nitrogen concentration obtained by SIMS is 1×10 atoms / cm or more and 5×10 atoms / cm or less. For example, at the oxide insulating layer 121, the oxide semiconductor layer 122, the oxide insulating layer 123, and at each interface, the nitrogen concentration obtained by SIMS is 1×10 atoms / cm or more and 5×10 15 atoms / cm 3 or less, preferably 1×10 19 atoms / cm3 Hereinafter, preferably 1×10 15 atoms / cm 3 or more and 5×10 18 atoms / cm 3 or less, more preferably 1×10 15 atoms / cm 3 or more and 1×10 18 atoms / cm 3 or less, even more preferably 1×10 15 atoms / cm 3 or more and 5×10 17 atoms / c m 3 or less. By doing so, the transistor 10 can have electrical characteristics in which the threshold voltage becomes a pulse.

[0132] However, this is not the case when the oxide semiconductor layer 122 has excess zinc. The excess zinc may form oxygen vacancies in the oxide semiconductor layer 122. Therefore, when there is excess zinc, having 0.001 to 3 atomic% of nitrogen in the oxide semiconductor layer 122 may inactivate the oxygen vacancies caused by the excess zinc. Therefore, the nitrogen can eliminate the variation in the characteristics of the transistor and improve the reliability.

[0133] <Regarding carrier density> By reducing the impurities in the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123, the carrier density of the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 can be reduced. For this reason, the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 have a carrier density of 1×10 / cm 15 or less, preferably 3 ​ Or 1 x 10 13 / cm 3 Less than 8 × 10, more preferably 11 / cm 3 Less than, better Preferably 1 x 10 11 / cm 3 less than 1 x 10 10 / cm 3 is less than 1×10 -9 / cm 3 That's all.

[0134] From the above, the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 are By using oxides with low impurity concentrations and low defect level densities, even better electrical properties can be achieved. Here, a transistor with low impurity concentration and defect level can be fabricated. Low oxygen density (low oxygen vacancies) is called high purity intrinsic or substantially high purity intrinsic. The oxide, which is highly pure intrinsic or substantially highly pure intrinsic, has a low carrier generation source. Therefore, the carrier density can be reduced in the oxide. The transistor in which the region is formed tends to have electrical characteristics in which the threshold voltage is positive. In addition, the oxide, which is highly pure intrinsic or substantially highly pure intrinsic, has a low defect level density. In addition, the trap level density may also be lower. The oxide has a significantly small off-state current and a low voltage between the source and drain electrodes (drain The off-state current was measured by the semiconductor parameter analyzer in the range of 1V to 10V. below the measurement limit of the -13 A or less can be obtained. Therefore, a transistor in which a channel region is formed in the oxide has small fluctuations in electrical characteristics. It can be a highly reliable transistor.

[0135] In addition, the off-current of a transistor using the oxide highly purified as described above in the channel formation region is extremely small. For example, when the voltage between the source and the drain is about 0.1 V, 5 V, or 10 V, the off-current normalized by the channel width of the transistor can be reduced to several yA / μm to several zA / μm.

[0136] In addition, the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 may have, for example, a non-single crystal structure. The non-single crystal structure includes, for example, CAAC-OS, polycrystalline structure, microcrystalline structure, or amorphous structure, which will be described later. In the non-single crystal structure, the amorphous structure has the highest density of defect levels, and CAAC-OS has the lowest density of defect levels.

[0137] In addition, the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 may have, for example, a microcrystalline structure. The microcrystalline oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 may contain, for example, microcrystals with a size of 1 nm or more and less than 10 nm in the film. Or, the microcrystalline oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 have, for example, a mixed-phase structure having crystal portions of 1 nm or more and less than 10 nm in an amorphous phase.

[0138] The oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 may have, for example, an amorphous structure. The amorphous oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 have, for example, a disordered atomic arrangement and no crystal component. Or, The oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 have , for example, a perfect amorphous structure and have no crystal part.

[0139] Also, the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 may be a mixed film having regions of two or more structures of CA AC-OS, a microcrystalline structure, and an amorphous structure. As the mixed film, for example, there is a single-layer structure having an amorphous structure region, a microcrystalline structure region, and a CAAC -OS region. Or, as the mixed film, for example, there is a laminated structure of an amorphous structure region, a microcrystalline structure region, and a CAAC-OS region.

[0140] Note that the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 may have, for example, a single crystal structure.

[0141] Also, the oxide insulating layer 121 and the oxide insulating layer 123 function as barrier films for suppressing the formation of levels due to impurities caused by the constituent elements of the insulating layer 110 and the gate insulating layer 150 from mixing into the oxide semiconductor layer 122. For example, when an insulating film containing silicon is used as the insulating layer 110 or the gate insulating layer 150,

[0142] silicon in the gate insulating layer 150 or carbon that may be mixed into the insulating layer 110 and the gate insulating layer 150 may be mixed into the oxide insulating layer 121 or the oxide insulating layer 123 from the interface to about several nm. When impurities such as silicon and carbon enter the oxide semiconductor layer 122 they may form impurity levels, and the impurity levels may become donors to generate electrons and cause n-type conversion. to occur.

[0143] However, if the film thicknesses of the oxide insulating layer 121 and the oxide insulating layer 123 are thicker than several nanometers, since impurities such as silicon and carbon that have mixed in do not reach the oxide semiconductor layer 122, the influence of impurity levels is reduced.

[0144] Therefore, by providing the oxide insulating layer 121 and the oxide insulating layer 123, variations in the electrical characteristics (such as threshold voltage) of the transistor can be reduced.

[0145] Accordingly, by forming the oxide into a stacked structure of the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123, a channel can be formed in the oxide semiconductor layer 122, and a transistor having a high field-effect mobility and stable electrical characteristics can be formed.

[0146] Note that the oxide does not necessarily have to be three layers including the oxide insulating layer, and may have a single-layer, two-layer, four-layer structure, or even a structure of five or more layers. In the case of a single layer, a layer corresponding to the oxide semiconductor layer 122 shown in this embodiment may be used.

[0147] <Band diagram> Here, the band diagram of a transistor according to an aspect of the present invention will be described with reference to FIGS. 2(A) and 2(B). The band diagram shown in FIG. 2(B) shows the energy level (Ec) at the lower end of the conduction band and the energy level at the upper end of the valence band (Ev) for the insulating layer 110, the oxide insulating layer 121, the oxide semiconductor layer 122, the oxide insulating layer 123, and the gate insulating layer 15 0 for ease of understanding. (Ev).

[0148] As shown in FIG. 2(B), for the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 1 In 23, the energy level at the lower end of the conduction band changes continuously. This is because the elements constituting the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 are common, and it can also be understood from the fact that oxygen diffuses easily among them. Therefore, although the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 are a laminate of films with different compositions, it can be said that they are physically continuous.

[0149] The oxide semiconductor film laminated with a common main component is fabricated not simply by laminating each layer but by making a continuous joint (here, in particular, a U-shaped well structure where the energy level at the lower end of the conduction band changes continuously between layers). That is, a laminated structure is formed so that there are no impurities that form defect energy levels such as trap centers or recombination centers at the interfaces of each layer. If impurities are mixed between the layers of the laminated multilayer film, the continuity of the energy band is lost, and carriers are trapped or recombined at the interface and disappear.

[0150] Note that Ec of the oxide insulating layer 121 and the oxide insulating layer 123 is shown for the case where they are the same, but they may be different from each other.

[0151] From FIG. 2(B), it can be seen that the oxide semiconductor layer 122 becomes a well, and in the transistor 10, a channel is formed in the oxide semiconductor layer 122. Note that a channel with a U-shaped well structure in which the energy at the lower end of the conduction band changes continuously with the oxide semiconductor layer 122 as the bottom can also be called an embedded channel.

[0152] ​​​Note that in the vicinity of the interfaces between the oxide insulating layer 121 and the oxide insulating layer 123 and an insulating film such as a silicon oxide film trap levels may be formed due to impurities and defects. The presence of the oxide insulating layer 1 21 and the oxide insulating layer 123 can separate the oxide semiconductor layer 122 from the trap levels. However, when the energy difference between the Ec of the oxide insulating layer 121 or the oxide insulating layer 12 3 and the Ec of the oxide semiconductor layer 122 is small, electrons in the oxide semiconductor layer 122 may reach the trap levels across the energy difference. When electrons that become negative charges are trapped at the trap levels, negative fixed charges are generated at the insulating film interface, and the threshold voltage of the transistor shifts in the positive direction. Furthermore, there is a concern that traps may not be fixed and electrical characteristics may fluctuate in the long-term storage test of the transistor.

[0153] Therefore, in order to reduce fluctuations in the threshold voltage of the transistor, an energy difference needs to be provided between the Ec of the oxide insulating layer 121 and the oxide insulating layer 123 and the oxide semiconductor layer 122. Each such energy difference is preferably 0.1 eV or more, and more preferably 0. 2 eV or more.

[0154] Note that the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 preferably contain crystal portions. In particular, by using crystals oriented along the c-axis, stable electrical characteristics can be imparted to the transistor.

[0155] Also, in the band diagram as shown in Fig. 2(B), without providing the oxide insulating layer 123 and between the oxide semiconductor layer 122 and the gate insulating layer 150, an In-Ga oxide (for example, with an atomic ratio of I An In-Ga oxide with n:Ga = 7:93) may be provided, or gallium oxide or the like may be provided. Further, an In-Ga oxide may be provided between the oxide insulating layer 123 and the gate insulating layer 150 in the state where the oxide insulating layer 123 is present, or gallium oxide or the like may be provided .

[0156] The oxide semiconductor layer 122 uses an oxide having a larger electron affinity than the oxide insulating layer 121 and the oxide insulating layer 123. For example, as the oxide semiconductor layer 122, an oxide having an electron affinity 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, more preferably 0.2 eV or more and 0.4 eV or less larger than that of the oxide insulating layer 12 1 and the oxide insulating layer 123 can be used.

[0157] The transistor shown in this embodiment has an oxide insulating layer 121 and an oxide insulating layer 123 containing one or more metal elements constituting the oxide semiconductor layer 122. Therefore, it is difficult to form interface levels at the interface between the oxide insulating layer 121 and the oxide semiconductor layer 122 and at the interface between the oxide insulating layer 123 and the oxide semiconductor layer 122. Thus, by providing the oxide insulating layer 121 and the oxide insulating layer 123, variations and fluctuations in electrical characteristics such as the threshold voltage of the transistor can be reduced.

[0158] 《Gate Insulating Layer 150》 The gate insulating layer 150 contains oxygen (O), nitrogen (N), fluorine (F), aluminum (Al ), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge ), yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd) can have hafnium (Hf), tantalum (Ta), titanium (Ti), etc. For example, aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride oxide (SiNxOy) , silicon nitride (SiNx), gallium oxide (GaOx), germanium oxide (GeOx ), yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (La Ox), neodymium oxide (NdOx), hafnium oxide (HfOx) and tantalum oxide ( TaOx) can have one or more kinds. Further, the gate insulating layer 150 may be a laminate of the above materials Note that the gate insulating layer 150 may contain lanthanum (La), nitrogen, zirconium (Zr), etc. as impurities.

[0159] It is desirable that the gate insulating layer 150 has a lot of oxygen. The oxygen contained in the gate insulating layer 150 reaches the oxide semiconductor layer 12 2 through the oxide insulating layer 123 by performing heat treatment. Thereby, the oxygen vacancies (Vo) existing in the oxide semiconductor layer 122 can be reduced .

[0160] Further, an example of the laminated structure of the gate insulating layer 150 will be described. The gate insulating layer 150 has, for example, oxygen, nitrogen, silicon, hafnium, etc. Specifically, it preferably contains hafnium oxide and silicon oxide or silicon oxynitride.

[0161] Hafnium oxide has a higher relative dielectric constant than silicon oxide and silicon oxynitride. Therefore compared with the case of using silicon oxide, the film thickness of the gate insulating layer 150 can be increased, so , the leakage current due to the tunnel current can be reduced. That is, a transistor with a small off-current can be realized. Furthermore, hafnium oxide having a crystal structure has a higher relative dielectric constant than hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor with a small off-current, it is preferable to use hafnium oxide having a crystal structure. Examples of the crystal structure include monoclinic and cubic systems. However, one aspect of the present invention is not limited thereto. Here, the surface to be formed of hafnium oxide having a crystal structure may have interface levels caused by defects. The interface levels may function as trap centers. Therefore, when hafnium oxide is disposed close to the channel region of the transistor, the electrical characteristics of the transistor may deteriorate due to the interface levels. Therefore, in order to reduce the influence of the interface levels, it may be preferable to dispose another film between the channel region of the transistor and hafnium oxide to separate them from each other. This film has a buffering function. The film having a buffering function may be a film included in the gate insulating layer 150, or may be a film included in the oxide semiconductor film. That is, as the film having a buffering function, silicon oxide, silicon oxynitride, an oxide semiconductor, or the like can be used. Note that, for the film having a buffering function, for example, a semiconductor or insulator having a larger energy gap than the semiconductor that becomes the channel region is used. Alternatively, for the film having a buffering function, for example, a semiconductor or insulator having a smaller electron affinity than the semiconductor that becomes the channel region is used. Alternatively, for the film having a buffering function, for example, a semiconductor having a larger ionization energy than the semiconductor that becomes the channel region is used. However, one aspect of the present invention is not limited thereto. Here, the surface to be formed of hafnium oxide having a crystal structure may have interface levels caused by defects. The interface levels may function as trap centers. Therefore, when hafnium oxide is disposed close to the channel region of the transistor, the electrical characteristics of the transistor may deteriorate due to the interface levels. Therefore, in order to reduce the influence of the interface levels, it may be preferable to dispose another film between the channel region of the transistor and hafnium oxide to separate them from each other. This film has a buffering function. The film having a buffering function may be a film included in the gate insulating layer 150, or may be a film included in the oxide semiconductor film. That is, as the film having a buffering function, silicon oxide, silicon oxynitride, an oxide semiconductor, or the like can be used. Note that, for the film having a buffering function, for example, a semiconductor or insulator having a larger energy gap than the semiconductor that becomes the channel region is used. Alternatively, for the film having a buffering function, for example, a semiconductor or insulator having a smaller electron affinity than the semiconductor that becomes the channel region is used. Alternatively, for the film having a buffering function, for example, a semiconductor having a larger ionization energy than the semiconductor that becomes the channel region is used. However, one aspect of the present invention is not limited thereto. However, one aspect of the present invention is not limited thereto.

[0162] Here, the surface to be formed of hafnium oxide having a crystal structure may have interface levels caused by defects. The interface levels may function as trap centers. Therefore, when hafnium oxide is disposed close to the channel region of the transistor, the electrical characteristics of the transistor may deteriorate due to the interface levels. Therefore, in order to reduce the influence of the interface levels, it may be preferable to dispose another film between the channel region of the transistor and hafnium oxide to separate them from each other. This film has a buffering function. The film having a buffering function may be a film included in the gate insulating layer 150, or may be a film included in the oxide semiconductor film. That is, as the film having a buffering function, silicon oxide, silicon oxynitride, an oxide semiconductor, or the like can be used. Note that, for the film having a buffering function, for example, a semiconductor or insulator having a larger energy gap than the semiconductor that becomes the channel region is used. Alternatively, for the film having a buffering function, for example, a semiconductor or insulator having a smaller electron affinity than the semiconductor that becomes the channel region is used. Alternatively, for the film having a buffering function, for example, a semiconductor having a larger ionization energy than the semiconductor that becomes the channel region is used. However, one aspect of the present invention is not limited thereto. Here, the surface to be formed of hafnium oxide having a crystal structure may have interface levels caused by defects. The interface levels may function as trap centers. Therefore, when hafnium oxide is disposed close to the channel region of the transistor, the electrical characteristics of the transistor may deteriorate due to the interface levels. Therefore, in order to reduce the influence of the interface levels, it may be preferable to dispose another film between the channel region of the transistor and hafnium oxide to separate them from each other. This film has a buffering function. The film having a buffering function may be a film included in the gate insulating layer 150, or may be a film included in the oxide semiconductor film. That is, as the film having a buffering function, silicon oxide, silicon oxynitride, an oxide semiconductor, or the like can be used. Note that, for the film having a buffering function, for example, a semiconductor or insulator having a larger energy gap than the semiconductor that becomes the channel region is used. Alternatively, for the film having a buffering function, for example, a semiconductor or insulator having a smaller electron affinity than the semiconductor that becomes the channel region is used. Alternatively, for the film having a buffering function, for example, a semiconductor having a larger ionization energy than the semiconductor that becomes the channel region is used. However, one aspect of the present invention is not limited thereto. Here, the surface to be formed of hafnium oxide having a crystal structure may have interface levels caused by defects. The interface levels may function as trap centers. Therefore, when hafnium oxide is disposed close to the channel region of the transistor, the electrical characteristics of the transistor may deteriorate due to the interface levels. Therefore, in order to reduce the influence of the interface levels, it may be preferable to dispose another film between the channel region of the transistor and hafnium oxide to separate them from each other. This film has a buffering function. The film having a buffering function may be a film included in the gate insulating layer 150, or may be a film included in the oxide semiconductor film. That is, as the film having a buffering function, silicon oxide, silicon oxynitride, an oxide semiconductor, or the like can be used. Note that, for the film having a buffering function, for example, a semiconductor or insulator having a larger energy gap than the semiconductor that becomes the channel region is used. Alternatively, for the film having a buffering function, for example, a semiconductor or insulator having a smaller electron affinity than the semiconductor that becomes the channel region is used. Alternatively, for the film having a buffering function, for example, a semiconductor having a larger ionization energy than the semiconductor that becomes the channel region is used. However, one aspect of the present invention is not limited thereto. Here, the surface to be formed of hafnium oxide having a crystal structure may have interface levels caused by defects. The interface levels may function as trap centers. Therefore, when hafnium oxide is disposed close to the channel region of the transistor, the electrical characteristics of the transistor may deteriorate due to the interface levels. Therefore, in order to reduce the influence of the interface levels, it may be preferable to dispose another film between the channel region of the transistor and hafnium oxide to separate them from each other. This film has a buffering function. The film having a buffering function may be a film included in the gate insulating layer 150, or may be a film included in the oxide semiconductor film. That is, as the film having a buffering function, silicon oxide, silicon oxynitride, an oxide semiconductor, or the like can be used. Note that, for the film having a buffering function, for example, a semiconductor or insulator having a larger energy gap than the semiconductor that becomes the channel region is used. Alternatively, for the film having a buffering function, for example, a semiconductor or insulator having a smaller electron affinity than the semiconductor that becomes the channel region is used. Alternatively, for the film having a buffering function, for example, a semiconductor having a larger ionization energy than the semiconductor that becomes the channel region is used. However, one aspect of the present invention is not limited thereto. Here, the surface to be formed of hafnium oxide having a crystal structure may have interface levels caused by defects. The interface levels may function as trap centers. Therefore, when hafnium oxide is disposed close to the channel region of the transistor, the electrical characteristics of the transistor may deteriorate due to the interface levels. Therefore, in order to reduce the influence of the interface levels, it may be preferable to dispose another film between the channel region of the transistor and hafnium oxide to separate them from each other. This film has a buffering function. The film having a buffering function may be a film included in the gate insulating layer 150, or may be a film included in the oxide semiconductor film. That is, as the film having a buffering function, silicon oxide, silicon oxynitride, an oxide semiconductor, or the like can be used. Note that, for the film having a buffering function, for example, a semiconductor or insulator having a larger energy gap than the semiconductor that becomes the channel region is used. Alternatively, for the film having a buffering function, for example, a semiconductor or insulator having a smaller electron affinity than the semiconductor that becomes the channel region is used. Alternatively, for the film having a buffering function, for example, a semiconductor having a larger ionization energy than the semiconductor that becomes the channel region is used. However, one aspect of the present invention is not limited thereto. Here, the surface to be formed of hafnium oxide having a crystal structure may have interface levels caused by defects. The interface levels may function as trap centers. Therefore, when hafnium oxide is disposed close to the channel region of the transistor, the electrical characteristics of the transistor may deteriorate due to the interface levels. Therefore, in order to reduce the influence of the interface levels, it may be preferable to dispose another film between the channel region of the transistor and hafnium oxide to separate them from each other. This film has a buffering function. The film having a buffering function may be a film included in the gate insulating layer 150, or may be a film included in the oxide semiconductor film. That is, as the film having a buffering function, silicon oxide, silicon oxynitride, an oxide semiconductor, or the like can be used. Note that, for the film having a buffering function, for example, a semiconductor or insulator having a larger energy gap than the semiconductor that becomes the channel region is used. Alternatively, for the film having a buffering function, for example, a semiconductor or insulator having a smaller electron affinity than the semiconductor that becomes the channel region is used. Alternatively, for the film having a buffering function, for example, a semiconductor having a larger ionization energy than the semiconductor that becomes the channel region is used. However, one aspect of the present invention is not limited thereto. Here, the surface to be formed of hafnium oxide having a crystal structure may have interface levels caused by defects. The interface levels may function as trap centers. Therefore, when hafnium oxide is disposed close to the channel region of the transistor, the electrical characteristics of the transistor may deteriorate due to the interface levels. Therefore, in order to reduce the influence of the interface levels, it may be preferable to dispose another film between the channel region of the transistor and hafnium oxide to separate them from each other. This film has a buffering function. The film having a buffering function may be a film included in the gate insulating layer 150, or may be a film included in the oxide semiconductor film. That is, as the film having a buffering function, silicon oxide, silicon oxynitride, an oxide semiconductor, or the like can be used. Note that, for the film having a buffering function, for example, a semiconductor or insulator having a larger energy gap than the semiconductor that becomes the channel region is used. Alternatively, for the film having a buffering function, for example, a semiconductor or insulator having a smaller electron affinity than the semiconductor that becomes the channel region is used. Alternatively, for the film having a buffering function, for example, a semiconductor having a larger ionization energy than the semiconductor that becomes the channel region is used. A conductor or an insulator is used.

[0163] On the other hand, there is a case where the threshold voltage of the transistor can be controlled by trapping charges in the interface states (trap centers) on the surface to be formed of hafnium oxide having the above-described crystal structure. In order to stably store the charges, for example, an insulator having a larger energy gap than hafnium oxide may be disposed between the channel region and hafnium oxide. Alternatively, a semiconductor or an insulator having a smaller electron affinity than hafnium oxide may be disposed. Alternatively, a semiconductor or an insulator having a larger ionization energy than hafnium oxide may be disposed in the film having a buffer function. By using such an insulator, the release of the charges trapped in the interface states is less likely to occur, and the charges can be retained for a long period of time. Examples of such an insulator include silicon oxide and silicon oxynitride. In order to capture charges in the interface states in the gate insulating layer 150, electrons may be moved from the oxide semiconductor layer 122 toward the gate electrode layer 160. As a specific example, at a high temperature (for example, 125°C or higher and 450°C or lower, typically 150°C or higher and 300°C or lower), the potential of the gate electrode layer 160 is set to be higher than the potentials of the source electrode and the drain electrode for 1 second or longer, typically 1 minute or longer.

[0164] In the transistor in which a desired amount of electrons are captured in the interface states such as the gate insulating layer 150 in this way, the threshold voltage shifts to the positive side. By adjusting the voltage of the gate electrode layer 160 and the time for applying the voltage, the amount of electrons captured (the amount of variation in the threshold voltage) can be controlled. For example, at a high temperature ( for example, 125°C or higher and 450°C or lower, typically 150°C or higher and 300°C or lower), the potential of the gate electrode layer 160 is set to be higher than the potentials of the source electrode and the drain electrode for 1 second or longer, typically 1 minute or longer. should be maintained.

[0165] In the transistor in which a desired amount of electrons are captured in the interface states such as the gate insulating layer 150 in this way, the threshold voltage shifts to the positive side. By adjusting the voltage of the gate electrode layer 160 and the time for applying the voltage, the amount of electrons captured (the amount of variation in the threshold voltage) can be controlled. ​ This is possible. As long as charges can be captured, it does not matter if it is not within the gate insulating layer 150. A stacked film having a similar structure may be used for other insulating layers.

[0166] 《Gate electrode layer 160》 The gate electrode layer 160 can have a material such as, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), copper (Cu), yttrium (Y), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), silver (Ag), tantalum (Ta), tungsten (W), or silicon (Si). Further, the gate electrode layer 160 can be a stack. When it is a stack, it may be used in combination with a material containing nitrogen, such as a nitride of the above materials. r), cobalt (Co), nickel (Ni), copper (Cu), yttrium (Y), zirconium nium (Zr), molybdenum (Mo), ruthenium (Ru), silver (Ag), tantalum (T a) tungsten (W), or silicon (Si). Also, the gate electrode layer 160 can be laminated. When laminated, for example, it may be used in combination with a nitrogen-containing material such as a nitride of the above materials. In addition, the gate electrode layer 160 can be laminated. When laminated, for example, it may be used in combination with a nitrogen-containing material such as a nitride of the above materials. In addition, the gate electrode layer 160 can be laminated. When laminated, it may be used in combination with a nitrogen-containing material such as a nitride of the above materials.

[0167] 《Sidewall insulating layer 176》 The sidewall insulating layer 176 can have the same material as the gate insulating layer 150.

[0168] 《Insulating layer 180》 The insulating layer 180 can have the same material as the gate insulating layer 150.

[0169] Also, the insulating layer 180 may be a laminate. The insulating layer 180 preferably has more oxygen than the stoichiometric composition. Since the oxygen released from the insulating layer 180 can be diffused through the gate insulating layer 150 into the channel formation region of the oxide semiconductor layer 122, oxygen can fill the oxygen vacancies formed in the channel formation region. Therefore, stable electrical characteristics of the transistor can be obtained. The insulating layer 180 preferably has more oxygen than the stoichiometric composition. Since the oxygen released from the insulating layer 180 can be diffused through the gate insulating layer 150 into the channel formation region of the oxide semiconductor layer 122, oxygen can fill the oxygen vacancies formed in the channel formation region. Therefore, stable electrical characteristics of the transistor can be obtained. Since the oxygen released from the insulating layer 180 can be diffused through the gate insulating layer 150 into the channel formation region of the oxide semiconductor layer 122, oxygen can fill the oxygen vacancies formed in the channel formation region. Therefore, stable electrical characteristics of the transistor can be obtained. Since the oxygen released from the insulating layer 180 can be diffused through the gate insulating layer 150 into the channel formation region of the oxide semiconductor layer 122, oxygen can fill the oxygen vacancies formed in the channel formation region. Thus, stable electrical characteristics of the transistor can be obtained. Therefore, stable electrical characteristics of the transistor can be obtained.

[0170] 《Conductive layer 190》 The conductive layer 190 can use the same material as the gate electrode layer 160.

[0171] 《Conductive layer 195》 The conductive layer 195 can use the same material as the gate electrode layer 160.

[0172] <Method for manufacturing a transistor> Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. 5 to 15. Note that parts overlapping with those described in the configuration of the transistor are omitted. In addition, the direction A1 - A2 shown in FIGS. 5 to 15 may be referred to as the channel length direction shown in FIGS. 1(A) and 1(B). Further, the direction A3 - A4 shown in FIGS. 5 to 15 may be referred to as the channel width direction shown in FIGS. 1(A) and 1(C).

[0173] In the present embodiment, each layer (insulating layer, oxide semiconductor layer, conductive layer, etc.) constituting the transistor can be formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulse laser deposition (PLD) method. Alternatively, it can be formed by a coating method or a printing method. As the film formation method, a sputtering method and a plasma CVD method are representative, but a thermal CVD method may also be used. As an example of the thermal CVD method, a metal organic chemical vapor deposition (MOCVD) method or an atomic layer deposition (ALD) method may be used. Also, in the sputtering method, the embedding property can be improved by combining the long throw method and the collimate method. ​​​​​​​​​​​

[0174] <Thermal CVD method> Since the thermal CVD method is a film formation method that does not use plasma, it has the advantage that defects are not generated due to plasma damage. It has the advantage that it is not generated.

[0175] Also, in the thermal CVD method, a source gas and an oxidizing agent are simultaneously fed into the chamber, and the inside of the chamber is under atmospheric pressure or reduced pressure, and reacted near or on the substrate to deposit on the substrate, thereby film formation may be performed.

[0176] Also, thermal CVD methods such as the MOCVD method and the ALD method can form various films such as the metal films, semiconductor films, and inorganic insulating films described so far. For example, when forming an In-Ga-Zn-O film trimethylindium, trimethylgallium, and dimethylzinc can be used. The chemical formula of trimethylindium is In(CH3)3 . Also, the chemical formula of trimethylgallium is Ga(CH3)3. Also, dimethylzinc has the chemical formula Zn(CH3)2. Also, it is not limited to these combinations, and triethylgallium (chemical formula Ga(C2H5)3) can be used instead of trimethylgallium and diethylzinc (chemical formula Zn(C2H5)2) can be used instead of dimethylzinc . It can also be done.

[0177] <ALD method> In a film formation apparatus using a conventional CVD method, one or more source gases (precursors) for the reaction are simultaneously supplied to the chamber during film formation. In a film formation apparatus using the ALD method, precursors for the reaction are sequentially introduced into the chamber, and film formation is performed by repeating the order of gas introduction. For example, by switching each switching valve (also called a high-speed valve) the precursors for the reaction are sequentially introduced into the chamber, and the film formation is performed by repeating the order of gas introduction. For example, by switching each switching valve (also called a high-speed valve) it is possible to perform film formation by repeating the order of gas introduction. For example, by switching each switching valve (also called a high-speed valve) Instead, two or more types of precursors are sequentially supplied to the chamber, and an inert gas (such as argon or nitrogen) is introduced after the first precursor so that the plurality of types of precursors are not mixed, and then the second precursor is introduced. Alternatively, after discharging the first precursor by evacuation, the second precursor can be introduced. Instead, two or more types of precursors are sequentially supplied to the chamber, and an inert gas (such as argon or nitrogen) is introduced after the first precursor so that the plurality of types of precursors are not mixed, and then the second precursor is introduced. Alternatively, after discharging the first precursor by evacuation, the second precursor can be introduced. Instead, two or more types of precursors are sequentially supplied to the chamber, and an inert gas (such as argon or nitrogen) is introduced after the first precursor so that the plurality of types of precursors are not mixed, and then the second precursor is introduced. Alternatively, after discharging the first precursor by evacuation, the second precursor can be introduced. Instead, two or more types of precursors are sequentially supplied to the chamber, and an inert gas (such as argon or nitrogen) is introduced after the first precursor so that the plurality of types of precursors are not mixed, and then the second precursor is introduced. Alternatively, after discharging the first precursor by evacuation, the second precursor can be introduced.

[0178] Figures 3(A), 3(B), 3(C), and 3(D) show the film formation process of the ALD method. The first precursor 601 is adsorbed on the surface of the substrate (see Figure 3(A)), and the first single layer is formed (see Figure 3(B)). At this time, metal atoms and the like contained in the precursor can bind to the hydroxyl groups present on the substrate surface. The metal atoms may be bonded with alkyl groups such as methyl groups and ethyl groups. After evacuating the first precursor 601, it reacts with the second precursor 602 introduced (see Figure 3(C)), and the second single layer is laminated on the first single layer to form a thin film (see Figure 3(D)). For example, when the second precursor contains an oxidizing agent, a chemical reaction occurs between the metal atoms present in the first precursor or the alkyl groups bonded to the metal atoms and the oxidizing agent, and an oxide film can be formed. Figures 3(A), 3(B), 3(C), and 3(D) show the film formation process of the ALD method. The first precursor 601 is adsorbed on the surface of the substrate (see Figure 3(A)), and the first single layer is formed (see Figure 3(B)). At this time, metal atoms and the like contained in the precursor can bind to the hydroxyl groups present on the substrate surface. The metal atoms may be bonded with alkyl groups such as methyl groups and ethyl groups. After evacuating the first precursor 601, it reacts with the second precursor 602 introduced (see Figure 3(C)), and the second single layer is laminated on the first single layer to form a thin film (see Figure 3(D)). For example, when the second precursor contains an oxidizing agent, a chemical reaction occurs between the metal atoms present in the first precursor or the alkyl groups bonded to the metal atoms and the oxidizing agent, and an oxide film can be formed. Figures 3(A), 3(B), 3(C), and 3(D) show the film formation process of the ALD method. The first precursor 601 is adsorbed on the surface of the substrate (see Figure 3(A)), and the first single layer is formed (see Figure 3(B)). At this time, metal atoms and the like contained in the precursor can bind to the hydroxyl groups present on the substrate surface. The metal atoms may be bonded with alkyl groups such as methyl groups and ethyl groups. After evacuating the first precursor 601, it reacts with the second precursor 602 introduced (see Figure 3(C)), and the second single layer is laminated on the first single layer to form a thin film (see Figure 3(D)). For example, when the second precursor contains an oxidizing agent, a chemical reaction occurs between the metal atoms present in the first precursor or the alkyl groups bonded to the metal atoms and the oxidizing agent, and an oxide film can be formed. Figures 3(A), 3(B), 3(C), and 3(D) show the film formation process of the ALD method. The first precursor 601 is adsorbed on the surface of the substrate (see Figure 3(A)), and the first single layer is formed (see Figure 3(B)). At this time, metal atoms and the like contained in the precursor can bind to the hydroxyl groups present on the substrate surface. The metal atoms may be bonded with alkyl groups such as methyl groups and ethyl groups. After evacuating the first precursor 601, it reacts with the second precursor 602 introduced (see Figure 3(C)), and the second single layer is laminated on the first single layer to form a thin film (see Figure 3(D)). For example, when the second precursor contains an oxidizing agent, a chemical reaction occurs between the metal atoms present in the first precursor or the alkyl groups bonded to the metal atoms and the oxidizing agent, and an oxide film can be formed. Figures 3(A), 3(B), 3(C), and 3(D) show the film formation process of the ALD method. The first precursor 601 is adsorbed on the surface of the substrate (see Figure 3(A)), and the first single layer is formed (see Figure 3(B)). At this time, metal atoms and the like contained in the precursor can bind to the hydroxyl groups present on the substrate surface. The metal atoms may be bonded with alkyl groups such as methyl groups and ethyl groups. After evacuating the first precursor 601, it reacts with the second precursor 602 introduced (see Figure 3(C)), and the second single layer is laminated on the first single layer to form a thin film (see Figure 3(D)). For example, when the second precursor contains an oxidizing agent, a chemical reaction occurs between the metal atoms present in the first precursor or the alkyl groups bonded to the metal atoms and the oxidizing agent, and an oxide film can be formed. Figures 3(A), 3(B), 3(C), and 3(D) show the film formation process of the ALD method. The first precursor 601 is adsorbed on the surface of the substrate (see Figure 3(A)), and the first single layer is formed (see Figure 3(B)). At this time, metal atoms and the like contained in the precursor can bind to the hydroxyl groups present on the substrate surface. The metal atoms may be bonded with alkyl groups such as methyl groups and ethyl groups. After evacuating the first precursor 601, it reacts with the second precursor 602 introduced (see Figure 3(C)), and the second single layer is laminated on the first single layer to form a thin film (see Figure 3(D)). For example, when the second precursor contains an oxidizing agent, a chemical reaction occurs between the metal atoms present in the first precursor or the alkyl groups bonded to the metal atoms and the oxidizing agent, and an oxide film can be formed. Figures 3(A), 3(B), 3(C), and 3(D) show the film formation process of the ALD method. The first precursor 601 is adsorbed on the surface of the substrate (see Figure 3(A)), and the first single layer is formed (see Figure 3(B)). At this time, metal atoms and the like contained in the precursor can bind to the hydroxyl groups present on the substrate surface. The metal atoms may be bonded with alkyl groups such as methyl groups and ethyl groups. After evacuating the first precursor 601, it reacts with the second precursor 602 introduced (see Figure 3(C)), and the second single layer is laminated on the first single layer to form a thin film (see Figure 3(D)). For example, when the second precursor contains an oxidizing agent, a chemical reaction occurs between the metal atoms present in the first precursor or the alkyl groups bonded to the metal atoms and the oxidizing agent, and an oxide film can be formed. Figures 3(A), 3(B), 3(C), and 3(D) show the film formation process of the ALD method. The first precursor 601 is adsorbed on the surface of the substrate (see Figure 3(A)), and the first single layer is formed (see Figure 3(B)). At this time, metal atoms and the like contained in the precursor can bind to the hydroxyl groups present on the substrate surface. The metal atoms may be bonded with alkyl groups such as methyl groups and ethyl groups. After evacuating the first precursor 601, it reacts with the second precursor 602 introduced (see Figure 3(C)), and the second single layer is laminated on the first single layer to form a thin film (see Figure 3(D)). For example, when the second precursor contains an oxidizing agent, a chemical reaction occurs between the metal atoms present in the first precursor or the alkyl groups bonded to the metal atoms and the oxidizing agent, and an oxide film can be formed. Figures 3(A), 3(B), 3(C), and 3(D) show the film formation process of the ALD method. The first precursor 601 is adsorbed on the surface of the substrate (see Figure 3(A)), and the first single layer is formed (see Figure 3(B)). At this time, metal atoms and the like contained in the precursor can bind to the hydroxyl groups present on the substrate surface. The metal atoms may be bonded with alkyl groups such as methyl groups and ethyl groups. After evacuating the first precursor 601, it reacts with the second precursor 602 introduced (see Figure 3(C)), and the second single layer is laminated on the first single layer to form a thin film (see Figure 3(D)). For example, when the second precursor contains an oxidizing agent, a chemical reaction occurs between the metal atoms present in the first precursor or the alkyl groups bonded to the metal atoms and the oxidizing agent, and an oxide film can be formed.

[0179] The ALD method is a film formation method based on surface chemical reactions. The precursor is adsorbed on the surface to be coated, and a self-limiting mechanism acts to form a single layer. For example, a precursor such as trimethylaluminum reacts with the hydroxyl groups (OH groups) present on the surface to be coated. At this time, only a surface reaction due to heat occurs, so that the precursor can come into contact with the surface to be coated, and metal atoms and the like in the precursor can be adsorbed on the surface to be coated through thermal energy. Also, the precursor The ALD method is a film formation method based on surface chemical reactions. The precursor is adsorbed on the surface to be coated, and a self-limiting mechanism acts to form a single layer. For example, a precursor such as trimethylaluminum reacts with the hydroxyl groups (OH groups) present on the surface to be coated. At this time, only a surface reaction due to heat occurs, so that the precursor can come into contact with the surface to be coated, and metal atoms and the like in the precursor can be adsorbed on the surface to be coated through thermal energy. Also, the precursor The ALD method is a film formation method based on surface chemical reactions. The precursor is adsorbed on the surface to be coated, and a self-limiting mechanism acts to form a single layer. For example, a precursor such as trimethylaluminum reacts with the hydroxyl groups (OH groups) present on the surface to be coated. At this time, only a surface reaction due to heat occurs, so that the precursor can come into contact with the surface to be coated, and metal atoms and the like in the precursor can be adsorbed on the surface to be coated through thermal energy. Also, the precursor The ALD method is a film formation method based on surface chemical reactions. The precursor is adsorbed on the surface to be coated, and a self-limiting mechanism acts to form a single layer. For example, a precursor such as trimethylaluminum reacts with the hydroxyl groups (OH groups) present on the surface to be coated. At this time, only a surface reaction due to heat occurs, so that the precursor can come into contact with the surface to be coated, and metal atoms and the like in the precursor can be adsorbed on the surface to be coated through thermal energy. Also, the precursor The ALD method is a film formation method based on surface chemical reactions. The precursor is adsorbed on the surface to be coated, and a self-limiting mechanism acts to form a single layer. For example, a precursor such as trimethylaluminum reacts with the hydroxyl groups (OH groups) present on the surface to be coated. At this time, only a surface reaction due to heat occurs, so that the precursor can come into contact with the surface to be coated, and metal atoms and the like in the precursor can be adsorbed on the surface to be coated through thermal energy. Also, the precursor The precursor has a high vapor pressure, is thermally stable and does not self-decompose at the stage before film formation, and chemisorbs quickly onto the substrate. Also, since the precursor is introduced as a gas, if there is sufficient time for the precursors introduced alternately to diffuse, it is possible to form a film with good coverage even in a region having unevenness with a high aspect ratio.

[0180] In addition, in the ALD method, by controlling the gas introduction order and repeating a plurality of times until a desired thickness is obtained, it is possible to form a thin film with excellent step coverage. Since the thickness of the thin film can be adjusted by the number of repetitions, precise film thickness adjustment is possible. Also, by increasing the evacuation ability, the film formation rate can be increased, and the impurity concentration in the film can be further reduced.

[0181] In addition, the ALD method includes an ALD method using heat (thermal ALD method) and an ALD method using plasma (plasma ALD method). In the thermal ALD method, the reaction of the precursor is carried out using thermal energy, and in the plasma ALD method, the reaction of the precursor is carried out in a radical state.

[0182] By forming a film using the ALD method, an extremely thin film can be formed with high precision. Also, by forming a film using the ALD method, the surface coverage rate can be increased even for a surface having unevenness.

[0183] <Plasma ALD> In addition, by forming a film by the plasma ALD method, film formation at a lower temperature is possible compared to the ALD method using heat (thermal ALD method). The plasma ALD method can form a film without reducing the film formation rate even at, for example, 100 °C or lower. Also, in the plasma ALD method, N2 is used as the plasma gas. ​​​​​​​​​​​​ Since it can be radicalized by Rasma, it is possible to form not only oxides but also nitrides. It is possible.

[0184] Also, in the plasma ALD method, the oxidizing power of the oxidant can be enhanced. As a result, when film formation is carried out by ALD, the precursors remaining in the film or the organic components desorbed from the precursors can be reduced, and carbon, chlorine, hydrogen, etc. in the film can be reduced, and a film with a low impurity concentration can be obtained. It is possible to have a film with a low impurity concentration.

[0185] Also, when performing plasma ALD, when generating radical species, plasma can be generated in a state separated from the substrate, such as ICP (Inductively Coupled Plasma), and plasma damage to the substrate or the film on which the protective film is formed can be suppressed. It is also possible to generate plasma in a state separated from the substrate, such as ICP (Inductively Coupled Plasma), and suppress plasma damage to the substrate or the film on which the protective film is formed. It is possible to suppress plasma damage.

[0186] From the above, by using the plasma ALD method, compared with other film formation methods, the process temperature can be lowered, and the surface coverage rate can be increased, and the film can be formed. As a result, it is possible to suppress the intrusion of water and hydrogen from the outside. Therefore, the reliability of transistor characteristics can be improved. As a result, it is possible to suppress the intrusion of water and hydrogen from the outside. Therefore, the reliability of transistor characteristics can be improved. It is possible to improve the reliability of transistor characteristics.

[0187] <Description of the ALD apparatus> Fig. 4(A) shows an example of a film formation apparatus using the ALD method. The film formation apparatus using the ALD method includes a film formation chamber (chamber 1701), a raw material supply unit 1711a, a raw material supply unit 1711b, high-speed valves 1712a and 1712b which are flow controllers, a raw material inlet 1713 a, a raw material inlet 1713b, a raw material outlet 1714, and an exhaust device 1715. The chamber The raw material inlets 1713a and 1713b installed within number 1701 are each connected to the raw material supply units 1711a and 1711b via supply pipes and valves. The raw material outlet 1714 is connected to the exhaust device 1715 via an exhaust pipe, valves, and a pressure regulator.

[0188] Inside the chamber, there is a substrate holder 1716 equipped with a heater, and the substrate 1700 to be coated is placed on the substrate holder.

[0189] In the raw material supply units 1711a and 1711b, a precursor is formed from solid raw materials or liquid raw materials by means of a vaporizer, heating means, etc. Alternatively, the raw material supply units 1711a and 1711b may be configured to supply a gaseous precursor.

[0190] Also, although an example is shown where two raw material supply units 1711a and 1711b are provided, it is not particularly limited, and three or more may be provided. Further, the high-speed valves 1712a and 17 12b can be precisely controlled by time and are configured to supply either the precursor or the inert gas. The high-speed valves 1712a and 1712b are flow controllers for the precursor and can also be said to be flow controllers for the inert gas.

[0191] In the film-forming apparatus shown in Fig. 4(A), the substrate 1700 is carried onto the substrate holder 1716, and after the chamber 1701 is sealed, the substrate 1700 is heated by the heater of the substrate holder 1716 to a desired temperature (for example, 100 °C or higher or 150 °C or higher), and the supply of the precursor, exhaust by the exhaust device 1715, supply of the inert gas, and exhaust by the exhaust device 1715 are repeated to form a thin film on the substrate surface. ​

[0192] In the film forming apparatus shown in FIG. 4(A), the raw material supply units 1711a and 1711b are provided with By appropriately selecting the raw materials (volatile organometallic compounds, etc.), hafnium, aluminum, Oxides containing one or more elements selected from the group consisting of sulphur, tantalum, zirconium, etc. (complex oxides) Specifically, an insulating layer containing hafnium oxide can be formed. an insulating layer containing aluminum; an insulating layer containing aluminum oxide; an insulating layer containing aluminum silicate or an insulating layer containing aluminum silicate; In addition, the raw material supply unit 1711a and the raw material supply unit 1711b can form an insulating layer. By appropriately selecting the raw materials (volatile organometallic compounds, etc.) to be prepared, tungsten It is also possible to deposit thin films such as titanium layers, titanium nitride layers, and other metal layers. can.

[0193] For example, when a hafnium oxide layer is formed using a film forming apparatus that uses the ALD method, a solvent and liquids containing hafnium precursor compounds (hafnium alkoxides, tetrakisdimethyl A vaporized precursor of hafnium amide (such as TDMAH) and Two types of gases are used: oxidant and ozone (O3). The first precursor supplied from the raw material supply unit 1711b is TDMAH. The second precursor is ozone. The chemical formula of tetrakisdimethylamidohafnium is The material is Hf[N(CH3)2]4. Other materials include tetrakis(ethylmethyl) Nitrogen has the function of eliminating charge trapping levels. Therefore, since the precursor contains nitrogen, hafnium oxide with a low charge trapping level density can be formed. can be formed into a film.

[0194] For example, when forming an aluminum oxide layer by a film-forming apparatus using the ALD method, a precursor obtained by vaporizing a liquid (such as TMA) containing a solvent and an aluminum precursor compound and two types of gases, H2O as an oxidizing agent, are used. In this case, the first precursor supplied from the raw material supply unit 1711a is TMA, and the second precursor supplied from the raw material supply unit 1711b is H2O. Note that the chemical formula of trimethylaluminum is Al(CH3)3. Also, as other material liquids, there are tris(dimethylamide)aluminum, triisobutylaluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), and the like.

[0195] For example, when forming a silicon oxide film by a film-forming apparatus using ALD, hexachlorodisilane is adsorbed on the film-forming surface, chlorine contained in the adsorbate is removed, and radicals of an oxidizing gas (O2, nitrous oxide) are supplied to react with the adsorbate.

[0196] For example, when forming a tungsten film by a film-forming apparatus using ALD, WF6 gas and B2H6 gas are sequentially introduced repeatedly to form an initial tungsten film, and then WF6 gas and H2 gas are sequentially introduced repeatedly to form a tungsten film. Note that SiH^4 gas may be used instead of B2H6 gas.

[0197] For example, when forming an oxide semiconductor film, such as In-Ga-Zn-O, by a film-forming apparatus using ALD ​​​​​​​​​​​When forming a film, In(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form an In- O layer, and then Ga(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form a GaO layer, and then Zn(CH3)2 gas and O3 gas are sequentially and repeatedly introduced to form a ZnO layer. Note that the order of these layers is not limited to this example. Also, these gases can be mixed to form a mixed compound layer such as an In-Ga-O layer, an In-Zn-O layer, or a Ga-Zn-O layer . Note that instead of O3 gas, H2O gas obtained by bubbling pure water with an inert gas such as Ar can be used, but it is preferable to use O3 gas without H. Also, instead of In (CH3)3 gas, In(C2H5)3 gas can be used. Also, instead of Ga(CH (CH3)3 gas, Ga(C2H5)3 gas can be used. Also, instead of Zn(CH3)2 gas, Zn(C2H5)2 gas can be used.

[0198] 《Multi-chamber manufacturing apparatus》 Also, an example of a multi-chamber manufacturing apparatus having at least one film-forming apparatus shown in Fig. 4(A) is shown in Fig. 4(B).

[0199] The manufacturing apparatus shown in Fig. 4(B) can continuously form a laminated film without exposing it to the atmosphere, aiming to prevent the incorporation of impurities and improve throughput.

[0200] The manufacturing apparatus shown in Fig. 4(B) has at least a load chamber 1702, a transfer chamber 1720, a pretreatment chamber 1703, a chamber 1701 which is a film-forming chamber, and an unload chamber  1706. Note that the chambers of the manufacturing apparatus (including the load chamber, processing chamber, transfer chamber, film-forming chamber, unload chamber, etc.) are filled with an inert gas (such as nitrogen gas) with a controlled dew point to prevent the adhesion of moisture, etc. ​​​It is preferably stored, and desirably the reduced pressure is maintained.

[0201] In addition, chambers 1704 and 1705 may be film forming apparatuses using the same ALD method as chamber 1701, or may be film forming apparatuses using the plasma CVD method. Further, it may be a film forming apparatus using the sputtering method, or a film forming apparatus using the MOCVD method.

[0202] For example, a film forming apparatus using the plasma CVD method is used as chamber 1704, and a chamber using the MOCVD method is used as chamber 1705, and an example of forming a laminated film is shown below. Shown.

[0203] In FIG. 4(B), a top view of the transfer chamber 1720 shows an example of a hexagon, but depending on the number of layers of the laminated film, it may be a manufacturing apparatus connected to more chambers as a polygon with more sides. In addition, in FIG. 4(B), the top surface shape of the substrate is shown as a rectangle, but it is not particularly limited. Also, in FIG. 4(B), an example of a single wafer type is shown, but it may be a batch type film forming apparatus that forms a film on a plurality of substrates at once.

[0204] <Formation of Insulating Layer 110> First, an insulating layer 110 is formed on the substrate 100. The insulating layer 110 is formed by the plasma CVD method, thermal CVD method (MOCVD method, ALD method), or sputtering method, etc., which is preferable.

[0205] In forming the insulating layer 110, by using a material that does not contain hydrogen or has a hydrogen content of 1% or less, the generation of oxygen vacancies in the oxide semiconductor can be suppressed, and the operation of the transistor can be stabilized.

[0206] For example, as the insulating layer 110, silicon oxynitride with a thickness of 100 nm can be used by plasma CVD method.

[0207] Next, a first heat treatment may be performed to desorb water, hydrogen, etc. contained in the insulating layer 110. As a result, it is possible to reduce the concentration of water, hydrogen, etc. contained in the insulating layer 110, and by the heat treatment, the diffusion amount of water, hydrogen, etc. into the first oxide insulating film formed later can be reduced.

[0208] <Formation of the first oxide insulating film and the oxide semiconductor film> Subsequently, a first oxide insulating film that becomes the oxide insulating layer 121 and an oxide semiconductor film that becomes the oxide semiconductor layer 122 are formed on the insulating layer 110. The first oxide insulating film and the oxide semiconductor film can be formed by a sputtering method, MOCVD method, PLD method, etc., and it is more preferable to form them by using the sputtering method. As the sputtering method, an RF sputtering method, DC sputtering method, AC sputtering method, etc. can be used. In addition, in the sputtering method, by creating it by a facing target method (also called a facing electrode method, a gas phase sputtering ring method, a VDSP (Vapor Depotion Sputtering) method), plasma damage during film formation can be reduced.

[0209] For example, when forming an oxide semiconductor film by a sputtering method, each chamber in the sputtering apparatus is evacuated to a high vacuum (5×10 using an adsorption type vacuum exhaust pump such as a cryopump in order to remove water etc. that become impurities for the oxide semiconductor layer 122 as much as possible. ​​​​​​​​​​​-7 from Pa to 1×10 -4 Pa (it is possible up to this level), and the substrate to be formed into a film can be heated to 100°C or higher, preferably 400°C or higher. Or, it is preferable to prevent the gas containing carbon components, moisture, etc. from flowing back into the chamber from the exhaust system by combining a turbo molecular pump and a cold trap. Also, an exhaust system combining a turbo molecular pump and a cryopump may be used.

[0210] In addition, in order to obtain a high-purity intrinsic oxide semiconductor layer, it is desirable not only to evacuate the chamber to a high vacuum but also to purify the sputtering gas to a high purity. The oxygen gas or argon gas used as the sputtering gas should have a dew point of -40°C or lower, preferably -80°C or lower, more preferably -100°C or lower. By using a highly purified gas, it is possible to prevent moisture and the like from being incorporated into the oxide semiconductor film as much as possible.

[0211] As the sputtering gas, noble gas (typically argon), oxygen, or a mixed gas of noble gas and oxygen can be appropriately used.

[0212] When forming an oxide semiconductor film, for example, when using the sputtering method, the substrate temperature is set to 20°C or higher and 750°C or lower, preferably 150°C or higher and 450°C or lower, more preferably 200°C or higher and 420°C or lower. By forming an oxide semiconductor film, a CAAC-OS film can be formed.

[0213] For the first oxide insulating film, it is desirable to select a material with a smaller electron affinity than the oxide semiconductor film.

[0214] ​​​​​​In addition, in the case of forming the first oxide insulating film and the oxide semiconductor film, for example, by sputtering, by using a multi-chamber sputtering apparatus, the first oxide insulating film and the oxide semiconductor film can be continuously formed without being exposed to the atmosphere. In that case, it is possible to suppress the entry of unnecessary impurities and the like into the interface between the first oxide insulating film and the oxide semiconductor film, and it is possible to reduce the interface state density. As a result, the electrical characteristics of the transistor, particularly the electrical characteristics in the reliability test, can be stabilized. Moreover, when there is damage in the insulating layer 110, the presence of the oxide insulating layer 121 can keep the oxide semiconductor layer 122, which becomes the main conduction path, away from the damaged part, and as a result

[0215] the electrical characteristics of the transistor, particularly the electrical characteristics in the reliability test, can be stabilized. For example, as the first oxide insulating film, an oxide insulating film formed to a thickness of 20 nm by sputtering using In: Ga:Zn = 1:3:4 (atomic ratio) as a target can be used. Also, as the oxide semiconductor film, by sputtering, using In:Ga:Zn = 1:1:1 (atomic ratio) as a target, an oxide semiconductor film formed to a thickness of 15 nm can be used.

[0216] In addition, by performing a second heat treatment after forming the first oxide insulating film and the oxide semiconductor film, the oxygen deficiency amount of the first oxide insulating film and the oxide semiconductor film can be reduced. The temperature of the second heat treatment is 250°C or higher and lower than the substrate distortion point, preferably 300°C or higher and 650 °C or lower.

[0217]

[0218] °C or lower. ​​​°C or less, and more preferably 350°C or more and 550°C or less.

[0219] The second heat treatment is carried out using a rare gas such as helium, neon, argon, xenon, or krypton. It is preferable to carry out the reaction in an inert gas atmosphere containing nitrogen or an inert gas atmosphere. After heating in an oxygen atmosphere or dry air (dew point below -80°C, preferably -100 The heating may be carried out in an air atmosphere at a temperature of 120°C or less, preferably -120°C or less, or in a reduced pressure atmosphere. In addition to the dry air, inert gases and oxygen containing hydrogen, water, etc. It is preferable that the dew point is not more than -80°C, and preferably not more than -100°C. The treatment time is preferably from 3 minutes to 24 hours.

[0220] In the heat treatment, instead of an electric furnace, heat conduction from a heating element such as a resistance heating element or Alternatively, a device that heats the object to be treated by thermal radiation may be used. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas to perform heat treatment. For the gas, a noble gas such as argon or an inert gas such as nitrogen is used.

[0221] Note that the second heat treatment is performed to form an oxide insulating layer 121 and an oxide semiconductor layer 122, which will be described later. It may be performed after the etching.

[0222] For example, in a nitrogen atmosphere, after performing a heat treatment at 450°C for 1 hour, in an oxygen atmosphere it is possible to perform a heat treatment at 450°C for 1 hour.

[0223] By the above steps, reduction of oxygen deficiency in the first oxide insulating film and the oxide semiconductor film, and reduction of impurities such as hydrogen and water can be achieved. Further, the first oxide insulating film and the oxide semiconductor film with reduced localized level density can be formed.

[0224] Note that by high-density plasma irradiation using oxygen as a material, the same effect as the heat treatment can be obtained. The irradiation time is 1 minute or more and 3 hours or less, preferably 3 minutes or more and 2 hours or less, more preferably 5 minutes or more and 1 hour or less.

[0225] <Formation of the first conductive film> Next, a first conductive film used as a hard mask is formed on the oxide semiconductor film. The first conductive film can be formed using a sputtering method, a chemical vapor deposition (CVD) method (including a metalorganic chemical vapor deposition (MOC VD) method, a metal chemical vapor deposition method, an atomic layer deposition (ALD) method, or a plasma chemical vapor deposition (PECVD) method), an evaporation method, a pulsed laser deposition (PLD) method, etc. It can be formed.

[0226] The material of the first conductive film is copper (Cu), tungsten (W), molybdenum (Mo), gold (A u), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt ( Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (S a single body made of a low-resistance material such as r), or an alloy, or a compound mainly composed of these It is preferable to use a single layer or a laminate of a conductive film containing the same.

[0227] For example, a tungsten film with a thickness of 20 to 100 nm can be formed as the first conductive film by sputtering.

[0228] In this embodiment, the first conductive film is formed as a hard mask, but it is not limited thereto, and an insulating film may be formed.

[0229] <Formation of Oxide Insulating Layer 121 and Oxide Semiconductor Layer 122> Next, a resist mask is formed on the first conductive film by a lithography process. When forming the resist mask, the first conductive film is selectively etched using the resist mask to form a hard mask. Subsequently, after removing the resist on the hard mask, the oxide semiconductor film and the first oxide insulating film are selectively etched respectively to form the oxide semiconductor layer 122 and the oxide insulating layer 121 in an island shape (see Figure 5). As the etching method, a dry etching method can be used.

[0230] For example, using methane gas and argon gas as etching gases, the first oxide insulating film and the oxide semiconductor film are selectively etched using the resist mask and the hard mask, whereby the oxide insulating layer 121 and the oxide semiconductor layer 122 can be formed. After the formation of the oxide insulating layer 121 and the oxide semiconductor layer

[0231] 122, the first conductive film is removed. As a result, the edge roughness of the oxide semiconductor layer after etching can be reduced as compared with that of the resist mask. It can be reduced.

[0232] <Formation of Oxide Insulating Layer 123> Next, an oxide insulating layer 123 is formed on the oxide semiconductor layer 122 and the insulating layer 110 (see Fig. 6). The oxide insulating layer 123 can be formed in the same manner as the oxide semiconductor film and the first oxide insulating film. The material of the oxide insulating layer 123 can be selected so that its electron affinity is smaller than that of the oxide semiconductor film. Note that the oxide insulating layer 123 may be processed using a resist mask or the gate electrode layer 160 as a mask. For example, as the oxide insulating layer 123, an oxide semiconductor film formed by sputtering using a target with an atomic ratio of In:Ga:Zn = 1:3:2 and having a thickness of 5 nm can be used.

[0233]

[0234] It can be used. <Formation of Insulating Film 150a> Next, an insulating film 150a that will become the gate insulating layer 150 is formed on the oxide insulating layer 123. For the insulating film 150a, for example, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide can be used. Note that the insulating film 150a may be a laminate of the above materials. The insulating film 150a can be formed using a sputtering method, a CVD method (such as a plasma CVD method, an MOCVD method, an ALD method), an MBE method, or the like. Also, the insulating film 150a can be formed by appropriately using the same method as that for the insulating layer 110.

[0235] For example, 10 nm of silicon oxynitride is formed by plasma CVD as the insulating film 150a. This can be done.

[0236] <Formation of the conductive film 160a> Next, a conductive film 160a that will become the gate electrode layer 160 is formed on the insulating film 150a. (Refer to Fig. 7) As the conductive film 160a, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), copper (Cu), yttrium (Y), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), silver (Ag), tantalum (Ta), tungsten (W), or an alloy material with these as the main components can be used. The conductive film 160a can be formed by sputtering, CVD (such as plasma CVD, MOCVD, ALD, etc.), MBE, evaporation, plating, or the like. Also, as the conductive film 160a, a conductive film containing nitrogen may be used, or a laminate of the above conductive film and a conductive film containing nitrogen may be used. For example, as the conductive film 160a, a laminated structure in which 10 nm of titanium nitride is formed by ALD and 150 nm of tungsten is formed by metal CVD can be used. This can be done.

[0237] For example, as the conductive film 160a, a laminated structure in which 10 nm of titanium nitride is formed by ALD and 150 nm of tungsten is formed by metal CVD can be used. This can be done.

[0238] <Formation of the gate electrode layer 160 and the gate insulating layer 150> Next, a resist mask is formed on the conductive film 160a by a lithography process, and using the resist mask, the conductive film 160a is selectively etched to form the gate electrode layer 160. Subsequently, after removing the resist on the gate electrode layer 160, the gate electrode layer 160 is used as a mask. Use it to selectively etch the insulating film 150a to form the gate insulating layer 150. (See FIG. 8).

[0239] Note that the formation methods of the gate electrode layer 160 and the gate insulating layer 150 are not limited to the above methods. . For example, after providing the groove portion, it may be formed by embedding an insulating film and a conductive film.

[0240] <Formation of the low-resistance region 125> Next, using the gate electrode layer 160 as a mask, an ion addition process of ions 167 is performed on the second region and the third region of the oxide semiconductor layer 122 and the oxide insulating layer 123 (see FIG. 9). The materials to be added include hydrogen (H), fluorine (F), boron (B), phosphorus (P), helium (He) , neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), tungsten (W) , aluminum (Al), molybdenum (Mo), indium (In), etc. can be used. As the addition method, there are an ion doping method, an ion implantation method, a plasma immersion ion implantation method, a high-density plasma treatment method, etc. In miniaturization, by using the ion implantation method, the addition of impurities other than predetermined ions can be suppressed, so it is preferable. Also, the ion doping method and the plasma immersion ion implantation method are excellent in the case of processing a large area.

[0241] In the ion addition process of ions 167, it is desirable to adjust the acceleration voltage of the ions according to the ion species and the implantation depth. For example, it can be 1 kV or more and 100 kV or less, 3 kV or more and 60 kV or less. 12 2 17 2 Also, the dose amount of the ions is 1×10 ions / cm 12 2 0 17 ions / cm 2Less than 1 × 10 13 ions / cm 2 5x10 or more 1 6 ions / cm 2 It is desirable to do the following:

[0242] The ion addition treatment causes oxygen deficiency in the oxide semiconductor layer 122 and the oxide insulating layer 123. A loss is formed, and low resistance regions 125 are formed in the second and third regions (see FIG. 10). In the second region, the low resistance region 125 may be formed over the entire surface or only part of the surface. Note that the low-resistance region 125 is not necessarily formed in the oxide insulating layer 123.

[0243] In addition, by performing the third heat treatment after the ion addition treatment, the The damage to the film can be repaired. In addition, the heat treatment can It can be diffused up to the oxide insulating layer 121 .

[0244] <Formation of Sidewall Insulating Layer 176> Next, a first insulating film that will become the sidewall insulating layer 176 is formed on the gate electrode layer 160. The first insulating film is subjected to an etching process by a dry etching method, A sidewall insulating layer 176 having regions in contact with the side surfaces of the gate electrode layer 160 and the gate insulating layer 150 (See Figure 11).

[0245] <Formation of low resistance region 127> Next, a conductive film 168 is formed (see FIG. 12). The conductive film 168 is made of titanium (Ti). , Molybdenum (Mo), Tungsten (W), Chromium (Cr), Vanadium (V), Niobium Metals such as Nb, Ta, Zr, and Hf In addition to the materials, these nitride films can be used.

[0246] After forming the conductive film 168, it is desirable to perform a fourth heat treatment. By performing this heat treatment, the metal atoms can be diffused into the oxide semiconductor layer 122 and the oxide insulating layer 123, and a low-resistance region 127 can be formed (see FIG. 13). Also, by forming the low-resistance region 127, the resistance (e.g., sheet resistance) on the surfaces of the oxide semiconductor layer 122 and the oxide insulating layer 123 can be reduced.

[0247] Further, in the low-resistance region 127, the metal atoms may form an alloy with the oxide semiconductor layer 122 and the oxide insulating layer 123.

[0248] After forming the low-resistance region 127, the conductive film 168 is removed. The removal method may be a wet etching method or a dry etching method. For example, the conductive film 168 can be removed with a mixed solution of aqueous ammonia and aqueous hydrogen peroxide.

[0249] Note that the present invention is not limited to the above method, and the low-resistance region 127 may be formed. For example, the low-resistance region 127 can be formed by adding ion 16 9 (see FIG. 14). As ion 1 69, it is desirable to use titanium (Ti), molybdenum (Mo), tungsten (W), chromium (C r), vanadium (V), niobium (Nb), tantalum (Ta), zirconium (Zr), hafnium (Hf), etc.

[0250] Also, by performing a fourth heat treatment after the ion addition treatment, the damage to the film generated during the ion addition treatment can be repaired. Further, by this heat treatment, the ion-added material can be It can be diffused up to the oxide insulating layer 121.

[0251] As described above, the resistance of the second region and the third region can be reduced, and the source region and the drain region can be formed. Note that the second region can be substantially an LDD region because it contains fewer ion-added elements and alloys than the third region.

[0252] Next, a third insulating film that becomes the insulating layer 180 is formed. The method of forming the third insulating film can be the same as that of the insulating layer 110. After forming the third insulating film, a planarization process is performed to form the insulating layer 180.

[0253] Next, etching is performed by a dry etching method to provide an opening in the third insulating film.

[0254] Next, after forming a second conductive film that becomes the conductive layer 190 in the opening, a planarization process is performed to form the conductive layer 190.

[0255] Next, a third conductive film that becomes the conductive layer 195 is formed on the conductive layer 190. By using a photolithography method, a nanoimprinting method, etc. for the third conductive film, the conductive layer 195 is formed (see FIG. 15).

[0256] By using the above manufacturing method, the transistor 10 can be formed. By using the above manufacturing method, an extremely fine transistor with a channel length of 100 nm or less, 30 nm or less, and further 20 nm or less can be manufactured.

[0257] <Modification Example 1 of Transistor 10: Transistor 11> ​​​​​​​​​​For the transistor 11 having a shape different from that of the transistor 10 shown in FIG. 1, it will be described with reference to FIG. 16. It will be described.

[0258] FIGS. 16(A), 16(B), and 16(C) are top views and cross-sectional views of the transistor 11. FIG. 16(A) is a top view of the transistor 11, FIG. 16(B) is a cross-sectional view between the dashed line B1 - B2 in FIG. 16(A), and FIG. 16(C) is a cross-sectional view between B3 - B4. ) and FIG. 16(C) is a cross-sectional view between B3 - B4.

[0259] The transistor 11 is different from the transistor 10 in that the oxide insulating layer 123 is provided only in the portion where it overlaps with the gate electrode layer 160 and the gate insulating layer 150. By having the structure of the transistor 11, the resistance of the low-resistance region 125 and the low-resistance region 127 can be lowered. Thereby, the electrical characteristics of the transistor can be improved.

[0260] By having the structure of the transistor 11, the resistance of the low-resistance region 125 and the low-resistance region 127 can be lowered. Thereby, the electrical characteristics of the transistor can be improved. Thereby, the electrical characteristics of the transistor can be improved. Thereby, the electrical characteristics of the transistor can be improved.

[0261] <Modified Example 2 of Transistor 10: Transistor 12> For the transistor 12 having a shape different from that of the transistor 10 shown in FIG. 1, it will be described with reference to FIG. 17. It will be described.

[0262] FIGS. 17(A), 17(B), and 17(C) are top views and cross-sectional views of the transistor 12. FIG. 17(A) is a top view of the transistor 11, FIG. 17(B) is a cross-sectional view between the dashed line C1 - C2 in FIG. 17(A), and FIG. 17(C) is a cross-sectional view between C3 - C4. ) and FIG. 17(C) is a cross-sectional view between C3 - C4.

[0263] The transistor 12 is different from the transistor 10 in that it has a conductive layer 165.

[0264] 《Conductive Layer 165》 For the conductive layer 165, the same material as that of the gate electrode layer 160 can be used. The conductive layer 16 5 may be a single layer or a laminate.

[0265] The conductive layer 165 can have the same function as the gate electrode layer 160. The conductive layer 165 may be configured to apply the same potential as the gate electrode layer 160, or may be configured to apply different potentials.

[0266] Also, in the transistor 12 provided with the conductive layer 165, the insulating layer 110 can have the same structure and function as the gate insulating layer 150.

[0267] By having the structure of the transistor 12, the electrical characteristics (e.g., threshold voltage) of the transistor can be controlled.

[0268] <Modified Example 3 of Transistor 10: Transistor 13> The transistor 13 having a different shape from the transistor 10 shown in FIG. 1 will be described with reference to FIG. 18.

[0269] FIGS. 18(A), 18(B), and 18(C) are a top view and a cross-sectional view of the transistor 13. FIG. 18(A) is a top view of the transistor 13, FIG. 18(B) is a cross-sectional view between the dashed line D1 - D2 in FIG. 18(A), and FIG. 18(C) is a cross-sectional view between D3 - D4.

[0270] The transistor 13 is different from the transistor 10 in that it has the insulating layer 170 and the insulating layer 172.

[0271] 《Insulating Layer 170》 The insulating layer 170 contains oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), indium (In), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), indium (In), ​​​​​It can contain yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (Hf), tantalum (Ta), titanium (Ti), etc. Aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride oxide (SiNxOy), silicon nitride (SiNx), gallium oxide (GaOx), germanium oxide (GeOx), yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx), neodymium oxide (NdOx), hafnium oxide (HfOx), and tantalum oxide (TaOx) can be included in one or more kinds.

[0272] The insulating layer 170 preferably includes an aluminum oxide (AlOx) film. The aluminum oxide film can have a blocking effect of not allowing the film to permeate impurities such as hydrogen and moisture, and both oxygen. Therefore, the aluminum oxide film can prevent the mixing of impurities such as hydrogen and moisture, which are factors causing fluctuations in the electrical characteristics of the transistor, into the oxide insulating layer 121, oxide semiconductor layer 122, and oxide insulating layer 123 during and after the manufacturing process of the transistor, prevent the release of oxygen, which is the main component material, from the oxide insulating layer 121, oxide semiconductor layer 122, and oxide insulating layer 123, and prevent the unnecessary release of oxygen from the insulating layer 110, and is suitable for use as a protective film. Moreover, the insulating layer 170 is preferably a film having an oxygen supply ability. When forming the insulating layer 170, a mixed layer is formed at the interface with another oxide layer, and oxygen is replenished in the mixed layer or another oxide layer. Then, by heat treatment, oxygen diffuses into the oxide semiconductor layer. During and after the manufacturing process of the transistor, it can prevent the mixing of impurities such as hydrogen and moisture, which are factors causing fluctuations in the electrical characteristics of the transistor, into the oxide insulating layer 121, oxide semiconductor layer 122, and oxide insulating layer 123, prevent the release of oxygen, which is the main component material, from the oxide insulating layer 121, oxide semiconductor layer 122, and oxide insulating layer 123, and prevent the unnecessary release of oxygen from the insulating layer 110, and has the effect of being a protective film suitable for use. It can prevent the mixing of impurities such as hydrogen and moisture, which are factors causing fluctuations in the electrical characteristics of the transistor, into the oxide insulating layer 121, oxide semiconductor layer 122, and oxide insulating layer 123, prevent the release of oxygen, which is the main component material, from the oxide insulating layer 121, oxide semiconductor layer 122, and oxide insulating layer 123, and prevent the unnecessary release of oxygen from the insulating layer 110, and has the effect of being a protective film suitable for use. Moreover, the insulating layer 170 is preferably a film having an oxygen supply ability. When forming the insulating layer 170, a mixed layer is formed at the interface with another oxide layer, and oxygen is replenished in the mixed layer or another oxide layer. Then, by heat treatment, oxygen diffuses into the oxide semiconductor layer. During and after the manufacturing process of the transistor, it can prevent the mixing of impurities such as hydrogen and moisture, which are factors causing fluctuations in the electrical characteristics of the transistor, into the oxide insulating layer 121, oxide semiconductor layer 122, and oxide insulating layer 123, prevent the release of oxygen, which is the main component material, from the oxide insulating layer 121, oxide semiconductor layer 122, and oxide insulating layer 123, and prevent the unnecessary release of oxygen from the insulating layer 110, and has the effect of being a protective film suitable for use. It is suitable for use as a protective film.

[0273] Also, the insulating layer 170 is preferably a film having an oxygen supply ability. When forming the insulating layer 170, a mixed layer is formed at the interface with another oxide layer, and oxygen is replenished in the mixed layer or another oxide layer. Then, by heat treatment, oxygen diffuses into the oxide semiconductor layer. When forming the insulating layer 170, a mixed layer is formed at the interface with another oxide layer, and oxygen is replenished in the mixed layer or another oxide layer. Then, by heat treatment, oxygen diffuses into the oxide semiconductor layer. When forming the insulating layer 170, a mixed layer is formed at the interface with another oxide layer, and oxygen is replenished in the mixed layer or another oxide layer. Then, by heat treatment, oxygen diffuses into the oxide semiconductor layer. It is possible to replenish oxygen for oxygen deficiencies in the conductor layer and improve transistor characteristics (e.g., threshold voltage, reliability, etc.).

[0274] Also, the insulating layer 170 may be a single layer or a laminate. Also, another insulating layer may be provided above or below the insulating layer 170. For example, an insulating film containing one or more of magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide can be used. The insulating layer 170 preferably has more oxygen than the stoichiometric composition. Oxygen released from the insulating layer 170 can be diffused into the channel formation region of the oxide semiconductor layer 122 via the gate insulating layer 150 or the insulating layer 110, so that oxygen deficiencies formed in the channel formation region can be replenished with oxygen. Therefore, stable transistor electrical characteristics can be obtained.

[0275] 《Insulating layer 172》 The insulating layer 172 can contain oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (Hf), tantalum (Ta), titanium (Ti), etc. For example, aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (Si Ox), silicon oxynitride (SiOxNy), silicon nitride oxide (SiNxOy), nitride Silicon (SiNx), gallium oxide (GaOx), germanium oxide (GeOx), acid yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx) , neodymium oxide (NdOx), hafnium oxide (HfOx) and tantalum oxide (TaO x) can be used as an insulating film containing one or more of them. Further, the insulating layer 172 may be a laminate of the above materials.

[0276] The insulating layer 172 preferably contains an aluminum oxide film. The aluminum oxide film can have a blocking effect of not allowing the film to permeate impurities such as hydrogen and moisture, and both oxygen. Therefore, the aluminum oxide film can prevent the oxidation of impurities such as hydrogen and moisture, which are factors causing fluctuations in the electrical characteristics of the transistor, from mixing into the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 during and after the manufacturing process of the transistor. It is suitable for use as a protective film having an effect of preventing the release of oxygen from the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123, and preventing the unnecessary release of oxygen from the insulating layer 110.

[0277] Further, the insulating layer 172 can have a function as a protective film. By providing the insulating layer 172, the gate insulating layer 150 can be protected from plasma damage. This can suppress the formation of electron traps near the channel.

[0278] <Method for manufacturing transistor 13> A part of the method for manufacturing the transistor 13 will be described with reference to FIG. 19. Note that the description of the same parts as in the method for manufacturing the transistor 10 will be incorporated herein.

[0279] ​​​​​​​​​​​ <Formation of Insulating Layer 172> Form an insulating layer 172 on the oxide insulating layer 123, sidewall insulating layer 176, and gate electrode layer 160. The insulating layer 172 is preferably formed by a metalorganic chemical vapor deposition (MOCVD) method or an atomic layer deposition (ALD: Atomic Layer Deposition) method. This can suppress damage to the gate insulating layer 150 and also suppress oxidation of the gate electrode layer.

[0280] Also, the thickness of the insulating layer 172 is 1 nm or more and 30 nm or less, preferably 3 nm or more and 10 nm or less.

[0281] Also, after forming the insulating layer 172, an ion implantation process may be performed on the oxide semiconductor layer 122 and the oxide insulating layer 123. This can form the low-resistance regions 125 and 127 while reducing damage to the oxide semiconductor layer 122 during the ion implantation process.

[0282] Also, the insulating layer 172 may be processed and provided using a lithography method, a nanoimprinting method, a dry etching method, etc. after film formation, or may be only formed.

[0283] <Formation of Insulating Layer 170> Next, form an insulating layer 170 on the insulating layer 172. The insulating layer 170 may be a single layer or a laminate. The insulating layer 170 can be formed using the same materials, methods, etc. as the insulating layer 110.

[0284] Also, the insulating layer 170 is preferably an aluminum oxide film formed by a sputtering method. When forming an aluminum oxide film by a sputtering method, the ​​​​As the gas, it is desirable to have oxygen gas. Also, the oxygen gas is 1% by volume or more and 100% by volume or less, preferably 4% by volume or more and 100% by volume or less, more preferably 10% by volume or more and 100% by volume or less. By setting oxygen to 1% by volume or more, surplus oxygen can be supplied to the inside of the insulating layer or to the insulating layer in contact therewith. Also, oxygen can be added to the layer in contact with the said layer.

[0285] For example, as the insulating layer 170, using aluminum oxide as a target, as the gas used during sputtering a film can be formed by containing 50% by volume of oxygen gas, and the thickness can be set to 20 nm or more and 40 nm or less.

[0286] Next, it is preferable to perform a heat treatment. Typically, the heat treatment is performed at 150°C or more and below the glass transition temperature of the substrate, preferably 250°C or more and 500°C or less, more preferably 300°C or more and 450°C or less. By this heat treatment, the oxygen 173 added to the insulating layer (for example, insulating layer 110) diffuses and moves to the oxide semiconductor layer 122, and oxygen can be supplied to the oxygen vacancies present in the oxide semiconductor layer 122 (see Fig. 19).

[0287] For example, a heat treatment at 400°C for 1 hour can be performed in an oxygen atmosphere.

[0288] Note that the heat treatment may be performed at any time during other processes. By performing the heat treatment, defects present in the film can be repaired and the interface state density can be reduced.

[0289] <Addition of Oxygen> Note that the process of adding oxygen is not limited to the process via the insulating layer 170 and may be performed. Oxygen The addition process may be performed on the insulating layer 110, or may be performed on the first oxide insulating film or the oxide insulating layer 1 23, or may be performed on other insulating layers. As the oxygen to be added, any one or more of oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, etc. are used. Also As a method of adding oxygen, there are ion doping method, ion implantation method, plasma immersion ion implantation method, etc.

[0290] In addition, when using the ion implantation method as a method of adding oxygen, oxygen atomic ions may be used or oxygen molecular ions may be used. When using oxygen molecular ions, the damage to the film to be added can be reduced Oxygen molecular ions are separated on the surface of the film to which the oxygen is added and added as oxygen atomic ions In order to separate oxygen atoms from oxygen molecules, energy is used. Therefore, when oxygen molecular ions are added to the film to which the oxygen is added The energy per oxygen atomic ion is lower than that when oxygen atomic ions are added to the film to which the oxygen is added For this reason, the damage to the film to which the oxygen is added can be reduced able.

[0291] In addition, by using oxygen molecular ions, the energy of each oxygen atomic ion injected into the film to which the oxygen is added is reduced, so the position where the oxygen atomic ions are injected is shallow Therefore, in subsequent heat treatment, oxygen atoms are more likely to move, and more oxygen can be supplied to the oxide semiconductor film

[0292] In addition, when injecting oxygen molecular ions, the energy per oxygen atomic ion is lower than that when injecting oxygen atomic ions. For this reason, injecting using oxygen molecular ions ​​​​ This makes it possible to increase the acceleration voltage and throughput. Also, by performing implantation using oxygen molecular ions, the dose amount can be halved compared to the case of using oxygen atomic ions. As a result, the throughput can be increased.

[0293] When adding oxygen to the film to which the oxygen is added, it is preferable to add oxygen to the film to which the oxygen is added under conditions such that the peak of the concentration profile of oxygen atomic ions is located. As a result, compared to the case of implanting oxygen atomic ions, the acceleration voltage during implantation can be lowered, and damage to the film to which the oxygen is added can be reduced. That is, the amount of defects in the film to which the oxygen is added can be reduced, and 21 variations in the electrical characteristics of the transistor can be 3 suppressed. Furthermore, the amount of oxygen atoms added at the interface between the insulating layer 110 and the oxide insulating layer 121 is less 20 than 1×10 3 atoms / cm 19 or less than 1×10 3 atoms / cm By adding oxygen to the film to which the oxygen is added so that it is less than this, the amount of oxygen added to the insulating layer 110 can be

[0294] reduced. As a result, damage to the film to which the oxygen is added can be reduced, and variations in the electrical characteristics of the is also acceptable. As an atmosphere containing oxygen, there is an atmosphere containing oxidizing gases such as oxygen, ozone, nitrous oxide, and nitrogen dioxide. Note that by exposing the film to which the oxygen is added to the plasma generated with a bias applied to the substrate 100 side, it is possible and preferable to increase the amount of oxygen added to the film to which the oxygen is added. Examples of an apparatus for performing such plasma treatment include an ashing apparatus. For example, oxygen molecular ions with an acceleration voltage of 60 kV and a dose amount of 2×10 / cm can be added to the insulating layer 110 by ion implantation method. The above process can also be applied to the transistor 10 and other transistors.

[0295] 16 / cm 2 of oxygen molecular ions can be added to the insulating layer 110 by ion implantation method. The above process can also be applied to the transistor 10 and other transistors.

[0296]

[0297]

[0298]

[0299]

[0300] (Embodiment 2) <Structure of Oxide Semiconductor> Hereinafter, the structure of the oxide semiconductor will be described.

[0300] The oxide semiconductor can be divided into a single crystal oxide semiconductor and other non-single crystal oxide semiconductors. As the non-single crystal oxide semiconductor, CAAC-OS (c-axis-aligned crystalline oxide semiconductor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semicond uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-l ike oxide semiconductor) and amorphous oxide semiconductor, etc. exist .

[0301] From another perspective, oxide semiconductors can be divided into amorphous oxide semiconductors and other crystalline oxide sem iconductors. Examples of crystalline oxide semiconductors include single crystal oxide semiconductors, CAAC- OS, polycrystalline oxide semiconductors, and nc-OS, etc.

[0302] An amorphous structure is generally isotropic, has no inhomogeneous structure, is in a metastable state where the atomic arrangement is not fixed, has a flexible bond angle, has short-range order but no long-range order , etc.

[0303] That is, a stable oxide semiconductor cannot be called a completely amorphous oxide semiconductor. Also, an anisotropic (for example, having a periodic structure in a microscopic region ) oxide semiconductor cannot be called a completely amorphous oxide semiconductor. On the other hand, a-li ke OS is anisotropic but has an unstable structure with voids (also called voids). In terms of being unstable, a-like OS is physically close to an amorphous oxide semiconductor .

[0304] <caac-os> First, CAAC-OS will be described.

[0305] CAAC-OS is a type of oxide semiconductor having a plurality of c-axis oriented crystal parts (also referred to as pellets).

[0306] The case where CAAC-OS is analyzed by X-ray diffraction (XRD) will be described. For example, for CAAC-OS having crystals of InGaZnO4 classified into the space group R-3m, when performing a structural analysis by the out-of-plane method, as shown in Fig. 20(A), a peak appears near a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that in CAAC-OS, the crystal has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the surface (also referred to as the surface to be formed) on which the CAAC-OS film is formed, or the upper surface. In addition to the peak near 2θ of 31°, a peak may also appear near 2θ of 36°. The peak near 2θ of 36° is due to a crystal structure classified into the space group Fd-3m. Therefore, it is preferable that CAAC-OS does not show this peak.

[0307] On the other hand, when performing a structural analysis on CAAC-OS by the in-plane method in which X-rays are incident from a direction parallel to the surface to be formed, a peak appears near 2θ of 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. And, even when the analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed near 56°, as shown in Fig. 20(B), no distinct peak appears. On the other hand, for single crystal InGaZ ​​​​​​​​​​When φ scanning was performed with 2θ fixed near 56° with respect to nO4, as shown in Fig. 20(C), six peaks attributable to crystal planes equivalent to the (110) plane were observed. Therefore, from the structural analysis using XRD, it can be confirmed that the orientation of the a-axis and b-axis of CAAC-OS is irregular.

[0308] Next, CAAC-OS analyzed by electron diffraction will be described. For example, for CAAC-OS having a crystal of InGaZnO4, when an electron beam with a probe diameter of 300 nm is incident parallel to the formed surface of CAAC-OS, a diffraction pattern as shown in Fig. 20(D) (also referred to as a limited field of view electron diffraction pattern) may appear. This diffraction pattern contains spots due to the (009) plane of the InGaZnO4 crystal. Therefore, it can also be seen by electron diffraction that the pellets contained in CAAC-OS have c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface. On the other hand, for the same sample, the diffraction pattern when an electron beam with a probe diameter of 300 nm is incident perpendicular to the sample surface is shown in Fig. 20(E). From Fig. 20(E), a ring-shaped diffraction pattern was confirmed. Therefore, it can also be seen by electron diffraction using an electron beam with a probe diameter of 300 nm that the a-axis and b-axis of the pellets contained in CAAC-OS have no orientation. Note that the first ring in Fig. 20(E) is considered to be due to the (010) plane and the (100) plane of the InGaZnO4 crystal, etc. Also, the second ring in Fig. 20(E) is considered to be due to the (110) plane, etc.

[0309] Also, for a transmission electron microscope (TEM: Transmission Electron Mi The composite analysis image of the bright-field image and diffraction pattern of CAAC-OS was observed by a (also referred to as a high-resolution TEM image). Multiple pellets can be confirmed. . On the other hand, even in a high-resolution TEM image, there may be cases where the boundaries between pellets, that is, grain boundaries (also called grain boundaries), cannot be clearly confirmed. Therefore, it can be said that in CAAC -OS, a decrease in electron mobility due to grain boundaries is less likely to occur.

[0310] Fig. 21(A) shows a high-resolution TEM image of a cross-section of CAAC-OS observed from a direction substantially parallel to the sample surface. For the observation of the high-resolution TEM image, a spherical aberration corrector function was used. The high-resolution TEM image using the spherical aberration corrector function is particularly called a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image can be observed, for example, by a JEOL JEM-ARM200F atomic-resolution analytical electron microscope manufactured by JEOL Ltd. .

[0311] From Fig. 21(A), pellets, which are regions where metal atoms are arranged in layers, can be confirmed. It can be seen that the size of one pellet is more than 1 nm or more than 3 nm. Therefore, the pellet can also be called a nanocrystal (nc). Also, CAAC-OS can be called an oxide semiconductor having CANC (C-Axis Aligned nanocrystals). The pellet reflects the unevenness of the formed surface or the upper surface of CAAC -OS and is parallel to the formed surface or the upper surface of CAAC-OS.

[0312] In addition, FIGS. 21(B) and 21(C) show Cs-corrected high-resolution TEM images of the plane of CAAC -OS observed from a direction substantially perpendicular to the sample surface. FIGS. 21(D) and 21(E) are images obtained by image processing of FIGS. 21(B) and 21(C), respectively. Hereinafter, the method of image processing will be described. First, an FFT image is obtained by performing fast Fourier transform (FFT) processing on FIG. 21(B). Next, in the obtained FFT image, a mask process is performed to leave the range between 2.8 nm and 5.0 nm -1 with the origin as a reference. Next, the masked FFT image is subjected to inverse fast Fourier transform (IFFT) -1 processing to obtain an image obtained by image processing. The image thus obtained is called an FFT filtering image. The FFT filtering image is an image obtained by extracting the periodic components from the Cs-corrected high-resolution TEM image and shows the lattice array. In FIG. 21(D), the disordered portions of the lattice array are indicated by broken lines. The region surrounded by the broken lines is one pellet. And the portions indicated by the broken lines are the connecting parts between the pellets

[0313] . Since the broken lines are hexagonal, it can be seen that the pellets are hexagonal. Note that the shape of the pellets is not always a regular hexagon and is often an irregular hexagon. In FIG. 21(E), the area between the aligned region of the lattice array and another aligned region of the lattice array is indicated by a dotted line

[0314] . Even in the vicinity of the dotted line, no distinct grain boundaries can be confirmed. When the surrounding lattice points are connected with the lattice points in the vicinity of the dotted line as the center, a distorted hexagon can be formed. That is, the lattice array ​​It can be seen that the formation of grain boundaries is suppressed by distorting it. This is because CAAC -OS can tolerate strain due to the non-dense atomic arrangement in the a-b plane direction and the change in the bond distance between atoms when metal elements are substituted. It is considered possible.

[0315] As shown above, CAAC-OS has c-axis orientation and a complex structure in which a number of pellets (nanocrystals) are connected in the a-b plane direction and has a strained crystal structure. Therefore, CA AC-OS can also be referred to as an oxide semiconductor having a CAA crystal (c-axis-aligned a-b-pl ane-anchored crystal).

[0316] CAAC-OS is a highly crystalline oxide semiconductor. Since the crystallinity of an oxide semiconductor may decrease due to the incorporation of impurities or the generation of defects, CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects ( such as oxygen deficiency).

[0317] Note that impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metal elements. For example, an element with a stronger binding force to oxygen than the metal elements constituting the oxide semiconductor, such as silicon, deprives the oxide semiconductor of oxygen, disturbs the atomic arrangement of the oxide semiconductor, and becomes a factor in reducing the crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have a large atomic radius (or molecular radius), so they disturb the atomic arrangement of the oxide semiconductor and become a factor in reducing the crystallinity.

[0318] When an oxide semiconductor has impurities or defects, its characteristics may vary depending on light, heat, etc. ​​​​​For example, impurities contained in an oxide semiconductor can act as carrier traps or For example, oxygen vacancies in oxide semiconductors can act as carrier traps. In some cases, the SiO 2 can become a carrier generation source by capturing hydrogen.

[0319] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Specifically, 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 Less than, More preferably, 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than a career Such an oxide semiconductor can be a highly pure intrinsic or CAAC-OS is essentially a highly pure intrinsic oxide semiconductor. The state density is low, that is, the oxide semiconductor has stable characteristics.

[0320] <nc-os> Next, nc-OS will be described.

[0321] The case of analyzing nc-OS by XRD will be described. For example, for nc-OS , when performing structure analysis by the out-of-plane method, no peak indicating orientation appears . That is, the crystal of nc-OS has no orientation.

[0322] Also, for example, when a thin film of nc-OS having a crystal of InGaZnO4 is thinned and an electron beam with a probe diameter of 50 nm is incident parallel to the surface to be formed in a region with a thickness of 34 nm , a ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in Fig. 22 (A) is observed. Also, the diffraction pattern (nanobeam electron diffraction pattern) when an electron beam with a probe diameter of 1 nm is incident on the same sample is shown in Fig. 22(B). From Fig. 22(B), a plurality of spots are observed within the ring-shaped region . Therefore, the order of nc-OS is not confirmed when an electron beam with a probe diameter of 50 nm is incident, but the order is confirmed when an electron beam with a probe diameter of 1 nm is incident . Also, when an electron beam with a probe diameter of 1 nm is incident on a region with a thickness of less than 10 nm, an electron diffraction pattern in which spots are arranged in a substantially regular hexagonal shape may be observed as shown in Fig. 22(C). Therefore, it can be seen that in the range where the thickness is less than 10 nm, nc-OS has a highly ordered region, that is, has a crystal. Note that since the crystals are oriented in various directions

[0323] , there are also regions where a regular electron diffraction pattern is not observed.

[0324] In Fig. 22(D), the Cs-corrected high-resolution cross-section of nc-OS observed from a direction substantially parallel to the surface to be formed

[0324] The TEM image of the solution energy is shown. In the high-resolution TEM image, nc-OS can confirm the crystal part in the areas indicated by the auxiliary lines, etc. has a region where the crystal part can be confirmed, such as the areas shown by the auxiliary lines, and a region where a clear crystal part cannot be confirmed. The crystal part contained in nc-OS has a size of 1 nm or more and 10 nm or less, and is often particularly 1 nm or more and 3 nm or less. Note that an oxide semiconductor with a crystal part size larger than 1 0 nm and 100 nm or less is sometimes called a microcrystalline oxide semiconductor. crystalline oxide semiconductor). In nc-OS, for example, in a high-resolution TEM image, there are cases where crystal grain boundaries cannot be clearly confirmed. Note that the nanocrystals may have the same origin as the pellets in CAAC-OS. Therefore, in the following, the crystal part of nc-OS may sometimes be called a pellet.

[0325] Thus, nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, nc-OS shows no regularity in the crystal orientation between different pellets. Therefore, no orientation is seen in the entire film. Therefore, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or an amorphous oxide semiconductor.

[0326] Note that since there is no regularity in the crystal orientation between pellets (nanocrystals), nc-OS can be referred to as an oxide semiconductor having RANC (Random Aligned nanocrystals), or an oxide semiconductor having NANC (Non-Aligned nanocrystals).

[0327] nc-OS is an oxide semiconductor with higher regularity than amorphous oxide semiconductors. Therefore, nc-OS has a lower density of defect levels than a-like OS and amorphous oxide semiconductors. However, nc-OS does not show regularity in crystal orientation among different pellets. Therefore, nc-OS has a higher density of defect levels than CAAC-OS.

[0328] <a-like OS> a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors.

[0329] Fig. 23 shows a high-resolution cross-sectional TEM image of a-like OS. Here, Fig. 23(A) is the high-resolution cross-sectional TEM image of a-like OS at the start of electron irradiation. Fig. 23(B ) is the high- 8 e - / nm 2 -resolution cross-sectional TEM image of a-like OS after irradiation with electrons (e - ) at 4.3×10 . From Fig. 23(A) and Fig. 23(B), it can be seen that a-like OS has stripe-like bright regions extending in the vertical direction from the start of electron irradiation. Also, it can be seen that the shape of the bright regions changes after electron irradiation. Note that the bright regions are presumed to be loose or low-density regions.

[0330] Since it has looseness, a-like OS has an unstable structure. Below, in order to show that a-like OS has an unstable structure compared to CAAC-OS and nc-OS, changes in the structure due to electron irradiation are shown.

[0331] As samples, a-like OS, nc-OS, and CAAC-OS are prepared. Any of the samples is In-Ga-Zn oxide.​

[0332] First, high-resolution cross-sectional TEM images of each sample are obtained. From the high-resolution cross-sectional TEM images, each sample has a crystalline part.

[0333] The unit lattice of the InGaZnO4 crystal is known to have a structure in which three In-O layers and six Ga-Zn- O layers, a total of nine layers, are stacked in layers in the c-axis direction. The distance between these adjacent layers is about the same as the lattice plane spacing of the (009) plane (also referred to as the d value).) and its value is determined to be 0.29 nm from crystal structure analysis. Therefore, hereinafter, a portion where the lattice fringe spacing is 0.28 nm or more and 0.30 nm or less is regarded as the crystalline part of InGaZn O4. Note that the lattice fringes correspond to the a-b plane of the InGaZnO4 crystal.

[0334] FIG. 24 is an example in which the average size of the crystalline parts (from 22 to 30 locations) of each sample is investigated. Note that the length of the lattice fringes described above is defined as the size of the crystalline part. From FIG. 24, it can be seen that the crystalline part of a-like OS becomes larger according to the cumulative irradiation dose of electrons related to the acquisition of TEM images and the like. From FIG. 24, it can be seen that the crystalline part (also referred to as the initial nucleus), which was about 1.2 nm in size at the initial stage of observation by TEM, grows to about 1.9 nm in size when the cumulative irradiation dose of electrons (e - ) reaches 4.2×10 8 e - / nm 2 . On the other hand, it can be seen that there is no change in the size of the crystalline part of nc -OS and CAAC-OS in the range from the start of electron irradiation to a cumulative irradiation dose of electrons of 4.2×10 8 e - / nm 2 . From FIG. 24,​​ Regardless of the cumulative electron irradiation dose, the sizes of the crystalline parts of nc-OS and CAAC-OS are found to be about 1.3 nm and about 1.8 nm, respectively. Note that the electron beam irradiation and the TEM observation were performed using a Hitachi transmission electron microscope H-9000NAR. The electron beam irradiation conditions were an acceleration voltage of 300 kV, a current density of 6.7×10 5 e - / (nm 2 ·s), and the diameter of the irradiation region was 230 nm.

[0335] Thus, crystal growth of a-like OS may be observed by electron irradiation. On the other hand, crystal growth of nc-OS and CAAC-OS due to electron irradiation is hardly observed. That is, it can be seen that a-like OS has a less stable structure than nc-OS and CAAC-OS.

[0336] Also, because of having voids, a-like OS has a lower density structure than nc-OS and CAAC-OS. Specifically, the density of a-like OS is 78.6% or more and less than 92.3% of the density of a single crystal of the same composition. Also, the density of nc-OS and the density of CAAC -OS are 92.3% or more and less than 100% of the density of a single crystal of the same composition. An oxide semiconductor having a density less than 78% of the density of a single crystal is difficult to form a film itself.

[0337] For example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of a single crystal InGaZnO4 having a rhombohedral crystal structure is 6.357 g / cm ³. Therefore, for example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio] 3 ​​​​​​, the density of the a-like OS is 5.0 g / cm 3 or more and less than 5.9 g / cm 3 . Also , for example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of the nc-OS and the density of the CAAC-OS are 5.9 g / cm 3 or more and less than 6.3 g / cm 3 .

[0338] In addition, when there is no single crystal with the same composition, by combining single crystals with different compositions in any ratio, the density corresponding to the single crystal in the desired composition can be estimated. The density corresponding to the single crystal in the desired composition may be estimated using the weighted average with respect to the ratio of combining single crystals with different compositions. However, it is preferable to estimate the density by combining as few types of single crystals as possible.

[0339] As described above, the oxide semiconductor has various structures, each having various characteristics. In addition, the oxide semiconductor may be, for example, a laminated film having two or more of an amorphous oxide semiconductor, a-like OS, nc-OS, CAAC-OS.

[0340] (Embodiment 3) In this embodiment, an example of a circuit using the transistor of one aspect of the present invention will be described with reference to the drawings. .

[0341] [Cross-sectional structure] FIG. 25(A) shows a cross-sectional view of a semiconductor device of one aspect of the present invention. In FIG. 25(A), the X 1-X2 direction indicates the channel length direction, and the Y1-Y2 direction indicates the channel width direction. The semiconductor device shown in FIG. 25(A) has a transistor 2200 using a first semiconductor material at the lower part, and on the upper It has a transistor 2100 using a second semiconductor material. In FIG. 25(A), As the transistor 2100 using the second semiconductor material, an example in which the transistor exemplified in the previous embodiment is applied is shown. Note that the left side of the dashed-dotted line is a cross-section in the channel length direction of the transistor, and the right side is a cross-section in the channel width direction.

[0342] It is preferable that the first semiconductor material and the second semiconductor material are materials having different bandgaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (including silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, organic semiconductor, etc.), and the second semiconductor material can be an oxide semiconductor. Transistors using materials other than oxide semiconductors, such as single-crystal silicon, are easy to operate at high speed. On the other hand, by applying the transistor exemplified in the previous embodiment to a transistor using an oxide semiconductor, the S value (subthreshold value) can be reduced, and a fine transistor can be obtained. In addition, since the switching speed is fast, high-speed operation is possible, and since the off-current is low, the leakage current is small.

[0343] The transistor 2200 may be either an n-channel type transistor or a p-channel type transistor, and an appropriate transistor may be used depending on the circuit. In addition, except for using the transistor of one aspect of the present invention using an oxide semiconductor, it is not necessary to limit the specific configuration of the semiconductor device to what is shown here in terms of the materials and structures used.

[0344] In the configuration shown in FIG. 25(A), a transistor 2100 is provided above a transistor 2200 via an insulator 2201 and an insulator 2207. A plurality of wirings 2202 are provided between the transistor 2200 and the transistor 2100. Also, a plurality of plugs 2203 embedded in various insulators electrically connect the wirings and electrodes provided in the upper layer and the lower layer, respectively. Further, an insulator 2204 covering the transistor 2100 and a wiring 2205 are provided on the insulator 2204.

[0345] In this way, by stacking two types of transistors, the occupied area of the circuit is reduced, and a plurality of circuits can be arranged with higher density.

[0346] Here, when a silicon-based semiconductor material is used for the transistor 2200 provided in the lower layer, hydrogen in the insulator provided near the semiconductor film of the transistor 2200 terminates the dangling bonds of silicon and has the effect of improving the reliability of the transistor 2200. On the other hand, when an oxide semiconductor is used for the transistor 2100 provided in the upper layer, hydrogen in the insulator provided near the semiconductor film of the transistor 21 00 becomes one of the factors for generating carriers in the oxide semiconductor, and thus may be a factor for reducing the reliability of the transistor 2100 in some cases. Therefore, when the transistor 2100 using an oxide semiconductor is stacked and provided above the transistor 2200 using a silicon-based semiconductor material, it is particularly effective to provide an insulator 2207 having a function of preventing the diffusion of hydrogen between them. By confining hydrogen in the lower layer with the insulator 220 7, the reliability of the transistor 2200 is improved. In addition, by suppressing the diffusion of hydrogen from the lower layer to the upper layer, the reliability of the transistor 2100 can be improved simultaneously.

[0347] As the insulator 2207, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), etc. can be used.

[0348] Also, so as to cover the transistor 2100 configured to include an oxide semiconductor film, it is preferable to form a block film having a function of preventing the diffusion of hydrogen on the transistor 2100. As the block film, the same materials as those of the insulator 2207 can be used, and in particular, it is preferable to apply aluminum oxide. The aluminum oxide film has a high blocking effect of not allowing the film to permeate impurities such as hydrogen and moisture and oxygen. Therefore, by using an aluminum oxide film as the block film covering the transistor 2100, it is possible to prevent the desorption of oxygen from the oxide semiconductor film included in the transistor 2100 and also to prevent the incorporation of water and hydrogen into the oxide semiconductor film. Note that the block film may be used by laminating the insulator 2204, or may be provided below the insulator 2204.

[0349] Note that the transistor 2200 can be not only a planar-type transistor but also various types of transistors. For example, it can be a transistor such as a FIN (fin) type or a TRI-GATE (tri-gate) type. An example of a cross-sectional view in that case is shown in As shown in Fig. 25(D). In Fig. 25(D), the X1-X2 direction indicates the channel length direction, and the Y1- Y2 direction indicates the channel width direction. An insulator 2212 is provided on the semiconductor substrate 2211. The semiconductor substrate 2211 has a thin convex portion (also referred to as a fin) at the tip. Note that an insulator may be provided on the convex portion. Note that the tip of the convex portion does not have to be thin, and for example, it may be a substantially rectangular parallelepiped convex portion or a convex portion with a thick tip. A gate insulator 2214 is provided on the convex portion of the semiconductor substrate 2211, and a gate electrode 2213 is provided thereon. Source regions and drain regions 2 215 are formed in the semiconductor substrate 2211. Here, an example in which the semiconductor substrate 2211 has a convex portion is shown, but the semiconductor device according to one aspect of the present invention is not limited to this. For example, an SOI substrate may be processed to form a semiconductor region having a convex portion.

[0350] <Circuit configuration example> In the above configuration, various circuits can be configured by appropriately connecting the electrodes of the transistor 2100 and the transistor 2200. Hereinafter, an example of a circuit configuration that can be realized by using the semiconductor device according to one aspect of the present invention will be described.

[0351] <CMOS inverter circuit> The circuit diagram shown in Fig. 25(B) shows a configuration of a so-called CMOS inverter in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and their gates are connected.

[0352] <CMOS analog switch> Also, the circuit diagram shown in Fig. 25(C) shows the transistors 2100 and 2200 It shows a configuration in which each source and drain are connected. By adopting such a configuration, it can function as a so-called CMOS analog switch.

[0353] <Example of a memory device> Using the transistor which is one aspect of the present invention, an example of a semiconductor device (memory device) capable of maintaining the stored content even in a situation where no power is supplied and having no limitation on the number of write operations is shown in FIG. 26.

[0354] The semiconductor device shown in FIG. 26(A) includes a transistor 3200 using a first semiconductor material, a transistor 3300 using a second semiconductor material, and a capacitor element 3400. Note that as the transistor 3300, the transistor described in the previous embodiment can be used.

[0355] FIG. 26(B) shows a cross-sectional view of the semiconductor device shown in FIG. 26(A). In FIG. 26(B), the X1-X2 direction indicates the channel length direction, and the Y1-Y2 direction indicates the channel width direction. The cross-sectional view of the semiconductor device shows a configuration in which a back gate is provided for the transistor 3300, but a configuration without a back gate may also be used.

[0356]

[0357] The transistor 3300 is a transistor in which a channel is formed in a semiconductor having an oxide semiconductor. Since the transistor 3300 has a small off-current, by using it, it is possible to retain the stored content for a long time. That is, it is possible to obtain a semiconductor memory device that does not require a refresh operation or requires an extremely low frequency of refresh operations, so that the power consumption can be sufficiently reduced.​​​​​​​​​​In FIG. 26A, a first wiring 3001 is electrically connected to a source electrode of a transistor 3200. The second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. The third wiring 3003 is connected to the source electrode or drain of the transistor 3300. The fourth wiring 3004 is electrically connected to one of the drain electrodes of the transistor 3300. The gate electrode of the transistor 3200 is electrically connected to the transistor 3200. The other of the source electrode and the drain electrode of the transistor 3300 and the capacitor 3400 The fifth wiring 3005 is electrically connected to the first terminal of the capacitor 3400. are electrically connected.

[0358] In the semiconductor device shown in FIG. 26A, the potential of the gate electrode of the transistor 3200 can be held. By taking advantage of this feature, it is possible to write, store, and read information as follows: do.

[0359] Writing and holding of information will be described. First, the potential of the fourth wiring 3004 is changed by a transistor. The transistor 3300 is turned on by applying a potential to the transistor 3300. As a result, the potential of the third wiring 3003 is applied to the gate electrode of the transistor 3200 and and the capacitance element 3400. That is, the gate electrode of the transistor 3200 is A predetermined charge is applied (write). Here, the charge that gives two different potential levels is (hereinafter referred to as Low level charge and High level charge) After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off. By turning off the transistor 3300, the gate of the transistor 3200 The charge applied to the word electrode is retained (holding).

[0360] Since the off-current of the transistor 3300 is extremely small, the charge at the gate electrode of the transistor 3200 is retained over a long period of time.

[0361] Next, the reading of information will be described. With a predetermined potential (constant potential) applied to the first wiring 3001 and an appropriate potential (reading potential) applied to the fifth wiring 3005, depending on the amount of charge held at the gate electrode of the transistor 3200, the second wiring 3002 takes on different potentials . Generally, when the transistor 3200 is of the n-channel type, the apparent threshold voltage V when a high-level charge is applied to the gate electrode of the transistor 3200 is lower than the apparent threshold voltage V when a low-level charge is applied to the gate electrode of the transistor 3200. Here, the apparent threshold voltage means th_H the potential of the fifth wiring 3005 required to turn the transistor 3200 "on". Therefore, by setting the potential of the fifth wiring 3005 to be between V and V th_L as V0, the charge applied to the gate electrode of the transistor 3200 can be discriminated . For example, in writing, when a high-level charge was applied, if the potential of the fifth wiring 3005 becomes V0 (> V ), the transistor 3200 becomes "on". When a low-level charge was applied, even if the potential of the fifth wiring 3005 becomes V0 (< V th_H ) and V th_L , the transistor 3200 remains "off". For example, in writing, when a high-level charge is applied, if the potential of the fifth wiring 3005 becomes V0 (> V ), the transistor 3200 becomes "on". When a low-level charge is applied, even if the potential of the fifth wiring 3005 becomes V0 (< V th_H ), the transistor 3200 remains "off". If a low-level charge was applied, even if the potential of the fifth wiring 3005 becomes V0 (< V ), the transistor 3200 remains in the "off state". th_L ), the transistor 3200 remains in the "off state". Therefore, by determining the potential of the second wiring 3002, the stored information can be read. read out.

[0362] When memory cells are arranged and used in an array, it is necessary to be able to read only the information of a desired memory cell. For example, in a memory cell from which information is not read, a potential such that the transistor 3200 is in the "off state" regardless of the potential applied to the gate electrode, that is, a potential smaller than V is applied to the fifth wiring 3005, so that only the information of the desired memory cell can be read. Alternatively, in a memory cell from which information is not read, a potential such that the transistor 3200 is in the "on state" regardless of the potential applied to the gate electrode, that is, a potential larger than V is applied to the fifth wiring 3005, so that only the information of the desired memory cell can be read. th_H can be configured. Alternatively, in a memory cell from which information is not read, a potential such that the transistor 3200 is in the "on state" regardless of the potential applied to the gate electrode, that is, a potential larger than V is applied to the fifth wiring 3005, so that only the information of the desired memory cell can be read. state", that is, a potential larger than V th_L is applied to the fifth wiring 3005, so that only the information of the desired memory cell can be read.

[0363] The semiconductor device shown in FIG. 26(C) is different from FIG. 26(A) in that the transistor 3200 is not provided. Also in this case, writing and holding operations of information are possible by the same operation as described above. is possible. possible.

[0364] Next, reading of information will be described. When the transistor 3300 is turned on, the floating third wiring 3003 and the capacitor element 3400 are electrically connected, and charge is redistributed between the third wiring 3003 and the capacitor element 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 takes different values depending on the potential of the first terminal of the capacitor element 3400 ( or the charge stored in the capacitor element 3400). or the charge stored in the capacitor element 3400). or the charge stored in the capacitor element 3400). or the charge stored in the capacitor element 3400).

[0365] For example, let the potential of the first terminal of the capacitive element 3400 be V, the capacitance of the capacitive element 3400 be C, the capacitance component of the third wiring 3003 be CB, and the potential of the third wiring 3003 before charge redistribution be VB0. Then, the potential of the third wiring 3003 after charge redistribution is (CB × VB0 + C × V) / (CB + C). Therefore, assuming that the potential of the first terminal of the capacitive element 3400 takes two states of V1 and V0 (V1 > V0) as the state of the memory cell, when the potential V1 is held, the potential of the third wiring 3003 (=(CB × VB0 + C × V1) / (CB + C)) can be seen to be higher than the potential of the third wiring 3003 when the potential V0 is held (=(CB × VB0 + C × V0) / (CB + C)). And information can be read by comparing the potential of the third wiring 3003 with a predetermined potential. In this case, a transistor to which the above-described first semiconductor material is applied may be used as a drive circuit for driving the memory cell, and a transistor to which the second semiconductor material is applied may be stacked on the drive circuit as the transistor 3300. In the semiconductor device according to this embodiment, by applying a transistor with an extremely small off-current using an oxide semiconductor in the channel formation region, it is possible to hold the stored content for an extremely long period of time. That is, the refresh operation becomes unnecessary or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced. Also, when there is no power supply (however, it is desirable that the potential is fixed),

[0366] it is possible to hold the stored content for an extremely long period of time. That is, the refresh operation becomes unnecessary or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced. Also, when there is no power supply (however, it is desirable that the potential is fixed), it is possible to hold the stored content for an extremely long period of time. That is, the refresh operation becomes unnecessary or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced. Also, when there is no power supply (however, it is desirable that the potential is fixed),

[0367] it is possible to hold the stored content for an extremely long period of time. That is, the refresh operation becomes unnecessary or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced. Also, when there is no power supply (however, it is desirable that the potential is fixed), a transistor to which the above-described first semiconductor material is applied may be used as a drive circuit for driving the memory cell, and a transistor to which the second semiconductor material is applied may be stacked on the drive circuit as the transistor 3300. a transistor to which the above-described first semiconductor material is applied may be used as a drive circuit for driving the memory cell, and a transistor to which the second semiconductor material is applied may be stacked on the drive circuit as the transistor 3300.

[0368] In the semiconductor device according to this embodiment, by applying a transistor with an extremely small off-current using an oxide semiconductor in the channel formation region, it is possible to hold the stored content for an extremely long period of time. That is, the refresh operation becomes unnecessary or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced. Also, when there is no power supply (however, it is desirable that the potential is fixed), it is possible to hold the stored content for an extremely long period of time. That is, the refresh operation becomes unnecessary or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced. Also, when there is no power supply (however, it is desirable that the potential is fixed), it is possible to hold the stored content for an extremely long period of time. That is, the refresh operation becomes unnecessary or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced. Also, when there is no power supply (however, it is desirable that the potential is fixed), it is possible to hold the stored content for an extremely long period of time. That is, the refresh operation becomes unnecessary or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced. Also, when there is no power supply (however, it is desirable that the potential is fixed), it is possible to hold the stored content for an extremely long period of time. That is, the refresh operation becomes unnecessary or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced. Also, when there is no power supply (however, it is desirable that the potential is fixed), However, it is possible to retain the memory content over a long period of time.

[0369] In addition, in the semiconductor device shown in this embodiment, a high voltage is not required for writing information, and there is no problem of element degradation. For example, unlike conventional non-volatile memories, it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, so problems such as degradation of the gate insulating layer do not occur at all. That is, in the semiconductor device according to the disclosed invention, there is no limit to the number of rewritable times, which is a problem in conventional non-volatile memories, and the reliability is dramatically improved. Furthermore, since information is written depending on the on-state and off-state of the transistor, high-speed operation can be easily realized. By using the semiconductor device shown in this embodiment, a storage device with low power consumption and high capacity (for example, 1 terabit or more) can be fabricated. In the present specification and the like, for all terminals of active elements (such as transistors and diodes), passive elements (such as capacitive elements and resistive elements), etc., even if the connection destination is not specified, a person skilled in the art may be able to configure an aspect of the invention. That is, it can be said that an aspect of the invention is clear even without specifying the connection destination. And when the content of the specified connection destination is described in the present specification and the like, it may be possible to determine that an aspect of the invention without specifying the connection destination is described in the present specification and the like. In particular, when multiple cases are conceivable as the connection destination of the terminal, it is not necessary to limit the connection destination of the terminal to a specific location. Therefore, active elements (such as transistors and diodes), passive elements (such as capacitive elements and resistors)

[0370] By using the semiconductor device shown in this embodiment, a storage device with low power consumption and high capacity (for example, 1 terabit or more) can be fabricated.

[0371] Note that in this specification and the like, for all terminals of active elements (such as transistors and diodes), passive elements (such as capacitive elements and resistive elements), etc., even if the connection destination is not specified, a person skilled in the art may be able to configure an aspect of the invention. That is, it can be said that an aspect of the invention is clear even without specifying the connection destination. And when the content of the specified connection destination is described in this specification and the like, it may be possible to determine that an aspect of the invention without specifying the connection destination is described in this specification and the like. In particular, when multiple cases are conceivable as the connection destination of the terminal, it is not necessary to limit the connection destination of the terminal to a specific location. Therefore, active elements (such as transistors and diodes), passive elements (such as capacitive elements and resistors) ​​​​​​​​​​​​By specifying the connection destination only for some terminals of elements etc., it may be possible to constitute an aspect of the invention.

[0372] In this specification etc., for a certain circuit, if at least the connection destination is specified, it may be possible for a person skilled in the art to specify the invention. Or, for a certain circuit, if at least the function is specified, it may be possible for a person skilled in the art to specify the invention. Thus, it can be said that if the function is specified, an aspect of the invention is clear. And, if an aspect of the invention for which the function is specified can be determined to be described in this specification etc., then. Therefore, for a certain circuit, even if the function is not specified, if the connection destination is specified, it is disclosed as an aspect of the invention and it may be possible to constitute an aspect of the invention. Or for a certain circuit, even if the connection destination is not specified, if the function is specified, it is disclosed as an aspect of the invention and it may be possible to constitute an aspect of the invention.

[0373] In this specification etc., in a figure or text described in a certain embodiment, it is possible to extract a part thereof and constitute an aspect of the invention. Therefore, when a figure or text describing a certain part is described, the content obtained by extracting a part of the figure or text is also disclosed as an aspect of the invention and it is assumed that it may be possible to constitute an aspect of the invention. Therefore, for example, for drawings in which a single or a plurality of active elements (such as transistors, diodes etc.), wirings, passive elements (such as capacitive elements, resistive elements), conductive layers, insulating layers, semiconductors, organic materials etc.), inorganic materials, components, devices, operation methods, manufacturing methods etc. are described, Alternatively, in the description, it is possible to extract a part thereof to constitute an aspect of the invention. Let it be so. For example, having N (N is an integer) circuit elements (transistors, capacitor elements, etc.) from a circuit diagram constituted by, M (M is an integer and M < N) circuit elements (transistors, capacitors elements, etc.) can be extracted to constitute an aspect of the invention. As another example, from a cross-sectional view constituted by N layers (N is an integer), M (M is an integer and M < N) layers can be extracted to constitute an aspect of the invention. As yet another example, from a flowchart constituted by N (N is an integer) elements, M (M is an integer and M < N) elements can be extracted to constitute an aspect of the invention.

[0374] <Imaging device> Hereinafter, an imaging device according to an aspect of the present invention will be described.

[0375] FIG. 27(A) is a plan view showing an example of an imaging device 200 according to an aspect of the present invention. The imaging device 200 includes a pixel unit 210, a peripheral circuit 260 for driving the pixel unit 210, and peripheral circuits 270, 280, and 290. The pixel unit 210 has a plurality of pixels 211 arranged in a matrix of p rows and q columns (p and q are integers of 2 or more). The peripheral circuit 260, peripheral circuit 270, peripheral circuit 280, and peripheral circuit 290 each have a function of connecting to a plurality of pixels 211 and supplying signals for driving the plurality of pixels 211. In the present specification and the like, all of the peripheral circuit 260, peripheral circuit 270, peripheral circuit 280, and peripheral circuit 290 may be referred to as "peripheral circuit" or "driving circuit". For example, the peripheral circuit 260 can be said to be a part of the peripheral circuit.

[0376] ​​ Also, the peripheral circuit has at least one of a logic circuit, a switch, a buffer, an amplifier circuit, or a conversion circuit. Further, the peripheral circuit may be formed on the substrate forming the pixel portion 210. Also, a semiconductor device such as an IC chip may be used for part or all of the peripheral circuit. Note that any one or more of the peripheral circuits 260, 270, 280, and 290 may be omitted. Also, as shown in FIG. 27(B), in the pixel portion 210 included in the imaging device 200, the pixel 211 may be arranged obliquely. By arranging the pixel 211 obliquely, the pixel pitch in the row direction and the column direction can be shortened. Thereby, the imaging quality of the imaging device 200 can be further improved. <Configuration Example 1 of Pixel> One pixel 211 included in the imaging device 200 is composed of a plurality of sub-pixels 212, and a filter (color filter) that transmits light in a specific wavelength band is combined with each sub-pixel 212, whereby information for realizing color image display can be obtained. FIG. 28(A) is a plan view showing an example of the pixel 211 for obtaining a color image. The pixel 211 shown in FIG. 28(A) includes a sub-pixel 212 (hereinafter also referred to as "sub-pixel 212R") provided with a color filter that transmits light in the red (R) wavelength band, a sub-pixel 212 (hereinafter also referred to as "sub-pixel 212G") provided with a color filter that transmits light in the green (G) wavelength band, and a sub-pixel 212 provided with a color filter that transmits light in the blue (B) wavelength band.

[0377] Also, as shown in FIG. 27(B), in the pixel portion 210 included in the imaging device 200, the pixel 211 may be arranged obliquely. By arranging the pixel 211 obliquely, the pixel pitch in the row direction and the column direction can be shortened. Thereby, the imaging quality of the imaging device 200 can be further improved. Also, as shown in FIG. 27(B), in the pixel portion 210 included in the imaging device 200, the pixel 211 may be arranged obliquely. By arranging the pixel 211 obliquely, the pixel pitch in the row direction and the column direction can be shortened. Thereby, the imaging quality of the imaging device 200 can be further improved. Also, as shown in FIG. 27(B), in the pixel portion 210 included in the imaging device 200, the pixel 211 may be arranged obliquely. By arranging the pixel 211 obliquely, the pixel pitch in the row direction and the column direction can be shortened. Thereby, the imaging quality of the imaging device 200 can be further improved. Also, as shown in FIG. 27(B), in the pixel portion 210 included in the imaging device 200, the pixel 211 may be arranged obliquely. By arranging the pixel 211 obliquely, the pixel pitch in the row direction and the column direction can be shortened. Thereby, the imaging quality of the imaging device 200 can be further improved.

[0378] <Configuration Example 1 of Pixel> One pixel 211 included in the imaging device 200 is composed of a plurality of sub-pixels 212, and a filter (color filter) that transmits light in a specific wavelength band is combined with each sub-pixel 212, whereby information for realizing color image display can be obtained. One pixel 211 included in the imaging device 200 is composed of a plurality of sub-pixels 212, and a filter (color filter) that transmits light in a specific wavelength band is combined with each sub-pixel 212, whereby information for realizing color image display can be obtained. One pixel 211 included in the imaging device 200 is composed of a plurality of sub-pixels 212, and a filter (color filter) that transmits light in a specific wavelength band is combined with each sub-pixel 212, whereby information for realizing color image display can be obtained.

[0379] FIG. 28(A) is a plan view showing an example of the pixel 211 for obtaining a color image. The pixel 211 shown in FIG. 28(A) includes a sub-pixel 212 (hereinafter also referred to as "sub-pixel 212R") provided with a color filter that transmits light in the red (R) wavelength band, a sub-pixel 212 (hereinafter also referred to as "sub-pixel 212G") provided with a color filter that transmits light in the green (G) wavelength band, and a sub-pixel 212 provided with a color filter that transmits light in the blue (B) wavelength band. FIG. 28(A) is a plan view showing an example of the pixel 211 for obtaining a color image. The pixel 211 shown in FIG. 28(A) includes a sub-pixel 212 (hereinafter also referred to as "sub-pixel 212R") provided with a color filter that transmits light in the red (R) wavelength band, a sub-pixel 212 (hereinafter also referred to as "sub-pixel 212G") provided with a color filter that transmits light in the green (G) wavelength band, and a sub-pixel 212 provided with a color filter that transmits light in the blue (B) wavelength band. FIG. 28(A) is a plan view showing an example of the pixel 211 for obtaining a color image. The pixel 211 shown in FIG. 28(A) includes a sub-pixel 212 (hereinafter also referred to as "sub-pixel 212R") provided with a color filter that transmits light in the red (R) wavelength band, a sub-pixel 212 (hereinafter also referred to as "sub-pixel 212G") provided with a color filter that transmits light in the green (G) wavelength band, and a sub-pixel 212 provided with a color filter that transmits light in the blue (B) wavelength band. FIG. 28(A) is a plan view showing an example of the pixel 211 for obtaining a color image. The pixel 211 shown in FIG. 28(A) includes a sub-pixel 212 (hereinafter also referred to as "sub-pixel 212R") provided with a color filter that transmits light in the red (R) wavelength band, a sub-pixel 212 (hereinafter also referred to as "sub-pixel 212G") provided with a color filter that transmits light in the green (G) wavelength band, and a sub-pixel 212 provided with a color filter that transmits light in the blue (B) wavelength band. FIG. 28(A) is a plan view showing an example of the pixel 211 for obtaining a color image. The pixel 211 shown in FIG. 28(A) includes a sub-pixel 212 (hereinafter also referred to as "sub-pixel 212R") provided with a color filter that transmits light in the red (R) wavelength band, a sub-pixel 212 (hereinafter also referred to as "sub-pixel 212G") provided with a color filter that transmits light in the green (G) wavelength band, and a sub-pixel 212 provided with a color filter that transmits light in the blue (B) wavelength band. It has a sub-pixel 212B (hereinafter also referred to as "sub-pixel 212"). The sub-pixel 212 can function as a photosensor. It can function.

[0380] The sub-pixels 212 (sub-pixel 212R, sub-pixel 212G, and sub-pixel 212B) are electrically connected to wiring 231, wiring 247, wiring 248, wiring 249, and wiring 250. Also, the sub-pixels 212R, sub-pixel 212G, and sub-pixel 212B are each connected to an independent wiring 253. Also, in this specification and the like, for example, the wiring 248 and wiring 249 connected to the pixel 211 in the nth row (n is an integer of 1 or more and p or less) are described as wiring 248[n] and wiring 249[n] respectively. Also, for example, the wiring 253 connected to the pixel 211 in the mth column (m is an integer of 1 or more and q or less) is described as wiring 253[m]. In FIG. 28(A), the wiring 253 connected to the sub-pixel 212R of the pixel 211 in the mth column is wiring 253[m]R, the wiring 253 connected to the sub-pixel 212G is wiring 253[m]G, and the wiring 253 connected to the sub-pixel 212B is wiring 253[m]B. The sub-pixel 212 is electrically connected to the peripheral circuit via the above wiring. It is electrically connected to wiring 247, wiring 248, wiring 249, wiring 250. Also, the sub-pixel 212R, sub-pixel 212G, and sub-pixel 212B are each connected to an independent wiring 253. Also, in this specification and the like, for example, the wiring 248 and wiring 249 connected to the pixel 211 in the nth row (n is an integer of 1 or more and p or less) are described as wiring 248[n] and wiring 249[n] respectively. Also, for example, the wiring 253 connected to the pixel 211 in the mth column (m is an integer of 1 or more and q or less) is described as wiring 253[m]. In FIG. 28(A), the wiring 253 connected to the sub-pixel 212R of the pixel 211 in the mth column is wiring 253[m]R, the wiring 253 connected to the sub-pixel 212G is wiring 253[m]G, and the wiring 253 connected to the sub-pixel 212B is wiring 253[m]B. The sub-pixel 212 is electrically connected to the peripheral circuit via the above wiring. The sub-pixels 212R, sub-pixel 212G, and sub-pixel 212B are each connected to an independent wiring 253. Also, in this specification and the like, for example, the wiring 248 and wiring 249 connected to the pixel 211 in the nth row (n is an integer of 1 or more and p or less) are described as wiring 248[n] and wiring 249[n] respectively. Also, for example, the wiring 253 connected to the pixel 211 in the mth column (m is an integer of 1 or more and q or less) is described as wiring 253[m]. In FIG. 28(A), the wiring 253 connected to the sub-pixel 212R of the pixel 211 in the mth column is wiring 253[m]R, the wiring 253 connected to the sub-pixel 212G is wiring 253[m]G, and the wiring 253 connected to the sub-pixel 212B is wiring 253[m]B. The sub-pixel 212 is electrically connected to the peripheral circuit via the above wiring. Also, in this specification and the like, for example, the wiring 248 and wiring 249 connected to the pixel 211 in the nth row (n is an integer of 1 or more and p or less) are described as wiring 248[n] and wiring 249[n] respectively. Also, for example, the wiring 253 connected to the pixel 211 in the mth column (m is an integer of 1 or more and q or less) is described as wiring 253[m]. In FIG. 28(A), the wiring 253 connected to the sub-pixel 212R of the pixel 211 in the mth column is wiring 253[m]R, the wiring 253 connected to the sub-pixel 212G is wiring 253[m]G, and the wiring 253 connected to the sub-pixel 212B is wiring 253[m]B. The sub-pixel 212 is electrically connected to the peripheral circuit via the above wiring. The sub-pixels 212R, sub-pixel 212G, and sub-pixel 212B are each connected to an independent wiring 253. Also, in this specification and the like, for example, the wiring 248 and wiring 249 connected to the pixel 211 in the nth row (n is an integer of 1 or more and p or less) are described as wiring 248[n] and wiring 249[n] respectively. Also, for example, the wiring 253 connected to the pixel 211 in the mth column (m is an integer of 1 or more and q or less) is described as wiring 253[m]. In FIG. 28(A), the wiring 253 connected to the sub-pixel 212R of the pixel 211 in the mth column is wiring 253[m]R, the wiring 253 connected to the sub-pixel 212G is wiring 253[m]G, and the wiring 253 connected to the sub-pixel 212B is wiring 253[m]B. The sub-pixel 212 is electrically connected to the peripheral circuit via the above wiring. Also, for example, the wiring 253 connected to the pixel 211 in the mth column (m is an integer of 1 or more and q or less) is described as wiring 253[m]. In FIG. 28(A), the wiring 253 connected to the sub-pixel 212R of the pixel 211 in the mth column is wiring 253[m]R, the wiring 253 connected to the sub-pixel 212G is wiring 253[m]G, and the wiring 253 connected to the sub-pixel 212B is wiring 253[m]B. The sub-pixel 212 is electrically connected to the peripheral circuit via the above wiring. Also, for example, the wiring 253 connected to the pixel 211 in the mth column (m is an integer of 1 or more and q or less) is described as wiring 253[m]. In FIG. 28(A), the wiring 253 connected to the sub-pixel 212R of the pixel 211 in the mth column is wiring 253[m]R, the wiring 253 connected to the sub-pixel 212G is wiring 253[m]G, and the wiring 253 connected to the sub-pixel 212B is wiring 253[m]B. The sub-pixel 212 is electrically connected to the peripheral circuit via the above wiring. In FIG. 28(A), the wiring 253 connected to the sub-pixel 212R of the pixel 211 in the mth column is wiring 253[m]R, the wiring 253 connected to the sub-pixel 212G is wiring 253[m]G, and the wiring 253 connected to the sub-pixel 212B is wiring 253[m]B. The sub-pixel 212 is electrically connected to the peripheral circuit via the above wiring. The sub-pixels 212R, sub-pixel 212G, and sub-pixel 212B are each connected to an independent wiring 253. Also, in this specification and the like, for example, the wiring 248 and wiring 249 connected to the pixel 211 in the nth row (n is an integer of 1 or more and p or less) are described as wiring 248[n] and wiring 249[n] respectively. Also, for example, the wiring 253 connected to the pixel 211 in the mth column (m is an integer of 1 or more and q or less) is described as wiring 253[m]. In FIG. 28(A), the wiring 253 connected to the sub-pixel 212R of the pixel 211 in the mth column is wiring 253[m]R, the wiring 253 connected to the sub-pixel 212G is wiring 253[m]G, and the wiring 253 connected to the sub-pixel 212B is wiring 253[m]B. The sub-pixel 212 is electrically connected to the peripheral circuit via the above wiring. The sub-pixels 212R, sub-pixel 212G, and sub-pixel 212B are each connected to an independent wiring 253. Also, in this specification and the like, for example, the wiring 248 and wiring 249 connected to the pixel 211 in the nth row (n is an integer of 1 or more and p or less) are described as wiring 248[n] and wiring 249[n] respectively. Also, for example, the wiring 253 connected to the pixel 211 in the mth column (m is an integer of 1 or more and q or less) is described as wiring 253[m]. In FIG. 28(A), the wiring 253 connected to the sub-pixel 212R of the pixel 211 in the mth column is wiring 253[m]R, the wiring 253 connected to the sub-pixel 212G is wiring 253[m]G, and the wiring 253 connected to the sub-pixel 212B is wiring 253[m]B. The sub-pixel 212 is electrically connected to the peripheral circuit via the above wiring. The sub-pixel 212 is electrically connected to the peripheral circuit via the above wiring.

[0381] Also, the imaging device 200 has a configuration in which sub-pixels 212 provided with color filters that transmit light in the same wavelength band of adjacent pixels 211 are electrically connected to each other via a switch. FIG. 28(B) shows a connection example of the sub-pixel 212 of the pixel 211 arranged in the nth row and mth column and the sub-pixel 212 of the pixel 211 arranged in the (n + 1)th row and mth column adjacent to the pixel 211. In FIG. 28(B), the sub-pixel 212R arranged in the nth row and mth column and the sub-pixel 212R arranged in the (n + 1)th row and mth column The sub-pixel 212 is electrically connected to the peripheral circuit via the above wiring. Also, the imaging device 200 has a configuration in which sub-pixels 212 provided with color filters that transmit light in the same wavelength band of adjacent pixels 211 are electrically connected to each other via a switch. FIG. 28(B) shows a connection example of the sub-pixel 212 of the pixel 211 arranged in the nth row and mth column and the sub-pixel 212 of the pixel 211 arranged in the (n + 1)th row and mth column adjacent to the pixel 211. In FIG. 28(B), the sub-pixel 212R arranged in the nth row and mth column and the sub-pixel 212R arranged in the (n + 1)th row and mth column Also, the imaging device 200 has a configuration in which sub-pixels 212 provided with color filters that transmit light in the same wavelength band of adjacent pixels 211 are electrically connected to each other via a switch. FIG. 28(B) shows a connection example of the sub-pixel 212 of the pixel 211 arranged in the nth row and mth column and the sub-pixel 212 of the pixel 211 arranged in the (n + 1)th row and mth column adjacent to the pixel 211. In FIG. 28(B), the sub-pixel 212R arranged in the nth row and mth column and the sub-pixel 212R arranged in the (n + 1)th row and mth column Also, the imaging device 200 has a configuration in which sub-pixels 212 provided with color filters that transmit light in the same wavelength band of adjacent pixels 211 are electrically connected to each other via a switch. FIG. 28(B) shows a connection example of the sub-pixel 212 of the pixel 211 arranged in the nth row and mth column and the sub-pixel 212 of the pixel 211 arranged in the (n + 1)th row and mth column adjacent to the pixel 211. In FIG. 28(B), the sub-pixel 212R arranged in the nth row and mth column and the sub-pixel 212R arranged in the (n + 1)th row and mth column The sub-pixels 212R arranged in n rows and m columns are connected via the switches 201. The sub-pixel 212G arranged in the n+1th row and the mth column is connected to the switch 202. The sub-pixels 212B arranged in the nth row and the mth column are connected via the The sub-pixel 212B arranged at the center is connected via the switch 203.

[0382] The color filters used for the subpixels 212 are not limited to red (R), green (G), and blue (B). color filters that transmit cyan (C), yellow (Y) and magenta (M) light, respectively. A single pixel 211 may have sub-pixels for detecting light of three different wavelength bands. By providing 212, a full color image can be obtained.

[0383] Alternatively, color filters that transmit red (R), green (G), and blue (B) light are installed. In addition to the sub-pixel 212, a sub-pixel having a color filter that transmits yellow (Y) light is provided. Pixel 211 may be used with pixel 212. Alternatively, cyan (C), yellow (Y), In addition to the sub-pixel 212 provided with a color filter that transmits light of blue (Y) and magenta (M), The pixel 21 has a sub-pixel 212 provided with a color filter that transmits blue (B) light. One pixel 211 may have sub-pixels 2 that detect light in four different wavelength bands. By providing the lens 12, the color reproducibility of the acquired image can be further improved.

[0384] Also, for example, in FIG. 28(A), the sub-pixel 212 detects light in the red wavelength band, a subpixel 212 for detecting light in a wavelength band, and a subpixel 212 for detecting light in a blue wavelength band; The pixel ratio (or light receiving area ratio) does not have to be 1:1:1. For example, It may be a Bayer array with the (light-receiving area ratio) of red:green:blue = 1:2:1. Or, the pixel number ratio (light-receiving area ratio) may be red:green:blue = 1:6:1.

[0385] Note that the number of sub-pixels 212 provided in the pixel 211 may be one, but two or more are preferred. For example , by providing two or more sub-pixels 212 that detect light in the same wavelength band, redundancy can be increased and the reliability of the imaging device 200 can be enhanced.

[0386] Also, by using an IR (IR: Infrared) filter that absorbs or reflects visible light and transmits infrared light, an imaging device 200 that detects infrared light can be realized.

[0387] Also, by using an ND (ND: Neutral Density) filter (attenuating filter), it is possible to prevent output saturation that occurs when a large amount of light is incident on the photoelectric conversion element (light-receiving element). By combining ND filters with different light attenuation amounts, the dynamic range of the imaging device can be increased.

[0388] Also, in addition to the filters described above, a lens may be provided in the pixel 211. Here, an arrangement example of the pixel 211, the filter 254, and the lens 255 will be described using the cross-sectional view of FIG. 29. By providing the lens 255, the photoelectric conversion element can efficiently receive incident light. Specifically , as shown in FIG. 29(A), a structure can be adopted in which light 256 is made to enter the photoelectric conversion element 220 through the lens 255 formed in the pixel 211, the filter 25 4 (filter 254R, filter 254G, and filter 254B), and the pixel circuit 2 30 and the like.

[0389] However, as shown in the region surrounded by the dashed line, a part of the light 256 indicated by the arrow may be blocked by a part of the wiring 257. Therefore, as shown in FIG. 29(B), it is preferable to arrange the lens 255 and the filter 254 on the photoelectric conversion element 220 side so that the photoelectric conversion element 220 can efficiently receive the light 256. By making the light 256 incident on the photoelectric conversion element 220 from the photoelectric conversion element 220 side, an imaging device 200 with high detection sensitivity can be provided.

[0390] As the photoelectric conversion element 220 shown in FIG. 29, a photoelectric conversion element in which a pn-type junction or a pin-type junction is formed may be used.

[0391] Alternatively, the photoelectric conversion element 220 may be formed using a substance having a function of absorbing radiation and generating charges. Examples of substances having a function of absorbing radiation and generating charges include selenium, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, cadmium zinc alloy, etc.

[0392] For example, when selenium is used for the photoelectric conversion element 220, a photoelectric conversion element 2 20 having a light absorption coefficient over a wide wavelength band such as visible light, ultraviolet light, infrared light, X-rays, and gamma rays can be realized.

[0393] Here, one pixel 211 included in the imaging device 200 may have a sub-pixel 212 having a first filter in addition to the sub-pixel 212 shown in FIG. 28.

[0394] <Example 2 of pixel configuration> Hereinafter, an example of configuring a pixel using a transistor using silicon and a transistor using an oxide semiconductor will be described.

[0395] FIG. 30(A) and FIG. 30(B) are cross-sectional views of the elements constituting the imaging device. In FIG. 30(A) the X1-X2 direction indicates the channel length direction, and the Y1-Y2 direction indicates the channel width direction. In FIG. 30(B), the X1-X2 direction indicates the channel length direction, and the Y1-Y2 direction indicates the channel width direction.

[0396] The imaging device shown in FIG. 30(A) includes a silicon transistor 351 provided on a silicon substrate 300, a transistor 353 using an oxide semiconductor stacked and disposed on the transistor 351, and a photodiode 360 provided on the silicon substrate 300 and having an anode 361 and a cathode 362. Each transistor and photodiode 360 has electrical continuity with various plugs 370 and wirings 371, 372, and 373. Further, the anode 361 of the photodiode 360 has electrical connection with the plug 370 through a low-resistance region 363.

[0397] The imaging device also includes a layer 310 having a transistor 351 and a photodiode 360 provided on the silicon substrate 300, a layer 320 provided in contact with the layer 310 and having a wiring 371, a layer 33 0 provided in contact with the layer 320 and having a transistor 353 and an insulating layer 380, and a layer 340 provided in contact with the layer 330 and having wirings 372 and 373.

[0398] Note that in an example of the cross-sectional view of FIG. 30(A), in the silicon substrate 300, the light-receiving surface of the photodiode 360 is formed on the surface opposite to the surface on which the transistor 3 51 is formed. ​​​​​​By adopting such a configuration, an optical path can be secured without being affected by various transistors, wirings, etc. Therefore, pixels with a high aperture ratio can be formed. Note that the light-receiving surface of the photodiode 360 can be made the same as the surface on which the transistor 351 is formed.

[0399] In addition, when forming a pixel using only transistors using an oxide semiconductor, layer 310 may be a layer having a transistor using an oxide semiconductor. Or layer 310 may be omitted, and a pixel may be formed only with transistors using an oxide semiconductor.

[0400] Also, in the cross-sectional view of FIG. 30(A), the photodiode 360 provided in layer 310 and the transistor provided in layer 330 can be formed so as to overlap. Then, the integration degree of the pixel can be increased. That is, the resolution of the imaging device can be increased.

[0401] Also, FIG. 30(B) shows that the imaging device can have a structure in which the photodiode 365 is disposed on the transistor on the layer 340 side. In FIG. 30(B), for example, layer 310 has a transistor 351 using silicon, layer 320 has a wiring 371, layer 330 has a transistor 353 using an oxide semiconductor and an insulating layer 380, layer 340 has a photodiode 365, and is electrically connected to the wiring 373 and the wiring 374 via the plug 370. By adopting the element configuration shown in FIG. 30(B), the aperture ratio can be improved.

[0402]

[0403] In addition, for the photodiode 365, an amorphous silicon film, a microcrystalline silicon film, etc. are used. A pin-type diode element or the like may be used. The photodiode 365 is an n-type semiconductor 368, an i-type semiconductor 367, and a p-type semiconductor 366 are stacked in this order and have a structure. It is preferable to use amorphous silicon for the i-type semiconductor 367. Also, the p-type semi conductor 366 and the n-type semiconductor 368 may each contain a dopant that imparts the respective conductivity type and can use amorphous silicon or microcrystalline silicon. The photodiode 365 having an amorphous silicon as a photoelectric conversion layer has high sensitivity in the wavelength region of visible light and can easily detect weak visible light.

[0404] Note that this embodiment can be appropriately combined with other embodiments shown in this specification .

[0405] (Embodiment 4) In this embodiment, an example of a circuit configuration to which a transistor having an oxide semiconductor layer described in the above embodiment (OS transistor) can be applied will be described with reference to FIGS. 31 to 34 .

[0406] FIG. 31(A) shows a circuit diagram of an inverter that can be applied to a memory, an FPGA, a CPU, etc. The inverter 2800 outputs a signal whose logic is inverted from the signal applied to the input terminal IN to the output terminal OUT. The inverter 2800 has a plurality of OS transistors . The signal S BG is a signal that can switch the electrical characteristics of the OS transistor.

[0407] FIG. 31(B) is a circuit diagram that is an example of the inverter 2800. The inverter 2800 has an OS transistor 2810 and an OS transistor 2820. Inverter 2 800 can be fabricated in an n-channel type and can have a so-called unipolar circuit configuration. Since an inverter can be fabricated with a unipolar circuit configuration, it can be fabricated at a lower cost compared to the case of fabricating an inverter (CMOS inverter) with CMOS (Complementary Metal Oxide Semiconductor).

[0408] Note that the inverter 2800 having an OS transistor can also be disposed on a CMOS formed of Si transistors. Since the inverter 2800 can be disposed on top of the CMOS circuit configuration, an increase in circuit area due to the addition of the inverter 2800 can be suppressed.

[0409] The OS transistor 2810 and the OS transistor 2820 each have a first gate that functions as a front gate, a second gate that functions as a back gate, a first terminal that functions as one of a source or a drain, and a second terminal that functions as the other of the source or the drain.

[0410] The first gate of the OS transistor 2810 is connected to the second terminal. The second gate of the OS transistor 2810 is connected to a wiring that transmits the signal S BG The first terminal of the OS transistor 2810 is connected to a wiring that supplies the voltage VDD. The second terminal of the OS transistor 2810 is connected to the output terminal OUT.

[0411] The first gate of the OS transistor 2820 is connected to the input terminal IN. The second gate of the OS transistor 2820 is connected to the input terminal IN. The first terminal of the OS transistor 2820 is connected to a wiring that supplies the voltage VDD. The second terminal of the OS transistor 2820 is connected to the output terminal OUT. ​​​​​​​​​​​1 The terminal is connected to the output terminal OUT. The second terminal of the OS transistor 2820 is connected to the wiring that supplies the voltage VSS.

[0412] FIG. 31(C) is a timing chart for explaining the operation of the inverter 2800 . In the timing chart of FIG. 31(C), the signal waveform of the input terminal IN, the signal waveform of the output terminal OUT, the BG signal waveform of the signal S, and the change in the threshold voltage of the OS transistor 2810 are shown.

[0413] The signal S BG is applied to the second gate of the OS transistor 2810, so that the threshold voltage of the OS transistor 2810 can be controlled.

[0414] The signal S BG has a voltage V BG_A for shifting the threshold voltage negatively and a voltage V for shifting the threshold voltage positively. By applying the voltage V BG_B to the second gate, the OS transistor 2810 can be shifted negatively to the threshold voltage V BG_A . Also, by applying the voltage V to the second gate, the OS transistor 2810 can be shifted positively to the threshold voltage V TH_A . Also, by applying the voltage V BG_B to the second gate, the OS transistor with the threshold voltage V TH_B can be shifted positively.

[0415] To visualize the above description, FIG. 32(A) shows a graph of the Vg-Id curve, which is one of the electrical characteristics of the transistor .

[0416] The electrical characteristics of the OS transistor 2810 described above are obtained by setting the voltage of the second gate to the voltage V BG_A of ​By increasing it in this way, it can be shifted to the curve represented by the dashed line 2840 in Fig. 32(A). This is possible. Also, the electrical characteristics of the OS transistor 2810 described above can be shifted to the curve represented by the solid line 2841 in Fig. 32(A) by reducing the voltage of the second gate as small as voltage V is. As shown in Fig. 32(A), the OS transistor 28 BG_B 10 can shift the threshold voltage plus or minus by switching the signal S to voltage V 10 to voltage V BG or voltage V BG_A or the like as follows. BG_B By shifting the threshold voltage to the positive threshold voltage V

[0417] TH_B TH_B B

[0418]

[0419] TH_A By shifting it negatively, the OS transistor 2810 can be made into a state where current easily flows. FIG. 32(C) visually shows this state. As shown in FIG. 32(C), the current I flowing at this time can be made at least larger than the current I A flowing through the power supply. Therefore, when the signal applied to the input terminal IN is at a low level and the OS transistor 2820 is in an off state (OFF), the voltage at the output terminal OUT can rise steeply. B As shown in FIG. 32(C), since the current flowing through the OS transistor 2810 can be made into a state where it easily flows, the signal waveform 2832 at the output terminal in the timing chart shown in FIG. 31(C) can be made to change steeply. In addition, the control of the threshold voltage of the OS transistor 2810 by the signal S

[0420] is preferably performed before the state of the OS transistor 2820 changes, that is, before times T1 and T2. For example, as shown in FIG. 31(C), before the time T1 when the signal applied to the input terminal IN switches to a high level, the threshold voltage V is preferably switched from the threshold voltage V to the threshold voltage V of the OS transistor 2810. Also, as shown in FIG. 31(C), before the time T2 when the signal applied to the input terminal IN switches to a low level,

[0421] the threshold voltage V BG is preferably switched from the threshold voltage V to the threshold voltage V of the OS transistor 2810. For example, as shown in FIG. 31(C), before the time T1 when the signal applied to the input terminal IN switches to a high level, the threshold voltage V is preferably switched from the threshold voltage V TH_A to the threshold voltage V TH_B of the OS transistor 2810. Also, as shown in FIG. 31(C), before the time T2 when the signal applied to the input terminal IN switches to a low level, the threshold voltage V is preferably switched from the threshold voltage V to the threshold voltage V TH_B of the OS transistor 2810. TH_A It is preferable to switch the threshold voltage of the OS transistor 2810 from the threshold voltage V to the threshold voltage V.

[0422] In the timing chart of FIG. 31(C), the signal S BG is switched according to the signal applied to the input terminal IN, but another configuration may also be used. For example, the voltage for controlling the threshold voltage may be maintained at the second gate of the OS transistor 2810 in a floating state. An example of a circuit configuration capable of realizing this configuration is shown in FIG. 33(A ). )

[0423] In FIG. 33(A), in addition to the circuit configuration shown in FIG. 31(B), it has an OS transistor 2850 . The first terminal of the OS transistor 2850 is connected to the second gate of the OS transistor 2810. The second terminal of the OS transistor 2850 is connected to a wiring for applying a voltage V BG_B (or a voltage V BG_A ). The first gate of the OS transistor 2850 is connected to a wiring for applying the signal S F . The second gate of the OS transistor 2850 is connected to a wiring for applying a voltage V BG_B (or a voltage V BG_A ).

[0424] The operation of FIG. 33(A) will be described using the timing chart of FIG. 33(B).

[0425] The voltage for controlling the threshold voltage of the OS transistor 2810 is applied to the second gate of the OS transistor 2810 before the time T3 when the signal applied to the input terminal IN switches to the high level. The signal S is set to the high level to turn on the OS transistor 2850 F , and a voltage V for controlling the threshold voltage is applied to the node N BG . BG_B

[0426] Node N BG becomes voltage V BG_B After that, the OS transistor 2850 is turned off Since the off-current of the OS transistor 2850 is extremely small, it can continue to be in the off state and, once the voltage V BG held at the node N BG_B can be retained. Therefore the number of operations of applying the voltage V BG_B to the second gate of the OS transistor 2850 is reduced so that the power consumption required for rewriting the voltage V BG_B can be reduced.

[0427] In addition, in the circuit configurations of FIGS. 31(B) and 33(A), although the configuration of applying the voltage applied to the second gate of the OS transistor 2810 by external control is shown, another configuration may be used. For example, a voltage for controlling the threshold voltage may be generated based on the signal applied to the input terminal IN and applied to the second gate of the OS transistor 2810. An example of a circuit configuration capable of realizing the said configuration is shown in FIG. 34(A). In FIG. 34(A), in the circuit configuration shown in FIG. 31(B), a CMOS inverter 2860 is provided between the input terminal IN and the second gate of the OS transistor

[0428] 2810. The input terminal of the CMOS inverter 2860 is connected to the input terminal IN. The output terminal of the CMOS inverter 2860 is connected to the second gate of the OS transistor 2810. The operation of FIG. 34(A) will be d...

Claims

1. a first transistor having silicon in a channel formation region; a second transistor having an oxide semiconductor in a channel formation region; a capacitive element; and having a gate of the first transistor, one of a source and a drain of the second transistor, and one electrode of the capacitive element are electrically connected; a first conductive layer is provided which has a region located above the channel formation region of the first transistor and functions as a gate electrode of the first transistor; a first insulating layer is provided which has a region located above the first conductive layer and a region located below the channel formation region of the second transistor; an oxide semiconductor layer having the channel formation region of the second transistor is provided; a second conductive layer is provided which functions as one electrode of the capacitive element; a third conductive layer is provided which has a region located above the second conductive layer and functions as the other electrode of the capacitive element; a fourth conductive layer is provided which has a region located below the oxide semiconductor layer and functions as a first gate electrode of the second transistor; a fifth conductive layer is provided which has a region located above the oxide semiconductor layer and functions as a second gate electrode of the second transistor; a second insulating layer is provided which has a region in contact with the fifth conductive layer; the second conductive layer is located above the channel formation region of the first transistor and has a region overlapping the channel formation region of the first transistor; the second conductive layer is located above the oxide semiconductor layer and has a region overlapping the oxide semiconductor layer; the third conductive layer has a region overlapping the channel formation region of the first transistor and a region overlapping the channel formation region of the second transistor; the second insulating layer has a first opening and a second opening; the second conductive layer is electrically connected to the oxide semiconductor layer through the first opening; the second conductive layer is electrically connected to the first conductive layer through the second opening; the first opening has a region overlapping the oxide semiconductor layer and a region overlapping the third conductive layer and does not have an overlap with the first conductive layer; the second opening has a region overlapping the third conductive layer and does not have an overlap with the oxide semiconductor layer; A semiconductor device in which the fourth conductive layer has a region located above the first insulating layer.

2. A first transistor having silicon in a channel formation region, A second transistor having an oxide semiconductor in a channel formation region, A capacitor element, and The gate of the first transistor, one of the source and drain of the second transistor, and one electrode of the capacitor element are electrically connected, A first conductive layer is provided which has a region located above the channel formation region of the first transistor and functions as a gate electrode of the first transistor, A first insulating layer is provided which has a region located above the first conductive layer and a region located below the channel formation region of the second transistor, An oxide semiconductor layer having the channel formation region of the second transistor is provided, A second conductive layer is provided which functions as one electrode of the capacitor element, A third conductive layer is provided which has a region located above the second conductive layer and functions as the other electrode of the capacitor element, A fourth conductive layer is provided which has a region located below the oxide semiconductor layer and functions as a first gate electrode of the second transistor, A fifth conductive layer is provided which has a region located above the oxide semiconductor layer and functions as a second gate electrode of the second transistor, A second insulating layer having a region in contact with the fifth conductive layer is provided, The second conductive layer is located above the channel formation region of the first transistor and has a region overlapping with the channel formation region of the first transistor, The second conductive layer is located above the oxide semiconductor layer and has a region overlapping with the oxide semiconductor layer, The third conductive layer has a region overlapping with the channel formation region of the first transistor and a region overlapping with the channel formation region of the second transistor, The second insulating layer has a first opening and a second opening, The second conductive layer is electrically connected to the oxide semiconductor layer through the first opening, The second conductive layer is electrically connected to the first conductive layer through the second opening, The first opening has a region overlapping with the oxide semiconductor layer and a region overlapping with the third conductive layer, and does not have an overlap with the first conductive layer. The second opening has a region overlapping with the third conductive layer and has no overlap with the oxide semiconductor layer. The fourth conductive layer has a region located above the first insulating layer. In a cross-sectional view in the channel length direction of the second transistor, a part of the lower surface of the fifth conductive layer is located below the lower surface of the oxide semiconductor layer. A semiconductor device.

3. A first transistor having silicon in a channel formation region; A second transistor having an oxide semiconductor in a channel formation region; A capacitive element, and The gate of the first transistor, one of the source and drain of the second transistor, and one electrode of the capacitive element are electrically connected. A first conductive layer is provided which has a region located above the channel formation region of the first transistor and functions as a gate electrode of the first transistor. A first insulating layer is provided which has a region located above the first conductive layer and a region located below the channel formation region of the second transistor. An oxide semiconductor layer having a channel formation region of the second transistor is provided. A second conductive layer is provided which functions as one electrode of the capacitive element. A third conductive layer is provided which has a region located above the second conductive layer and functions as the other electrode of the capacitive element. A fourth conductive layer is provided which has a region located below the oxide semiconductor layer and functions as a first gate electrode of the second transistor. A fifth conductive layer is provided which has a region located above the oxide semiconductor layer and functions as a second gate electrode of the second transistor. A second insulating layer having a region in contact with the fifth conductive layer is provided. The second conductive layer is located above the channel formation region of the first transistor and has a region overlapping with the channel formation region of the first transistor. The second conductive layer is located above the oxide semiconductor layer and has a region overlapping with the oxide semiconductor layer. The third conductive layer has a region overlapping with the channel formation region of the first transistor and a region overlapping with the channel formation region of the second transistor. The second insulating layer has a first opening and a second opening. The second conductive layer is electrically connected to the oxide semiconductor layer through the first opening. The second conductive layer is electrically connected to the first conductive layer through the second opening. The first opening has a region overlapping with the oxide semiconductor layer and a region overlapping with the third conductive layer, and does not have an overlap with the first conductive layer. The second opening has a region overlapping with the third conductive layer and does not have an overlap with the oxide semiconductor layer. The fourth conductive layer has a region located above the first insulating layer. In a cross-sectional view in the channel length direction of the second transistor, a part of the lower surface of the fifth conductive layer is located below the lower surface of the oxide semiconductor layer. A semiconductor device in which the channel length direction of the first transistor has a direction along the channel length direction of the second transistor.

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