Semiconductor module
The semiconductor module addresses IC warping by using insulating layers with tailored thermal expansion coefficients to manage thermal stress, ensuring reliability and efficient heat dissipation.
Patent Information
- Application Number
- JP2024005927
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-01-18
- Publication Date
- 2025-07-31
AI Technical Summary
Semiconductor ICs embedded in substrate bodies can warp due to thermal expansion mismatch between the semiconductor IC and the covering metal film.
A semiconductor module design with a substrate body comprising insulating layers of varying thermal expansion coefficients, where the redistribution layer has a smaller thermal expansion coefficient than the back surface conductor, and the second insulating layer has a larger coefficient than the third, offsetting thermal stress and preventing warping.
The design effectively suppresses warping of the semiconductor IC by managing thermal expansion differences, enhancing reliability and heat dissipation while maintaining electrical connectivity and reducing resistance.
Smart Images
Figure 2025111966000001_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor module.
Background Art
[0002] Patent Document 1 discloses a semiconductor module in which a semiconductor IC (Integrated Circuit) is embedded in a substrate body having a multilayer structure.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0004] In this type of semiconductor module, when the back surface of the semiconductor IC embedded in the substrate body is covered with a metal film or the like, the semiconductor IC may be warped.
[0005] In the present disclosure, a technique for suppressing warping of a semiconductor IC in a semiconductor module having a structure in which the semiconductor IC is embedded in a substrate body is described.
Means for Solving the Problems
[0006] According to one aspect of the present disclosure, a semiconductor module includes a substrate body including a first insulating layer, a second insulating layer laminated on one surface of the first insulating layer, and a third insulating layer laminated on the other surface of the first insulating layer, a first semiconductor IC having a main surface provided with a redistribution layer and a back surface located on the opposite side of the main surface and at least partially covered with a back surface conductor, wherein the first semiconductor IC is embedded in the first insulating layer such that the main surface faces the second insulating layer side and the back surface faces the third insulating layer side, the thermal expansion coefficient of the redistribution layer is smaller than the thermal expansion coefficient of the back surface conductor, and the thermal expansion coefficient of the second insulating layer is larger than the thermal expansion coefficient of the third insulating layer.
Effect of the Invention
[0007] According to the present disclosure, in a semiconductor module having a structure in which a semiconductor IC is embedded in a substrate body, a technique for suppressing warping of the semiconductor IC is provided.
Brief Description of the Drawings
[0008]
Figure 1
Figure 2
Figure 3
Figure 4
Embodiments for Carrying Out the Invention
[0009] Hereinafter, embodiments of the technique according to the present disclosure will be described in detail with reference to the accompanying drawings.
[0010] FIG. 1 is a schematic cross-sectional view for explaining the configuration of a semiconductor module 100 according to an embodiment of the technology related to the present disclosure.
[0011] The semiconductor module 100 shown in FIG. 1 includes a substrate body 10 having a structure in which insulating layers 11 to 13 are laminated, and conductor layers L1 to L4 provided inside or on the surface of the substrate body 10. The insulating layer 11 is located substantially at the center in the thickness direction of the substrate body 10, the insulating layer 12 is laminated on one surface 11A thereof, and the insulating layer 13 is laminated on the other surface 11B thereof. The surface of the insulating layer 12 constitutes one surface 10A of the substrate body 10. The surface of the insulating layer 13 constitutes the other surface 10B of the substrate body 10. A part of the surface 10A of the substrate body 10 is covered with a solder resist 21. A part of the surface 10B of the substrate body 10 is covered with a solder resist 22.
[0012] The insulating layer 12 may contain an inorganic filler made of silica or the like. According to this, the strength of the insulating layer 12 can be increased, and the coefficient of thermal expansion of the insulating layer 12 can be reduced. The insulating layer 13 may contain a glass cloth. According to this, the strength of the insulating layer 13 can be further increased, and the coefficient of thermal expansion of the insulating layer 13 can be further reduced. In contrast, the insulating layer 11 does not have to contain an inorganic filler, a glass cloth, or the like. The coefficient of thermal expansion of the insulating layer 12 may be larger than the coefficient of thermal expansion of the insulating layer 13. The thickness T12 of the insulating layer 12 may be thinner than the thickness T13 of the insulating layer 13.
[0013] The conductor layer L1 is located on the surface 10A of the substrate body 10. The conductor layer L4 is located on the surface 10B of the substrate body 10. The conductor layer L2 is located between the insulating layer 11 and the insulating layer 12. The conductor layer L3 is located between the insulating layer 11 and the insulating layer 13.
[0014] A semiconductor IC 40 is embedded in the insulating layer 11. The semiconductor IC 40 may be an integrated circuit formed using various semiconductor materials. As an example, it may be a power device using GaN as a substrate material (for example, a device used for power conversion, control, etc.). A plurality of terminal electrodes 43 to 45 are provided on the main surface 41 of the semiconductor IC 40 facing the insulating layer 12 side. When the semiconductor IC 40 is a MOS power device, the terminal electrode 43 may be a source, the terminal electrode 44 may be a drain, and the terminal electrode 45 may be a gate. The terminal electrodes 43 to 45 may be composed of a redistribution layer provided on the main surface 41 of the semiconductor IC 40. The back surface 42 of the semiconductor IC 40, which is located on the opposite side of the main surface 41 and faces the insulating layer 13 side, is covered with a back surface conductor 46 that contributes to heat dissipation. The entire back surface 42 of the semiconductor IC 40 may be covered with the back surface conductor 46, or only a part thereof may be covered with the back surface conductor 46. The conductor constituting the back surface conductor 46 may be, for example, Cu, or a laminate of Ti and Cu.
[0015] In the example shown in FIG. 2(a), a plurality of source electrode patterns 47 and a plurality of drain electrode patterns 48 are alternately arranged on the main surface 41 of the semiconductor IC 40. In the example shown in FIG. 2(b), the plurality of source electrode patterns 47 are connected to the terminal electrode 43 located in the redistribution layer W via a plurality of via conductors 47A, and the plurality of drain electrode patterns 48 are connected to the terminal electrode 44 located in the redistribution layer W via a plurality of via conductors 48A. In the example shown in FIG. 2(c), the wiring pattern 91 located in the conductor layer L2 is connected to the terminal electrode 43 via a plurality of via conductors 91A, and the wiring pattern 92 located in the conductor layer L2 is connected to the terminal electrode 44 via a plurality of via conductors 92A.
[0016] The conductor constituting the redistribution layer W may be a laminate of Cu, Ni, and Au. The coefficient of thermal expansion of the redistribution layer W may be smaller than that of the back surface conductor 46. In this case, the semiconductor IC 40 is likely to warp with temperature changes.
[0017] A plurality of external terminals including external terminals 61 to 63 are provided on the conductor layer L1. The external terminals 61 to 63 are exposed from the surface 10A of the substrate body 10. In the example shown in FIG. 1, the external terminal 61 is connected to the terminal electrode 43 of the semiconductor IC 40 via a plurality of via conductors 71 and wiring patterns 91, and the external terminal 62 is connected to the terminal electrode 44 of the semiconductor IC 40 via a plurality of via conductors 72 and wiring patterns 92.
[0018] The via conductor 71 is formed in the insulating layers 11 and 12 and embedded in a via V71 that exposes the wiring pattern 91, whereby the terminal electrode 43 of the semiconductor IC 40 and the external terminal 61 are electrically connected. The via conductor 72 is formed in the insulating layers 11 and 12 and embedded in a via V72 that exposes the wiring pattern 92, whereby the terminal electrode 44 of the semiconductor IC 40 and the external terminal 62 are electrically connected. It is not essential to provide the wiring patterns 91 and 92, and the via conductors 71 and 72 may be directly connected to the terminal electrodes 43 and 44, respectively. In this way, the external terminals 61 and 62 are respectively arranged directly above the terminal electrodes 43 and 44, and the terminal electrodes 43 and 44 are respectively connected to the external terminals 61 and 62 via the via conductors 71 and 72, so that the resistance value between the terminal electrodes 43 and 44 and the external terminals 61 and 62 is reduced. Moreover, since the terminal electrodes 43 and 44 and the external terminals 61 and 62 are connected via a plurality of via conductors 71 and 72, respectively, the resistance value between the two is further reduced.
[0019] When the semiconductor IC 40 is a power device, a large current flows through the terminal electrodes 43 and 44, the via conductors 71 and 72, and the external terminals 61 and 62. Therefore, the insulating layer 12 that insulates them requires high insulation. By using an inorganic filler-containing resin without a glass cloth in the insulating layer 12, the insulation is improved compared to the case where a glass cloth is included. Further, when the insulating layer 12 contains an inorganic filler, migration is less likely to occur compared to the case where a glass cloth is included, so that high reliability can be obtained.
[0020] At a position overlapping with the back conductor 46 provided in the semiconductor IC 40, a plurality of vias V74 are formed in the insulating layers 11 and 13 to expose the back conductor 46. A via conductor 74 connected to the back conductor 46 is embedded in the via V74, and the back conductor 46 is connected to a conductor pattern 64 that contributes to heat dissipation provided in the conductor layer L4 via the via conductor 74. A ground potential may be applied to the conductor pattern 64. In addition to the conductor pattern 64, a plurality of external terminals 65 are provided in the conductor layer L4. The conductor pattern 64 and the external terminals 65 are exposed from the surface 10B of the substrate body 10.
[0021] A semiconductor IC 50 having a plurality of terminal electrodes 51 is mounted on the surface 10B of the substrate body 10. The semiconductor IC 50 is mounted on the surface 10B of the substrate body 10 such that the terminal electrodes 51 and the external terminals 65 are electrically connected. When the semiconductor IC 40 embedded in the insulating layer 11 is a power device, the semiconductor IC 50 may include a driver circuit for driving the semiconductor IC 40. The wiring pattern for supplying the ground potential to the semiconductor IC 50 may be electrically separated from the back conductor 46. The semiconductor IC 50 may be mounted at a position overlapping with the semiconductor IC 40 in plan view. According to this, the wiring length of the wiring connecting the semiconductor IC 50 and the semiconductor IC 40 can be shortened, and the overall planar size of the semiconductor module 100 can be reduced.
[0022] In the example shown in FIG. 1, one of the external terminals 65 is connected to a wiring pattern 80 located in the conductor layer L3 via a via conductor 75 provided through the insulating layer 13. The wiring pattern 80 is connected to a wiring pattern 82 located in the conductor layer L2 via a via conductor 81 provided through the insulating layer 12. The wiring pattern 82 is connected to an external terminal 63 located in the conductor layer L1 via a via conductor 73 provided through the insulating layer 11.
[0023] The semiconductor module 100 according to this embodiment further includes a molding resin 30 that covers the surface 10B of the substrate body 10. The molding resin 30 embeds the semiconductor IC 50 and is in contact with the conductor pattern 64. The molding resin 30 functions as a member that increases the strength of the entire semiconductor module 100, protects the semiconductor IC 50, and further dissipates the heat generated by the semiconductor IC 40. The molding resin 30 may contain a filler for enhancing thermal conductivity. Also, the outer surface of the molding resin 30 may be covered with a metal layer 31 for enhancing heat dissipation.
[0024] In the example shown in FIG. 1, the via conductors 71 and 72 have a filled via shape (a shape in which the inside of the via is filled with a conductor), while the via conductor 74 has a conformal via shape that forms a recess R without completely filling the via V74. When the via conductors 71 and 72 have a filled via shape, the resistance value between the semiconductor IC 40 and the external terminals 61 and 62 is reduced, and the heat dissipation through the external terminals 61 and 62 is enhanced. The via conductors 73 and 75 may also have a filled via shape.
[0025] On the other hand, since the via conductor 74 has a conformal via shape, a part of the molding resin 30 is embedded in the recess R formed thereby. As a result, due to the anchor effect, peeling at the interface between the conductor pattern 64, the via conductor 74, and the molding resin 30 is less likely to occur. That is, when the recess R does not exist, the flat conductor pattern 64 contacts the molding resin 30, so peeling is likely to occur at the interface between the two when the temperature change is repeated. However, in this embodiment, since a part of the molding resin 30 is embedded in the recess R formed by the via conductor 74, peeling between the two is less likely to occur even when the temperature change is repeated.
[0026] In order to further enhance the adhesion of the mold resin 30, the shape of the via conductor 74 may be controlled such that the depth D of the recess R is greater than the thickness T13 of the insulating layer 13, as in the semiconductor module 100A according to the first modification shown in FIG. 3. Further, when the mold resin 30 contains a filler, the filler density of the mold resin 30 may be locally low within the recess R. According to this, the adhesion between the mold resin 30 and the via conductor 74 can be further enhanced. The filler density within the recess R can be controlled by the particle size of the filler added to the mold resin 30 or the like.
[0027] As described above, in the semiconductor module 100 according to the present embodiment, the surface 10B of the substrate body 10 is covered with the mold resin 30. Since the mold resin 30 is in contact with the conductor pattern 64 and the via conductor 74, and the via conductor 74 is connected to the back surface conductor 46 of the semiconductor IC 40, it is possible to efficiently dissipate the heat generated by the semiconductor module 100 to the mold resin 30 side. Moreover, since the via conductor 74 has a conformal via shape and a part of the mold resin 30 is embedded in the recess R formed thereby, peeling of the mold resin 30 due to repeated temperature changes is less likely to occur.
[0028] On the other hand, since the via conductors 71, 72, 75 connected to the semiconductor ICs 40, 50 have a field via shape, it is possible to obtain high conductivity and high heat dissipation. Further, the insulating layer 11 for embedding the semiconductor IC 40 is thicker than the other insulating layers 12, 13, and the via conductor 81 passing through this may have a conformal via shape.
[0029] Further, when the coefficient of thermal expansion of the redistribution layer W is smaller than the coefficient of thermal expansion of the back surface conductor 46, the semiconductor IC 40 is likely to warp with temperature changes. However, if the coefficient of thermal expansion of the insulating layer 12 located on the redistribution layer W side is larger than the coefficient of thermal expansion of the insulating layer 13 located on the back surface conductor 46 side, the stress generated in the semiconductor IC 40 due to the difference in the coefficient of thermal expansion between the redistribution layer W and the back surface conductor 46 is offset, and warping can be suppressed.
[0030] In addition, when the difference in the coefficient of thermal expansion between the rewiring layer W and the back surface conductor 46 is not so large, the stress caused by the difference in the coefficient of thermal expansion between the insulating layer 12 and the insulating layer 13 may be greater than the stress caused by the difference in the coefficient of thermal expansion between the rewiring layer W and the back surface conductor 46. In this case, the stress caused by the difference in the coefficient of thermal expansion between the rewiring layer W and the back surface conductor 46 is excessively canceled out by the stress caused by the difference in the coefficient of thermal expansion between the insulating layer 12 and the insulating layer 13. That is, when the difference in the coefficient of thermal expansion between the insulating layer 12 and the insulating layer 13 is larger than the difference in the coefficient of thermal expansion between the rewiring layer W and the back surface conductor 46, the stress is excessively canceled out, and the semiconductor IC 40 may warp in the reverse direction. In such a case, the influence of the stress due to the difference in the coefficient of thermal expansion between the insulating layer 12 and the insulating layer 13 may be reduced by making the thickness T12 of the insulating layer 12 thinner than the thickness T13 of the insulating layer 13.
[0031] Furthermore, the area of the wiring patterns included in the conductor layers L1 and L2 located on the insulating layer 12 side as viewed from the insulating layer 11 may be made larger than the area of the wiring patterns included in the conductor layers L3 and L4 located on the insulating layer 13 side as viewed from the insulating layer 11, thereby reducing the influence of the difference in the coefficient of thermal expansion between the insulating layer 12 and the insulating layer 13. That is, by increasing the area of the wiring patterns included in the conductor layers L1 and L2, the overall coefficient of thermal expansion of the conductor layers L1 and L2 and the insulating layer 12 becomes smaller, so that the difference from the overall coefficient of thermal expansion of the conductor layers L3 and L4 and the insulating layer 13 can be adjusted, and warping of the semiconductor IC 40 can be suppressed.
[0032] As described above, embodiments of the technology according to the present disclosure have been described. However, the technology according to the present disclosure is not limited to the above-described embodiments, and various modifications can be made without departing from the gist thereof, and it goes without saying that those are also included in the scope of the technology according to the present disclosure.
[0033] For example, the semiconductor module 100 in the above-described embodiment has the mold resin 30. However, as one aspect, the technology according to the present disclosure is also applicable to a semiconductor module having no mold resin, such as the semiconductor module 100B according to the second modification.
[0034] The technology according to the present disclosure includes, but is not limited to, the following configuration examples.
[0035] A semiconductor module according to one aspect of the present disclosure includes a substrate body including a first insulating layer, a second insulating layer laminated on one surface of the first insulating layer, and a third insulating layer laminated on the other surface of the first insulating layer, a main surface provided with a redistribution layer, and a first semiconductor IC having a back surface located on the opposite side of the main surface and at least a part of which is covered with a back surface conductor. The first semiconductor IC is embedded in the first insulating layer such that the main surface faces the second insulating layer side and the back surface faces the third insulating layer side. The coefficient of thermal expansion of the redistribution layer is smaller than that of the back surface conductor, and the coefficient of thermal expansion of the second insulating layer is larger than that of the third insulating layer. According to this, the stress applied to the first semiconductor IC due to the difference in the coefficients of thermal expansion between the redistribution layer and the back surface conductor is relaxed by the difference in the coefficients of thermal expansion between the second insulating layer and the third insulating layer.
[0036] In the above semiconductor module, the substrate body has a first surface located on the second insulating layer side and a second surface located on the third insulating layer side. The redistribution layer of the first semiconductor IC is connected to a first external terminal provided on the first surface of the substrate body via a first via conductor embedded in the first and second insulating layers, and the back surface conductor of the first semiconductor IC may be embedded in the first and third insulating layers and connected to a second via conductor exposed on the second surface of the substrate body. According to this, the heat generated by the first semiconductor IC is efficiently dissipated.
[0037] In the above semiconductor module, the second insulating layer may contain an inorganic filler. According to this, the coefficient of thermal expansion of the second insulating layer can be reduced, and the reliability of the product can be enhanced.
[0038] In the above semiconductor module, the third insulating layer may contain a glass cloth. According to this, the coefficient of thermal expansion of the third insulating layer can be further reduced, and the strength of the substrate body can be enhanced.
[0039] The above semiconductor module may further include a molding resin that covers the second surface of the substrate body so as to be in contact with the second via conductor. According to this, it becomes possible to obtain higher heat dissipation characteristics.
[0040] The above semiconductor module further includes a second external terminal provided on the second surface of the substrate body, and a second semiconductor IC mounted on the second surface of the substrate body so as to be connected to the second external terminal. The first semiconductor IC is a power device, the second semiconductor IC includes a driver circuit for driving the first semiconductor IC, and the second semiconductor IC may overlap the first semiconductor IC and be embedded in the molding resin. According to this, it becomes possible to protect the second semiconductor IC with the molding resin.
[0041] In the above semiconductor module, the difference in the coefficient of thermal expansion between the second insulating layer and the third insulating layer may be larger than the difference in the coefficient of thermal expansion between the redistribution layer and the back surface conductor. According to this, the stress applied to the first semiconductor IC due to the difference in the coefficient of thermal expansion between the redistribution layer and the back surface conductor is further relaxed.
[0042] In the above semiconductor module, the thickness of the second insulating layer may be thinner than the thickness of the third insulating layer. According to this, it becomes possible to relax the excessive cancellation of stress due to the difference in the coefficient of thermal expansion between the second insulating layer and the third insulating layer.
[0043] In the above semiconductor module, the area of the wiring pattern located on the second insulating layer side as viewed from the first insulating layer may be larger than the area of the wiring pattern located on the third insulating layer side as viewed from the first insulating layer. According to this, it becomes possible to relax the excessive cancellation of stress due to the difference in the coefficient of thermal expansion between the second insulating layer and the third insulating layer.
Description of Reference Numerals
[0044] 10 Substrate body 10A, 10B Surfaces of the substrate body 11~13 Insulating layers Surfaces of the insulating layers 11A and 11B Soldermasks 21 and 22 Molding resin 30 Metal layer 31 Main surface 41 Back surface 42 Terminal electrodes 43 to 45 Back surface conductor 46 Source electrode pattern 47 Via conductors 47A and 48A Drain electrode pattern 48 Terminal electrode 51 External terminals 61 to 63 and 65 Conductor pattern 64 Via conductors 71 to 75 Wiring patterns 80 and 82 Via conductor 81 Wiring patterns 91 and 92 Via conductors 91A and 92A Semiconductor modules 100, 100A, and 100B Semiconductor ICs 40 and 50 Conductor layers L1 to L4 Recess R Vias V71, V72, and V74 Rewiring layer W
Claims
1. A substrate body including a first insulating layer, a second insulating layer laminated on one surface of the first insulating layer, and a third insulating layer laminated on the other surface of the first insulating layer; A first semiconductor IC having a main surface provided with a redistribution layer and a back surface located on the opposite side of the main surface and at least partially covered with a back surface conductor; The first semiconductor IC is embedded in the first insulating layer such that the main surface faces the second insulating layer side and the back surface faces the third insulating layer side; The coefficient of thermal expansion of the redistribution layer is smaller than that of the back surface conductor; The coefficient of thermal expansion of the second insulating layer is larger than that of the third insulating layer; A semiconductor module.
2. The substrate body has a first surface located on the second insulating layer side and a second surface located on the third insulating layer side; The redistribution layer of the first semiconductor IC is connected to a first external terminal provided on the first surface of the substrate body via a first via conductor embedded in the first and second insulating layers; The back surface conductor of the first semiconductor IC is connected to a second via conductor embedded in the first and third insulating layers and exposed on the second surface of the substrate body; The semiconductor module according to Claim 1.
3. The second insulating layer contains an inorganic filler; The semiconductor module according to Claim 2.
4. The third insulating layer contains a glass cloth; The semiconductor module according to Claim 3.
5. Further comprising a molding resin covering the second surface of the substrate body so as to contact the second via conductor; The semiconductor module according to any one of Claims 2 to 4.
6. A second external terminal provided on the second surface of the substrate body; A second semiconductor IC mounted on the second surface of the substrate body so as to be connected to the second external terminal; The first semiconductor IC is a power device; The second semiconductor IC includes a driver circuit for driving the first semiconductor IC; The second semiconductor IC overlaps the first semiconductor IC and is embedded in the molding resin; The semiconductor module according to Claim 5.
7. The difference in the coefficient of thermal expansion between the second insulating layer and the third insulating layer is larger than the difference in the coefficient of thermal expansion between the redistribution layer and the back surface conductor; The semiconductor module according to Claim 1.
8. The thickness of the second insulating layer is thinner than the thickness of the third insulating layer. The semiconductor module according to claim 7.
9. The area of the wiring pattern located on the second insulating layer side when viewed from the first insulating layer is larger than the area of the wiring pattern located on the third insulating layer side when viewed from the first insulating layer. The semiconductor module according to claim 1.
Citation Information
Patent Citations
Electronic component built-in substrate and manufacturing method of the same
JP2013229548A