Semiconductor device and manufacturing method for semiconductor device

Abstract

To provide a semiconductor device whose size can be reduced while securing the voltage withstanding, and a manufacturing method for the semiconductor device.SOLUTION: A semiconductor device includes a semiconductor substrate and a semiconductor layer existing on the semiconductor substrate. The semiconductor layer includes a first potential region including a drain region extending in a first direction in a plan view, a second potential region that surrounds the first potential region in the plan view and includes a source region that is aligned with the drain region in a second direction intersecting with the first direction, a drift region that exists inside the second potential region in the plan view and exists between the drain region and the source region, an inside region that exists inside the second potential region and outside the drift region in the plan view. At least a part of a surface layer of the inside region includes an impurity region separated from the drift region. The surface layer has an average impurity concentration of less than 2.4×1016 cm-3.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device.

Background Art

[0002] Patent Document 1 discloses a semiconductor device including a chip having a main surface, a drain region of a first conductivity type formed in a surface layer portion of the main surface, a source region of the first conductivity type formed in a region different from the drain region in the surface layer portion of the main surface, a back gate region of a second conductivity type formed in a region different from the drain region and the source region in the surface layer portion of the main surface so as to be electrically separated from the drain region and the source region, a gate insulating film covering the source region on the main surface, and a gate electrode formed on the gate insulating film.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

[0004] [Summary] An object according to one aspect of the present disclosure is to provide a semiconductor device and a method of manufacturing the semiconductor device capable of achieving miniaturization while ensuring breakdown voltage.

[0005] A semiconductor device according to an aspect of the present disclosure includes a semiconductor substrate and a semiconductor layer located on the semiconductor substrate. The semiconductor layer includes a first potential region including a drain region extending in a first direction in a plan view, a second potential region surrounding the first potential region in the plan view and including a source region aligned with the drain region in a second direction intersecting the first direction, a drift region located inside the second potential region in the plan view and between the drain region and the source region, and an inner region located inside the second potential region in the plan view and outside the drift region. At least a part of the surface layer of the inner region is provided with an impurity region separated from the drift region, and the average impurity concentration of the surface layer is 2.4×10 16 cm -3 or less.

[0006] A method for manufacturing a semiconductor device according to an aspect of the present disclosure includes a step of forming a semiconductor layer on a semiconductor substrate, and a step of forming, in the semiconductor layer, a first potential region including a drain region extending in a first direction, a second potential region surrounding the first potential region in the plan view and including a source region aligned with the drain region in a second direction intersecting the first direction, a drift region located inside the second potential region in the plan view and between the drain region and the source region, and an inner region located inside the second potential region in the plan view and outside the drift region. The method further includes a step of forming an impurity region separated from the drift region in at least a part of the surface layer of the inner region, and the average impurity concentration of the surface layer is 2.4×10 16 cm -3 or less.

Brief Description of the Drawings

[0007]

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[0008] [Detailed Description] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, the same reference numerals will be used for the same elements or elements having the same function, and redundant descriptions will be omitted. The terms "identical" and similar words in this specification are not limited to "exactly identical". Also, since the drawings are for conceptually explaining the embodiments, the dimensions and ratios of the components shown may be different from the actual ones in some cases.

[0009] FIG. 1 is a plan view showing a chip of the semiconductor device according to the present embodiment. FIG. 2 is an enlarged view of region II shown in FIG. 1. FIG. 3 is a partially cut-away perspective cross-sectional view of region III shown in FIG. 2. FIG. 4 is a cross-sectional view of region III shown in FIG. 2. As shown in FIG. 1, the semiconductor device 1A includes a silicon chip 2 (semiconductor chip) having a rectangular parallelepiped shape. The chip 2 is one of a plurality of devices formed on a silicon wafer having a diameter of, for example, 300 mm (about 12 inches).

[0010] The chip 2 has a first main surface 3 and a second main surface 4 which are a pair of main surfaces, and a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D connecting the first main surface 3 and the second main surface 4. Hereinafter, the extending direction of the third side surface 5C and the fourth side surface 5D in plan view is defined as the first direction X, the extending direction of the first side surface 5A and the second side surface 5B in plan view is defined as the second direction Y, and the normal direction of the first main surface 3 and the second main surface 4 is defined as the third direction Z. The first direction X is a direction intersecting the second direction Y in plan view, and the third direction Z corresponds to the thickness direction of the chip 2.

[0011] The first main surface 3 and the second main surface 4 are formed in a rectangular shape when viewed from the third direction Z, but are not limited thereto. In the present embodiment, the first main surface 3 is the upper surface, and the second main surface 4 is the bottom surface. Therefore, the configuration located near the first main surface 3 in the third direction Z corresponds to the configuration located on the top surface side (upper side) of the semiconductor device 1A, and the configuration near the second main surface 4 in the third direction Z corresponds to the configuration located on the bottom surface side (lower side) of the semiconductor device 1A.

[0012] The semiconductor device 1A includes a first semiconductor region 6 located in the upper region within the chip 2. The first semiconductor region 6 is a region having a first conductivity type and has a layer shape. Therefore, the first semiconductor region 6 may also be referred to as a semiconductor layer. The first semiconductor region 6 is at least a part of an epitaxial semiconductor layer. The first semiconductor region 6 is exposed from the first side surface 5A, the second side surface 5B, the third side surface 5C, and the fourth side surface 5D. The thickness of the first semiconductor region 6 is, for example, 5 μm or more and 20 μm or less. In the present embodiment, the first conductivity type is n-type.

[0013] The semiconductor device 1A includes a second semiconductor region 7 (semiconductor substrate) located in the lower region within the chip 2. The second semiconductor region 7 has a second conductivity type and is a region fixed at a predetermined potential, and exhibits a layer shape extending along the second main surface 4. The second semiconductor region 7 is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In the present embodiment, the second semiconductor region 7 is fixed at a back gate potential. The back gate potential may be a reference potential serving as a reference for circuit operation or a ground potential. In the present embodiment, the second conductivity type is p-type.

[0014] The second semiconductor region 7 is connected to the first semiconductor region 6. The thickness of the second semiconductor region 7 may be 50 μm or more and 400 μm or less. The second semiconductor region 7 is at least a part of a p-type semiconductor substrate. That is, the chip 2 has a first semiconductor region 6 included in an epitaxial semiconductor layer and a second semiconductor region 7 included in the semiconductor substrate. In other words, the chip 2 has a stacked structure including a semiconductor substrate and an epitaxial semiconductor layer located on the semiconductor substrate.

[0015] The semiconductor device 1A includes a plurality of device regions 8 partitioned on the first main surface 3. In the semiconductor device 1A, the number and arrangement of the plurality of device regions 8 are appropriately determined. Each of the plurality of device regions 8 includes a functional device formed using regions inside and outside the chip 2. The functional device includes, for example, at least one of a semiconductor switching device, a semiconductor rectifying device, and a passive device. The functional device may include a circuit network in which at least two of a semiconductor switching device, a semiconductor rectifying device, and a passive device are combined.

[0016] The semiconductor switching device includes at least one of, for example, a MISFET (Metal Insulator Semiconductor Field Effect Transistor), a BJT (Bipolar Junction Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor). The semiconductor rectifying device may include at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The passive device may include at least one of a resistor, a capacitor, an inductor, and a fuse.

[0017] The plurality of device regions 8 includes at least one transistor region 9. The transistor region 9 includes an FET structure (transistor structure). In the present embodiment, the FET structure has a so-called LDMISFET (Lateral Double diffused MISFET) structure. The FET structure is, for example, a high breakdown voltage device to which a drain voltage of 1000 V or more can be applied in the off state. Hereinafter, the structure of the transistor region 9 will be described.

[0018] The transistor region 9 is a region partitioned by a separation region (not shown), and includes an n-type region 10 located in the first semiconductor region 6, a first potential region 11, a second potential region 12, and a drift region 13. In the present embodiment, the n-type region 10 is a part of a portion of the first semiconductor region 6 partitioned by the separation region. The n-type impurity concentration of the n-type region 10 is, for example, equal to the n-type impurity concentration of the first semiconductor region 6. The n-type impurity concentration of the first semiconductor region 6 is, for example, 1.0×10 14 cm -3 or more and 1.0×10 16 cm -3 or less. The n-type region 10 has an oval shape in plan view, but is not limited thereto. The n-type region 10 may have a circular shape, an elliptical shape, a polygonal shape (for example, a rectangular shape), or the like.

[0019] The first potential region 11 is a region to which a first potential is applied and is located at the center of the n-type region 10. The second potential region 12 is a region to which a second potential different from the first potential is applied, is separated from the first potential region 11 in a cross-sectional view, and is located above the first semiconductor region 6. The second potential region 12 is located within the separation region in a plan view and surrounds the first potential region 11. For example, the first potential region 11 is a high-potential region to which a high potential (first potential) is applied, and the second potential region 12 is a low-potential region to which a low potential (second potential) lower than the high potential is applied. The drift region 13 is located between the first potential region 11 and the second potential region 12 in the n-type region 10.

[0020] The first potential region 11 includes a well region 14 and a drain region 15. Each of the well region 14 and the drain region 15 is provided on the upper side within the first semiconductor region 6. The well region 14 surrounds the drain region 15 in a plan view and is in contact with the drain region 15. For this reason, the potential of the well region 14 and the potential of the drain region 15 are fixed to the same potential (drain potential). In a plan view, the drain region 15 is separated from the periphery of the well region 14. In other words, in a plan view, the drain region 15 is located inside the periphery of the well region 14. The n-type impurity concentration of the well region 14 is higher than the n-type impurity concentration of the n-type region 10. Also, the n-type impurity concentration of the drain region 15 is higher than the n-type impurity concentration of the well region 14. The n-type impurity concentration of the well region 14 is, for example, 1.0×10 15 cm -3 or more and 1.0×10 18 cm -3 or less. The n-type impurity concentration of the drain region 15 is, for example, 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less.

[0021] In this embodiment, the well region 14 has an oval shape extending along the n-type region 10 in a plan view, but is not limited thereto. The well region 14 may have a circular shape, an elliptical shape, or a polygonal shape (e.g., a rectangular shape) in a plan view. In this embodiment, the drain region 15 has an oval shape similar to the well region 14 in a plan view, but is not limited thereto. The drain region 15 may have a circular shape, an elliptical shape, or a polygonal shape (e.g., a rectangular shape) in a plan view.

[0022] The second potential region 12 includes a p-type body region 16 located between the separation region and the well region 14 in a plan view. The body region 16 extends, for example, along the periphery of the n-type region 10. Specifically, the body region 16 has an oval ring shape surrounding the n-type region 10 in a plan view. The body region 16 extends to the boundary between the first semiconductor region 6 and the second semiconductor region 7 in the third direction Z. Therefore, the body region 16 is electrically connected to the second semiconductor region 7 and is fixed to the potential (e.g., the back gate potential) of the second semiconductor region 7. The body region 16 may be provided in both the first semiconductor region 6 and the second semiconductor region 7. The p-type impurity concentration of the body region 16 is, for example, 1.0×10 15 cm -3 or more and 1.0×10 18 cm -3 or less. In this embodiment, the body region 16 includes a first body region 16-1 and a second body region 16-2.

[0023] The first body region 16-1 is provided in both the first semiconductor region 6 and the second semiconductor region 7. Therefore, a part of the first body region 16-1 is provided at the boundary between the first semiconductor region 6 and the second semiconductor region 7. The first body region 16-1 is electrically connected to the second semiconductor region 7. The p-type impurity concentration of the first body region 16-1 is higher than the p-type impurity concentration of the second semiconductor region 7. The second body region 16-2 is a region provided in the first semiconductor region 6 and on the first body region 16-1, and is electrically connected to the first body region 16-1. The p-type impurity concentration of the second body region 16-2 is lower than the p-type impurity concentration of the first body region 16-1, for example.

[0024] As shown in FIG. 2, in a plan view, the body region 16 is partitioned into a first region 16A, a second region 16B, a third region 16C, and a fourth region 16D. Each of the first region 16A and the second region 16B is a strip-shaped portion extending along the first direction X in the plan view, and they extend in parallel to each other. The first region 16A and the second region 16B are provided such that the drain region 15 is located between the first region 16A and the second region 16B in the second direction Y in the plan view. In the first direction X, the length of the first region 16A and the length of the second region 16B may each be less than or equal to the length of the drain region 15.

[0025] The third region 16C is a strip-shaped portion connecting one end portion of the first region 16A in the first direction X and one end portion of the second region 16B in the first direction X. In the present embodiment, the third region 16C extends in an arc-shaped strip between one end portion of the first region 16A and one end portion of the second region 16B in the plan view, but is not limited thereto. The third region 16C may extend along the second direction Y.

[0026] The fourth region 16D is a strip-shaped portion connecting the other end portion of the first region 16A in the first direction X and the other end portion of the second region 16B in the first direction X. In the present embodiment, the fourth region 16D extends in an arc-shaped strip between the other end portion of the first region 16A and the other end portion of the second region 16B in the plan view, but is not limited thereto. The fourth region 16D may extend along the second direction Y.

[0027] The semiconductor device 1A includes a source region 17 provided in the body region 16 and aligned with the drain region 15 in the second direction Y. In the present embodiment, the semiconductor device 1A includes a plurality of source regions 17, but is not limited thereto. Each of the plurality of source regions 17 is an n-type region and is fixed to the source potential. Specifically, the source potential is applied to each of the plurality of source regions 17 from the outside of the chip 2. In the n-type region 10, a p-type channel region 18 in the above FET structure is formed between the source region 17 and the drift region 13 in the second direction Y. Therefore, a current path extending in the second direction Y is formed in the channel region 18 between the source region 17 and the drift region 13 in the second direction Y. The source potential corresponds to the second potential. The n-type impurity concentration of the source region 17 is higher than the n-type impurity concentration of the well region 14. The n-type impurity concentration of the source region 17 may be equal to the n-type impurity concentration of the drain region 15. The n-type impurity concentration of the source region 17 is, for example, 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less. In the channel region 18, conduction and non-conduction of the current path between the drain region 15 and the source region 17 are controlled.

[0028] Each of the plurality of source regions 17 has a strip shape in a plan view and is located inside the body region 16 and inside the outer peripheral edge of the body region 16. Also, each of the plurality of source regions 17 constitutes a part of the surface layer of the body region 16. A part of the plurality of source regions 17 is located in the first region 16A. Each end of the part in the first direction X is located inside each end of the first region 16A in the first direction X, but is not limited thereto. The other part of the plurality of source regions 17 is located in the second region 16B. Each end of the other part in the first direction X is located inside each end of the second region 16B in the first direction X, but is not limited thereto. None of the plurality of source regions 17 is located in the third region 16C and the fourth region 16D. In the first direction X, the length of each source region 17 is, for example, equal to or less than the length of the drain region 15. For example, when one source region 17 is located in the body region 16, the source region 17 is located in either the first region 16A or the second region 16B of the body region 16.

[0029] The second potential region 12 includes a contact region 19 provided in the body region 16. In the present embodiment, the semiconductor device 1A includes a plurality of contact regions 19, but is not limited thereto. Each of the plurality of contact regions 19 is a p-type region. The p-type impurity concentration of each contact region 19 may be higher than the p-type impurity concentration of the body region 16. For example, the p-type impurity concentration of the contact region 19 is, for example, 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less.

[0030] Each contact region 19 has a strip shape in plan view and is located within the body region 16 and inside the outer peripheral edge of the body region 16. Also, each contact region 19 is located closer to the outer peripheral edge of the body region 16 than the source region 17. Each contact region 19 constitutes a part of the surface layer of the body region 16. Each contact region 19 is in contact with, but not limited to, the outer peripheral edge of the body region 16. A part of the plurality of contact regions 19 is located within the first region 16A. Each end of the part in the first direction X is located inside, but not limited to, each end of the first region 16A in the first direction X. The other part of the plurality of contact regions 19 is located within the second region 16B. Each end of the other part in the first direction X is located inside, but not limited to, each end of the second region 16B in the first direction X. In the present embodiment, none of the plurality of contact regions 19 is located in the third region 16C and the fourth region 16D, but it is not limited to this. In the first direction X, the length of each contact region 19 is, for example, equal to or less than the length of the drain region 15.

[0031] Each of the plurality of contact regions 19 is located between the corresponding source region 17 and the outer peripheral edge of the body region 16 in plan view. Also, each of the plurality of contact regions 19 is adjacent to the corresponding source region 17 in plan view. For this reason, on the surface layer of the body region 16, the source region 17 fixed to the source potential and the contact region 19 fixed to a potential different from the source potential coexist.

[0032] The semiconductor device 1A includes an n-type drift region 13 that is located inside the second potential region 12 in a plan view and is located between the drain region 15 and the source region 17. The drift region 13 is located within the n-type region 10. In the present embodiment, the drift region 13 extends in the second direction Y. The drift region 13 forms a current path. The width of the drift region 13 is, for example, 50 μm or more and 200 μm or less. The width of the drift region 13 corresponds to the distance between the first potential region 11 and the second potential region 12 along the second direction Y. The width of the drift region 13 is, for example, substantially constant along the second direction Y. The n-type impurity concentration of the drift region 13 is, for example, the same as the n-type impurity concentration of the first semiconductor region 6.

[0033] The semiconductor device 1A includes an insulating film 22 that selectively covers the surface 6a of the first semiconductor region 6 in the transistor region 9. The insulating film 22 contains silicon oxide. The insulating film 22 includes a LOCOS film (Local oxidation of silicon film) formed by selective oxidation of the first semiconductor region 6, a buried oxide film (STI: Shallow Trench Isolation) that fills a shallow trench provided in the first semiconductor region 6, and the like. The insulating film 22 may have a single-layer structure or a laminated structure. The insulating film 22 is located on the first semiconductor region 6 and covers the region between the drain region 15 and the source region 17 in the first semiconductor region 6. The insulating film 22 is located, for example, on the n-type region 10 and has an oval ring shape surrounding the drain region 15 in plan view, and includes an inner edge portion 22a and an outer edge portion 22b. In FIG. 2, the outer edge portion 22b is indicated by a broken line. The inner edge portion 22a of the insulating film 22 is located outside the drain region 15. The outer edge portion 22b is located inside the inner edge of the body region 16 in plan view. Note that a part of the body region 16, the source region 17, the contact region 19, and the drift region 13 is exposed from the insulating film 22. The insulating film 22 is defined into a first region 22c where an operation region OR of a field electrode 25 described later is provided and a second region 22d where a termination region TR of the field electrode 25 is provided (see FIG. 6 described later). Although not shown, in this embodiment, the insulating film 22 is defined into a pair of first regions 22c and a pair of second regions 22d.

[0034] As shown in FIGS. 2 to 4, the semiconductor device 1A includes a field electrode 25 (field plate) located on the insulating film 22 in the transistor region 9. The field electrode 25 has functions such as suppressing the disturbance of the electric field in the first semiconductor region 6 and the like, suppressing local electric field concentration, and monitoring the high-voltage drain-gate voltage Vdg, and is a high-resistance film connected to the first potential region 11 and the second potential region 12. The field electrode 25 overlaps with the portion where the n-type region 10 is located in the third direction Z. In the present embodiment, the field electrode 25 does not overlap with the channel region 18 in the third direction Z. The field electrode 25 includes, for example, polysilicon. The field electrode 25 is electrically connected to at least the drain region 15. In the present embodiment, the field electrode 25 forms a potential gradient that gradually changes from the first potential region 11 toward the second potential region 12. By providing such a field electrode 25, the bias of the electric field distribution in the n-type region 10 is suppressed. The thickness of the field electrode 25 is, for example, 50 nm or more and 100 nm or less.

[0035] As shown in FIG. 2, the field electrode 25 has an operating region OR located between the drain region 15 and the source region 17, and a termination region TR located outside the operating region OR in a plan view. In the present embodiment, the operating region OR of the field electrode 25 is located between a pair of termination regions TR in the first direction X. Also, each termination region TR is located outside the operating region OR in the first direction X. In other words, each termination region TR is located outside the operating region OR in a direction intersecting or orthogonal to the current path. Alternatively, it can be said that one of the termination regions TR is located between the drain region 15 and the third region 16C of the body region 16 in a plan view, and the other termination region TR is located between the drain region 15 and the fourth region 16D of the body region 16 in a plan view.

[0036] The operation region OR is a region including a portion of the field electrode 25 that overlaps the current path. In a plan view, one end of the operation region OR in the first direction X is located between one end 17a of the source region 17 and one end 15a of the drain region 15 in the first direction X, but is not limited thereto. For example, as shown in FIG. 2, in a plan view, one end of the operation region OR in the first direction X may be aligned with one end 17a of the source region 17 in the first direction X, or may be aligned with one end 15a of the drain region 15 in the first direction X, or may be aligned with one end of the straight portion of the drain region 15 in the first direction X. Also, in a plan view, the other end of the operation region OR in the first direction X is located between the other end 17b of the source region 17 and the other end 15b of the drain region 15 in the first direction X, but is not limited thereto. For example, in a plan view, the other end of the operation region OR in the first direction X may be aligned with the other end 17b of the source region 17 in the first direction X, or may be aligned with the other end 15b of the drain region 15 in the first direction X, or may be aligned with the other end of the straight portion of the drain region 15 in the first direction X. Note that the one end of the operation region OR corresponds to the boundary between the operation region OR and one of the terminal regions TR, and overlaps the boundary between each first region 22c and one of the second regions 22d of the insulating film 22 in the first direction X.

[0037] The whole or most of each terminal region TR is a region including a portion of the field electrode 25 that does not overlap the current path. The field electrode 25 is routed linearly on the insulating film 22.

[0038] The field electrode 25, for example, surrounds the first potential region 11 including the drain region 15 a plurality of times in a concentric shape in a plan view. In the present embodiment, the field electrode 25 has a spiral shape surrounding the first potential region 11 in a plan view. The field electrode 25 has a first end 26 located in the vicinity of the drain region 15, a second end 27 located in the vicinity of the body region 16, and a spiral portion 28 extending between the first end 26 and the second end 27. The arrangement of the first end 26 and the second end 27 is arbitrary.

[0039] The first end portion 26 is a connection portion electrically connected to the drain region 15 and is the innermost portion (innermost peripheral portion) in the field electrode 25. The potential applied to the first end portion 26 is the first potential or a potential in the vicinity thereof. The second end portion 27 is the outermost portion (outermost peripheral portion) in the field electrode 25. The potential applied to the second end portion 27 is the second potential or a potential in the vicinity thereof. The second end portion 27 may overlap the drift region 13 in the third direction Z. The spiral portion 28 is a portion (connection portion) connecting the first end portion 26 and the second end portion 27, and is wound in an oval spiral shape from the first end portion 26 toward the second end portion 27 so as to surround the drain region 15 in plan view.

[0040] The field electrode 25 forms a potential gradient in the spiral direction from the first end portion 26 toward the second end portion 27. Further, the field electrode 25 forms a potential gradient that gradually decreases according to the winding pitch of the spiral portion 28 from the first potential region 11 toward the second potential region 12 in a direction orthogonal to the spiral direction. The field electrode 25 thins out the electric field in the drift region 13 and suppresses the deviation of the electric field distribution in the drift region 13.

[0041] The field electrode 25 may have a line width of 0.5 μm or more and 5 μm or less. The line width is defined by the width in a direction orthogonal to the extending direction (that is, the spiral direction) of the field electrode 25. The field electrode 25 may have a resistance value of 10 MΩ or more and 100 MΩ or less. The line width of the first line portion 25a and the line width of the second line portion 25b may each be substantially constant.

[0042] The pitch of the field electrode 25 may be 1 μm or more and 10 μm or less. The pitch of the field electrode 25 is defined by the distance between adjacent line portions (that is, the winding pitch of the spiral portion 28). The number of windings of the field electrode 25 is, for example, 5 or more and 100 or less. The number of windings may be 75 or less, or may be 50 or less.

[0043] The semiconductor device 1A includes an inner field electrode 29 that is located on the insulating film 22 and is connected to the field electrode 25. The inner field electrode 29 is located closer to the drain region 15 than the field electrode 25 in a plan view. In the present embodiment, the inner field electrode 29 is located in a region surrounded by the field electrode 25 in a plan view. The potential of the inner field electrode 29 is fixed to the first potential. The inner field electrode 29 may be a part of the field electrode 25. In this case, the inner field electrode 29 functions as the innermost peripheral portion of the field electrode 25. The inner field electrode 29 includes, for example, the same material as the field electrode 25.

[0044] The inner field electrode 29 is disposed at a position spaced apart from the drain region 15 in a plan view. In the present embodiment, the inner field electrode 29 has an oval ring shape surrounding the drain region 15. The inner field electrode 29 may overlap the well region 14 in the third direction Z. The width of the inner field electrode 29 is, for example, 1 μm or more and 15 μm or less. The inner field electrode 29 may be formed wider than the field electrode 25. In this case, the width of the inner field electrode 29 is, for example, 1.5 times or more and 5 times or less the width of the field electrode 25. Note that the width of the inner field electrode 29 may be equal to or less than the line width of the field electrode 25.

[0045] The semiconductor device 1A includes a gate insulating film 31 that contacts the first semiconductor region 6 and is located on the channel region 18. A part of the gate insulating film 31 overlaps the insulating film 22. The thickness of the gate insulating film 31 is less than the thickness of the insulating film 22 and is, for example, 10 nm or more and 200 nm or less. The gate insulating film 31 has a single-layer structure or a stacked structure and includes, for example, a silicon oxide film. In the present embodiment, the gate insulating film 31 has an oval ring shape surrounding the insulating film 22 in a plan view. The gate insulating film 31 covers a part of the drift region 13 and a part of the body region 16.

[0046] The semiconductor device 1A includes a gate electrode 32 positioned on the gate insulating film 31. The gate electrode 32 includes, for example, a metal film, an alloy film, conductive polysilicon, etc. When the gate electrode 32 includes conductive polysilicon, the conductive polysilicon includes at least one of an n-type region and a p-type region. The gate electrode 32 overlaps not only the channel region 18 but also the drift region 13 in the third direction Z. The gate electrode 32 has an oval ring shape extending along the channel region 18 in plan view, but is not limited thereto. The gate electrode 32 has a lead-out portion 33 drawn out from above the gate insulating film 31 onto the insulating film 22. The lead-out portion 33 has an oval ring shape surrounding a field electrode 25 to be described later in plan view and is positioned on the drift region 13. Also, the entire gate electrode 32 is positioned outside the field electrode 25 in plan view.

[0047] The gate electrode 32 includes an inner edge portion 32a and an outer edge portion 32b. The inner edge portion 32a is formed by the lead-out portion 33. The outer edge portion 32b is positioned in a region overlapping the body region 16 in plan view. In this embodiment, the width of the gate electrode 32 is non-uniform along the circumferential direction, but is not limited thereto. Specifically, as shown in FIG. 2, the gate electrode 32 has a gate overhang portion 34 that protrudes toward the drain region 15 at the outer edge portion 32b (lead-out portion 33). The gate overhang portion 34 is a portion provided according to the shape of the field electrode 25 to be described later. By providing the gate overhang portion 34, the distance between the gate electrode 32 and the field electrode 25 is kept substantially constant in plan view.

[0048] The first semiconductor region 6 includes a plurality of RESURF regions 20 located in a part of the surface layer 13a of the drift region 13. The plurality of RESURF regions 20 are located below the first region 22c of the insulating film 22. On the other hand, the plurality of RESURF regions 20 are not located below the second region 22d of the insulating film 22. A part of the plurality of RESURF regions 20 is located in the region between the well region 14 and the first region 16A of the body region 16, and another part of the plurality of RESURF regions 20 is located in the region between the well region 14 and the second region 16B of the body region 16. The plurality of RESURF regions 20 are not provided in the region between the well region 14 and the third region 16C of the body region 16, and the region between the well region 14 and the fourth region 16D of the body region 16. Each of the plurality of RESURF regions 20 is provided on the surface and in the vicinity thereof in the drift region 13, and exhibits a line shape extending along the second direction Y in a plan view. The plurality of RESURF regions 20 not only contact the insulating film 22 but may also contact the gate insulating film 31. Each of the plurality of RESURF regions 20 is provided, for example, in the region between the well region 14 and the body region 16, and forms a current path continuously extending between the well region 14 and the body region 16. The RESURF region 20 may contact the well region 14 or the body region 16. The plurality of RESURF regions 20 may be provided between the drain region 15 and the source region 17. Note that the surface layer 13a of the drift region 13 is located within the drift region 13 and is a portion including the surface 6a of the first semiconductor region 6 and the vicinity thereof. The thickness of the surface layer 13a is, for example, 1 μm or more and 5 μm or less. The thickness of the surface layer 13a may correspond to the thickness of the RESURF region 20.

[0049] Each of the plurality of RESURF regions 20 indicates an n-type. The n-type impurity concentration of each RESURF region 20 is higher than the n-type impurity concentration of the drift region 13 and lower than the n-type impurity concentration of the well region 14. The n-type impurity concentration of each RESURF region 20 may be 3.0×10 15 cm -3 or more and 5.0×10 17 cm -3 or less. Further, the RESURF region 20 and the impurity region 81 described later can be formed simultaneously.

[0050] The semiconductor device 1A includes an insulating layer 40 that covers a plurality of device regions 8. The insulating layer 40 has a stacked structure including a plurality of interlayer insulating films 41 stacked on one another. The number of stacked interlayer insulating films 41 is arbitrary and is not limited to a specific value. The insulating layer 40 may include three or more interlayer insulating films 41. In FIG. 4, a first interlayer insulating film 41A and a second interlayer insulating film 41B among the plurality of interlayer insulating films 41 are shown.

[0051] The first interlayer insulating film 41A and the second interlayer insulating film 41B are stacked in order in the third direction Z. The first interlayer insulating film 41A covers at least the surface 6a of the first semiconductor region 6, the insulating film 22, the gate insulating film 31, and the gate electrode 32. The second interlayer insulating film 41B covers the first interlayer insulating film 41A. Each of the thickness of the first interlayer insulating film 41A and the thickness of the second interlayer insulating film 41B is determined according to, for example, the function required for the field electrode 25, the thickness of the insulating film 22, and the like. Each of the first interlayer insulating film 41A and the second interlayer insulating film 41B includes at least one of a silicon oxide film and a silicon nitride film. For this reason, each of the first interlayer insulating film 41A and the second interlayer insulating film 41B may have a single-layer structure or a stacked structure.

[0052] A plurality of wiring films 42 are provided in the insulating layer 40. In the present embodiment, the plurality of interlayer insulating films 41 and the plurality of wiring films 42 are alternately stacked, and thus a multilayer wiring structure is provided on the first semiconductor region 6. The number of stacked wiring films 42 is arbitrary and is not limited to a specific value. In FIG. 4, among the plurality of wiring films 42, a first wiring film 42A located on the first interlayer insulating film 41A and a second wiring film 42B located on the second interlayer insulating film 41B are shown. Each wiring film 42 includes at least one of, for example, an Al film, a Cu film, an AlSiCu alloy film, an AlSi alloy film, and an AlCu alloy film. For this reason, each of the first wiring film 42A and the second wiring film 42B may have a single-layer structure or a stacked structure.

[0053] Inside the insulating layer 40, a plurality of first vias 43 and a plurality of second vias 49 are provided. Each of the plurality of first vias 43 is a conductive part that electrically connects conductive parts such as a first potential region 11, a second potential region 12, and a field electrode 25 located under the first interlayer insulating film 41A and the first wiring film 42A, and penetrates the first interlayer insulating film 41A. Each of the plurality of second vias 49 is a conductive part that electrically connects a conductive part such as the first wiring film 42A located under the second interlayer insulating film 41B, for example, and the second wiring film 42B, and penetrates the second interlayer insulating film 41B. Each of the plurality of first vias 43 and the plurality of second vias 49 is, for example, a tungsten plug.

[0054] The first wiring film 42A includes, for example, a first drain wiring 44, a first source wiring 45, a first gate wiring 46, a field wiring 47, and a field wiring 48. The first drain wiring 44 is electrically connected to the drain region 15 through one or more first vias 43. The first source wiring 45 is electrically connected to the source region 17 through one or more first vias 43. The first gate wiring 46 is electrically connected to the gate electrode 32 through one or more first vias 43. The field wiring 47 is electrically connected to the first end portion 26 of the field electrode 25 through one or more first vias 43. The field wiring 47 is electrically connected to the inner field electrode 29 through one or more first vias 43, for example. The field wiring 47 may be a part of the first drain wiring 44. The field wiring 48 is electrically connected to the second end portion 27 of the field electrode 25 through one or more first vias 43. The field wiring 48 may be a part of the first source wiring 45.

[0055] The plurality of second wiring films 42B includes, for example, a second drain wiring 50, a second source wiring 51, and a second gate wiring (not shown). The second drain wiring 50 is electrically connected to the first drain wiring 44 and the field wiring 47 via a plurality of second vias 49. The second drain wiring 50 overlaps with the drain region 15 and the field wiring 47. The second drain wiring 50 may overlap with the entire area of the drain region 15 and the entire area of the field wiring 47. The second drain wiring 50 may overlap with the inner field electrode 29. The second source wiring 51 is electrically connected to the first source wiring 45 and the field wiring 48 via a plurality of second vias 49. The second source wiring 51 has an annular shape extending along the body region 16 in a plan view. The second source wiring 51 may overlap with the gate electrode 32 and the field wiring 48. The second source wiring 51 may overlap with the entire area of the body region 16, the entire area of the gate electrode 32, and the entire area of the field wiring 48.

[0056] FIG. 5 is another enlarged view of region II shown in FIG. 1. FIG. 6 is a cross-sectional view taken along line VI-VI of FIG. 5. In FIG. 5, a portion located below the insulating film 22 in region II is shown. As shown in FIGS. 5 and 6, the first semiconductor region 6 includes a pair of inner regions IR that are located inside the second potential region 12 and outside the drift region 13 in a plan view. Therefore, each of the pair of inner regions IR is located below the second region 22d of the insulating film 22. One of the inner regions IR is surrounded by the drift region 13, the drain region 15, and the third region 16C in a plan view. The other inner region IR is surrounded by the drift region 13, the drain region 15, and the fourth region 16D in a plan view. In the present embodiment, each of the pair of inner regions IR has a semi-circular shape along the n-type region 10 in a plan view, but is not limited thereto. At least one of the pair of inner regions IR may have a polygonal shape (e.g., a rectangular shape) in a plan view, for example. In the present embodiment, one of the inner regions IR and the other inner region IR have the same shape as each other. Therefore, hereinafter, unless otherwise specified, one of the inner regions IR will be described, and the description of the other inner region IR will be omitted.

[0057] The inner region IR has a surface layer IR1 and a lower layer IR2 located below the surface layer IR1. The surface layer IR1 is located within the inner region IR and is a portion including the surface 6a of the first semiconductor region 6 and its vicinity. The thickness of the surface layer IR1 is, for example, about 1 μm. The lower layer IR2 is a portion of the first semiconductor region 6 that is within the inner region IR and is located below the surface layer IR1. In the inner region IR, the lower layer IR2 is located between the surface layer IR1 and the second semiconductor region 7 in the third direction Z.

[0058] A plurality of impurity regions 81 that are separated from the drift region 13 are provided in at least a part of the surface layer IR1. Therefore, the plurality of RESURF regions 20 located within the drift region 13 are separated from the plurality of impurity regions 81. The plurality of impurity regions 81 are provided in the inner region IR at the surface 6a of the first semiconductor region 6 and its vicinity. The plurality of impurity regions 81 can constitute a part of the surface 6a of the first semiconductor region 6. In this case, the impurity region 81 can be in contact with the insulating film 22. The width of the impurity region 81 is, for example, 0.5 μm or more and 5 μm or less. The thickness of the impurity region 81 is about the same as the thickness of the surface layer IR1.

[0059] Each of the plurality of impurity regions 81 has an arc shape in a plan view. The plurality of impurity regions 81 are arranged along the first direction X and are spaced apart from each other. Therefore, in the surface layer IR1, the impurity regions 81 and the regions where the impurity regions 81 are not provided are alternately arranged in the first direction X. For example, each of the plurality of impurity regions 81 has an arc shape along the shape of the third region 16C of the body region 16 and is located on a concentric circle centered on one end portion 15a of the drain region 15 in the first direction X, but is not limited thereto. From the viewpoint of improving the breakdown voltage of the semiconductor device 1A, etc., the interval S between two adjacent impurity regions 81 is constant, but is not limited thereto. The interval S is, for example, 0.5 μm or more and 5 μm or less. Each of the plurality of impurity regions 81 located in the other inner region IR described above has an arc shape along the shape of the fourth region 16D of the body region 16 and is located on a concentric circle centered on the other end portion 15b of the drain region 15 in the first direction X, but is not limited thereto.

[0060] Each of the plurality of impurity regions 81 has a first end portion 81a and a second end portion 82b. The first end portion 81a is located in the vicinity of the drift region 13 located between the drain region 15 and the first region 16A of the body region 16. The second end portion 81b is located in the vicinity of the drift region 13 located between the drain region 15 and the second region 16B of the body region 16.

[0061] The conductivity type of the impurity contained in the impurity region 81 is the same as the conductivity type of the impurity contained in the RESURF region 20 and is n-type. The n-type impurity concentration of the impurity region 81 is higher than the n-type impurity concentration of the lower layer IR2 of the inner region IR and lower than the n-type impurity concentration of the well region 14. The n-type impurity concentration of the impurity region 81 is, for example, 3.0×10 15 cm -3 or more and 5.0×10 17 cm -3 or less. The n-type impurity concentration may be 5.0×10 15 cm -3 or more, or may be 7.0×10 15 cm -3 or more, or may be 9.0×1015 cm -3 The above may also be applicable, or 3.25×10 17 cm -3 The following may also be applicable, or 1.0×10 17 cm -3 The following may also be applicable, or 8.0×10 16 cm -3 The following may also be applicable, or 6.0×10 16 cm -3 The following may also be applicable, or 4.8×10 16 cm -3 The following may also be applicable. From the perspective of simplifying the manufacturing process of the semiconductor device 1A, the n-type impurity concentration in the impurity region 81 may be the same as the n-type impurity concentration in the resurf region 20. Note that the n-type impurity concentration in the lower layer IR2 is, for example, the same as the n-type impurity concentration in the n-type region 10.

[0062] From the perspective of improving the breakdown voltage of the semiconductor device 1A, the average impurity concentration in the surface layer IR1 of the inner region IR is higher than the n-type impurity concentration in the lower layer IR2, and is 3.0×10 15 cm -3 or more and 2.4×10 16 cm -3 less than. The average impurity concentration may be 4.0×10 15 cm -3 or more, or 5.0×10 15 cm -3 or more, or 1.8×10 16 cm -3 or less, or 1.0×10 16 cm -3 or less. The average impurity concentration (AIC) of the surface layer IR1 is calculated by the following formula, where the area ratio of the impurity region 81 in the surface layer IR1 in plan view is ARa (%), the impurity concentration of the impurity region 81 is ICa (cm -3 ), the area ratio of the region other than the impurity region 81 in the surface layer IR1 in plan view is ARb (%), and the impurity concentration of the region is ICb (cm -3 ). Formula: AIC = ARa / 100×ICa + ARb / 100×ICb

[0063] In a plan view, the ratio (area ratio) in which the impurity region 81 is provided in the surface layer IR1 is, for example, 10% or more and 100% or less. The ratio is appropriately set according to the impurity concentration in the impurity region 81 and the average impurity concentration set in the inner region IR. For example, when the impurity concentration in the impurity region 81 is 4.0×10 16 cm -3 and the average impurity concentration is set to 2.0×10 16 cm -3 the area ratio of the impurity region 81 in the surface layer IR1 is 50%.

[0064] Next, with reference to FIGS. 7A to 7D, an example of a method for manufacturing a main part of the semiconductor device according to the present embodiment will be described. Each of FIGS. 7A to 7D is a cross-sectional view for explaining the method for manufacturing a main part of the semiconductor device according to the present embodiment.

[0065] First, as shown in FIG. 7A, a first semiconductor region 6, which is a semiconductor layer, is formed on a second semiconductor region 7, which is a semiconductor substrate (first step). In the first step, a first semiconductor region 6, which is an n-type semiconductor layer, is formed on the second semiconductor region 7. For example, the first semiconductor region 6 is epitaxially grown on the second semiconductor region 7. Thereby, a high-quality semiconductor layer is formed on the second semiconductor region 7. Note that, before the first step, the second semiconductor region 7 may be doped with a p-type impurity such as boron in advance. Thereby, a p-type impurity region 101, which will later become an element isolation region, a part of the first body region 16-1, the second body region 16-2, etc., is formed in the second semiconductor region 7.

[0066] Next, as shown in FIG. 7B, a first potential region 11 including a drain region 15 and a second potential region 12 surrounding the first potential region 11 in a plan view are formed in the first semiconductor region 6 (second step). In the second step, first, a part of the first semiconductor region 6 is doped with an n-type impurity such as phosphorus, and another part of the first semiconductor region 6 is doped with a p-type impurity. As a result, an n-type impurity region that will later become the well region 14 and a p-type impurity region that will later become another part of the first body region 16-1 and the second body region 16-2 are formed in the first semiconductor region 6. Subsequently, a high-concentration n-type impurity is doped into a part of the n-type impurity region and a part of the p-type impurity region. Thereby, the well region 14 and the drain region 15 are formed. At this time, although not shown, a source region and the like are also formed. Then, a high-concentration p-type impurity is doped into another part of the p-type impurity region provided in the first semiconductor region 6. Thereby, the body region 16 and the contact region 19 are formed. After the second step, although not shown, a drift region 13 (see FIG. 3 etc.) located inside the second potential region 12 in a plan view and between the drain region 15 and the source region 17 (see FIG. 3 etc.), and an inner region IR located inside the second potential region 12 in a plan view and outside the drift region 13 are formed in the first semiconductor region 6.

[0067] Next, as shown in FIG. 7C, a plurality of impurity regions 81 are formed in at least a part of the surface layer IR1 of the inner region IR of the first semiconductor region 6 (third step). In the third step, at least a part of the surface layer IR1 is doped with an n-type impurity. In this embodiment, a part of the surface layer IR1 is doped with an n-type impurity. As a result, the plurality of impurity regions 81 are formed at equal intervals along the second direction Y. Although not shown, in the third step, a part of the surface layer 13a (see FIG. 3 etc.) of the drift region 13 may be doped with an n-type impurity to form a resurf region 20 (see FIG. 3 etc.) in the surface layer 13a. In this case, the plurality of impurity regions 81 and the resurf region 20 can be formed during the third step. In other words, the plurality of impurity regions 81 and the resurf region 20 can be formed simultaneously.

[0068] Next, as shown in FIG. 7D, after the formation of the impurity region 81, an insulating film 22 is formed on the first semiconductor region 6 (fourth step). In the fourth step, for example, an insulating film 22 which is a LOCOS film is formed by selective oxidation of the first semiconductor region 6. In this case, the thickness of the plurality of impurity regions 81 (that is, the thickness of the surface layer IR1) is thinned. Therefore, the thickness of the impurity region 81 formed in the third step may be the value obtained by adding in advance the decrease due to the formation of the insulating film 22.

[0069] Then, a gate insulating film 31, a gate electrode 32, a field electrode 25, a first interlayer insulating film 41A, a second interlayer insulating film 41B, etc., which are not shown, are formed by a known method. Thus, the semiconductor device 1A is manufactured.

[0070] The operation and effect achieved by the semiconductor device 1A according to the present embodiment described above will be described with reference to FIG. 8. FIG. 8 is a diagram showing the simulation result of the current-voltage characteristics of the semiconductor device. In FIG. 8, the vertical axis represents the drain current, and the horizontal axis represents the drain voltage. The plot line L1 shows the current-voltage characteristics when the average impurity concentration of the surface layer IR1 is 3.0×10 15 cm -3 . The plot line L4 shows the current-voltage characteristics when the average impurity concentration of the surface layer IR1 is 2.4×10 16 cm -3 . Each of the plot lines L2 and L3 shows the current-voltage characteristics when the average impurity concentration of the surface layer IR1 is not less than L1 and less than L4. As shown in FIG. 8, when impurities are implanted into the surface layer IR1 of the inner region IR of the semiconductor device 1A, the breakdown voltage tends to be improved compared to the case where no impurities are implanted into the surface layer IR1. However, when the average impurity concentration of the surface layer IR1 exceeds a predetermined value, the breakdown voltage tends to decrease compared to the case where no impurities are implanted into the surface layer IR1. According to FIG. 8, when the average impurity concentration of the surface layer IR1 is 2.4×10 16 cm -3 , the breakdown voltage of the semiconductor device 1A decreases compared to the case where no impurities are implanted into the surface layer IR1.

[0071] Here, in the semiconductor device 1A manufactured by the above manufacturing method according to the present embodiment, the first semiconductor region 6 has an inner region IR that is located inside the second potential region 12 and outside the drift region 13 in a plan view. An impurity region 81 that is separated from the drift region 13 is provided in the surface layer IR1 in the inner region IR, and the average impurity concentration of the surface layer IR1 is 2.4×10 16 cm -3 or less. As a result, it becomes possible to improve the breakdown voltage of the semiconductor device 1A without expanding the inner region IR located outside the drift region 13. Rather, it becomes possible to improve the breakdown voltage of the semiconductor device 1A while reducing the inner region IR. Therefore, in the present embodiment, it is possible to achieve miniaturization while ensuring the breakdown voltage.

[0072]

[0073] In one example, the inner region IR has a lower layer IR2 located below the surface layer IR1, and the average impurity concentration of the surface layer IR1 may be higher than the impurity concentration of the lower layer IR2. In this case, it becomes difficult for a leakage current to occur through the lower layer IR2. 15 cm -3 In one example, the average impurity concentration of the surface layer IR1 may be 3.0×10 16 cm -3 or more and less than 2.4×10

[0074] 15 cm -3 In one example, the impurity concentration of the impurity region 81 may be 3.0×10 16 cm -3 or more and 4.8×10

[0075]

[0076] In one example, the ratio of the surface layer IR1 where the impurity region 81 is provided may be 10% or more and 100% or less. In this case, it becomes easy to control the average impurity concentration of the surface layer IR1 within a predetermined range.In one example, a plurality of impurity regions 81 are provided in the surface layer IR1 of the inner region IR, and at least a part of the plurality of impurity regions 81 may have an arc shape in a plan view and be arranged along the first direction X. Further, each of the plurality of impurity regions 81 has an arc shape in a plan view and is arranged along the first direction X, and the interval between two adjacent impurity regions 81 may be constant. Thereby, the stepwise change of the potential in the inner region IR is made better.

[0077] In one example, the first semiconductor region 6 is located in a part of the surface layer 13a of the drift region 13 and further has a RESURF region 20 separated from the impurity region 81. The conductivity type of the impurity contained in the RESURF region 20 is the same as the conductivity type of the impurity contained in the impurity region 81, and the impurity concentration of the RESURF region 20 may be higher than the impurity concentration of the drift region 13 and the same as the impurity concentration of the impurity region 81.

[0078] In one example, in the step of forming the impurity region 81, a RESURF region 20 that is located in a part of the surface layer 13a of the drift region 13 and separated from the impurity region 81 may be formed simultaneously with the formation of the impurity region 81. Thereby, the impurity region 81 and the RESURF region 20 can be formed in the same step. Therefore, an improvement in manufacturing efficiency can be realized.

[0079] In one example, an insulating film 22 may be formed on the first semiconductor region 6 after the formation of the impurity region 81. In this case, the impurity region 81 can be accurately formed in the surface layer IR1.

[0080] Hereinafter, a modification of the above-described embodiment will be described. In the description of the modification, the description overlapping with the above-described embodiment will be omitted, and the different parts will be described. That is, within the technically possible range, the description of the above-described embodiment may be appropriately used for the modification.

[0081] FIG. 9 is an enlarged view of a main part of a semiconductor device according to a first modification of the embodiment. As shown in FIG. 9, the semiconductor device 1B according to the first modification is different from the semiconductor device 1A of the above embodiment in that it includes a plurality of impurity regions 82 instead of the plurality of impurity regions 81. The plurality of impurity regions 82 and a surface region 20 (not shown) are separated from each other. The plurality of impurity regions 82 are scattered in the surface layer IR1 in a plan view. In the present embodiment, the plurality of impurity regions 82 are in a dot shape in a plan view and are arranged in a lattice pattern, but it is not limited thereto. The impurity region 82 may be circular, polygonal, elliptical, or linear in a plan view.

[0082] Also in the first modification described above, the same operational effects as those of the above embodiment are achieved.

[0083] FIG. 10 is an enlarged view of a main part of a semiconductor device according to a second modification of the embodiment. As shown in FIG. 10, the semiconductor device 1C according to the first modification is different from the semiconductor device 1A of the above embodiment in that it includes an impurity region 83 instead of the impurity region 81. The impurity region 83 and a surface region 20 (not shown) are separated from each other. The plurality of impurity regions 83 are scattered in the surface layer IR1 of the inner region IR in a plan view. In the present embodiment, the plurality of impurity regions 83 are in a dot shape in a plan view and are arranged in a staggered pattern, but it is not limited thereto. The impurity region 83 may be circular, polygonal, elliptical, or linear in a plan view.

[0084] Also in the second modification described above, the same operational effects as those of the above embodiment are achieved.

[0085] As described above, the embodiments and modifications of the present disclosure have been described, but the present disclosure can be implemented in other forms as well. Also, the above embodiment and each of the above modifications may be appropriately combined with each other. For example, the above embodiment and the above first modification or the above second modification may be combined. For example, at least one of the plurality of impurity regions 81 and the plurality of impurity regions 82 and the plurality of impurity regions 83 may be provided on the surface layer of the inner region.

[0086] In the above-described embodiments and the above-described modifications, a configuration in which the conductivity types of various semiconductor regions are inverted may be adopted. That is, a p-type portion may be made n-type, and an n-type portion may be made p-type. In this case, the source region may be included in the first potential region, and the drain region may be included in the second potential region.

[0087] In the above-described embodiments and the above-described modifications, although a MISFET is formed in the transistor region, the present invention is not limited thereto. For example, a JFET having a field plate shown in the above-described embodiments or the like may be formed in the transistor region. Even in this case, the same operational effects as those in the above-described embodiments or the like can be exhibited.

[0088] In the above-described embodiments and the above-described modifications, the semiconductor device can be applied to a power module used in an inverter circuit that drives an electric motor used as a power source for, for example, an automobile (including an electric vehicle), a train, an industrial robot, an air conditioner, an air compressor, a fan, a vacuum cleaner, a dryer, a refrigerator, or the like. Further, the semiconductor device can also be applied to a power module used in an inverter circuit of a solar cell, a wind power generator, or other power generation devices. Alternatively, the semiconductor device can also be applied to a circuit module that constitutes an analog control power supply, a digital control power supply, or the like.

[0089] As described above, the embodiments and modifications according to one aspect of the present disclosure have been described in detail, but these are merely specific examples used to clarify the technical content of the present disclosure, and the present disclosure should not be construed as being limited to these specific examples. The scope of the present disclosure is limited only by the appended claims.

[0090] Hereinafter, characteristic examples extracted from the descriptions of this specification and the drawings are shown.

[0091] [A1] A semiconductor substrate, A semiconductor layer located on the semiconductor substrate, Comprising, The semiconductor layer is, a first potential region including a drain region extending in a first direction in a plan view; a second potential region surrounding the first potential region in a plan view and including a source region aligned with the drain region in a second direction intersecting the first direction; a drift region located inside the second potential region in a plan view and positioned between the drain region and the source region; a semiconductor device having, in a plan view, an inner region located inside the second potential region and outside the drift region; an impurity region separated from the drift region is provided in at least a part of a surface layer of the inner region; the average impurity concentration of the surface layer is less than 2.4×10 16 cm -3 ;

[0092] [A2] the inner region has a lower layer located below the surface layer; the semiconductor device according to [A1], wherein the average impurity concentration of the surface layer is higher than the impurity concentration of the lower layer.

[0093] [A3] the average impurity concentration of the surface layer is 3.0×10 15 cm -3 or more and less than 2.4×10 16 cm -3 ; the semiconductor device according to [A1] or [A2].

[0094] [A4] the impurity concentration of the impurity region is 3.0×10 15 cm -3 or more and 4.8×10 16 cm -3 or less; the semiconductor device according to any one of [A1] to [A3].

[0095] [A5] the ratio of the surface layer where the impurity region is provided is 10% or more and 100% or less; the semiconductor device according to any one of [A1] to [A4].

[0096] [A6] A plurality of the impurity regions are provided on the surface layer of the inner region, and at least a part of the plurality of the impurity regions has an arc shape in a plan view and is arranged along the first direction. The semiconductor device according to any one of [A1] to [A5].

[0097] [A7] Each of the plurality of the impurity regions has an arc shape in a plan view and is arranged along the first direction, and the interval between two adjacent impurity regions is constant. The semiconductor device according to [A6].

[0098] [A8] A part of the plurality of the impurity regions is scattered on the surface layer in a plan view. The semiconductor device according to [A6].

[0099] [A9] A plurality of the impurity regions are provided on the surface layer of the inner region, and the plurality of the impurity regions are scattered on the surface layer in a plan view. The semiconductor device according to any one of [A1] to [A5].

[0100] [A10] The semiconductor layer is located at a part of the surface layer of the drift region and further has a RESURF region separated from the impurity region, and the conductivity type of the impurity contained in the RESURF region is the same as the conductivity type of the impurity contained in the impurity region, and the impurity concentration of the RESURF region is higher than the impurity concentration of the drift region and is the same as the impurity concentration of the impurity region. The semiconductor device according to any one of [A1] to [A9].

[0101] [A11] A step of forming a semiconductor layer on a semiconductor substrate, forming a first potential region including a drain region extending in a first direction in the semiconductor layer, a second potential region surrounding the first potential region in plan view and including a source region aligned with the drain region in a second direction intersecting the first direction, a drift region located inside the second potential region in plan view and between the drain region and the source region, and an inner region located inside the second potential region in plan view and outside the drift region; forming an impurity region spaced apart from the drift region in at least a part of a surface layer of the inner region; comprising; wherein an average impurity concentration of the surface layer is less than 2.4×10 16 cm -3 a method of manufacturing a semiconductor device.

[0102] [A12] wherein the inner region has a lower layer located below the surface layer, and the average impurity concentration of the surface layer is higher than an impurity concentration of the lower layer, the method of manufacturing a semiconductor device according to [A11].

[0103] [A13] wherein the average impurity concentration of the surface layer is 3.0×10 15 cm -3 or more and less than 2.4×10 16 cm -3 the method of manufacturing a semiconductor device according to [A11] or [A12].

[0104] [A14] in the step of forming the impurity region, a RESURF region located in a part of a surface layer of the drift region and spaced apart from the impurity region is formed simultaneously with the formation of the impurity region, the method of manufacturing a semiconductor device according to [A11] to [A13].

[0105] [A15] after the formation of the impurity region, an insulating film is formed on the semiconductor layer, the method of manufacturing a semiconductor device according to [A11] to [A14].

Description of Reference Numerals

[0106] 1A, 1B, 1C... semiconductor device, 2... chip, 3... first main surface, 4... second main surface, 5A... first side surface, 5B... second side surface, 5C... third side surface, 5D... fourth side surface, X... first direction, Y... second direction, Z... third direction, 6... first semiconductor region, 6a... surface, 7... second semiconductor region, 8... device region, 9... transistor region, 10... n-type region, 11... first potential region, 12... second potential region, 13... drift region, 13a... surface layer, 14... well region, 15... drain region, 15a... one end portion, 15b... other end portion, 16... body region, 16A... first region, 16B... second region, 16C... third region, 16D... fourth region, 17... source region, 18... channel region, 19... contact region, 20... resurf region, 22... insulating film, 22c... first region, 22d... second region, 25... field electrode, 28... spiral portion, 29... inner field electrode, 31... gate insulating film, 32... gate electrode, 33... lead-out portion, 34... gate overhang portion, 40... insulating layer, 41... interlayer insulating film, 41A... first interlayer insulating film, 41B... second interlayer insulating film, 42... wiring film, 42A... first wiring film, 42B... second wiring film, 43... first via, 49... second via, 44... first drain wiring, 45... first source wiring, 46... first gate wiring, 47, 48... field wiring, 50... second drain wiring, 51... second source wiring, 81~83... impurity region, 81a... first end portion, 81b... second end portion, II, III... region, IR... inner region, IR1... surface layer, IR2... lower layer, OR... operation region, TR... terminal region, L1, L2, L3, L4... plot line.

Claims

1. A semiconductor substrate, A semiconductor layer located on the semiconductor substrate, Comprising, The semiconductor layer, A first potential region including a drain region extending in a first direction in a plan view, A second potential region surrounding the first potential region in a plan view and including a source region aligned with the drain region in a second direction intersecting the first direction, A drift region located inside the second potential region in a plan view and located between the drain region and the source region, In a plan view, an inner region located inside the second potential region and located outside the drift region, and having, At least a part of the surface layer of the inner region is provided with an impurity region separated from the drift region, The average impurity concentration of the surface layer is 2.4×10 １６ cm －３ less than, a semiconductor device.

2. The inner region has a low layer located below the surface layer, The average impurity concentration of the surface layer is higher than the impurity concentration of the low layer. The semiconductor device according to claim 1.

3. The average impurity concentration of the surface layer is 3.0×10 １５ cm －３ or more and 2.4×10 １６ cm －３ less than that. The semiconductor device according to claim 1 or 2.

4. The impurity concentration in the impurity region is 3.0×10 １５ cm －３ or more and 4.8×10 １６ cm －３ or less. The semiconductor device according to claim 1 or 2.

5. The ratio of the surface layer where the impurity region is provided is 10% or more and 100% or less. The semiconductor device according to claim 1 or 2.

6. A plurality of the impurity regions are provided on the surface layer of the inner region, At least a part of the plurality of impurity regions has an arc shape in a plan view and is arranged along the first direction. The semiconductor device according to claim 1 or 2.

7. Each of the plurality of impurity regions has an arc shape in a plan view and is arranged along the first direction, The interval between two adjacent impurity regions is constant. The semiconductor device according to claim 6.

8. A part of the plurality of impurity regions is scattered on the surface layer in a plan view. The semiconductor device according to claim 6.

9. A plurality of the impurity regions are provided on the surface layer of the inner region, The plurality of impurity regions are scattered on the surface layer in a plan view. The semiconductor device according to claim 1 or 2.

10. The semiconductor layer is located on a part of the surface layer of the drift region and further has a RESURF region separated from the impurity region, The conductivity type of the impurity included in the RESURF region is the same as the conductivity type of the impurity included in the impurity region, The impurity concentration of the RESURF region is higher than the impurity concentration of the drift region and the same as the impurity concentration of the impurity region. The semiconductor device according to claim 1 or 2.

11. A step of forming a semiconductor layer on a semiconductor substrate, forming, in the semiconductor layer, a first potential region including a drain region extending in a first direction, a second potential region surrounding the first potential region in a plan view and including a source region aligned with the drain region in a second direction intersecting the first direction, a drift region positioned inside the second potential region in the plan view and between the drain region and the source region, and an inner region positioned inside the second potential region in the plan view and outside the drift region; forming an impurity region separated from the drift region in at least a part of a surface layer of the inner region; comprising; The average impurity concentration of the surface layer is less than 2.4×10 １６ cm －３ A method for manufacturing a semiconductor device.

12. the inner region has a lower layer positioned below the surface layer; the method of manufacturing a semiconductor device according to claim 11, wherein an average impurity concentration of the surface layer is higher than an impurity concentration of the lower layer.

13. The average impurity concentration of the surface layer is 3.0 × 10 １５ cm －３ or more and 2.4 × 10 １６ cm －３ less than that, and the method for manufacturing a semiconductor device according to claim 11 or 12.

14. in the step of forming the impurity region, a RESURF region positioned in a part of a surface layer of the drift region and separated from the impurity region is formed simultaneously with the formation of the impurity region, the method of manufacturing a semiconductor device according to claim 11 or 12.

15. an insulating film is formed on the semiconductor layer after the formation of the impurity region, the method of manufacturing a semiconductor device according to claim 11 or 12.

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