Semiconductor device and manufacturing method for semiconductor device

Abstract

To provide a semiconductor device in which the decrease in withstanding voltage can be suppressed and the decrease in on resistance can be reduced, and a manufacturing method for the semiconductor device.SOLUTION: A semiconductor device includes a semiconductor layer 4 existing on a semiconductor substrate 3, a gate insulating film 18 existing on the semiconductor layer 4, and a gate 19 existing on the gate insulating film 18. The semiconductor layer 4 includes a source region 14, a drain region 15 arranged beside the source region 14 in a first direction X, and a drift region 16 existing at least between the source region 14 and the drain region 15. The gate insulating film 18 includes a first insulating part 18a and a second insulating part 18b that is thinner than the first insulating part 18a. The drift region 16 includes a first region 16a overlapping with the first insulating part 18a in a thickness direction, and a second region 16b overlapping with the second insulating part 18b in the thickness direction. The impurity concentration of the second region 16b is higher than that of the first region 16a.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device.

Background Art

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor layer of a first conductivity type, a body region of a second conductivity type formed in the semiconductor layer, a source region of the first conductivity type formed in the body region, a drain region of the first conductivity type formed in the semiconductor layer, and a gate electrode facing a channel region between the source region and an outer edge of the body region. The gate electrode includes a first edge adjacent to the source region, and a first opening formed in a portion spaced apart from the first edge toward the drain region or a recess formed by selectively recessing the first edge toward the drain region. In this semiconductor device, the body region selectively has a portion exposed to the first opening or the recess of the gate electrode, and includes a body contact region of the second conductivity type formed in the portion of the body region exposed to the first opening or the recess and having an impurity concentration higher than that of the body region.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] An object according to one aspect of the present disclosure is to provide a semiconductor device and a method of manufacturing the semiconductor device capable of achieving both suppression of breakdown voltage reduction and reduction of on-resistance.

[0005] A semiconductor device according to one aspect of the present disclosure includes a semiconductor substrate, a semiconductor layer located on the semiconductor substrate, a gate insulating film located on the semiconductor layer, and a gate located on the gate insulating film. The semiconductor layer includes a source region, a drain region aligned with the source region in a first direction, and a drift region located at least between the source region and the drain region. The gate insulating film includes a first insulating portion and a second insulating portion thinner than the first insulating portion. The drift region includes a first region overlapping the first insulating portion in the thickness direction of the semiconductor substrate and a second region overlapping a part of the second insulating portion in the thickness direction. The impurity concentration of the second region is higher than the impurity concentration of the first region.

[0006] A method for manufacturing a semiconductor device according to another aspect of the present disclosure includes a first step of forming a semiconductor layer including a drift region on a semiconductor substrate, a second step of selectively forming a first insulating film on the semiconductor layer, and a third step of forming a second insulating film covering the first insulating film and then patterning the second insulating film to form a gate insulating film including a first insulating portion and a second insulating portion thinner than the first insulating portion. A fourth step of forming a gate on the gate insulating film, and a fifth step of introducing an impurity into a part of a portion overlapping the second insulating portion in the drift region. And a sixth step of forming a source region and a drain region in the semiconductor layer. After the fifth step, in the drift region, a first region into which no impurity is introduced and a second region into which an impurity is introduced and which is in contact with the drain region are formed. The impurity concentration of the second region is higher than the impurity concentration of the first region.

Brief Description of the Drawings

[0007]

Figure 1

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[0008] [Detailed Description] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, the same reference numerals will be used for the same elements or elements having the same function, and redundant descriptions will be omitted. The terms "identical" and similar terms in this specification are not limited to "exactly identical". Also, since the drawings are for conceptually explaining the embodiments, the dimensions and ratios of the components shown may be different from the actual ones.

[0009] FIG. 1 is a schematic perspective view showing a semiconductor device according to the present embodiment. FIG. 2 is a schematic plan view of a main part of the first element region. FIG. 3 is a partially cutaway perspective sectional view of a region surrounded by the dashed-dotted line III shown in FIG. 2. FIG. 4 is a schematic sectional view taken along line A-A of FIG. 3. FIG. 5 is a schematic sectional view taken along line B-B of FIG. 3.

[0010] As shown in FIG. 1, the semiconductor device 1 includes, for example, a chip-shaped integrated circuit (IC) device. The semiconductor device 1 may be referred to as SSI (Small Scale IC), MSI (Middle Scale IC), LSI (Large Scale IC), VLSI (Very Large Scale IC), ULSI (Ultra Large Scale IC), etc., based on the number of circuit elements to be integrated. In the present embodiment, the semiconductor device 1 has a rectangular parallelepiped shape, but is not limited thereto. The semiconductor device 1 has a first main surface 1A and a second main surface 1B which are a pair of main surfaces, and a first side surface 1C, a second side surface 1D, a third side surface 1E, and a fourth side surface 1F that connect the first main surface 1A and the second main surface 1B. Hereinafter, the extending direction of the first side surface 1C and the second side surface 1D in plan view is defined as the first direction X, the extending direction of the third side surface 1E and the fourth side surface 1F in plan view is defined as the second direction Y, and the normal direction of the first main surface 1A and the second main surface 1B is defined as the third direction Z. The second direction Y is a direction that intersects the first direction X in plan view, and the third direction Z corresponds to the thickness direction of the semiconductor device 1. Note that the “plan view” in this specification corresponds to viewing from the third direction Z.

[0011] In the present embodiment, the first main surface 1A is the upper surface, and the second main surface 1B is the bottom surface. Therefore, a configuration located near the first main surface 1A in the third direction Z corresponds to a configuration located on the top surface side (upper side) of the semiconductor device 1, and a configuration located near the second main surface 1B in the third direction Z corresponds to a configuration located on the bottom surface side (lower side) of the semiconductor device 1.

[0012] The semiconductor device 1 is formed on a common semiconductor substrate 3 shown in FIG. 3 and the like, and has a plurality of element regions 2 including circuit elements (not shown). Each of the plurality of element regions 2 includes a functional device formed using regions inside and outside the semiconductor device 1. The functional device includes, for example, at least one of a semiconductor switching device, a semiconductor rectifying device, and a passive device. The functional device may include a circuit network in which at least two of a semiconductor switching device, a semiconductor rectifying device, and a passive device are combined. The semiconductor switching device includes, for example, at least one of a bipolar transistor, a MISFET (Metal Insulator Semiconductor Field Effect Transistor), a BJT (Bipolar Junction Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET. The semiconductor rectifying device may include at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The passive device may include at least one of a resistor, a capacitor, an inductor, and a fuse.

[0013] The plurality of element regions 2 include, for example, a first element region 2A and a plurality of second element regions 2B. The first element region 2A is, for example, an element region including LDMOS (Lateral double-diffused MOS) as a circuit element. The plurality of second element regions 2B are, for example, regions including circuit elements such as a protection diode for LDMOS, a resistor, and a capacitor. In FIG. 1, four element regions 2 are shown, but the semiconductor device 1 may have five or more element regions. Although not shown, each of the plurality of element regions 2 is surrounded by an element isolation region in a plan view. For example, a strip-shaped element isolation well region forming a closed curve in a plan view may be formed to reach the semiconductor substrate 3 (see FIG. 3 and the like).

[0014] The semiconductor device 1 has a semiconductor substrate 3 and a semiconductor layer 4. The semiconductor substrate 3 has a first conductivity type and is a region fixed at a predetermined potential, and extends along the second main surface 1B. The thickness of the semiconductor substrate 3 is, for example, 50 μm or more and 400 μm or less. The semiconductor substrate 3 is exposed, for example, from the first side surface 1C, the second side surface 1D, the third side surface 1E, and the fourth side surface 1F. In the present embodiment, the semiconductor substrate 3 is fixed at a back gate potential. The back gate potential may be a reference potential that serves as a reference for circuit operation or a ground potential. In the present embodiment, the first conductivity type is p-type, and the semiconductor substrate 3 is at least a part of a p-type semiconductor substrate.

[0015] The semiconductor layer 4 is located on the semiconductor substrate 3 and has a layer shape. The semiconductor layer 4 is, for example, an epitaxial semiconductor layer using the semiconductor substrate 3 as a seed. The thickness of the semiconductor layer 4 is, for example, 5 μm or more and 20 μm or less. The semiconductor layer 4 has a second conductivity type. The impurity concentration of the semiconductor layer 4 is, for example, 1.0×10 14 cm -3 or more and 1.0×10 16 cm -3 or less. In the present embodiment, the second conductivity type is n-type, and the semiconductor layer 4 is an n-type semiconductor layer.

[0016] As shown in FIG. 2, a plurality of LDMOSs including the LDMOS 100 are formed in the first element region 2A. The shapes of the respective LDMOSs included in the first element region 2A are substantially the same as each other. Therefore, hereinafter, only the LDMOS 100 will be mainly described. In FIG. 2, an interlayer insulating film (not shown) formed on the semiconductor layer 4, wirings (not shown) connected to the LDMOS 100, etc. are omitted. Note that the breakdown voltage of the LDMOS 100 in the off state is set to, for example, 10 V or more and 50 V or less.

[0017] As shown in FIGS. 2 to 5, the LDMOS 100 provided in the first element region 2A includes an embedded region 11, a body region 12, source regions 13 and 14, a drain region 15, a drift region 16, a contact region 17, a gate insulating film 18, a gate 19, a protective film 20, a first contact 21, a second contact 22, and a third contact 23. The body region 12, the source regions 13 and 14, the drain region 15, the drift region 16, and the contact region 17 are included in the semiconductor layer 4. The gate insulating film 18, the gate 19, and the protective film 20 are located on the semiconductor layer 4.

[0018] The embedded region 11 is a region selectively formed at least in the first element region 2A and has a second conductivity type. A part of the embedded region 11 is included in the semiconductor substrate 3. Another part of the embedded region 11 is included in the semiconductor layer 4. Therefore, the embedded region 11 is formed so as to straddle the boundary between the semiconductor substrate 3 and the semiconductor layer 4. The thickness of the embedded region 11 is, for example, 1 μm or more and 3 μm or less. The embedded region 11 is separated from the body region 12, the drift region 16, etc.

[0019] The body region 12 is a region selectively formed in the semiconductor layer 4 and has a first conductivity type. The body region 12 has, for example, an oval ring shape that extends along the second direction Y and surrounds the source regions 13 and 14 in a plan view and is in contact with the source region 13. Therefore, a part 12a of the body region 12 is located closer to the drain region 15 than the source region 14. The part 12a is provided at least on the surface of the semiconductor layer 4 and can form a part of the current path of the LDMOS 100. The dimension of the body region 12 along the third direction Z is, for example, 0.1 μm or more and 3 μm or less. The body region 12 is electrically connected to the semiconductor substrate 3, for example, and is fixed to the potential of the semiconductor substrate 3 (for example, the back gate potential). The impurity concentration of the body region 12 is, for example, 1.0×10 16 cm -3 or more and 1.0×10 18 cm -3The following applies. Note that the body region 12 may have a polygonal ring shape such as an elliptical ring shape or a square ring shape in a plan view.

[0020] The source region 13 (second source region) is a region selectively formed within the body region 12 and has a second conductivity type. The source region 13 has, for example, an oval ring shape surrounding the source region 14 in a plan view and is in contact with the source region 14. For this reason, a part 13a of the source region 13 is located closer to the drain region 15 than the source region 14. The part 13a is provided at least on the surface of the semiconductor layer 4 and can form a part of the current path of the LDMOS 100. The source region 13 is separated from the bottom surface and the side surface of the body region 12. For this reason, the dimension of the source region 13 along the third direction Z is shorter than the dimension of the body region 12 along the third direction Z, and is, for example, 0.05 μm or more and 0.2 μm or less. The impurity concentration of the source region 13 is, for example, 1.0×10 17 cm -3 or more and 1.0×10 19 cm -3 or less. Note that the source region 13 may have a polygonal ring shape such as an elliptical ring shape or a square ring shape in a plan view.

[0021] The source region 14 (first source region) is a region selectively formed within the source region 13 and has a second conductivity type. The source region 14 has, for example, an oval ring shape surrounded by the gate 19 and surrounding the contact region 17 in a plan view. The source region 14 is fixed to the source potential. For example, the source potential is applied to the source region 14 from the outside via the first contact 21 and the contact region 17. The source region 14 may have a polygonal ring shape such as an elliptical ring shape or a square ring shape in a plan view. The source region 14 is provided at least on the surface of the semiconductor layer 4 and is separated from the body region 12. For this reason, the dimension of the source region 14 along the third direction Z is shorter than the dimension of the source region 13 along the third direction Z, and is, for example, 0.1 μm or more and 0.5 μm or less. The impurity concentration of the source region 14 is higher than the impurity concentration of the source region 13. The impurity concentration of the source region 14 is, for example, 1.0×1018 cm -3 is 1.0×10 21 cm -3 or less below.

[0022] The drain region 15 is a region that is selectively formed in the semiconductor layer 4 and aligned with the source region 14 in the first direction X, and has a second conductivity type. In plan view, the drain region 15 is located outside the gate 19 and has a strip shape extending along the second direction Y. The drain region 15 functions as the drain of the LDMOS 100 and also functions as the drain of another LDMOS. The drain region 15 has, for example, a rectangular shape in plan view. The drain region 15 may have a polygonal shape such as a circular shape, an elliptical shape, or a triangular shape in plan view. The drain region 15 is provided at least on the surface of the semiconductor layer 4. The dimension of the drain region 15 along the third direction Z is approximately the same as the dimension of the source region 14 along the third direction Z, and is, for example, 0.1 μm or more and 0.5 μm or less. The impurity concentration of the drain region 15 is, for example, the same as the impurity concentration of the source region 14. The impurity concentration of the drain region 15 is, for example, 1.0×10 18 cm -3 is 1.0×10 21 cm -3 or less below.

[0023] The drift region 16 is a region that is selectively formed in the semiconductor layer 4 and has a second conductivity type. The drift region 16 is located at least between the source region 14 and the drain region 15 in the first direction X. In the present embodiment, the drift region 16 surrounds the drain region 15 in plan view and is in contact with the drain region 15. The drift region 16 is in contact with the bottom surface 15a of the drain region 15. Further, the drift region 16 is separated from the body region 12. The dimension of the drift region 16 along the third direction Z is approximately the same as the dimension of the body region 12 along the third direction Z, and is, for example, 0.1 μm or more and 0.5 μm or less. Details of the drift region 16 will be described later.

[0024] The contact region 17 is a region selectively formed within the body region 12, is in contact with the source region 14, and has a first conductivity type. The contact region 17 is, for example, surrounded by the source region 14 in plan view and is located at the center of the body region 12, and has an oval shape extending along the second direction Y. The positions of both ends of the contact region 17 in the second direction Y are substantially aligned with the positions of both ends of the drain region 15 in the second direction Y in the first direction X, but are not limited thereto. The bottom surface 17a of the contact region 17 is in contact with the source region 13. On the other hand, the contact region 17 is separated from the body region 12. The contact region 17 is provided at least on the surface of the semiconductor layer 4. The impurity concentration of the contact region 17 may be higher than the impurity concentration of the body region 12. For example, the impurity concentration of the contact region 17 is, for example, 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less.

[0025] The gate insulating film 18 is an insulating layer provided on the surface of the semiconductor layer 4 and is located between the semiconductor layer 4 and the gate 19. The gate insulating film 18 is formed of at least silicon oxide. For example, the gate insulating film 18 may have a portion formed only of silicon oxide and a portion formed of silicon oxide and silicon oxynitride (SiON). The gate insulating film 18 includes a first insulating portion 18a, and a second insulating portion 18b and a third insulating portion 18c that are thinner than the first insulating portion 18a.

[0026] The first insulating portion 18a is, for example, a laminated portion of the gate insulating film 18. In the present embodiment, the first insulating portion 18a includes, for example, a surface oxide film (LOCOS film: Local oxidation of silicon film) formed by selective oxidation of the semiconductor layer 4, an underlying layer such as a buried oxide film (STI: Shallow Trench Isolation) that fills a shallow trench provided in the semiconductor layer 4, and an upper layer that is an insulating layer formed on the underlying layer. The upper layer is formed, for example, by patterning a deposited film formed by a known method such as CVD. The thickness of the underlying layer is, for example, 50 nm or more and 500 nm or less, and the thickness of the upper layer is, for example, 50 nm or more and 500 nm or less. Therefore, the thickness of the first insulating portion 18a is, for example, 50 nm or more and 500 nm or less. The edge of the first insulating portion 18a has a tapered shape, but is not limited thereto. The dimension of the first insulating portion 18a along the first direction X is, for example, 0.5 μm or more and 5 μm or less. In the present embodiment, in the first element region 2A, the gate insulating film 18 includes two first insulating portions 18a. In this case, the dimension of each first insulating portion 18a along the second direction Y is, for example, 0.5 μm or more and 5 μm or less.

[0027] Each of the second insulating portion 18b and the third insulating portion 18c is, for example, a single-layer portion of the gate insulating film 18. In the present embodiment, each of the second insulating portion 18b and the third insulating portion 18c has only the above-described underlying layer. Therefore, the thickness of each of the second insulating portion 18b and the third insulating portion 18c corresponds to the thickness of the above-described underlying layer. Also, each of the second insulating portion 18b and the third insulating portion 18c can be said to be a portion of the gate insulating film 18 where the above-described upper layer is not formed.

[0028] The second insulating portion 18b is a part of the portion of the gate insulating film 18 that overlaps with the drift region 16 and is adjacent to the first insulating portion 18a in the second direction Y. The second insulating portion 18b may also overlap with a region of the semiconductor layer 4 that is located between the body region 12 and the drift region 16 in the first direction X. In the present embodiment, the second insulating portion 18b is sandwiched between two first insulating portions 18a in the second direction Y. In addition, each first insulating portion 18a and the second insulating portion 18b are provided continuously. The second insulating portion 18b is adjacent to the third insulating portion 18c in the first direction X. Therefore, one end of the second insulating portion 18b in the first direction X is in contact with the third insulating portion 18c. In the first direction X, the second insulating portion 18b is located closer to the drain region 15 than the third insulating portion 18c. The dimension of the second insulating portion 18b along the first direction X is shorter than the dimension of the first insulating portion 18a along the first direction X, and is, for example, 0.2 μm or more and 2 μm or less. Thus, the other end of the second insulating portion 18b in the first direction X is located closer to the source region 14 than the portion of the first insulating portion 18a that is closest to the drain region 15. From the viewpoint of on-resistance, the dimension of the second insulating portion 18b along the first direction X may be 0.5 μm or more and 5 μm or less. From the viewpoint of breakdown voltage, the dimension of the second insulating portion 18b along the first direction X may be 0.5 μm or more and 5 μm or less. The dimension of the second insulating portion 18b along the second direction Y is, for example, 0.2 μm or more and 2 μm or less. Therefore, the ratio of the dimension of the second insulating portion 18b along the second direction Y to the dimension of the gate insulating film 18 along the second direction Y is, for example, 20% or more and 80% or less. From the viewpoint of on-resistance, the ratio may be 40% or more and 80% or less. From the viewpoint of breakdown voltage, the above ratio may be 20% or more and 60% or less.

[0029] The third insulating portion 18c is a portion of the gate insulating film 18 that overlaps a part 12a of the body region 12 and a part 13a of the source region 13, and is adjacent to the first insulating portion 18a and the second insulating portion 18b in the first direction X. The dimension of the third insulating portion 18c along the first direction X is, for example, 0.4 μm or more and 2 μm or less. Both ends of the third insulating portion 18c in the second direction Y correspond to, for example, both ends of the gate insulating film 18 in the second direction Y. The third insulating portion 18c may overlap a part of the source region 14.

[0030] In the gate insulating film 18, a recess 18d defined by the first insulating portion 18a and the second insulating portion 18b is provided in a plan view. The recess 18d corresponds to a depression that is recessed from the drain region 15 toward the source region 14 along the first direction X. Inside the recess 18d, the surface of the semiconductor layer 4, that is, the surface of the drift region 16, is exposed from the gate insulating film 18. From the viewpoint of on-resistance, the recess 18d has a rectangular shape in a plan view, but is not limited thereto. The dimension of the recess 18d along the first direction X, that is, the depth of the recess 18d, corresponds to the difference between the dimension of the first insulating portion 18a and the dimension of the second insulating portion 18b along the first direction X. The dimension of the recess 18d along the second direction Y corresponds to the dimension of the second insulating portion 18b along the second direction Y.

[0031] Gate 19 is a conductor located on gate insulating film 18 and has a frame shape surrounding source region 14 in plan view. Gate 19 includes, for example, a metal film, an alloy film, conductive polysilicon, etc. When gate 19 includes conductive polysilicon, from the perspective of the conductivity of gate 19, the conductive polysilicon may include one of impurities of the first conductivity type and impurities of the second conductivity type. A part of gate 19 is located between source region 14 and drain region 15 in the first direction X in plan view. At least a part of semiconductor layer 4 overlapping with gate 19 functions as the channel region of LDMOS 100. The channel region is located, for example, between source region 14 and drift region 16 within semiconductor layer 4. In the above channel region, conduction and non-conduction of the current path between source region 14 and drain region 15 are controlled according to the potential applied to gate 19.

[0032] Gate 19 has a first portion 19a overlapping a part of the first insulating portion 18a, a second portion 19b overlapping the second insulating portion 18b, and a third portion 19c overlapping the third insulating portion 18c. In the third direction Z, the distance between the first portion 19a and semiconductor layer 4 is larger than the distance between the second portion 19b and semiconductor layer 4 and the distance between the third portion 19c and semiconductor layer 4. Therefore, the influence on semiconductor layer 4 accompanying the potential change of gate 19 is greater below the second portion 19b and below the third portion 19c than below the first portion 19a. Thus, in LDMOS 100, a current path can be easily formed in the portion of semiconductor layer 4 overlapping with the second portion 19b and the portion overlapping with the third portion 19c.

[0033] The protective film 20 is a patterned insulating film that covers at least a part of the portion exposed from the gate insulating film 18 in the drift region 16. In addition, the protective film 20 covers a part of the gate insulating film 18 and a part of the gate 19. The protective film 20 is located closer to the drain region 15 than the body region 12 in the first direction X. The protective film 20 covers, for example, a part of the first insulating portion 18a of the gate insulating film 18, a part of the second insulating portion 18b of the gate insulating film 18, and the portion exposed from the recess 18d in the semiconductor layer 4. Also, the protective film 20 covers a part of the first portion 19a of the gate 19 and a part of the second portion 19b of the gate 19. On the other hand, the protective film 20 does not cover the third portion 19c of the gate 19. The protective film 20 is formed, for example, by patterning a deposited film formed by a known method such as CVD. The thickness of the protective film 20 is, for example, 10 nm or more and 100 nm or less. The protective film 20 is, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like. The protective film 20 may have a single-layer structure or a laminated structure.

[0034] The first contact 21 is a portion where a wiring (not shown) and the contact region 17 are connected, and is located on the contact region 17. The second contact 22 is a portion where a wiring (not shown) and the drain region 15 are connected, and is located on the drain region 15. The third contact 23 is a portion where a wiring (not shown) and the gate 19 are connected, and is located on the gate 19. Each of the first contact 21, the second contact 22, and the third contact is, for example, an opening formed in an interlayer insulating film (not shown), and is filled with a conductor such as the above-mentioned wiring.

[0035] Next, the details of the drift region 16 described above will be explained. As shown in FIGS. 2 to 5, the drift region 16 includes a first region 16a that overlaps with the first insulating portion 18a in the third direction Z and a second region 16b that overlaps with a part of the second insulating portion 18b in the third direction Z. The ratio (volume %) occupied by the first region 16a in the drift region 16 is larger than the ratio occupied by the second region 16b in the drift region 16. For example, the ratio of the volume of the second region 16b to the volume of the first region 16a is 10% or more and 50% or less. As shown in FIG. 2, a part of the second region 16b is included in the LDMOS 100, and another part of the second region 16b is included in another LDMOS. The same applies to the first region 16a. The above-mentioned part is a part that overlaps with the drain region 15 in the first direction X and a part closer to the source region 14 than the drain region 15. The above-mentioned other part is a part located on the opposite side of the source region 14 via the drain region 15 in the first direction X. Hereinafter, only the parts of the first region 16a and the second region 16b included in the LDMOS 100 will be described.

[0036] The first region 16a is in contact with a part of the drain region 15. As shown in FIGS. 2 and 3, the first region 16a is in contact with the side surfaces and the bottom surface 15a at both ends of the drain region 15 in the second direction Y. The interval S1 along the first direction X from the portion 16c closest to the body region 12 in the first direction X in the first region 16a to the drain region 15 is, for example, -1 μm or more and 2 μm or less. That is, the portion 16c can be provided within the drain region 15. The dimension of the first region 16a along the third direction Z corresponds to the dimension of the drift region 16 along the third direction Z. The impurity concentration of the first region 16a is higher than the impurity concentration of the semiconductor layer 4, for example, 1.0×10 17 cm -3 or more and 1.0×10 19 cm -3 or less.

[0037] The second region 16b is an area surrounded by the first region 16a in a plan view, and has a strip shape extending along the first direction X. The second region 16b is provided at least on the surface of the semiconductor layer 4 and is covered by the protective film 20. The second region 16b is in contact with another part of the drain region 15. As shown in FIGS. 2 and 3, the second region 16b is in contact with the side surface and the bottom surface 15a of the central portion of the drain region 15 in the second direction Y. The interval S2 along the first direction X from the portion 16d closest to the body region 12 in the first direction X of the second region 16b to the drain region 15 is, for example, -1 μm or more and 2 μm or less. That is, the portion 16d may be provided within the drain region 15. The portion 16d overlaps the protective film 20 in the third direction Z in addition to the second insulating portion 18b and the gate 19, but is not limited thereto. The portion 16d may be located between the portion 16c of the first region 16a and the protective film 20 in the first direction X.

[0038] The second region 16b is adjacent to the first region 16a in the second direction Y. The dimension of the second region 16b along the second direction Y corresponds to the dimension of the recess 18d along the second direction Y, but is not limited thereto. The dimension of the second region 16b along the second direction Y may be larger or smaller than the dimension of the recess 18d along the second direction Y. The conductivity of the second region 16b is higher than that of the first region 16a. For this reason, in the drift region 16, current flows more easily in the second region 16b than in the first region 16a. In addition, the interval from the second region 16b to the gate 19 along the third direction Z is shorter than the interval from the first region 16a to the gate 19 along the third direction Z. Therefore, when the potential of the gate 19 is low or when the potential difference between the source region 14 and the drain region 15 is low, current flows more easily in the second region 16b than in the first region 16a. The impurity concentration of the second region 16b is higher than the impurity concentration of the first region 16a, for example, 1.0×10 17 cm -3 or more and 1.0×10 19 cm -3 or less.

[0039] As described above, the first region 16a overlaps with the first insulating portion 18a, and a part of the second region 16b overlaps with the second insulating portion 18b. Therefore, the breakdown voltage of the portion of the semiconductor layer 4 that overlaps with the first region 16a is higher than the breakdown voltage of the portion of the semiconductor layer 4 that overlaps with the second region 16b.

[0040] In this embodiment, the bottom surface 16e of the second region 16b is in contact with the first region 16a. Therefore, the dimension of the second region 16b along the third direction Z is shorter than the dimension of the first region 16a along the third direction Z, for example, 0.1 μm or more and 2 μm or less. From the viewpoint of on-resistance, the dimension of the second region 16b along the third direction Z is, for example, 0.5 μm or more and 2 μm or less. From the viewpoint of reducing leakage current, the dimension of the second region 16b along the third direction Z is, for example, 0.1 μm or more and 1 μm or less.

[0041] Next, with reference to FIGS. 6A to 6H, an example of a method for manufacturing a semiconductor device according to this embodiment will be described. Each of FIGS. 6A to 6H is a schematic cross-sectional view for explaining an example of a method for manufacturing a semiconductor device according to this embodiment. In each of FIGS. 6A to 6H, two end faces EF1 and EF2 of the LDMOS 100 are shown. The end face EF1 corresponds to a part of the cross-section shown in FIG. 4, and the end face EF2 corresponds to the cross-section shown in FIG. 5.

[0042] First, as a preparation step, as shown in FIG. 6A, after doping a part of the semiconductor substrate 3 with impurities of the second conductivity type, a semiconductor layer 4 is formed on the semiconductor substrate 3. In the preparation step, for example, the semiconductor layer 4 is epitaxially grown on the semiconductor substrate 3. During the growth of the semiconductor layer 4, the above-mentioned impurities doped in the semiconductor substrate 3 diffuse into the semiconductor layer 4 due to heat treatment (annealing) of the semiconductor layer 4 performed after the growth of the semiconductor layer 4. As a result, an embedded region 11 is formed in the semiconductor substrate 3 and the semiconductor layer 4. Although not shown, in the preparation step, another part of the semiconductor substrate 3 is doped with impurities of the first conductivity type. The doping of the impurities of the first conductivity type may be performed before or after the doping of the impurities of the second conductivity type. A part of the impurities of the first conductivity type diffuses into the semiconductor layer 4 due to heat treatment (annealing) performed during or after the growth of the semiconductor layer 4. Note that the above annealing does not necessarily have to be performed.

[0043] Next, as shown in FIG. 6B, a body region 12 and a drift region 16 are formed in the semiconductor layer 4 (first step). In the first step, the body region 12 is formed by doping a part of the semiconductor layer 4 with impurities of the first conductivity type, and the drift region 16 is formed by doping another part of the semiconductor layer 4 with impurities of the second conductivity type. In the first step, the doping of the impurities of the second conductivity type may be performed after the doping of the impurities of the first conductivity type. Alternatively, the doping of the impurities of the first conductivity type may be performed after the doping of the impurities of the second conductivity type. In the first step, annealing is performed on the semiconductor layer 4 after the above doping is performed.

[0044] Next, as shown in FIG. 6C, a gate insulating film 18 is formed on the semiconductor layer 4. In forming the gate insulating film 18, first, a first insulating film is selectively formed on the semiconductor layer 4 (second step). In the second step, for example, a part of the surface of the semiconductor layer 4 is oxidized by a known method to selectively form the first insulating film. Subsequently, after forming a second insulating film covering the first insulating film, the second insulating film is patterned to form a gate insulating film 18 including a first insulating portion 18a, a second insulating portion 18b, and a third insulating portion 18c (third step). In the third step, first, the second insulating film is formed at least on the first insulating film by a known method such as CVD. Subsequently, a part of the second insulating film is etched. For example, a part of the second insulating film is etched by dry etching or wet etching using a resist mask.

[0045] Next, as shown in FIG. 6D, a gate 19 is formed on the gate insulating film 18 (fourth step). In the fourth step, first, a conductive layer is formed on the semiconductor layer 4 and the gate insulating film 18. In this embodiment, a polysilicon layer is formed as the conductive layer. Subsequently, after forming a mask M1 on the polysilicon layer, the conductive layer is selectively etched using the mask M1. The mask M1 is, for example, a positive or negative resist mask.

[0046] Next, as shown in FIG. 6E, impurities are introduced into a part of the portion in the drift region 16 that overlaps with the second insulating portion 18b (fifth step). In the fifth step, first, a mask M2 is formed to cover a part of the semiconductor layer 4, a part of the gate insulating film 18, and a part of the gate 19. At this time, for example, a part of the drift region 16 at the end face EF2 is exposed from the mask M2. Subsequently, the exposed portion of the semiconductor layer 4 from the mask M2 is doped with impurities of the second conductivity type. In the present embodiment, impurities of the second conductivity type are implanted into a part of the semiconductor layer 4 by inclined doping. As a result, not only the portion of the semiconductor layer 4 exposed from the gate insulating film 18 but also a part of the portion of the semiconductor layer 4 overlapping with the gate insulating film 18 and the gate 19 are doped with impurities of the second conductivity type. Then, after doping with impurities of the second conductivity type, a heat treatment is performed on the semiconductor layer 4. As a result, at least in the drift region 16 shown by the end face EF2, a first region 16a into which impurities of the second conductivity type are not introduced and a second region 16b into which the impurities are introduced are formed. Therefore, the impurity concentration of the second region 16b is higher than the impurity concentration of the first region 16a. In the present embodiment, the gate 19 is formed of a polysilicon layer. Therefore, in the fifth step, the exposed portion of the gate 19 from the mask M2 can also be doped with impurities of the second conductivity type. Note that the mask M2 is, for example, a positive or negative resist mask.

[0047] Although not shown, in the fifth step, another part of the semiconductor layer 4 is doped with impurities of the second conductivity type. For example, a part of the body region 12 is doped with impurities of the second conductivity type. As a result, after the fifth step, a source region 13 (see FIG. 3 etc.) may be formed. Similarly, in the fifth step, another part of the semiconductor layer 4 is doped with impurities of the first conductivity type. As a result, after the fifth step, an element isolation region (not shown) etc. are formed. At this time, a mask different from the mask M2 is used to form the element isolation region etc.

[0048] Next, as shown in FIG. 6F, a source region 14 and a drain region 15 are formed in the semiconductor layer 4 (the sixth step). In the sixth step, first, a mask M3 is formed to cover a part of the semiconductor layer 4, a part of the gate insulating film 18, and a part of the gate electrode 19. Subsequently, the exposed portion of the semiconductor layer 4 from the mask M3 is doped with impurities of the second conductivity type. Thereby, the source region 14 is formed in the body region 12, and the drain region 15 is formed in the drift region 16. On the end face EF1, the drain region 15 is formed in the first region 16a of the drift region 16, and on the end face EF2, the drain region 15 is formed in the second region 16b of the drift region 16. In the present embodiment, the gate electrode 19 is formed of a polysilicon layer. Therefore, in the sixth step, the exposed portion of the gate electrode 19 from the mask M3 can also be doped with impurities of the second conductivity type. Note that the mask M3 is, for example, a positive or negative photoresist.

[0049] Next, as shown in FIG. 6G, a contact region 17 is formed in the semiconductor layer 4 (the seventh step). In the seventh step, first, a mask M4 is formed to cover a part of the semiconductor layer 4, the gate insulating film 18, and the gate electrode 19. Subsequently, the exposed portion of the semiconductor layer 4 from the mask M4 is doped with impurities of the first conductivity type. Thereby, the contact region 17 is formed in the source region 13. Although not shown, in the seventh step, another part of the semiconductor layer 4 is doped with impurities of the first conductivity type. Thereby, after the seventh step, an element isolation region (not shown) and the like are formed.

[0050] Next, as shown in FIG. 6H, a protective film 20 is formed to cover at least a part of the semiconductor layer 4 and a part of the gate electrode 19 (the eighth step). In the eighth step, first, an insulating film is formed to cover the semiconductor layer 4 and the gate electrode 19. Next, the insulating film is patterned to form the protective film 20 that covers at least the portion exposed from the gate insulating film 18 in the second region 16b of the drift region 16.

[0051] Subsequently, an interlayer insulating film, wiring, vias, etc. (not shown) are formed and patterned on the semiconductor layer 4, on the gate insulating film 18, on the gate 19, on the protective film 20, etc. Through the above processes, the semiconductor device 1 including the LDMOS 100 (see FIG. 2) is manufactured.

[0052] Next, with reference to the comparative examples described below, the effects achieved by the semiconductor device 1 manufactured by the manufacturing method according to the present embodiment will be described. The LDMOS included in the semiconductor device according to the comparative example described below has the same configuration as the LDMOS 100 included in the semiconductor device 1 according to the present embodiment, except that the gate insulating film does not include the second insulating portion 18b shown in FIG. 3 etc., and the drift region includes only the first region.

[0053] According to the LDMOS 100 included in the semiconductor device 1 according to the present embodiment, the gate insulating film 18 located on the semiconductor layer 4 includes a first insulating portion 18a and a second insulating portion 18b thinner than the first insulating portion 18a. The drift region 16 in the semiconductor layer 4 includes a first region 16a overlapping the first insulating portion 18a in the third direction Z and a second region 16b overlapping a part of the second insulating portion 18b in the third direction Z. The impurity concentration of the second region 16b is higher than the impurity concentration of the first region 16a. As a result, when the LDMOS 100 is turned on, current flows more easily at a lower voltage in the portion of the second region 16b overlapping the gate 19 than in the portion of the first region 16a overlapping the gate 19. Therefore, the on-resistance of the LDMOS 100 according to the present embodiment can be reduced compared to the on-resistance of the LDMOS according to the above comparative example. For example, the on-resistance of the LDMOS 100 can be reduced by several tens of percent compared to the on-resistance of the LDMOS according to the above comparative example. In addition, in the LDMOS 100, the first region 16a of the drift region 16 overlaps the first insulating portion 18a. Thereby, the breakdown voltage of the LDMOS 100 in the off state can be ensured. Therefore, according to the present embodiment, it is possible to provide the semiconductor device 1 capable of achieving both suppression of breakdown voltage reduction and reduction of on-resistance.

[0054] In one example, the semiconductor device 1 includes a protective film 20 located on the semiconductor layer 4, and the protective film 20 covers a portion exposed from the gate insulating film 18 in the second region 16b. Thereby, damage to the second region 16b during the manufacture of the semiconductor device 1 or the like can be prevented. Further, the protective film 20 may cover a part of the gate 19.

[0055] In one example, the second region 16b is in contact with the drain region 15. Thereby, the on-resistance of the LDMOS 100 can be favorably reduced.

[0056] In one example, the bottom surface 16e of the second region 16b is in contact with the first region 16a. Thereby, the leakage current of the LDMOS 100 due to the presence of the second region 16b can be reduced.

[0057] In one example, the second insulating portion 18b is adjacent to the first insulating portion 18a in the second direction Y, and the second region 16b is adjacent to the first region 16a in the second direction Y. Thereby, it is possible to favorably achieve both reduction of the on-resistance of the LDMOS 100 and suppression of the breakdown voltage drop.

[0058] Hereinafter, a modification of the above-described embodiment will be described. In the description of the modification, descriptions overlapping with those of the above-described embodiment will be omitted, and different parts will be described. That is, within the technically possible range, the descriptions of the above-described embodiment may be appropriately used for the modification.

[0059] FIG. 7 is a schematic plan view of a main part of a first element region according to a modification of the above-described embodiment. As shown in FIG. 7, the LDMOS 100A provided in the first element region 2C according to the modification includes an embedded region, a body region, a source region (not shown), a source region 14A, a drain region 15A, a drift region 16A, a contact region 17A, a gate insulating film 18A, a gate 19, a first contact 21A, a second contact 22A, and a third contact 23.

[0060] In LDMOS100A, the source region 14A and the contact region 17A are located outside the gate 19 in a plan view, and the drain region 15A is surrounded by the gate 19 in a plan view. In other words, the drain region 15A of LDMOS100A is located at the position where the source region 14 of LDMOS100 according to the above embodiment is provided. The drain region 15A has an oval shape extending along the second direction Y in a plan view. Also, the source region 14A and the contact region 17A of LDMOS100A are located at the position where the drain region 15 of LDMOS100 is provided. Each of the source region 14A and the contact region 17A has a strip shape extending along the second direction Y in a plan view. In a plan view, the contact region 17A is sandwiched by the source region 14A in the first direction X. Both ends of the source region 14A in the second direction Y are aligned with both ends of the contact region 17A in the second direction Y, respectively, but are not limited thereto. Also, the positions of both ends of the source region 14A in the second direction Y are substantially aligned with the positions of both ends of the drain region 15A in the second direction Y in the first direction X, but are not limited thereto.

[0061] The shapes of the body region and the source region (not shown) included in LDMOS100A, the drift region 16A, and the gate insulating film 18A are different from the shapes of the body region 12, the source region 13, the drift region 16, and the gate insulating film 18A included in LDMOS100 according to the above embodiment, respectively. On the other hand, the drift region 16A includes a first region 16a and a second region 16b in the same manner as in the above embodiment, and the gate insulating film 18A includes a first insulating portion 18a, a second insulating portion 18b, and a third insulating portion 18c in the same manner as in the above embodiment. The positions where the first contact 21A and the second contact 22A included in LDMOS100A are provided are different from the positions where the first contact 21 and the second contact 22 included in LDMOS100 according to the above embodiment are provided, respectively.

[0062] The cross-sectional shape of the LDMOS100A according to the modified example described above is substantially the same as the cross-sectional shape of the LDMOS100 according to the above embodiment. Therefore, also in the above modified example, the same operational effects as those of the above embodiment are achieved.

[0063] As described above, the embodiments and modified examples of the present disclosure have been explained, but the present disclosure can also be implemented in other forms.

[0064] In the above embodiment and the above modified example, a configuration in which the conductivity types of various semiconductor regions are inverted may be adopted. That is, a p-type region may be made an n-type region, and an n-type region may be made a p-type region. Alternatively, the first conductivity type may be n-type and the second conductivity type may be p-type.

[0065] In the above embodiment and the above modified example, the gate insulating film of one LDMOS includes two first insulating portions and a second insulating portion sandwiched between the two first insulating portions, but is not limited thereto. For example, the gate insulating film of one LDMOS may include three or more first insulating portions and two or more second insulating portions. In this case, the first insulating portion and the second insulating portion may be alternately provided in the second direction, and in the drift region, the first region and the second region may be alternately provided in the second direction. In this case, current is less likely to concentrate on a specific portion of the LDMOS, and suppression of damage to the LDMOS can be realized.

[0066] In the above embodiment and the above modified example, the semiconductor device can be applied to a power module used in an inverter circuit that drives an electric motor used as a power source for, for example, an automobile (including an electric vehicle), a train, an industrial robot, an air conditioner, an air compressor, a fan, a vacuum cleaner, a dryer, a refrigerator, etc. Further, the semiconductor device can also be applied to a power module used in an inverter circuit of a solar cell, a wind power generator, or other power generation devices. Alternatively, the semiconductor device can also be applied to a circuit module that constitutes an analog control power supply, a digital control power supply, or the like.

[0067] As described above in detail are the embodiments and modifications according to one aspect of the present disclosure, but these are merely specific examples used to clarify the technical content of the present disclosure, and the present disclosure should not be construed as being limited to these specific examples. The scope of the present disclosure is limited only by the appended claims.

[0068] The following are characteristic examples extracted from the descriptions of this specification and the drawings.

[0069] [A1] A semiconductor substrate, A semiconductor layer located on the semiconductor substrate, A gate insulating film located on the semiconductor layer, A gate located on the gate insulating film, Comprising, The semiconductor layer includes a source region, a drain region aligned with the source region in a first direction, and a drift region located at least between the source region and the drain region. The gate insulating film includes a first insulating portion and a second insulating portion thinner than the first insulating portion. The drift region includes a first region overlapping the first insulating portion in the thickness direction of the semiconductor substrate and a second region overlapping a part of the second insulating portion in the thickness direction. The impurity concentration of the second region is higher than the impurity concentration of the first region. A semiconductor device.

[0070] [A2] Further comprising a protective film located on the semiconductor layer, The protective film covers at least a part of the portion exposed from the gate insulating film in the second region. The semiconductor device according to [A1].

[0071] [A3] The protective film covers a part of the gate. The semiconductor device according to [A2].

[0072] [A4] The second region is a semiconductor device according to any one of [A1] to [A3], which is in contact with the drain region.

[0073] [A5] The bottom surface of the second region is a semiconductor device according to any one of [A1] to [A4], which is in contact with the first region.

[0074] [A6] The second insulating portion is adjacent to the first insulating portion in a second direction orthogonal to the thickness direction and the first direction. The second region is a semiconductor device according to any one of [A1] to [A5], which is adjacent to the first region in the second direction.

[0075] [A7] In the gate insulating film, the first insulating portion and the second insulating portion are alternately provided in a second direction orthogonal to the thickness direction and the first direction. In the drift region, the first region and the second region are alternately provided in the second direction. The semiconductor device is according to any one of [A1] to [A6].

[0076] [A8] The impurity concentration of the first region is 1.0×10 15 cm -3 or more and 1.0×10 17 cm -3 or less. The impurity concentration of the second region is 1.0×10 17 cm -3 or more and 1.0×10 19 cm -3 or less. The semiconductor device is according to any one of [A1] to [A7].

[0077] [A9] The thickness of the first insulating portion is 50 nm or more and 500 nm or less. The thickness of the second insulating portion is 10 nm or more and 100 nm or less. The semiconductor device is according to any one of [A1] to [A8].

[0078] [A10] A first step of forming a semiconductor layer including a drift region on a semiconductor substrate; A second step of selectively forming a first insulating film on the semiconductor layer; After forming a second insulating film covering the first insulating film, by patterning the second insulating film, a third step of forming a gate insulating film including a first insulating portion and a second insulating portion thinner than the first insulating portion; A fourth step of forming a gate electrode on the gate insulating film; A fifth step of introducing an impurity into a part of a portion of the drift region that overlaps with the second insulating portion; A sixth step of forming a source region and a drain region in the semiconductor layer; comprising After the fifth step, in the drift region, a first region into which the impurity is not introduced and a second region into which the impurity is introduced and which is in contact with the drain region are formed; The impurity concentration of the second region is higher than the impurity concentration of the first region; A method for manufacturing a semiconductor device.

[0079] [A11] The method for manufacturing a semiconductor device according to [A10], wherein after the sixth step, a protective film is formed to cover a portion of the second region that is exposed from the gate insulating film.

[0080] [A12] In the drift region, the first region and the second region are alternately provided in a second direction orthogonal to a thickness direction of the semiconductor substrate and a first direction in which the source region and the drain region are arranged side by side. The method for manufacturing a semiconductor device according to claim 10 or 11.

Description of reference numerals

[0081] 1…Semiconductor device, 1A…First main surface, 1B…Second main surface, 1C…First side surface, 1D…Second side surface, 1E…Third side surface, 1F…Fourth side surface, 2…Element region, 2A, 2C…First element region, 2B…Second element region, 3…Semiconductor substrate, 4…Semiconductor layer, 11…Embedded region, 12…Body region, 13, 14, 14A…Source region, 15, 15A…Drain region, 15a…Bottom surface, 16, 16A…Drift region, 16a…First region, 16b…Second region, 16c…Portion, 16d…Portion, 16e…Bottom surface, 17, 17A…Contact region, 17a…Bottom surface, 18, 18A…Gate insulating film, 18a…First insulating portion, 18b…Second insulating portion, 18c…Third insulating portion, 18d…Recess, 19…Gate, 19a…First portion, 19b…Second portion, 19c…Third portion, 20…Protective film, 21, 21A…First contact, 22, 22A…Second contact, 100, 100A…LDMOS, M1~M4…Mask, S1, S2…Interval.

Claims

1. A semiconductor substrate, a semiconductor layer located on the semiconductor substrate, a gate insulating film located on the semiconductor layer, a gate located on the gate insulating film, comprising: the semiconductor layer includes a source region, a drain region aligned with the source region in a first direction, and a drift region located at least between the source region and the drain region, the gate insulating film includes a first insulating portion and a second insulating portion thinner than the first insulating portion, the drift region includes a first region overlapping the first insulating portion in the thickness direction of the semiconductor substrate and a second region overlapping a part of the second insulating portion in the thickness direction, the impurity concentration of the second region is higher than that of the first region, a semiconductor device.

2. further comprising a protective film located on the semiconductor layer, the protective film covers at least a part of a portion exposed from the gate insulating film in the second region, the semiconductor device according to claim 1.

3. the protective film covers a part of the gate, the semiconductor device according to claim 2.

4. the second region is in contact with the drain region, the semiconductor device according to any one of claims 1 to 3.

5. the bottom surface of the second region is in contact with the first region, the semiconductor device according to any one of claims 1 to 3.

6. the second insulating portion is adjacent to the first insulating portion in a second direction orthogonal to the thickness direction and the first direction, the second region is adjacent to the first region in the second direction, the semiconductor device according to any one of claims 1 to 3.

7. in the gate insulating film, the first insulating portion and the second insulating portion are alternately provided in a second direction orthogonal to the thickness direction and the first direction, in the drift region, the first region and the second region are alternately provided in the second direction, the semiconductor device according to any one of claims 1 to 3.

8. The impurity concentration in the first region is 1.0×10 １５ cm －３ or more and 1.0×10 １７ cm －３ or less, and The impurity concentration in the second region is 1.0×10 １７ cm －３ or more and 1.0×10 １９ cm －３ or less. The semiconductor device according to any one of claims 1 to 3.

9. the thickness of the first insulating portion is 50 nm or more and 500 nm or less, the thickness of the second insulating portion is 10 nm or more and 100 nm or less, the semiconductor device according to any one of claims 1 to 3.

10. a first step of forming a semiconductor layer including a drift region on a semiconductor substrate, a second step of selectively forming a first insulating film on the semiconductor layer, After forming a second insulating film covering the first insulating film, by patterning the second insulating film, a third step of forming a gate insulating film including a first insulating portion and a second insulating portion thinner than the first insulating portion is performed. A fourth step of forming a gate electrode on the gate insulating film. A fifth step of introducing an impurity into a part of the portion overlapping the second insulating portion in the drift region. A sixth step of forming a source region and a drain region in the semiconductor layer. The semiconductor device manufacturing method includes: After the fifth step, in the drift region, a first region into which the impurity is not introduced and a second region into which the impurity is introduced and which is in contact with the drain region are formed. The impurity concentration of the second region is higher than the impurity concentration of the first region. A method of manufacturing a semiconductor device.

11. After the sixth step, a protective film is formed to cover a portion of the second region that is exposed from the gate insulating film. The method of manufacturing a semiconductor device according to claim 10.

12. In the drift region, the first region and the second region are alternately provided in a second direction orthogonal to the thickness direction of the semiconductor substrate and a first direction in which the source region and the drain region are arranged side by side. The method of manufacturing a semiconductor device according to claim 10 or 11.

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