Semiconductor device and manufacturing method for semiconductor device

Abstract

To provide a semiconductor device in which the decrease in withstanding voltage can be suppressed and the decrease in on resistance can be reduced, and a manufacturing method for the semiconductor device.SOLUTION: A semiconductor device includes a semiconductor layer 4 existing on a semiconductor substrate 3, a gate insulating film 18 existing on the semiconductor layer 4, and a gate 19 existing on the gate insulating film 18. The semiconductor layer 4 includes a source region 14, a drain region 15, a drift region 16 existing at least between the source region 14 and the drain region 15, and a channel region C existing between the source region 14 and the drift region 16. The drift region 16 includes a plurality of first impurity regions 16b separated from the channel region C and having a first conductivity type, and a plurality of second impurity regions 16b separated from the channel region C and having a second conductivity type. The first impurity regions 16b and the second impurity regions 16c are arranged alternately along a second direction Y.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device.

Background Art

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor layer of a first conductivity type, a body region of a second conductivity type formed in the semiconductor layer, a source region of the first conductivity type formed in the body region, a drain region of the first conductivity type formed in the semiconductor layer, and a gate facing a channel region between the source region and an outer edge of the body region, the gate including a first edge adjacent to the source region, and a first opening formed in a portion spaced from the first edge toward the drain region or a recess formed by selectively recessing the first edge toward the drain region. In this semiconductor device, the body region selectively has a portion exposed to the first opening or the recess of the gate, and includes a body contact region of the second conductivity type formed in the portion of the body region exposed to the first opening or the recess and having an impurity concentration higher than that of the body region.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] An object according to one aspect of the present disclosure is to provide a semiconductor device and a method of manufacturing the semiconductor device capable of achieving both suppression of breakdown voltage reduction and reduction of on-resistance.

[0005] A semiconductor device according to one aspect of the present disclosure includes a semiconductor substrate, a semiconductor layer located on the semiconductor substrate in a thickness direction of the semiconductor substrate, a gate insulating film located on the semiconductor layer in the thickness direction, and a gate located on the gate insulating film in the thickness direction, wherein the semiconductor layer includes a source region, a drain region aligned with the source region in a first direction, a drift region located at least between the source region and the drain region, and a channel region located between the source region and the drift region, wherein the drift region includes a plurality of first impurity regions spaced apart from the channel region and having a first conductivity type, and a plurality of second impurity regions spaced apart from the channel region and having a second conductivity type different from the first conductivity type, and the plurality of first impurity regions and the plurality of second impurity regions are alternately arranged at least along the thickness direction and a second direction intersecting the first direction.

[0006] A method for manufacturing a semiconductor device according to another aspect of the present disclosure includes a first step of forming a drift region in a semiconductor layer located on a semiconductor substrate, a second step of forming a gate insulating film on the semiconductor layer, a third step of forming a gate on the gate insulating film, a fourth step of forming a plurality of first impurity regions having a first conductivity type in a part of the drift region, a fifth step of forming a plurality of second impurity regions having a second conductivity type different from the first conductivity type in another part of the drift region, and a sixth step of forming a source region in the semiconductor layer and a drain region aligned with the source region in a first direction, wherein the plurality of first impurity regions and the plurality of second impurity regions are alternately aligned at least along the thickness direction of the semiconductor substrate and a second direction intersecting the first direction. [Brief explanation of the drawings]

[0007]

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[0008] [Detailed Description] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, the same reference numerals will be used for the same elements or elements having the same function, and redundant descriptions will be omitted. The terms "identical" and similar words in this specification are not limited to "exactly the same". Also, since the drawings are for conceptually explaining the embodiments, the dimensions and ratios of the components shown may be different from the actual ones.

[0009] Fig. 1 is a schematic perspective view showing a semiconductor device according to this embodiment. Fig. 2 is a schematic plan view of a main part of a first element region. Fig. 3 is a partially cutaway perspective cross-sectional view of a region surrounded by a dashed dotted line III shown in Fig. 2. Fig. 4 is a schematic cross-sectional view taken along line AA in Fig. 3. Fig. 5 is a schematic cross-sectional view taken along line BB in Fig. 3.

[0010] As shown in FIG. 1, the semiconductor device 1 includes, for example, a chip-shaped integrated circuit (IC) device. The semiconductor device 1 may be referred to as an SSI (Small Scale IC), an MSI (Middle Scale IC), an LSI (Large Scale IC), a VLSI (Very Large Scale IC), an ULSI (Ultra Large Scale IC), or the like, depending on the number of circuit elements integrated therein. In this embodiment, the semiconductor device 1 has a rectangular parallelepiped shape, but is not limited thereto. The semiconductor device 1 has a pair of main surfaces, namely, a first main surface 1A and a second main surface 1B, and a first side surface 1C, a second side surface 1D, a third side surface 1E, and a fourth side surface 1F connecting the first main surface 1A and the second main surface 1B. Hereinafter, the extending direction of the first side surface 1C and the second side surface 1D in a plan view is referred to as the first direction X, the extending direction of the third side surface 1E and the fourth side surface 1F in a plan view is referred to as the second direction Y, and the normal direction of the first main surface 1A and the second main surface 1B is referred to as the third direction Z. The second direction Y is a direction intersecting the first direction X in a plan view, and the third direction Z corresponds to the thickness direction of the semiconductor device 1. In this specification, "plan view" corresponds to viewing from the third direction Z.

[0011] In this embodiment, the first main surface 1A is the top surface, and the second main surface 1B is the bottom surface. Therefore, a configuration located near the first main surface 1A in the third direction Z corresponds to a configuration located on the top surface side (upper side) of the semiconductor device 1, and a configuration located near the second main surface 1B in the third direction Z corresponds to a configuration located on the bottom surface side (lower side) of the semiconductor device 1.

[0012] The semiconductor device 1 is formed on a common semiconductor substrate 3 shown in FIG. 3 and the like, and has a plurality of element regions 2 including circuit elements (not shown). Each of the plurality of element regions 2 includes a functional device formed using regions inside and outside the semiconductor device 1. The functional device includes, for example, at least one of a semiconductor switching device, a semiconductor rectifying device, and a passive device. The functional device may include a circuit network in which at least two of a semiconductor switching device, a semiconductor rectifying device, and a passive device are combined. The semiconductor switching device includes, for example, at least one of a bipolar transistor, a MISFET (Metal Insulator Semiconductor Field Effect Transistor), a BJT (Bipolar Junction Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET. The semiconductor rectifying device may include at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The passive device may include at least one of a resistor, a capacitor, an inductor, and a fuse.

[0013] The plurality of element regions 2 include, for example, a first element region 2A and a plurality of second element regions 2B. The first element region 2A is, for example, an element region including LDMOS (Lateral double-diffused MOS) as a circuit element. The plurality of second element regions 2B are, for example, regions including circuit elements such as a protection diode for LDMOS, a resistor, and a capacitor. In FIG. 1, four element regions 2 are shown, but the semiconductor device 1 may have five or more element regions. Although not shown, each of the plurality of element regions 2 is surrounded by an element isolation region in a plan view. For example, a strip-shaped element isolation well region forming a closed curve in a plan view may be formed to reach the semiconductor substrate 3 (see FIG. 3 and the like).

[0014] The semiconductor device 1 has a semiconductor substrate 3 and a semiconductor layer 4. The semiconductor substrate 3 has a first conductivity type and is a region fixed at a predetermined potential, and extends along the second main surface 1B. The thickness of the semiconductor substrate 3 is, for example, 50 μm or more and 400 μm or less. The semiconductor substrate 3 is exposed, for example, from the first side surface 1C, the second side surface 1D, the third side surface 1E, and the fourth side surface 1F. In the present embodiment, the semiconductor substrate 3 is fixed at a back gate potential. The back gate potential may be a reference potential that serves as a reference for circuit operation, or may be a ground potential. In the present embodiment, the first conductivity type is p-type, and the semiconductor substrate 3 is at least a part of a p-type semiconductor substrate.

[0015] The semiconductor layer 4 is located on the semiconductor substrate 3 in the third direction Z and has a layer shape. The semiconductor layer 4 is, for example, an epitaxial semiconductor layer using the semiconductor substrate 3 as a seed. The thickness of the semiconductor layer 4 is, for example, 5 μm or more and 20 μm or less. The semiconductor layer 4 has a second conductivity type. The impurity concentration of the semiconductor layer 4 is, for example, 1.0×10 14 cm -3 or more and 1.0×10 16 cm -3 or less. In the present embodiment, the second conductivity type is n-type, and the semiconductor layer 4 is an n-type semiconductor layer.

[0016] As shown in FIG. 2, a plurality of LDMOSs including the LDMOS 100 are formed in the first element region 2A. The shapes of the respective LDMOSs included in the first element region 2A are substantially the same as each other. Therefore, hereinafter, only the LDMOS 100 will be mainly described. In FIG. 2, an interlayer insulating film (not shown) formed on the semiconductor layer 4, wiring (not shown) connected to the LDMOS 100, and the like are omitted. Note that the breakdown voltage of the LDMOS 100 in the off state is set to, for example, 10 V or more and 50 V or less.

[0017] 2 to 5, the LDMOS 100 provided in the first element region 2A has a buried region 11, a body region 12, source regions 13 and 14, a drain region 15, a drift region 16, a contact region 17, a gate insulating film 18, a gate 19, a protective film 20, a first contact 21, a second contact 22, and a third contact 23. The body region 12, the source regions 13 and 14, the drain region 15, the drift region 16, and the contact region 17 are included in the semiconductor layer 4. The gate insulating film 18, the gate 19, and the protective film 20 are located on the semiconductor layer 4 in the third direction Z.

[0018] The buried region 11 is a region selectively formed in at least the first element region 2A, and has the second conductivity type. A part of the buried region 11 is included in the semiconductor substrate 3. Another part of the buried region 11 is included in the semiconductor layer 4. Therefore, the buried region 11 is formed so as to straddle the boundary between the semiconductor substrate 3 and the semiconductor layer 4. The thickness of the buried region 11 is, for example, not less than 1 μm and not more than 3 μm. The buried region 11 is separated from the body region 12, the drift region 16, etc.

[0019] The body region 12 is a region selectively formed in the semiconductor layer 4 and has a first conductivity type. For example, in a plan view, the body region 12 has an oval ring shape extending along the second direction Y and surrounding the source regions 13, 14, and is in contact with the source region 13. Therefore, a portion 12a of the body region 12 is located closer to the drain region 15 than the source region 14. The portion 12a is provided at least on the surface of the semiconductor layer 4 and can form part of the current path of the LDMOS 100. The dimension of the body region 12 along the third direction Z is, for example, not less than 0.05 μm and not more than 0.2 μm. The body region 12 is, for example, electrically connected to the semiconductor substrate 3 and fixed to the potential of the semiconductor substrate 3 (for example, the back gate potential). The impurity concentration of the body region 12 is, for example, 1.0×10 17 cm -3 Over 1.0 x 10 19 cm -3It is as follows. Note that the body region 12 may have a polygonal ring shape such as an elliptical ring shape or a square ring shape in a plan view.

[0020] The source region 13 (second source region) is a region selectively formed within the body region 12 and has a second conductivity type. The source region 13 has, for example, an oval ring shape surrounding the source region 14 in a plan view and is in contact with the source region 14. For this reason, a part 13a of the source region 13 is located closer to the drain region 15 than the source region 14. The part 13a is provided at least on the surface of the semiconductor layer 4 and can form a part of the current path of the LDMOS 100. The source region 13 is separated from the bottom surface and the side surface of the body region 12. For this reason, the dimension of the source region 13 along the third direction Z is shorter than the dimension of the body region 12 along the third direction Z, and is, for example, 0.05 μm or more and 0.2 μm or less. The impurity concentration of the source region 13 is, for example, 1.0×10 17 cm -3 or more and 1.0×10 19 cm -3 or less. Note that the source region 13 may have a polygonal ring shape such as an elliptical ring shape or a square ring shape in a plan view.

[0021] The source region 14 (first source region) is a region selectively formed within the source region 13 and has a second conductivity type. The source region 14 has, for example, an oval ring shape surrounded by the gate 19 and surrounding the contact region 17 in a plan view. The source region 14 is fixed to the source potential. For example, the source potential is applied to the source region 14 from the outside via the first contact 21 and the contact region 17. The source region 14 may have a polygonal ring shape such as an elliptical ring shape or a square ring shape in a plan view. The source region 14 is provided at least on the surface of the semiconductor layer 4 and is separated from the body region 12. For this reason, the dimension of the source region 14 along the third direction Z is shorter than the dimension of the source region 13 along the third direction Z, and is, for example, 0.1 μm or more and 0.5 μm or less. The impurity concentration of the source region 14 is higher than the impurity concentration of the source region 13. The impurity concentration of the source region 14 is, for example, 1.0×1018 cm -3 1.0×10 or more 21 cm -3 It is as follows.

[0022] The drain region 15 is a region that is selectively formed in the semiconductor layer 4 and aligned with the source region 14 in the first direction X, and has a second conductivity type. In plan view, the drain region 15 is located outside the gate 19 and has a strip shape extending along the second direction Y. The drain region 15 functions as the drain of the LDMOS 100 and also functions as the drain of another LDMOS. The drain region 15 has, for example, a rectangular shape in plan view. The drain region 15 may have a polygonal shape such as a circular shape, an elliptical shape, or a triangular shape in plan view. The drain region 15 is provided at least on the surface of the semiconductor layer 4. The dimension of the drain region 15 along the third direction Z is about the same as the dimension of the source region 14 along the third direction Z, for example, 0.1 μm or more and 0.5 μm or less. The impurity concentration of the drain region 15 is, for example, the same as the impurity concentration of the source region 14. The impurity concentration of the drain region 15 is, for example, 1.0×10 18 cm -3 1.0×10 or more 21 cm -3 It is as follows.

[0023] The drift region 16 is a region that is selectively formed in the semiconductor layer 4 and has a second conductivity type. The drift region 16 is located at least between the source region 14 and the drain region 15 in the first direction X. In the present embodiment, the drift region 16 surrounds the drain region 15 in plan view and is in contact with the drain region 15. The drift region 16 is in contact with the bottom surface 15a of the drain region 15. Further, the drift region 16 is separated from the body region 12. The dimension of the drift region 16 along the third direction Z is about the same as the dimension of the body region 12 along the third direction Z, for example, 0.1 μm or more and 0.5 μm or less. Details of the drift region 16 will be described later.

[0024] The contact region 17 is a region selectively formed in the body region 12, is in contact with the source region 14, and has the first conductivity type. For example, the contact region 17 is surrounded by the source region 14 in a plan view, is located in the center of the body region 12, and has an oval shape extending along the second direction Y. The positions of both ends of the contact region 17 in the second direction Y in the first direction X are substantially aligned with the positions of both ends of the drain region 15 in the second direction Y, but are not limited to this. A bottom surface 17a of the contact region 17 is in contact with the source region 13. On the other hand, the contact region 17 is separated from the body region 12. The contact region 17 is provided at least on the surface of the semiconductor layer 4. The impurity concentration of the contact region 17 may be higher than the impurity concentration of the body region 12. For example, the impurity concentration of the contact region 17 is, for example, 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 The following is the result.

[0025] The gate insulating film 18 is an insulating layer provided on the surface of the semiconductor layer 4, and is located between the semiconductor layer 4 and the gate 19. The gate insulating film 18 is made of at least silicon oxide. For example, the gate insulating film 18 may have a portion made of only silicon oxide and a portion made of silicon oxide and silicon oxynitride (SiON). The gate insulating film 18 includes a first insulating portion 18a and a second insulating portion 18b that is thinner than the first insulating portion 18a.

[0026] The first insulating portion 18a is, for example, a stacked portion of the gate insulating film 18. In the present embodiment, the first insulating portion 18a includes, for example, a lower layer such as a surface oxide film (LOCOS film: Local oxidation of silicon film) formed by selective oxidation of the semiconductor layer 4, a buried oxide film (STI: Shallow Trench Isolation) that fills a shallow trench provided in the semiconductor layer 4, and an upper layer that is an insulating layer formed on the lower layer. The upper layer is formed, for example, by patterning a deposited film formed by a known method such as CVD. The thickness of the lower layer is, for example, 50 nm or more and 500 nm or less, and the thickness of the upper layer is, for example, 50 nm or more and 500 nm or less. Therefore, the thickness of the first insulating portion 18a is, for example, 0.5 μm or more and 5 μm or less. The edge of the first insulating portion 18a has a tapered shape, but is not limited thereto. The dimension of the first insulating portion 18a along the first direction X is, for example, 0.5 μm or more and 5 μm or less. The dimension of the first insulating portion 18a along the second direction Y is, for example, 1 μm or more.

[0027] The second insulating portion 18b is, for example, a single-layer portion of the gate insulating film 18. In the present embodiment, the second insulating portion 18b has only the above-mentioned lower layer. Therefore, the thickness of the second insulating portion 18b corresponds to the thickness of the above-mentioned lower layer. The second insulating portion 18b can also be said to be a portion of the gate insulating film 18 where the above-mentioned upper layer is not formed. The second insulating portion 18b is a portion that overlaps a part 12a of the body region 12 and a part 13a of the source region 13 in the gate insulating film 18, and is adjacent to the first insulating portion 18a in the first direction X. The dimension of the second insulating portion 18b along the first direction X is, for example, 0.2 μm or more and 2 μm or less. Both ends of the second insulating portion 18b in the second direction Y correspond to, for example, both ends of the gate insulating film 18 in the second direction Y. The second insulating portion 18b may overlap a part of the source region 14.

[0028] The gate 19 is a conductor located on the gate insulating film 18 in the third direction Z and has a frame shape surrounding the source region 14 in plan view. The gate 19 includes, for example, a metal film, an alloy film, conductive polysilicon, etc. When the gate 19 includes conductive polysilicon, from the viewpoint of the conductivity of the gate 19, the conductive polysilicon may include one of the impurities of the first conductivity type and the impurities of the second conductivity type. A part of the gate 19 is located between the source region 14 and the drain region 15 in the first direction X in plan view. At least a part of the semiconductor layer 4 overlapping with the gate 19 functions as the channel region C of the LDMOS 100. The channel region C is located, for example, between the source region 14 and the drift region 16 in the semiconductor layer 4. In the channel region C, the conduction and non-conduction of the current path between the source region 14 and the drain region 15 are controlled according to the potential applied to the gate 19.

[0029] The gate 19 has a first portion 19a overlapping a part of the first insulating portion 18a and a second portion 19b overlapping the second insulating portion 18b. In the third direction Z, the distance between the first portion 19a and the semiconductor layer 4 is larger than the distance between the second portion 19b and the semiconductor layer 4. Therefore, the influence on the semiconductor layer 4 accompanying the potential change of the gate 19 is greater below the second portion 19b than below the first portion 19a. Thus, in the LDMOS 100, a current path can be easily formed in the portion of the semiconductor layer 4 overlapping with the second portion 19b.

[0030] The protective film 20 is a patterned insulating film that covers at least a part of the portion exposed from the gate insulating film 18 in the drift region 16. In addition, the protective film 20 covers a part of the gate insulating film 18 and a part of the gate 19. The protective film 20 is located closer to the drain region 15 than the body region 12 in the first direction X. The protective film 20 covers, for example, a part of the first insulating portion 18a of the gate insulating film 18 and a part of the first portion 19a of the gate 19. On the other hand, the protective film 20 does not cover the second insulating portion 18b of the gate insulating film 18 and the second portion 19b of the gate 19. The protective film 20 is formed, for example, by patterning a deposited film formed by a known method such as CVD. The thickness of the protective film 20 is, for example, 10 nm or more and 100 nm or less. The protective film 20 is, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like. The protective film 20 may have a single-layer structure or a laminated structure.

[0031] The first contact 21 is a portion where a wiring (not shown) and the contact region 17 are connected, and is located on the contact region 17. The second contact 22 is a portion where a wiring (not shown) and the drain region 15 are connected, and is located on the drain region 15. The third contact 23 is a portion where a wiring (not shown) and the gate 19 are connected, and is located on the gate 19. Each of the first contact 21, the second contact 22, and the third contact is, for example, an opening formed in an interlayer insulating film (not shown), and is filled with a conductor such as the above wiring.

[0032] Next, the details of the drift region 16 described above will be explained. As shown in FIGS. 2 to 5, the drift region 16 includes a main region 16a, a plurality of first impurity regions 16b that are spaced apart from the channel region C and have a first conductivity type, and a plurality of second impurity regions 16c that are spaced apart from the channel region C and have a second conductivity type. The plurality of first impurity regions 16b and the plurality of second impurity regions 16c are alternately arranged along the second direction Y. That is, in the drift region 16, a portion where p-type impurity regions and n-type impurity regions are alternately arranged along the second direction Y is formed. Further, each of the plurality of first impurity regions 16b and the plurality of second impurity regions 16c overlaps a portion extending along the second direction Y at the outer edge of the gate 19. In the present embodiment, each first impurity region 16b contacts one of the plurality of second impurity regions 16c. For this reason, in the drift region 16, a so-called super junction structure is formed by the plurality of first impurity regions 16b and the plurality of second impurity regions 16c.

[0033] As shown in FIG. 2, a part of the first impurity region 16b is included in the LDMOS 100, and another part of the first impurity region 16b is included in another LDMOS (not shown). The same applies to each of the main region 16a and the second impurity region 16c. The above part is a part that overlaps the drain region 15 in the first direction X and a part closer to the source region 14 than the drain region 15. The above other part is a part located on the opposite side of the source region 14 via the drain region 15 in the first direction X. Hereinafter, only the portions of the main region 16a, the first impurity region 16b, and the second impurity region 16c that are included in the LDMOS 100 will be described.

[0034] The main region 16a is a major portion of the drift region 16, and surrounds the plurality of first impurity regions 16b and the plurality of second impurity regions 16c in a planar view. The main region 16a is separated from the drain region 15. A distance S1 along the first direction X from a portion 16d of the main region 16a that is closest to the body region 12 in the first direction X to the drain region 15 is, for example, −1 μm or more and 2 μm or less. That is, the portion 16d may be provided within the drain region 15. The dimension of the main region 16a along the third direction Z corresponds to the dimension of the drift region 16 along the third direction Z. The impurity concentration of the main region 16a is higher than the impurity concentration of the semiconductor layer 4, and is, for example, 1.0×10 17 cm -3 Over 1.0 x 10 19 cm -3 The proportion (volume %) of the drift region 16 occupied by the main region 16a is greater than the proportions of the drift region 16 occupied by the first impurity region 16b and the second impurity region 16c. For example, the ratio of the volume of the first impurity region 16b to the volume of the main region 16a is 10% or more and 50% or less, and the ratio of the volume of the second impurity region 16c to the volume of the main region 16a is 10% or more and 50% or less.

[0035] Each of the plurality of first impurity regions 16b is an area surrounded by the main region 16a in a plan view and has a strip shape extending along the first direction X. A part of each first impurity region 16b is provided on the surface of the semiconductor layer 4 and covered by the gate insulating film 18. Therefore, the said part corresponds to a part of the surface of the drift region 16. Each first impurity region 16b is in contact with the drain region 15. As shown in FIGS. 3 and 4, each first impurity region 16b is in contact with the bottom surface 15a of the drain region 15 in the second direction Y. The dimension of each first impurity region 16b along the second direction Y is, for example, 0.2 μm or more and 2 μm or less. The interval S2 along the first direction X from the portion 16e closest to the body region 12 in the first direction X of the first impurity region 16b to the drain region 15 is, for example, -1 μm or more and 2 μm or less. That is, the portion 16e can be provided within the drain region 15. The portion 16f overlaps with the protective film 20 in addition to the first insulating portion 18a and the gate 19 in the third direction Z, but is not limited thereto. The impurity concentration of the first impurity region 16b is, for example, 1.0×10 17 cm -3 or more and 1.0×10 19 cm -3 or less. The impurity concentration of the first impurity region 16b can be appropriately adjusted depending on, for example, the impurity concentration of the second impurity region 16c, the breakdown voltage required for the LDMOS 100, and the like.

[0036] Each of the plurality of second impurity regions 16c is an area surrounded by the main region 16a in a plan view and has a strip shape extending along the first direction X. A part of each second impurity region 16c is provided on the surface of the semiconductor layer 4 and covered by the gate insulating film 18. Thus, the said part corresponds to another part of the surface of the drift region 16. The dimension of each second impurity region 16c along the second direction Y is, for example, 0.1 μm or more and 2 μm or less. Each second impurity region 16c is in contact with the drain region 15. As shown in FIGS. 3 and 4, each second impurity region 16c is in contact with the bottom surface 15a of the drain region 15 in the second direction Y. The interval S3 along the first direction X from the portion 16f closest to the body region 12 in the first direction X to the drain region 15 in the second impurity region 16c is shorter than the interval S1 and is, for example, 0.5 μm or more and 2 μm or less. In the present embodiment, both ends of each second impurity region 16c in the first direction X are aligned with both ends of each first impurity region 16b in the first direction X, respectively. Thus, the intervals S2 and S3 are the same. From the viewpoint of on-resistance, the ratio of the interval S1 to the interval S3 is, for example, 20% or more and 80% or less. The portion 16f overlaps with the protective film 20 in addition to the first insulating portion 18a and the gate 19 in the third direction Z, but is not limited thereto. From the viewpoint of on-resistance, the impurity concentration of the first impurity region 16b is higher than the impurity concentration of the main region 16a and is, for example, 1.0×10 16 cm -3 or more and 1.0×10 18 cm -3 or less.

[0037] In this embodiment, the bottom surface of each first impurity region 16b and the bottom surface of each second impurity region 16c are each in contact with the main region 16a. Therefore, the dimension of each first impurity region 16b along the third direction Z and the dimension of each second impurity region 16c along the third direction Z are each shorter than the dimension of the main region 16a along the third direction Z, and are, for example, 0.5 μm or more and 2 μm or less. From the viewpoint of on-resistance, the dimension of each first impurity region 16b along the third direction Z and the dimension of each second impurity region 16c along the third direction Z are each, for example, 0.1 μm or more and 1 μm or less. From the viewpoint of reducing leakage current, the dimension of each first impurity region 16b along the third direction Z and the dimension of each second impurity region 16c along the third direction Z are each, for example, 0.1 μm or more and 1 μm or less.

[0038] Next, with reference to FIGS. 6A to 6G, an example of a method for manufacturing a semiconductor device according to this embodiment will be described. Each of FIGS. 6A to 6G is a schematic cross-sectional view for explaining an example of a method for manufacturing a semiconductor device according to this embodiment. In each of FIGS. 6A to 6G, two end faces EF1 and EF2 of the LDMOS 100 are shown. The end face EF1 corresponds to a part of the cross section shown in FIG. 4, and the end face EF2 corresponds to a part of the cross section shown in FIG. 5. Although not shown, the region including the end face EF1 and the region including the end face EF2 are adjacent to each other in the second direction Y.

[0039] First, as a preparation step, as shown in FIG. 6A, after doping a part of the semiconductor substrate 3 with impurities of the second conductivity type, a semiconductor layer 4 is formed on the semiconductor substrate 3. In the preparation step, for example, the semiconductor layer 4 is epitaxially grown on the semiconductor substrate 3. During the growth of the semiconductor layer 4, the above-mentioned impurities doped in the semiconductor substrate 3 diffuse into the semiconductor layer 4 due to heat treatment (annealing) of the semiconductor layer 4 performed after the growth of the semiconductor layer 4. As a result, an embedded region 11 is formed in the semiconductor substrate 3 and the semiconductor layer 4. Although not shown, in the preparation step, another part of the semiconductor substrate 3 is doped with impurities of the first conductivity type. The doping of the impurities of the first conductivity type may be performed before or after the doping of the impurities of the second conductivity type. A part of the impurities of the first conductivity type diffuses into the semiconductor layer 4 due to heat treatment (annealing) performed during or after the growth of the semiconductor layer 4. Note that the above annealing does not necessarily have to be performed.

[0040] Next, as shown in FIG. 6B, a body region 12 and a drift region 16 are formed in the semiconductor layer 4 (first step). In the first step, the body region 12 is formed by doping a part of the semiconductor layer 4 with impurities of the first conductivity type, and the drift region 16 is formed by doping another part of the semiconductor layer 4 with impurities of the second conductivity type. In the first step, the doping of the impurities of the second conductivity type may be performed after the doping of the impurities of the first conductivity type. Alternatively, the doping of the impurities of the first conductivity type may be performed after the doping of the impurities of the second conductivity type. In the first step, annealing is performed on the semiconductor layer 4 after the above doping is performed.

[0041] Next, as shown in FIG. 6C, a gate insulating film 18 is formed on the semiconductor layer 4 (second step). In the second step, first, a first insulating film is selectively formed on the semiconductor layer 4. For example, the first insulating film is selectively formed by oxidizing a part of the surface of the semiconductor layer 4 by a known method. Subsequently, after forming a second insulating film covering the first insulating film, the second insulating film is patterned to form a gate insulating film 18 including a first insulating portion 18a and a second insulating portion 18b. For example, the second insulating film is formed at least on the first insulating film by a known method such as CVD. Subsequently, a part of the second insulating film is etched. For example, a part of the second insulating film is etched by dry etching or wet etching using a resist mask.

[0042] Next, as shown in FIG. 6D, a gate 19 is formed on the gate insulating film 18 (third step). In the third step, first, a conductive layer is formed on the semiconductor layer 4 and the gate insulating film 18. In this embodiment, a polysilicon layer is formed as the conductive layer. Subsequently, after forming a mask M1 on the polysilicon layer, the conductive layer is selectively etched using the mask M1. The mask M1 is, for example, a positive or negative resist mask.

[0043] Next, as shown in FIG. 6E, a plurality of first impurity regions 16b having a first conductivity type are formed in a part of the drift region 16 (fourth step). In the fourth step, first, a mask M2 is formed to cover a part of the semiconductor layer 4, a part of the gate insulating film 18, and a part of the gate 19. At this time, for example, a part of the drift region 16 at the end face EF1 is exposed from the mask M2. Subsequently, an impurity of the first conductivity type is doped into the portion of the semiconductor layer 4 that is exposed from the mask M2. In the present embodiment, an impurity of the first conductivity type is implanted into a part of the semiconductor layer 4 by inclined doping. As a result, not only the portion of the semiconductor layer 4 that is exposed from the gate insulating film 18 but also a part of the portion of the semiconductor layer 4 that overlaps the gate insulating film 18 and the gate 19 can be doped with an impurity of the first conductivity type. Then, after doping with the impurity of the first conductivity type, a heat treatment is performed on the semiconductor layer 4. Thereby, at least in the drift region 16 shown by the end face EF1, the main region 16a and the first impurity region 16b are formed. In the present embodiment, the gate 19 is formed of a polysilicon layer. Therefore, in the fourth step, the portion of the gate 19 that is exposed from the mask M2 can also be doped with an impurity of the first conductivity type. Note that the mask M2 is, for example, a positive or negative resist mask.

[0044] Although not shown, in the fourth step, another part of the semiconductor layer 4 is doped with an impurity of the first conductivity type. As a result, after the fifth step, an element isolation region (not shown) and the like are formed. At this time, a mask different from the mask M2 is used to form the element isolation region and the like.

[0045] Next, as shown in FIG. 6F, multiple second impurity regions 16c having the second conductivity type are formed in another portion of the drift region 16 (step 5). In step 5, a mask M3 is first formed to cover a portion of the semiconductor layer 4, a portion of the gate insulating film 18, and a portion of the gate 19. At this time, for example, a portion of the drift region 16 at the end face EF2 is exposed through the mask M3. Next, the portion of the semiconductor layer 4 exposed through the mask M3 is doped with impurities of the second conductivity type. In this embodiment, the impurities of the second conductivity type are implanted into a portion of the semiconductor layer 4 by gradient doping. As a result, not only the portion of the semiconductor layer 4 exposed through the gate insulating film 18 but also a portion of the semiconductor layer 4 overlapping with the gate insulating film 18 and the gate 19 can be doped with impurities of the second conductivity type. After doping with the impurities of the second conductivity type, the semiconductor layer 4 is subjected to a heat treatment. As a result, the main region 16a and the second impurity regions 16c are formed in at least the drift region 16 shown at the end face EF2. In this embodiment, the gate 19 is formed from a polysilicon layer. Therefore, in the fifth step, the portion of the gate 19 that is exposed from the mask M3 can also be doped with the impurity of the second conductivity type. The mask M3 is, for example, a positive or negative resist mask.

[0046] Although not shown, in the fifth step, another part of the semiconductor layer 4 is doped with the impurity of the second conductivity type. For example, the impurity of the second conductivity type is doped into a part of the body region 12. As a result, after the fifth step, the source region 13 (see FIG. 3, etc.) and the like may be formed.

[0047] Next, as shown in FIG. 6G, a source region 14 and a drain region 15 are formed in the semiconductor layer 4 (the sixth step). In the sixth step, first, a mask M4 is formed to cover a part of the semiconductor layer 4, a part of the gate insulating film 18, and a part of the gate 19. Subsequently, the exposed portion of the semiconductor layer 4 from the mask M4 is doped with impurities of the second conductivity type. As a result, the source region 14 is formed in the body region 12, and the drain region 15 is formed in the drift region 16. At the end face EF1, the drain region 15 is formed in the first impurity region 16b of the drift region 16, and at the end face EF2, the drain region 15 is formed in the second impurity region 16c of the drift region 16. In the present embodiment, the gate 19 is formed of a polysilicon layer. Therefore, in the sixth step, the exposed portion of the gate 19 from the mask M4 may also be doped with impurities of the second conductivity type. Note that the mask M4 is, for example, a positive or negative photoresist.

[0048] Next, although not shown, after a contact region 17 is formed in the semiconductor layer 4, a protective film 20 is formed to cover at least a part of the semiconductor layer 4 and a part of the gate 19 (see FIGS. 2, 3, etc.). Then, an interlayer insulating film, wiring, vias, etc., not shown, are formed and patterned on the semiconductor layer 4, the gate insulating film 18, the gate 19, the protective film 20, etc. Through the above steps, the semiconductor device 1 including the LDMOS 100 (see FIG. 2) is manufactured. In forming the contact region 17, first, a mask is formed to cover a part of the semiconductor layer 4, the gate insulating film 18, and the gate 19. Subsequently, the exposed portion of the semiconductor layer 4 from the mask is doped with impurities of the first conductivity type. As a result, the contact region 17 is formed in the body region 12. Also, in forming the protective film 20, first, an insulating film is formed to cover the semiconductor layer 4 and the gate 19. Next, the protective film 20 is formed by patterning the insulating film. Note that when the contact region 17 is formed, another part of the semiconductor layer 4 is doped with impurities of the first conductivity type. As a result, an element isolation region (not shown) etc. are formed.

[0049] Next, while referring to the comparative examples described below, the effects exhibited by the semiconductor device 1 manufactured by the manufacturing method according to the present embodiment will be described. In the drift region of the LDMOS included in the semiconductor device according to the comparative example described below, a plurality of first impurity regions and a plurality of second impurity regions are alternately provided along the thickness direction of the semiconductor substrate, and it has the same configuration as the LDMOS 100 included in the semiconductor device 1 according to the present embodiment, except for this.

[0050] According to the LDMOS 100 included in the semiconductor device 1 according to the present embodiment, the drift region 16 includes a plurality of first impurity regions 16b that are spaced apart from the channel region C and have a first conductivity type, and a plurality of second impurity regions 16c that are spaced apart from the channel region C and have a second conductivity type. The plurality of first impurity regions 16b and the plurality of second impurity regions 16c are alternately arranged along the second direction Y. As a result, a super junction structure is formed in the drift region 16, so that it is possible to achieve both suppression of breakdown voltage reduction and reduction of on-resistance of the LDMOS 100. Further, in the LDMOS 100, the plurality of first impurity regions 16b and the plurality of second impurity regions 16c can be formed simply by performing doping and annealing using different masks. On the other hand, in the LDMOS according to the above comparative example, when forming the plurality of first impurity regions and the plurality of second impurity regions, formation of a semiconductor layer by epitaxial growth multiple times, high-acceleration ion implantation into the semiconductor layer, etc. are performed. Therefore, in the manufacturing method of the semiconductor device 1 according to the present embodiment, a super junction structure can be formed with high reliability and low cost as compared with the above comparative example. In addition, in the present embodiment, the widths of the respective first impurity regions 16b and the widths of the respective second impurity regions 16c can be accurately controlled by a mask pattern. Therefore, the performance design of the LDMOS 100 can be facilitated.

[0051] In one example, each of the plurality of first impurity regions 16b and the plurality of second impurity regions 16c is in contact with the drain region 15. In this case, the breakdown voltage of the second impurity region 16c is improved due to the presence of the first impurity region 16b, and the on-resistance is reduced through the second impurity region 16c. Further, each of the plurality of first impurity regions 16b and the plurality of second impurity regions 16c may be in contact with the bottom surface 15a of the drain region 15.

[0052] In one example, a part of each of the plurality of first impurity regions 16b corresponds to a part of the surface of the drift region 16, and a part of each of the plurality of second impurity regions 16c corresponds to another part of the surface of the drift region 16. In this case, further reduction of the breakdown voltage of the LDMOS 100 is achieved.

[0053] In one example, the impurity concentration of the first impurity region is 1.0×10 15 cm -3 or more and 1.0×10 17 cm -3 or less, and the impurity concentration of the second impurity region is 1.0×10 16 cm -3 or more and 1.0×10 18 cm -3 or less. In this case, it is possible to satisfactorily achieve both suppression of the breakdown voltage reduction and reduction of the on-resistance of the LDMOS 100.

[0054] Hereinafter, modifications of the above-described embodiment will be described. In the description of the modifications, descriptions overlapping with those of the above-described embodiment will be omitted, and different parts will be described. That is, within the technically possible range, the descriptions of the above-described embodiment may be appropriately used for the modifications.

[0055] FIG. 7 is a schematic plan view of a main part of a first element region according to a first modification of the above embodiment. As shown in FIG. 7, in the LDMOS 100A provided in the first element region 2A according to the first modification, a plurality of first impurity regions 16b and a plurality of second impurity regions 16c form a substantially U-shaped in plan view, which is different from the above embodiment. In the first modification, each of a part of the plurality of first impurity regions 16b and a part of the plurality of second impurity regions 16c overlaps a portion of the outer edge of the gate 19 extending along the first direction X. In addition, the parts are adjacent to each other along a direction intersecting the second direction Y and the third direction Z. Therefore, in the first modification, a superjunction structure is also formed in a region different from the region between the source region 14 and the drain region 15 in the first direction X in the semiconductor layer 4. In plan view, each of the source region 14 and the contact region 17 is partially surrounded by the plurality of first impurity regions 16b and the plurality of second impurity regions 16c.

[0056] Also in the first modification described above, the same operational effects as those of the above embodiment are achieved. In the first modification, the plurality of first impurity regions 16b and the plurality of second impurity regions 16c form a substantially U-shaped in plan view, but it is not limited thereto.

[0057] FIG. 8 is a schematic plan view of a main part of a first element region according to a second modification of the above embodiment. As shown in FIG. 7, in the LDMOS 100B provided in the first element region 2A according to the second modification, a plurality of first impurity regions 16b and a plurality of second impurity regions 16c form a frame shape in plan view, which is different from the first modification. In the second modification, the plurality of first impurity regions 16b and the plurality of second impurity regions 16c form an oval ring shape in plan view, but it is not limited thereto. Therefore, in plan view, each of the source region 14 and the contact region 17 is surrounded by the plurality of first impurity regions 16b and the plurality of second impurity regions 16c. Also in the second modification described above, the same operational effects as those of the above embodiment are achieved.

[0058] Although the embodiments and modifications of the present disclosure have been described above, the present disclosure can also be embodied in other forms.

[0059] In the above embodiment and modified examples, the conductivity types of various semiconductor regions may be reversed. That is, p-type regions may be n-type regions and n-type regions may be p-type regions. Alternatively, the first conductivity type may be n-type and the second conductivity type may be p-type.

[0060] In the above embodiment and modified example, the source region and the contact region are surrounded by the gate in a plan view, and the drain region is located outside the gate in a plan view, but this is not limiting. For example, the drain region may be surrounded by the gate in a plan view, and the source region and the contact region may be located outside the gate in a plan view.

[0061] In the above embodiment and the above modified example, heat treatment is performed in both the fourth step and the fifth step, but this is not limiting. For example, heat treatment may not be performed in the fourth step, but may be performed in the fifth step.

[0062] In the above modification, the plurality of first impurity regions and the plurality of second impurity regions are formed in a plan view, but this is not limiting. For example, the plurality of first impurity regions and the plurality of second impurity regions may form part of a frame or a semicircular shape in a plan view.

[0063] In the above embodiments and modifications, the semiconductor device can be applied to a power module used in an inverter circuit that drives an electric motor used as a power source for, for example, automobiles (including electric vehicles), trains, industrial robots, air conditioners, air compressors, fans, vacuum cleaners, dryers, refrigerators, etc. The semiconductor device can also be applied to a power module used in an inverter circuit for a solar cell, a wind power generator, or other power generation device. Alternatively, the semiconductor device can be applied to a circuit module that constitutes an analog control power supply, a digital control power supply, etc.

[0064] As described above in detail for the embodiments and modifications according to one aspect of the present disclosure, these are merely specific examples used to clarify the technical content of the present disclosure, and the present disclosure should not be construed as being limited to these specific examples. The scope of the present disclosure is limited only by the appended claims.

[0065] The following are characteristic examples extracted from the descriptions of this specification and the drawings.

[0066] [A1] A semiconductor substrate, A semiconductor layer located on the semiconductor substrate in the thickness direction of the semiconductor substrate, A gate insulating film located on the semiconductor layer in the thickness direction, A gate located on the gate insulating film in the thickness direction, Comprising, The semiconductor layer includes a source region, a drain region aligned with the source region in a first direction, a drift region located at least between the source region and the drain region, and a channel region located between the source region and the drift region. The drift region includes a plurality of first impurity regions spaced apart from the channel region and having a first conductivity type, and a plurality of second impurity regions spaced apart from the channel region and having a second conductivity type different from the first conductivity type. The plurality of first impurity regions and the plurality of second impurity regions are alternately arranged along a second direction that intersects at least the thickness direction and the first direction. A semiconductor device.

[0067] [A2] Each of the plurality of first impurity regions and the plurality of second impurity regions is in contact with the drain region. The semiconductor device according to [A1].

[0068] [A3] Each of the plurality of first impurity regions and the plurality of second impurity regions is in contact with the bottom surface of the drain region. The semiconductor device according to [A2].

[0069] [A4] A part of each of the plurality of first impurity regions corresponds to a part of the surface of the drift region. A semiconductor device according to any one of [A1] to [A3], wherein a part of each of the plurality of second impurity regions corresponds to another part of the surface of the drift region.

[0070] [A5] A semiconductor device according to any one of [A1] to [A4], wherein the source region is surrounded by the plurality of first impurity regions and the plurality of second impurity regions when viewed from the thickness direction.

[0071] [A6] The impurity concentration of the first impurity region is 1.0×10 15 cm -3 or more and 1.0×10 17 cm -3 or less, The impurity concentration of the second impurity region is 1.0×10 16 cm -3 or more and 1.0×10 18 cm -3 or less. A semiconductor device according to any one of [A1] to [A5].

[0072] [A7] A first step of forming a drift region in a semiconductor layer located on a semiconductor substrate; A second step of forming a gate insulating film on the semiconductor layer; A third step of forming a gate on the gate insulating film; A fourth step of forming a plurality of first impurity regions having a first conductivity type in a part of the drift region; A fifth step of forming a plurality of second impurity regions having a second conductivity type different from the first conductivity type in another part of the drift region; A sixth step of forming a source region and a drain region aligned with the source region in a first direction in the semiconductor layer. The plurality of first impurity regions and the plurality of second impurity regions are arranged alternately along at least the thickness direction of the semiconductor substrate and a second direction intersecting the first direction. Method for manufacturing a semiconductor device.

Explanation of symbols

[0073] 1... semiconductor device, 1A... first main surface, 1B... second main surface, 1C... first side surface, 1D... second side surface, 1E... third side surface, 1F... fourth side surface, 2... element region, 2A... first element region, 2B... second element region, 3... semiconductor substrate, 4... semiconductor layer, 11... embedded region, 12... body region, 13, 14... source region, 15... drain region, 15a... bottom surface, 16... drift region, 16a... main region, 16b... first impurity region, 16c... second impurity region, 16d... portion, 16e... portion, 16f... portion, 17... contact region, 17a... bottom surface, 18... gate insulating film, 18a... first insulating portion, 18b... second insulating portion, 19... gate, 19a... first portion, 19b... second portion, 20... protective film, 21... first contact, 22... second contact, 100, 100A... LDMOS, C... channel region, M1 to M4... masks, S1 to S3... intervals.

Claims

1. A semiconductor substrate, a semiconductor layer located on the semiconductor substrate in the thickness direction of the semiconductor substrate, a gate insulating film located on the semiconductor layer in the thickness direction, a gate located on the gate insulating film in the thickness direction, comprising: the semiconductor layer includes a source region, a drain region aligned with the source region in a first direction, a drift region located at least between the source region and the drain region, and a channel region located between the source region and the drift region, the drift region includes a plurality of first impurity regions spaced apart from the channel region and having a first conductivity type, and a plurality of second impurity regions spaced apart from the channel region and having a second conductivity type different from the first conductivity type, the plurality of first impurity regions and the plurality of second impurity regions are alternately arranged along a second direction that intersects at least the thickness direction and the first direction, a semiconductor device.

2. The semiconductor device according to claim 1, wherein each of the plurality of first impurity regions and the plurality of second impurity regions is in contact with the drain region.

3. The semiconductor device according to claim 2, wherein each of the plurality of first impurity regions and the plurality of second impurity regions is in contact with the bottom surface of the drain region.

4. A part of each of the plurality of first impurity regions corresponds to a part of the surface of the drift region, A part of each of the plurality of second impurity regions corresponds to another part of the surface of the drift region. The semiconductor device according to any one of claims 1 to 3.

5. The semiconductor device according to any one of claims 1 to 3, wherein the source region is surrounded by the plurality of first impurity regions and the plurality of second impurity regions when viewed from the thickness direction.

6. The impurity concentration in the first impurity region is 1.0×10 １５ cm －３ or more and 1.0×10 １７ cm －３ or less, and The impurity concentration in the second impurity region is 1.0×10 １６ cm －３ or more and 1.0×10 １８ cm －３ or less. The semiconductor device according to any one of claims 1 to 3.

7. A first step of forming a drift region in a semiconductor layer located on a semiconductor substrate, A second step of forming a gate insulating film on the semiconductor layer, A third step of forming a gate on the gate insulating film, A fourth step of forming a plurality of first impurity regions having a first conductivity type in a part of the drift region, A fifth step of forming a plurality of second impurity regions having a second conductivity type different from the first conductivity type in another part of the drift region, And a sixth step of forming a source region and a drain region aligned with the source region in a first direction in the semiconductor layer. The plurality of first impurity regions and the plurality of second impurity regions are arranged alternately along at least a second direction that intersects the thickness direction of the semiconductor substrate and the first direction. A method of manufacturing a semiconductor device.

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