Field-effect transistor and method for manufacturing the same

Abstract

To effectively reduce an on-resistance of a field-effect transistor.SOLUTION: A method of manufacturing a field-effect transistor comprises the steps of: forming a plurality of trenches penetrating a source layer and a body layer and reaching a drift layer on a surface of a SiC substrate; and forming crystal defects in the source layer and the body layer. A region where the crystal defect is formed in the step of forming the crystal defect is exposed on a side surface of each trench. The method of manufacturing the field-effect transistor further includes the steps of: enlarging a width of each trench by etching the side surface of each trench after the trench and the crystal defect are formed; forming a gate electrode in each trench after the step of enlarging the width of each trench is performed; and forming a source electrode in contact with the source layer on the surface of the SiC substrate after the step of forming the gate electrode is performed.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The technology disclosed in this specification relates to a field-effect transistor and a method for manufacturing the same.

[0002] In a trench gate type field-effect transistor, there is a technology for making the interval between trenches extremely narrow. When the interval between trenches is made extremely narrow, the channels formed along the side surfaces of the respective trenches are joined to each other, and the channel resistance can be reduced.

[0003] Note that Patent Document 1 discloses a technology for altering an SiC substrate by implanting ions into the SiC substrate.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] As described above, when the interval between trenches is narrowed, the channel resistance can be reduced. On the other hand, when the interval between trenches is narrowed, the width of the semiconductor layer between trenches (that is, the semiconductor layer where the source layer and the body layer exist) located between the trenches becomes narrow. Since the width of the trench is wider on the surface side, the semiconductor layer between trenches has a tapered shape that becomes narrower toward the surface side. For this reason, when the interval between trenches is narrowed, the width of the source layer becomes particularly narrow. As a result, the contact resistance between the source layer and the source electrode increases. For this reason, even if the channel resistance is reduced, the on-resistance of the field-effect transistor cannot be effectively reduced. In this specification, a technology for effectively reducing the on-resistance of a field-effect transistor is proposed.

Means for Solving the Problems

[0006] The manufacturing method of the field-effect transistor disclosed in this specification includes forming a plurality of trenches that penetrate the source layer and the body layer and reach the drift layer on the surface of an SiC substrate having an n-type source layer, a p-type body layer, and an n-type drift layer separated from the source layer by the body layer, and forming crystal defects in the source layer and the body layer. After the steps of forming the trenches and forming the crystal defects are carried out, the region where the crystal defects are formed in the step of forming the crystal defects is exposed on the side surfaces of the respective trenches. This manufacturing method further includes a step of expanding the width of each trench by etching the side surfaces of the respective trenches after the steps of forming the trenches and forming the crystal defects are carried out, a step of forming a gate electrode in each trench after the step of expanding the width of each trench is carried out, and a step of forming a source electrode in contact with the source layer on the surface of the SiC substrate after the step of forming the gate electrode is carried out.

[0007] In this manufacturing method, with the region where the crystal defects are formed exposed on the side surfaces of the respective trenches, the width of each trench is expanded by etching the side surfaces of the trenches. As a result, the width of the semiconductor layer between the trenches becomes narrower. When crystal defects are exposed on the side surfaces of the trenches, the side surfaces of the trenches can be effectively etched in the lateral direction. By etching the side surfaces of the trenches in the lateral direction, it is possible to suppress the inclination of the side surfaces of the trenches in a direction in which the semiconductor layer between the trenches becomes a forward taper shape. For example, the inclination angle of the side surfaces of the trenches can be made smaller than before. Also, for example, the side surfaces of the trenches can be made to have a shape close to perpendicular to the surface of the SiC substrate, or the semiconductor layer between the trenches can be made to have an inverse taper shape. Therefore, according to this manufacturing method, the interval between the trenches can be narrowed while ensuring the width of the source layer. For this reason, the on-resistance of the field-effect transistor can be effectively reduced.

Brief Description of the Drawings

[0008]

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Mode for Carrying Out the Invention

[0009] In the manufacturing method of an example disclosed in this specification, the step of forming crystal defects may be carried out after the step of forming the trenches is carried out. The step of forming crystal defects may be a step of implanting ions into the side surfaces of the respective trenches at an angle inclined with respect to the thickness direction of the SiC substrate.

[0010] By implanting ions into the side surfaces of the trenches, crystal defects can be formed in the regions exposed on the side surfaces of the trenches. Therefore, the side surfaces of the trenches can be etched efficiently, and the width of the trenches can be suitably expanded.

[0011] The above manufacturing method may have a step of forming a sacrificial oxide film by oxidizing the side surfaces of the trenches after the step of forming crystal defects. The step of expanding the width of each trench may be a step of etching the sacrificial oxide film.

[0012] According to this configuration, the sacrificial oxide film grows at a high rate in the regions exposed on the side surfaces of the trenches (i.e., the regions where crystal defects are formed). Therefore, by etching the sacrificial oxide film, the width of the trenches can be suitably expanded.

[0013] In an example of the manufacturing method disclosed in this specification, the step of forming crystal defects may be a step of irradiating the source layer and the body layer with a laser to form crystal defects. The step of forming the trenches may be performed after the step of forming crystal defects.

[0014] According to this configuration, crystal defects can be suitably formed by the laser. The regions where crystal defects are formed are exposed on the side surfaces of the trenches when the trenches are formed. Therefore, the side surfaces of the trenches can be etched efficiently, and the width of the trenches can be suitably expanded.

[0015] In an example of the manufacturing method disclosed in this specification, the step of forming crystal defects may be a step of implanting inert ions into the source layer and the body layer to form crystal defects. The step of forming the trenches may be performed after the step of forming crystal defects.

[0016] In this configuration, crystal defects can be preferably formed by implanting inert ions. The region where the crystal defects are formed is exposed on the side surface of the trench when the trench is formed. Therefore, the side surface of the trench can be efficiently etched, and the width of the trench can be preferably expanded.

[0017] In an example of the manufacturing method disclosed in this specification, after the implementation of the step of expanding the width of each trench, the width of the source layer is wider than the width of the body layer.

[0018] According to this configuration, the contact resistance between the source layer and the source electrode can be further reduced.

[0019] In an example of the manufacturing method disclosed in this specification, before the implementation of the step of expanding the width of each trench, the interval between each trench may be 400 nm or more. Also, after the implementation of the step of expanding the width of each trench, the interval between each trench may be 10 nm or more and 200 nm or less.

[0020] In this way, by significantly reducing the interval between trenches, the channel resistance can be reduced.

[0021] An example of the field effect transistor disclosed in this specification includes a SiC substrate, a gate electrode, and a source electrode. The SiC substrate is a SiC substrate having an n-type source layer, a p-type body layer, and an n-type drift layer separated from the source layer by the body layer, and a plurality of trenches penetrating the source layer and the body layer on the surface to reach the drift layer are provided. The gate electrode is provided in each trench. The source electrode is in contact with the source layer on the surface of the SiC substrate. The interval between each trench is 10 nm or more and 200 nm or less. The width of the source layer is wider than the width of the body layer.

[0022] According to the structure of this field effect transistor, a low on-resistance can be realized.

Example

[0023] The field effect transistor 10 shown in FIG. 1 has a semiconductor substrate 12 (i.e., SiC substrate) made of SiC (i.e., silicon carbide). A plurality of trenches 14 are provided on the upper surface 12a of the SiC substrate 12. The inner surface of each trench 14 is covered with a gate insulating film 16. A gate electrode 18 is disposed in each trench 14. Each gate electrode 18 is insulated from the SiC substrate 12 by the gate insulating film 16. The upper surface of the gate electrode 18 is covered with an interlayer insulating film 20. The field effect transistor 10 has a source electrode 22 and a drain electrode 24. The source electrode 22 covers the upper surface 12a of the SiC substrate 12. The source electrode 22 is insulated from the gate electrode 18 by the interlayer insulating film 20. The drain electrode 24 covers the lower surface 12b of the SiC substrate 12.

[0024] The SiC substrate 12 has a source layer 30, a body layer 32, a drift layer 34, and a drain layer 36.

[0025] The source layer 30 is an n-type layer and is disposed in a range including the upper surface 12a of the SiC substrate 12. The source layer 30 makes ohmic contact with the source electrode 22. Also, the source layer 30 is in contact with the gate insulating film 16 on the side surface of the trench 14.

[0026] The body layer 32 is a p-type layer and is disposed below the source layer 30. The body layer 32 is in contact with the gate insulating film 16 on the side surface of the trench 14 below the source layer 30. The body layer 32 is electrically connected to the source electrode 22 at a position not shown.

[0027] The drift layer 34 is an n-type layer having a lower n-type impurity concentration than the source layer 30. The drift layer 34 is disposed below the body layer 32. The drift layer 34 is separated from the source layer 30 by the body layer 32. The drift layer 34 is in contact with the gate insulating film 16 on the side surface and the bottom surface of the trench 14 below the body layer 32.

[0028] The drain layer 36 is an n-type layer with a higher n-type impurity concentration than the drift layer 34. The drain layer 36 is disposed below the drift layer 34. The drain layer 36 is disposed in a range including the lower surface 12b of the SiC substrate 12. The drain layer 36 is in ohmic contact with the drain electrode 24.

[0029] Each trench 14 penetrates the source layer 30 and the body layer 32 from the upper surface 12a and reaches the drift layer 34. Hereinafter, the semiconductor layer within the range sandwiched between two trenches 14 is referred to as an inter-trench semiconductor layer 40. The source layer 30 and the body layer 32 are provided in each inter-trench semiconductor layer 40. In FIG. 1, the interval C1 indicates the interval between the trenches 14 on the upper surface 12a. The interval C1 is 10 nm or more and 200 nm or less. In the field effect transistor 10, the interval C1 between the trenches 14 is significantly smaller than that of a general trench-type field effect transistor. The interval C1 is narrower than the width of the trench 14. Also, the side surface of each trench 14 is substantially perpendicular to the upper surface 12a of the SiC substrate 12. Therefore, the widths of the source layer 30 and the body layer 32 are substantially equal to the interval C1.

[0030] When a potential equal to or higher than the threshold value is applied to the gate electrode 18, a channel is formed in the body layer 32 in the range adjacent to the gate insulating film 16. Since the width of the body layer 32 (that is, the interval C1) is extremely small, the channels formed on both sides of the body layer 32 are integrated. For example, as shown in FIG. 1, in one inter-trench semiconductor layer 40, channels CH1 and CH2 are formed in the body layer 32 along the two trenches 14 on both sides thereof. Since the interval C1 is small, the channel CH1 and the channel CH2 are coupled to each other, and the entire body layer 32 becomes a channel. By integrating the two channels in the horizontal direction in this way, a low channel resistance is realized. With the channel formed in this manner, when a potential higher than that of the source electrode 22 is applied to the drain electrode 24, electrons flow from the source electrode 22 through the source layer 30, the channel, the drift layer 34, and the drain layer 36 to the drain electrode 24.

[0031] FIG. 2 shows a field effect transistor of a comparative example. In FIG. 2, the same reference numerals as those in FIG. 1 are assigned to the corresponding parts in FIG. 1. As shown in FIG. 2, in the field effect transistor of the comparative example, the side surfaces of the trenches 14 are inclined such that the width of each trench 14 becomes narrower toward the lower side. For this reason, the semiconductor layer 40 between the trenches has a tapered shape in which the width becomes narrower toward the upper side. Therefore, in FIG. 2, the width of the source layer 30 is narrower than the width of the body layer 32. Therefore, when the width of the body layer 32 is narrowed to the extent that the channels are integrated, the width of the source layer 30 becomes further narrower, and the contact resistance between the source layer 30 and the source electrode 22 increases. Thus, in the structure of the field effect transistor of the comparative example, even if the channel resistance is reduced, the contact resistance increases, and the on-resistance cannot be effectively reduced.

[0032] On the other hand, in the field effect transistor 10 of FIG. 1, since the side surface of the trench 14 is substantially perpendicular to the upper surface 12a, the width of the source layer 30 is substantially equal to the width of the body layer 32. Therefore, in the field effect transistor 10, the width of the source layer 30 can be secured wider than that of the field effect transistor of the comparative example, and the contact resistance between the source layer 30 and the source electrode 22 can be reduced. Therefore, according to the structure of the field effect transistor 10, the on-resistance can be effectively reduced.

[0033] Next, a method for manufacturing the field effect transistors of Example 1 and the comparative example will be described. FIG. 3 shows the SiC substrate 12 before electrode formation. In Example 1 and the comparative example, the field effect transistor is manufactured from the SiC substrate 12 of FIG. 3. As shown in FIG. 3, inside the SiC substrate 12 before electrode formation, a source layer 30, a body layer 32, a drift layer 34, and a drain layer 36 are provided in this order from above. The drift layer 34 is separated from the source layer 30 by the body layer 32.

[0034] First, the manufacturing method of the comparative example will be described. In the manufacturing method of the comparative example, as shown in FIG. 4, a mask 50 having an opening 50a is formed on the upper surface 12a of the SiC substrate 12. Next, the upper surface 12a of the SiC substrate 12 is etched through the mask 50 by reactive ion etching or the like to form a plurality of trenches 14. Here, each trench 14 is formed so as to penetrate the source layer 30 and the body layer 32 and reach the drift layer 34. Thereafter, by forming each insulating film and each electrode, the field effect transistor shown in FIG. 2 is completed.

[0035] In the trench formation step in the manufacturing method of the comparative example, a wide trench 14 is formed by etching in the thickness direction of the SiC substrate 12 within the wide opening 50a. When such a wide trench 14 is formed, the side surface of the trench 14 is inclined so that the width of the trench 14 becomes narrower toward the lower side. Therefore, the width of the source layer 30 becomes narrower, and the contact resistance between the source layer 30 and the source electrode 22 becomes higher. For this reason, in the manufacturing method of the comparative example, it is difficult to reduce the on-resistance of the field effect transistor.

[0036] Next, the manufacturing method of Example 1 will be described. In the manufacturing method of Example 1, as shown in FIG. 5, a mask 52 having an opening 52a is formed on the upper surface 12a of the SiC substrate 12. The width of the opening 52a is narrower than the width of each trench 14 in FIG. 1. Next, the upper surface 12a of the SiC substrate 12 is etched through the mask 52 by reactive ion etching or the like to form a plurality of trenches 14. Here, each trench 14 is formed so as to penetrate the source layer 30 and the body layer 32 and reach the drift layer 34. The width of the trench 14 shown in FIG. 5 is narrower than the width of the trench 14 formed by the manufacturing method of the comparative example (that is, the trench 14 in FIG. 4). Thus, when the width of the trench 14 is narrow, by adjusting the etching conditions, the trench 14 can be formed such that the side surface of the trench 14 is substantially perpendicular to the upper surface 12a. Note that at this stage, the interval C1 between the trenches 14 is 400 nm or more.

[0037] Next, as shown in FIG. 6, ions are implanted into one side surface of the trench 14 by irradiating the SiC substrate 12 at an angle inclined with respect to the thickness direction of the SiC substrate 12. Thereby, crystal defects 70 are formed in the region exposed on the side surface of the trench 14. The type of ions implanted into the side surface of the trench 14 is not particularly limited. For example, any of n-type ions, p-type ions, and inert ions (that is, ions that do not become n-type or p-type in the SiC substrate) can be implanted. Next, as shown in FIG. 7, the implantation angle is inclined to the opposite side of FIG. 6, and ions are implanted into the other side surface of the trench 14 (that is, the side surface opposite to FIG. 6). Thereby, crystal defects 70 are formed in the region exposed on this side surface.

[0038] Next, by heating the SiC substrate 12 in an oxidation gas, the SiC substrate 12 is oxidized in the trench 14 as shown in FIG. 8. Thereby, a sacrificial oxide film 72 is formed on the inner surface of the trench 14. In the region where the crystal defects 70 are formed in the ion implantation steps of FIGS. 6 and 7, the oxidation reaction proceeds faster than in the region where the crystal defects 70 are not formed. Therefore, as shown in FIG. 8, a sacrificial oxide film 72 thicker than the bottom surface of each trench 14 is formed on the side surface of each trench 14. After the formation of the sacrificial oxide film 72, the mask 52 is removed.

[0039] Next, as shown in FIG. 9, the sacrificial oxide film 72 is removed by etching. As a result, the width of the trench 14 expands. By the process of expanding the width of the trench 14, the interval C1 between the trenches 14 is reduced from a value of 400 nm or more to a value of 200 nm or less. After the process of expanding the width of the trench 14, the interval C1 is 10 nm or more and 200 nm or less.

[0040] Next, as shown in FIG. 1, a gate insulating film 16 is formed on the inner surface of the trench 14. Next, a gate electrode 18 is formed in the trench 14. Next, an interlayer insulating film 20 is formed on the gate electrode 18. Next, a source electrode 22 is formed on the upper surface 12a of the SiC substrate 12. Next, a drain electrode 24 is formed on the lower surface 12b of the SiC substrate 12. Through the above steps, the field effect transistor 10 shown in FIG. 1 is completed.

[0041] In the manufacturing method of Example 1, after forming a narrow trench 14 (see FIG. 5), the side surface of the trench 14 is etched to expand the width of the trench 14, thereby forming a wide trench 14 (see FIG. 9). When the trench 14 is formed in this way, a trench 14 that is wide and has a side surface substantially perpendicular to the upper surface 12a can be formed. Therefore, the width of the source layer 30 can be made substantially equal to the width of the body layer 32. For this reason, while reducing the channel resistance, the contact resistance between the source layer 30 and the source electrode 22 can be reduced. Therefore, according to the manufacturing method of Example 1, a field-effect transistor 10 with a low on-resistance can be manufactured.

[0042] Also, in the manufacturing method of Example 1, since the width of the trench 14 is expanded by removing the sacrificial oxide film 72, the surface roughness of the side surface of the trench 14 can be reduced. For this reason, the channel resistance can be further reduced.

[0043] Also, the field-effect transistor 10 can also be manufactured by the manufacturing methods of Examples 2 to 4 described below.

Example

[0044] In the manufacturing method of Example 2, the steps up to the step shown in FIG. 7 are carried out in the same manner as in Example 1. In the manufacturing method of Example 2, next, the mask 52 is removed, and the SiC substrate 12 is etched as shown in FIG. 10. That is, in Example 2, the SiC substrate 12 is directly etched without forming the sacrificial oxide film 72. The etching method used here is not particularly limited, but for example, an etching method with high isotropy such as wet etching can be used. In the region where the crystal defect 70 is formed, the etching rate becomes faster than the region where the crystal defect 70 is not formed. For this reason, etching proceeds rapidly on the side surface of the trench 14, and the etching rate is extremely slow on the bottom surface of the trench 14 and the upper surface 12a of the SiC substrate 12. For this reason, the depth of the trench 14 hardly changes, and the width of the trench 14 expands. By the process of expanding the width of the trench 14, the interval C1 between the trenches 14 is reduced from a value of 400 nm or more to a value of 200 nm or less. After the process of expanding the width of the trench 14, the interval C1 is 10 nm or more and 200 nm or less.

[0045] Thereafter, in the same manner as in Example 1, by forming the gate insulating film 16, the gate electrode 18, the interlayer insulating film 20, the source electrode 22, and the drain electrode 24, the field effect transistor 10 shown in FIG. 1 is completed.

[0046] In the manufacturing method of Example 2, after forming the trench 14 (see FIG. 5) with a narrow width, the side surface of the trench 14 is etched to expand the width of the trench 14, thereby forming the trench 14 (see FIG. 10) with a wide width. When the trench 14 is formed in this way, it is possible to form the trench 14 having a wide width and a side surface substantially perpendicular to the upper surface 12a. Therefore, a field effect transistor 10 with low on-resistance can be manufactured.

Example

[0047] In the manufacturing method of Example 3, as shown in FIG. 11, the SiC substrate 12 is irradiated with a laser L. Here, the laser L is irradiated so that a focal point is formed inside the SiC substrate 12. When the laser L is irradiated in this way, crystal defects 70 are formed at the position of the focal point. Here, by moving the focal point, crystal defects 70 are formed throughout the range including the source layer 30, the body layer 32, and the drift layer 34 in the vicinity of the body layer 32 (that is, the depth range in which the trenches 14 are formed).

[0048] Next, as shown in FIG. 12, a mask 54 having an opening 54a is formed on the upper surface 12a of the SiC substrate 12. The width of the opening 54a is narrower than the width of each trench 14 in FIG. 1. Next, the upper surface 12a of the SiC substrate 12 is etched through the mask 54 by reactive ion etching or the like to form a plurality of trenches 14. Here, each trench 14 is formed so as to penetrate the source layer 30 and the body layer 32 and reach the drift layer 34. The trench 14 is formed so as to penetrate the region where the crystal defects 70 are formed. When the trench 14 is formed, the region where the crystal defects 70 are formed is exposed on the side surface of the trench 14. Since the width of the opening 54a is narrow, the width of the trench 14 is narrow. Therefore, the trench 14 can be formed such that the side surface of the trench 14 is substantially perpendicular to the upper surface 12a.

[0049] Next, as shown in FIG. 13, the SiC substrate 12 is etched. The etching method used here is not particularly limited, but for example, an etching method with high isotropy such as wet etching can be used. In the region where the crystal defects 70 are formed, the etching rate is faster than in the region where the crystal defects 70 are not formed. For this reason, etching proceeds rapidly on the side surface of the trench 14, and the etching rate is extremely slow on the bottom surface of the trench 14. For this reason, the width of the trench 14 expands with almost no change in the depth of the trench 14. By the process of expanding the width of the trench 14, the interval C1 between the trenches 14 is reduced from a value of 400 nm or more to a value of 200 nm or less. After the process of expanding the width of the trench 14, the interval C1 is 10 nm or more and 200 nm or less.

[0050] Next, the mask 54 is removed. Next, by annealing the SiC substrate 12, the crystal defects 70 remaining in the SiC substrate 12 are reduced. Thereafter, in the same manner as in Example 1, the gate insulating film 16, the gate electrode 18, the interlayer insulating film 20, the source electrode 22, and the drain electrode 24 are formed, and the field effect transistor 10 shown in FIG. 1 is completed.

[0051] In the manufacturing method of Example 3, after forming the narrow trench 14 (see FIG. 12), the side surface of the trench 14 is etched to expand the width of the trench 14, thereby forming the wide trench 14 (see FIG. 13). When the trench 14 is formed in this way, it is possible to form the trench 14 having a wide width and a side surface substantially perpendicular to the upper surface 12a. Therefore, a field effect transistor 10 with low on-resistance can be manufactured.

[0052] In FIG. 11, crystal defects 70 were formed in the entire depth range corresponding to the trench 14. However, in the manufacturing method of Example 3, the crystal defects 70 may be formed only in the region etched in the etching process of the side surface of the trench 14.

Example

[0053] In the manufacturing method of Example 4, as shown in FIG. 14, inert ions are implanted into the upper surface 12a of the SiC substrate 12. Thereby, crystal defects 70 are formed inside the SiC substrate 12. Here, crystal defects 70 are formed in the entire range including the source layer 30, the body layer 32, and the drift layer 34 in the vicinity of the body layer 32 (that is, the depth range where the trench 14 is formed).

[0054] Next, in the same manner as in Example 3, as shown in FIG. 12, a plurality of trenches 14 are formed on the upper surface 12a of the SiC substrate 12. Here, each trench 14 is formed so as to penetrate the source layer 30 and the body layer 32 and reach the drift layer 34. The trench 14 is formed so as to penetrate a region where crystal defects 70 are formed. When the trench 14 is formed, the region where the crystal defects 70 are formed is exposed on the side surface of the trench 14. Since the width of the opening 54a is narrow, the width of the trench 14 is narrow. Therefore, the trench 14 can be formed such that the side surface of the trench 14 is substantially perpendicular to the upper surface 12a.

[0055] Next, in the same manner as in Example 3, as shown in FIG. 13, the SiC substrate 12 is etched. In the region where the crystal defects 70 are formed, the etching rate is faster than that in the region where the crystal defects 70 are not formed. Therefore, the depth of the trench 14 hardly changes, while the width of the trench 14 expands. By the process of expanding the width of the trench 14, the interval C1 between the trenches 14 is reduced from a value of 400 nm or more to a value of 200 nm or less. After the process of expanding the width of the trench 14, the interval C1 is 10 nm or more and 200 nm or less.

[0056] Next, the mask 54 is removed. Next, by annealing the SiC substrate 12, the crystal defects 70 remaining in the SiC substrate 12 are reduced. Thereafter, in the same manner as in Example 1, the gate insulating film 16, the gate electrode 18, the interlayer insulating film 20, the source electrode 22, and the drain electrode 24 are formed, whereby the field effect transistor 10 shown in FIG. 1 is completed.

[0057] In the manufacturing method of Example 4, after forming the narrow trench 14 (see FIG. 12), the side surface of the trench 14 is etched to expand the width of the trench 14, thereby forming a wide trench 14 (see FIG. 13). When the trench 14 is formed in this way, a trench 14 having a wide width and a side surface substantially perpendicular to the upper surface 12a can be formed. Therefore, a field effect transistor 10 having a low on-resistance can be manufactured.

[0058] In addition, in FIG. 14, crystal defects 70 were formed throughout the depth range corresponding to the trench 14. However, in the manufacturing method of Example 4, the crystal defects 70 may be formed only in the region to be etched in the etching process of the side surface of the trench 14.

[0059] In the field effect transistor 10 described above, the side surface of the trench 14 was perpendicular to the upper surface 12a. However, by the manufacturing method of any one of Examples 1 to 4, as shown in FIG. 15, a field effect transistor may be manufactured in which the side surface of the trench 14 is inclined so that the width of the trench 14 becomes wider toward the lower side. In this configuration, the inter-trench semiconductor layer 40 has an inverted taper shape with a wider width toward the upper side. In this case, the width of the source layer 30 can be made wider than the width of the body layer 32, and the contact resistance between the source layer 30 and the source electrode 22 can be further reduced.

[0060] Also, by the manufacturing method of any one of Examples 1 to 4, as shown in FIG. 16, a field effect transistor may be manufactured in which the side surface of the trench 14 is inclined so that the width of the trench 14 becomes wider toward the upper side. Even in this case, according to the manufacturing method of Examples 1 to 4, the inclination angle of the side surface of the trench 14 can be made smaller than that in FIG. 2, and the contact resistance between the source layer 30 and the source electrode 22 can be reduced compared to FIG. 2.

[0061] In the manufacturing method of Examples 1 to 4, since the width of the trench 14 is expanded after the trench 14 is formed (that is, the width of the inter-trench semiconductor layer 40 is reduced), a mask with a wide pattern width can be used as the mask for forming the trench 14 (that is, the mask 52 in FIG. 5 and the mask 54 in FIG. 12). Therefore, the accuracy required for the photo equipment for forming the mask pattern is not so high, and a field effect transistor with a narrow interval C1 can be manufactured without using expensive photo equipment.

[0062] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Also, the technology illustrated in this specification or the drawings achieves multiple objectives simultaneously, and achieving one of those objectives by itself has technical utility.

Explanation of Reference Numerals

[0063] 10: Field effect transistor, 12: SiC substrate, 14: Trench, 18: Gate electrode, 22: Source electrode, 30: Source layer, 32: Body layer, 34: Drift layer

Claims

1. A method for manufacturing a field effect transistor, comprising: forming a plurality of trenches that penetrate the source layer and the body layer and reach the drift layer on the surface of a SiC substrate having an n-type source layer, a p-type body layer, and an n-type drift layer separated from the source layer by the body layer; forming crystal defects in the source layer and the body layer; After the steps of forming the trenches and forming the crystal defects are performed, the region where the crystal defects are formed in the step of forming the crystal defects is exposed on the side surfaces of the respective trenches, a step of expanding the width of each trench by etching the side surfaces of the respective trenches after the steps of forming the trenches and forming the crystal defects are performed; a step of forming a gate electrode in each trench after the step of expanding the width of each trench is performed; a step of forming a source electrode in contact with the source layer on the surface of the SiC substrate after the step of forming the gate electrode is performed. The manufacturing method further comprising:

2. The step of forming crystal defects is performed after the step of forming the trenches, The step of forming crystal defects is a step of implanting ions at an angle inclined with respect to the thickness direction of the SiC substrate on the side surfaces of the respective trenches. The manufacturing method according to Claim 1.

3. After the step of forming crystal defects is performed, a step of forming a sacrificial oxide film by oxidizing the side surfaces of the respective trenches is included, The step of expanding the width of each trench is a step of etching the sacrificial oxide film. The manufacturing method according to Claim 2.

4. The step of forming crystal defects is a step of forming crystal defects by irradiating the source layer and the body layer with a laser, The step of forming the trenches is performed after the step of forming crystal defects is performed. The manufacturing method according to Claim 1.

5. The step of forming crystal defects is a step of forming crystal defects by implanting inert ions into the source layer and the body layer, The step of forming the trenches is performed after the step of forming crystal defects is performed. The manufacturing method according to Claim 1.

6. ​ The manufacturing method according to any one of claims 1 to 5, wherein after the implementation of the step of expanding the width of each trench, the width of the source layer is wider than the width of the body layer.

7. Before the implementation of the step of expanding the width of each trench, the interval between each trench is 400 nm or more, After the implementation of the step of expanding the width of each trench, the interval between each trench is 10 nm or more and 200 nm or less, The manufacturing method according to any one of claims 1 to 5.

8. A field effect transistor, An SiC substrate having an n-type source layer, a p-type body layer, and an n-type drift layer separated from the source layer by the body layer, the SiC substrate having a plurality of trenches provided on the surface thereof that penetrate the source layer and the body layer and reach the drift layer, A gate electrode provided in each trench, A source electrode in contact with the source layer on the surface of the SiC substrate, having, the interval between each trench is 10 nm or more and 200 nm or less, the width of the source layer is wider than the width of the body layer, a field effect transistor.

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