Load drive circuit and transistor control circuit

Abstract

To realize a protection function against both power supply reverse connection and GND disconnection with a small area in a load driving circuit or the like.SOLUTION: A load driving circuit 1 according to an embodiment, includes: two transistors 3 connected in series with a load L; an off-driving circuit 5 that shifts the two transistors 3 to an off state; and a current limiting circuit 4 that is formed on a P-type semiconductor substrate, and limits a current flowing through the off-driving circuit 5. When sources of the two transistors 3 are connected to each other and the gates thereof are connected to each other, and a potential of a second power supply terminal 2n to be connected to a negative electrode of a power supply Ps rises above the potential of the sources of the two transistors 3, the off driving circuit 5 shifts the two transistors 3 to an off state based on a control current Ic flowing through a parasitic diode 4pd between the P-type semiconductor substrate and the current limiting circuit 4 and the current limiting circuit 4.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a load driving circuit and a transistor control circuit.

Background Art

[0002] Conventionally, in various electronic devices, a load driving circuit that supplies the voltage supplied from a power source to a load at a desired timing by switching the conduction state between a DC power source and the load has been used. A DC power source such as a car battery may be accidentally connected to the load with the positive and negative electrodes reversed from the original. Therefore, the load driving circuit may be provided with a protection circuit against such reverse connection of the power source. For example, in Patent Document 1, as shown in FIG. 9, a load driving circuit in which two transistors Q1 and Q2 are connected in series between the positive electrode of a power source VCC and a load L is disclosed. The drain of transistor Q1 and the drain of transistor Q2 are connected, and the source of transistor Q2 is connected to a power supply terminal 101 connected to the positive electrode of power source VCC. The load L is connected between the source of transistor Q1 and the GND terminal 102. Each element of the driving circuit of Patent Document 1 shown in FIG. 9 is formed on a P-type semiconductor substrate except for transistors Q1 and Q2.

[0003] As shown in FIG. 9, when the positive and negative electrodes of a power source VCC such as a battery are properly connected to the load L in the normal direction, transistors Q1 and Q2 are turned on by a driving signal sent from a charge pump circuit 103 at a desired timing, and the voltage from the power source VCC is supplied to the load L. On the other hand, when the positive and negative electrodes of the power source VCC are connected in the opposite direction to the normal direction with respect to the power supply terminal 101 and the GND terminal 102, a current flows from the GND terminal 102 through the parasitic diode PD3 of the diode D2 and the transistor Q3, the transistor Q3, and the resistor R1 to the power supply terminal 101 connected to the negative electrode of the power source VCC. Therefore, the transistor Q4 is turned on, and thereby the transistor Q2 is turned off. As a result, a current that tries to flow in the direction opposite to the normal direction through the load L and the transistors Q1 and Q2 is blocked.

[0004] Also, between the source and gate of transistor Q2 connected by transistor Q4 in the on state, a voltage exceeding its breakdown voltage is not applied. Further, between the gate of transistor Q1 and the source connected to the GND terminal via load L, due to the action of parasitic diode PD2 of transistor Q5, an excessive voltage is not applied. That is, load L and transistors Q1 and Q2 are protected.

[0005] On the other hand, in the connection of the power supply to the load driving circuit, in addition to the reverse connection of the power supply, a disconnection may occur between the GND terminal of the load driving circuit and the negative electrode of the power supply. Therefore, the load driving circuit may be provided with a protection circuit that prevents the application of an abnormal voltage to the load by turning off the load driving transistor when the GND is disconnected. For example, in Patent Document 2, as shown in FIG. 10, when the disconnection is schematically represented by a switch SW in an open state between terminal P2 and GND1, a semiconductor device in which a switch element M0 connected to load R0 is turned off is disclosed.

[0006] When the wiring between terminal P2 and GND1 is disconnected, the potential of terminal P4 decreases, so the gate-source voltage of switch element M3 decreases, and eventually switch element M3 turns off. As a result, switch element M4 turns on, and terminal P5 and terminal P4 are connected via resistor R7. Then, the decrease in the potential of terminal P4 accelerates, and switch element M0 gradually shifts to the off state, and the potential of terminal P5 decreases as it shifts. On the other hand, since current source IS stops due to the disconnection between terminal P2 and GND1, switch element M1 turns off. Then, as a result of the increase in the potential difference between terminal P1 and terminal P5 due to the decrease in the potential of terminal P5, a voltage equal to or higher than the threshold value of switch element M2 is applied between the gate and source of switch element M2, and switch element M2 turns on. As a result, there is a short circuit between terminal P4 and terminal P5, that is, between the gate and source of switch element M0, and switch element M0 completely turns off. In this way, it is possible to prevent the operation of switch element M0 from becoming unstable due to GND disconnection and an abnormal voltage from being applied to load R0.

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0008] As described above, Patent Document 1 discloses a protection circuit against reverse connection of a DC power supply, and Patent Document 2 discloses a protection circuit against disconnection of a GND wiring. However, in the load driving circuit of Patent Document 1, it is difficult to protect the load, transistors Q1 and Q2 from abnormal operation and excessive voltage when the GND wiring is disconnected. In the semiconductor device of Patent Document 2, it may not be possible to prevent a current flowing in a direction opposite to the normal direction from flowing through the load and the switch element M0 when the power supply is reversely connected. For example, when the semiconductor device of Patent Document 2 is formed on a P-type semiconductor substrate and the DC power supply is reversely connected to the semiconductor device and the load, the potential of the P-type semiconductor substrate that is originally connected to GND rises. In the semiconductor device of Patent Document 2 formed on the P-type semiconductor substrate, parasitic transistors are formed between the back gates of the switch elements M3 and M4, the base of the switch element Q1, and the cathode of the diode D101, and the P-type semiconductor substrate. Therefore, when the potential of the P-type semiconductor substrate rises due to reverse connection of the power supply, current flows through each element connected via the P-type semiconductor substrate and the parasitic diode. As a result, it may not be possible to obtain a desired voltage at each node in the semiconductor device, and there is a concern that the protection circuit may not function. Also, it is conceivable that each element may be destroyed due to a large current flowing through the parasitic diode.

[0009] Therefore, in order to prevent abnormal operation and excessive voltage caused by reverse connection of the power supply and disconnection of the GND wiring in a conventional load driving circuit, it is required to provide both a protection circuit against reverse connection of the power supply and a protection circuit against disconnection of the GND wiring. However, if both of these protection circuits are provided separately on the semiconductor substrate, it may not be possible to obtain a desired chip area and a small power consumption in the load driving circuit.

[0010] In view of the above problems, an object of the present invention is to realize a protection function against both reverse connection of the power supply and GND disconnection with a small area on a P-type semiconductor substrate in a load driving circuit and a transistor control circuit.

Means for Solving the Problems

[0011] A load driving circuit according to an embodiment of the present invention is a load driving circuit that switches the supply and stop of power from a power source to a load. The load driving circuit includes two transistors connected in series with the load between the positive and negative electrodes of the power source, a first power supply terminal to be connected to the positive electrode of the power source, a second power supply terminal to be connected to the negative electrode of the power source, an off-driving circuit connected to the sources and gates of the two transistors to shift the two transistors to an off state, a current limiting circuit formed on a P-type semiconductor substrate connected to the second power supply terminal to limit the current flowing through the off-driving circuit, and a control circuit that generates drive signals for the two transistors. A current path is provided between the first power supply terminal and the second power supply terminal. One of the two transistors has a drain connected to the positive or negative electrode of the power source, and the other of the two transistors has a drain connected to the load. In the two transistors, the sources are connected to each other and the gates are connected to each other. When the potential of the second power supply terminal rises above the potential of the sources of the two transistors, the off-driving circuit is configured to shift the two transistors to an off state based on a control current flowing through a parasitic diode between the P-type semiconductor substrate and the current limiting circuit and the current limiting circuit.

[0012] The transistor control circuit according to an embodiment of the present invention is a transistor control circuit that controls two transistors whose sources are connected to each other and whose gates are connected to each other to switch the conduction state between a power supply and a load. The transistor control circuit includes a first power supply terminal to be connected to the positive electrode of the power supply, a second power supply terminal to be connected to the negative electrode of the power supply, a first output terminal connected to the sources of the two transistors, a second output terminal connected to the gates of the two transistors, an off-drive circuit connected to the first output terminal and the second output terminal, a current limiting circuit formed on a P-type semiconductor substrate to limit the current flowing through the off-drive circuit, and a control circuit that generates drive signals for the two transistors. A current path is provided between the first power supply terminal and the second power supply terminal. When the potential of the second power supply terminal rises above the potential of the first output terminal in a state where the P-type semiconductor substrate is connected to the second power supply terminal, based on a control current flowing through a parasitic diode between the P-type semiconductor substrate and the current limiting circuit and the current limiting circuit, the off-drive circuit is configured to conduct between the first output terminal and the second output terminal. Transistor control circuit.

Effect of the Invention

[0013] According to the load drive circuit and the transistor control circuit of the present invention, it is considered that a protection function against both reverse power supply connection and GND disconnection can be realized with a small area on a P-type semiconductor substrate.

Brief Description of the Drawings

[0014]

Figure 1

Figure 2A

Figure 2B

Figure 3

Figure 4

Figure 5

Figure 6A

Figure 6B

Figure 7

Figure 8

Figure 9

Figure 10

DETAILED DESCRIPTION OF THE INVENTION

[0015] Embodiments of the load driving circuit and the transistor control circuit of the present invention will be described with reference to the drawings. However, the load driving circuit and the transistor control circuit of the present invention are not limited to the embodiments described below. For example, the circuits shown in the respective drawings may include circuit elements not shown, and conversely, may not include all of the circuit elements shown. Further, each element shown in the respective drawings can have arbitrary characteristics and constants unless otherwise specifically described, and it should be understood that the characteristics and constants of each element are limited only by the description in the claims.

[0016] <Configuration of Load Driving Circuit of Embodiment> FIG. 1 shows a load driving circuit 1 which is an example of the load driving circuit of the first embodiment. The load driving circuit 1 in FIG. 1 includes a transistor control circuit 10 which is an example of the transistor control circuit of the first embodiment. The load driving circuit 1 includes a first power supply terminal 2p, a second power supply terminal 2n, two transistors 3 including a first transistor 31 and a second transistor 32, a current limiting circuit 4, and an off driving circuit 5. The load driving circuit 1 in FIG. 1 further includes a control circuit 6 that supplies a driving signal (gate signal) to each of the two transistors 3, and a diode 61. When the potential of the first power supply terminal 2p is lower than the potential of the second power supply terminal 2n, the current flowing from the control circuit 6 toward the first power supply terminal 2p is blocked by the diode 61.

[0017] An external power supply Ps is connected to the load driving circuit 1, and a DC voltage of the power supply Ps is applied and power is supplied. In the example of FIG. 1, a load L is connected between the load connection terminal 2c of the load driving circuit 1 and the negative electrode of the power supply Ps. The two transistors 3 are connected in series with the load L between the positive electrode and the negative electrode of the power supply Ps. The load driving circuit 1 switches the supply and stop of power from the power supply Ps to the load L by the two transistors 3 including the first transistor 31 and the second transistor 32. The load driving circuit 1 is also a control circuit that controls the power supply to the load L.

[0018] The first power supply terminal 2p is a terminal to be connected to the positive electrode of the power supply Ps, and a potential of the positive electrode of the power supply Ps should be applied thereto. The second power supply terminal 2n is a terminal to be connected to the negative electrode of the power supply Ps, and a potential of the negative electrode of the power supply Ps should be applied thereto. For example, a GND potential is applied to the second power supply terminal 2n. Note that the wiring between the negative electrode of the power supply Ps and the second power supply terminal 2n is also referred to as "GND wiring", and the disconnection of the GND wiring is also simply referred to as "GND disconnection".

[0019] The two transistors 3 (the first transistor 31 and the second transistor 32) are both N-channel MOS field-effect transistors (hereinafter also referred to as N-type MOSFETs) in the load driving circuit 1 of FIG. 1. In the driving circuit 1 of FIG. 1, the first transistor 31 and the second transistor 32 are enhancement-type MOSFETs. One of the two transistors 3 (the first transistor 31 in FIG. 1) has a drain connected to the positive electrode of the power supply Ps, and the other of the two transistors 3 (the second transistor 32 in FIG. 1) has a drain connected to the load L.

[0020] One drain of the two transistors 3 may be directly connected to the positive electrode of the power supply Ps, or may be indirectly connected to the positive electrode of the power supply Ps via any element other than the other of the two transistors 3. Similarly, the other drain of the two transistors 3 may be directly connected to the negative electrode of the power supply Ps, or may be indirectly connected to the load L via any element other than one of the two transistors 3. In the driving circuit 1 of FIG. 1, the drain of the first transistor 31 is connected to the positive electrode of the power supply Ps via the first power supply terminal 2p. The drain of the second transistor 32 is connected to the load L via the load connection terminal 2c. One end of the load L is connected to the drain of the second transistor 32, and the other end is connected to the negative electrode of the power supply Ps.

[0021] Note that the two transistors 3 may be connected between the load L and the negative electrode of the power supply Ps. In that case, one of the two transistors 3 (for example, the second transistor 32 in FIG. 1) may have a drain connected to the negative electrode of the power supply Ps, and the other of the two transistors 3 (for example, the first transistor 31 in FIG. 1) may have a drain connected to the load L. One end of the load L is connected to the positive electrode of the power supply Ps, and the other end is connected to the drain of the other of the two transistors 3. That is, one of the two transistors 3 has a drain directly or indirectly connected to the positive electrode or the negative electrode of the power supply Ps.

[0022] In the two transistors 3, the sources are connected to each other and the gates are connected to each other. That is, the source of the first transistor 31 and the source of the second transistor 32 are connected, and the gate of the first transistor 31 and the gate of the second transistor 32 are connected. The sources of the two transistors 3 connected to each other and the gates connected to each other are connected to the off-drive circuit 5. Therefore, the off-drive circuit 5 can shift both of the two transistors 3 to the off state.

[0023] The load L can be any electrical element. For example, passive elements such as a resistor, an inductor, and a capacitor may be connected to the load drive circuit 1 as the load L, and active elements such as individual semiconductor elements such as transistors and semiconductor integrated circuit devices may be connected to the load drive circuit 1 as the load L. Further, the load L may be any electrical device such as an electric motor including inductive reactance, as an example.

[0024] The control circuit 6 generates drive signals for each of the two transistors 3. That is, the control circuit 6 generates gate signals (drive signals) for each of the two transistors 3 that shift the first transistor 31 and the second transistor 32 to the on state or the off state at a desired timing. Therefore, the output port 6a of the control circuit 6 is connected to the gates of the two transistors 3 via the second output terminal 22 of the transistor control circuit 10. The control circuit 6 is directly or indirectly connected to the first power supply terminal 2p and the second power supply terminal 2n, receives power supply from the power supply Ps via the first power supply terminal 2p, and generates drive signals for the two transistors 3. The control circuit 6 may have a charge pump function, and thus may generate a drive signal having a potential higher than the potential of the positive electrode of the power supply Ps. Further, the control circuit 6 preferably has a low voltage malfunction prevention function (UVLO), and is configured to stop the generation operation of the gate signal when the potential of the first power supply terminal 2p is lower than a predetermined threshold voltage.

[0025] In the load driving circuit of the embodiment, a current path Pi is provided between the first power supply terminal 2p and the second power supply terminal 2n. In the load driving circuit 1 of FIG. 1, the current path Pi is provided in the control circuit 6 connected between the first power supply terminal 2p and the second power supply terminal 2n. The current path Pi can be a path passing through any circuit element or circuit block in the control circuit 6. Since the current path Pi is provided between the first power supply terminal 2p and the second power supply terminal 2n, as will be described later, when the GND is disconnected, the potential of the second power supply terminal 2n rises based on the potential of the first power supply terminal 2p, and thus the protection function operates.

[0026] The off-driving circuit 5 is connected to the sources of two transistors 3 (the first transistor 31 and the second transistor 32) that are connected to each other. Further, the off-driving circuit 5 is connected to the gates of two transistors 3 that are connected to each other. Therefore, the off-driving circuit 5 can shift each of the two transistors 3 to the off state by applying a voltage equal to or lower than the gate-source threshold voltage of the two transistors 3 between the gates and sources of the two transistors 3. As will be described later, the off-driving circuit 5 shifts the two transistors 3 to the off state when the power supply Ps is reversely connected or the GND wiring is disconnected.

[0027] In the load driving circuit 1 of FIG. 1, the off-driving circuit 5 includes a first off transistor 51 that shifts each of the two transistors 3 to the off state, and a load element 54. In the example of FIG. 1, the first off transistor 51 is an N-type MOSFET. The drain of the first off transistor 51 is connected to the gates of the two transistors 3, and the source of the first off transistor 51 is connected to the sources of the two transistors 3. Therefore, the first off transistor 51 can shift each of the two transistors 3 to the off state by shifting to a state (for example, the on state of the first off transistor 51) in which the voltage between its drain and source is equal to or lower than the gate-source threshold voltage of the two transistors 3.

[0028] In the load driving circuit 1 of FIG. 1, the load element 54 is a resistance element. One end 541 of the load element 54 is connected to the gate of the first off transistor 51, and the other end 542 of the load element 54 is connected to the source of the first off transistor 51. The load element 54 generates a potential difference based on the control current Ic flowing through the load element 54 between both ends of the load element 54. The voltage generated between both ends of the load element 54 is applied between the gate and the source of the first off transistor 51. Therefore, the first off transistor 51 shifts to the on state based on the potential difference between both ends of the load element 54, or shifts to the off state based on the potential difference between both ends of the load element 54. That is, according to the control current Ic, the first off transistor 51 shifts from the on state to the off state, or from the off state to the on state.

[0029] The current limiting circuit 4 is connected to the off driving circuit 5 and limits the current flowing through the off driving circuit 5 so as not to become excessive. The current limiting circuit 4 is formed on a P-type semiconductor substrate Psub (see FIG. 2A) connected to the second power supply terminal 2n. In the load driving circuit 1 of FIG. 1, the current limiting circuit 4 is constituted by a depletion type transistor 41. The depletion type transistor 41 of FIG. 1 is an N-type MOSFET. As will be described later with reference to FIG. 2A, a parasitic diode 4pd having an anode on the second power supply terminal 2n side and a cathode on the depletion type transistor 41 side is formed between the drain of the depletion type transistor 41 formed on the P-type semiconductor substrate Psub and the second power supply terminal 2n.

[0030] On one hand, the gate and the source of the depletion-type transistor 41 are connected. The gate and the source of the depletion-type transistor 41 are connected to the gate (i.e., the control terminal) of the first off transistor 51 and one end 541 of the load element 54. When the potential of the drain is higher than the potential of the source in the depletion-type transistor 41 with the gate and the source connected, it functions as a constant current source that injects a constant current from the second power supply terminal 2n into the off-drive circuit 5. Note that the gate and the source of the depletion-type transistor 41 do not necessarily have to be short-circuited, and the gate and the source of the depletion-type transistor 41 may be connected via a fixed resistor having a resistance value corresponding to a desired constant current value.

[0031] The control current Ic limited to a predetermined constant current by the depletion-type transistor 41 flows into the load element 54 of the off-drive circuit 5. The current value of the control current Ic can be adjusted by appropriately selecting the gate length and the gate width of the depletion-type transistor 41 and / or the resistance value (i.e., conductivity) between the gate and the source of the depletion-type transistor 41. Therefore, the load drive circuit 1 may be configured such that the control current Ic based on the conductivity between the source and the gate of the depletion-type transistor 41 flows into the off-drive circuit 5. In other words, the load drive circuit 1 may be configured such that the control current Ic based on the gate length and the gate width of the depletion-type transistor 41 flows into the off-drive circuit 5.

[0032] <Configuration of the transistor control circuit of the embodiment> The transistor control circuit 10 of the embodiment is a circuit that controls two transistors, such as the two transistors 3 in FIG. 1, whose sources are connected to each other and whose gates are connected to each other, and switches the conduction state between the power supply Ps and the load L. The transistor control circuit 10 includes substantially all components other than the first transistor 31 and the second transistor 32 in the load driving circuit 1 of the first embodiment illustrated in FIG. 1. That is, in the example of FIG. 1, the transistor control circuit 10 includes a first power supply terminal 2pp to be connected to the positive electrode of the power supply Ps, a second power supply terminal 2nn to be connected to the negative electrode of the power supply Ps, a first output terminal 21 connected to the source of each of the two transistors 3, and a second output terminal 22 connected to the gate of each of the two transistors 3. In the example of FIG. 1, the first power supply terminal 2pp of the transistor control circuit 10 is connected to the positive electrode of the power supply Ps via the first power supply terminal 2p of the load driving circuit 1, and the second power supply terminal 2nn is connected to the negative electrode of the power supply Ps via the second power supply terminal 2n of the load driving circuit 1.

[0033] The transistor control circuit 10 further includes an off-drive circuit 5 connected to the first output terminal 21 and the second output terminal 22, a current limiting circuit 4 formed on a P-type semiconductor substrate Psub (see FIG. 2A) and limiting the current flowing through the off-drive circuit 5, and a control circuit 6 generating drive signals for the two transistors 3. A current path Pi is provided between the first power supply terminal 2pp and the second power supply terminal 2nn. In the example of FIG. 1, the current path Pi is provided in the control circuit 6. The off-drive circuit 5 and the current limiting circuit 4 of the transistor control circuit 10 each have a configuration as described above as the description of the configuration of the load driving circuit 1 of the first embodiment and have functions as described above. That is, the off-drive circuit 5 constituting the transistor control circuit 10 in FIG. 1 includes a first off transistor 51 and a load element 54. The current limiting circuit 4 constituting the transistor control circuit 10 in FIG. 1 is constituted by a depletion-type transistor 41 having a parasitic diode 4pd between it and the P-type semiconductor substrate Psub (see FIG. 2A).

[0034] Hereinafter, the structures of the components of the load driving circuit of the embodiment and the transistor control circuit of the embodiment (particularly the structure of the transistor), and the protection operations of the load driving circuit of the embodiment and the transistor control circuit are described. The matters described below apply to both the load driving circuit of the embodiment and the transistor control circuit of the embodiment, unless otherwise specified as applying to only one of the load driving circuit of the embodiment and the transistor control circuit of the embodiment. Also, the "load driving circuit of the embodiment and the transistor control circuit of the embodiment" is also simply referred to as the "load driving circuit of the embodiment etc.".

[0035] <Structure of Depletion-Type Transistor 41 and First Turn-Off Transistor 51> In FIG. 2A, an example of the structure of the depletion-type transistor 41 constituting the current limiting circuit 4 is schematically shown as a cross-sectional view. Note that at least one depletion-type transistor 41 is formed for one load driving circuit etc. of the embodiment. As shown in FIG. 2A, the depletion-type transistor 41 is formed on the P-type semiconductor substrate Psub.

[0036] An N-type buried layer Nb1 is formed in an appropriate region on the P-type semiconductor substrate Psub, and an N-type epitaxial layer Ne1 is formed so as to cover the N-type buried layer Nb1 and the surface of the P-type semiconductor substrate Psub around the N-type buried layer Nb1. Further, a P-type diffusion isolation layer Pp for separating the N-type epitaxial layer Ne1 from the surrounding region is formed around the N-type epitaxial layer Ne1. The depletion-type transistor 41 is formed in the N-type semiconductor region Na1 such as the N-type epitaxial layer Ne1 and the N-type buried layer Nb1 on the P-type semiconductor substrate Psub.

[0037] That is, a P-type well 41pw is formed in the N-type epitaxial layer Ne1, a P+ region 411p is formed in the P-type well 41pw, and an N+ region 411n and an N-type region 412n are formed on the sides of the P+ region 411p. And a source 4s is provided so as to contact the P+ region 411p and the N+ region 411n. On the other hand, separated from the P-type well 41pw, an N+ region 413n is formed, and a drain 4d is provided on the N+ region 413n. An insulating layer 41i made of an oxide film is formed so as to contact the N-type region 412n and the N-type epitaxial layer Ne1 between the drain 4d and the source 4s, and a gate 4g is provided on the insulating layer 41i.

[0038] A parasitic diode 4pd is formed between the P-type semiconductor substrate Psub, the N-type buried layer Nb1, and the N-type epitaxial layer Ne1. Therefore, the P-type semiconductor substrate Psub is connected to the drain 4d of the depletion-type transistor 41 via the parasitic diode 4pd. In the load driving circuit 1, the P-type semiconductor substrate Psub is connected to the second power supply terminal 2n. On the other hand, in the transistor control circuit 10, the P-type semiconductor substrate Psub is connected to the second power supply terminal 2nn via, for example, a lead frame (not shown) during the manufacturing stage of the transistor control circuit 10, or is connected to the second power supply terminal 2nn via a conductor pattern on a wiring substrate (not shown) when the transistor control circuit is in use. Alternatively, the P-type semiconductor substrate Psub may be connected in the semiconductor chip constituting the transistor control circuit 10 to a conductor region or a highly doped semiconductor region that is connected to the second power supply terminal 2nn when the transistor control circuit 10 is in use.

[0039] In the depletion-type transistor 41, if the potential difference between the gate 4g and the source 4s is less than the threshold value and the potential of the gate 4g is not lower than the potential of the source 4s, a current flows between the drain 4d and the source 4s. Therefore, between the drain 4d and the source 4s of the depletion-type transistor 41 where the source 4s and the gate 4g are connected directly or via a resistor with a relatively small resistance value, a current (control current Ic in FIG. 1) flows when the potential of the drain 4d is higher than the potential of the source 4s. That is, when the potential of the second power supply terminal 2n connected to the drain 4d via the parasitic diode 4pd is higher than the potential of the source 4s and the potential difference is greater than the forward voltage of the parasitic diode 4pd, the control current Ic flows into the off-drive circuit 5. As described above, the current value of the control current Ic can be adjusted by the gate length and gate width of the depletion-type transistor 41 and / or the selection of the conductivity between the gate and the source of the depletion-type transistor 41.

[0040] FIG. 2B schematically shows an example of the structure of the first off-transistor 51 that constitutes the off-drive circuit 5. In the load drive circuit 1 of FIG. 1, the first off-transistor 51 is an enhancement-type N-channel MOSFET. In the example of FIG. 2B, the first off-transistor 51 is formed on the P-type semiconductor substrate Psub, similar to the depletion-type transistor 41 of FIG. 2A. Specifically, the first off-transistor 51 shown in FIG. 2B is formed in the P-type semiconductor region Pw within the N-type semiconductor region Na2 formed on the P-type semiconductor substrate Psub. Since the P-type semiconductor region Pw sandwiches the N-type semiconductor region Na2 between the P-type semiconductor substrate Psub, it is electrically insulated from the P-type semiconductor substrate Psub. Therefore, the first off-transistor 51 is also electrically insulated from the P-type semiconductor substrate Psub.

[0041] That is, an N-type semiconductor region Na2 is formed, which includes an N-type embedded layer Nb2 formed in an appropriate region on a P-type semiconductor substrate Psub, and an N-type epitaxial layer Ne2 that covers the N-type embedded layer Nb2 and the surface of the surrounding P-type semiconductor substrate Psub. A P-type diffusion isolation layer Pp is formed around the N-type epitaxial layer Ne2 to separate the N-type epitaxial layer Ne2 from the surrounding region. And, in a P-type semiconductor region Pw composed of a P-type well within the N-type semiconductor region Na2, a first off-use transistor 51, which is an enhancement-type N-type MOSFET having the P-type semiconductor region Pw as a back gate, is formed.

[0042] That is, a gate 51g is provided between an N+ region 511n and an N+ region 512n formed in the P-type semiconductor region Pw, a drain 51d is provided on the N+ region 511n, and a source 51s is provided on the N+ region 512n. Further, a P+ region 511p is formed as a back gate BG within the P-type semiconductor region Pw. Since the first off-use transistor 51 is formed within the P-type semiconductor region Pw and is thus electrically insulated from the P-type semiconductor substrate Psub, for example, even if the potential of the P-type semiconductor substrate Psub rises due to reverse connection of the power supply Ps, no current flows into the first off-use transistor 51 from the P-type semiconductor substrate Psub side. Therefore, in the case of reverse connection of the power supply Ps or disconnection of the GND wiring, etc., the first transistor 31 and the second transistor 32 can be shifted to an off state to protect these two transistors and the load L.

[0043] Note that the first-off transistor 51 may not be formed on the P-type semiconductor substrate Psub. However, when the first-off transistor 51 is formed on the P-type semiconductor substrate Psub together with the current limiting circuit 4, it is advantageous for miniaturization of the load driving circuit 1 and the transistor control circuit 10. Further, all components of the load driving circuit 1 except the first transistor 31 and the second transistor 32 may be formed on the P-type semiconductor substrate Psub. That is, the entire transistor control circuit 10 of the embodiment may be integrated on the P-type semiconductor substrate Psub. It is considered that a smaller-sized load driving circuit 1 and transistor control circuit 10 are realized.

[0044] <Protection operation when power supply is reverse-connected> Next, the protection operation when the power supply Ps is reverse-connected to the first power supply terminals 2p and 2pp and the second power supply terminals 2n and 2nn in the load driving circuit and the like of the embodiment will be described with reference to FIG. 3. In FIG. 3, the path of the current (control current Ic) flowing when the power supply Ps is reverse-connected in the load driving circuit and the like of the embodiment is indicated by a broken-line arrow. In FIG. 3, the positive electrode of the power supply Ps is connected to the second power supply terminal 2n and the load L, and the negative electrode of the power supply Ps is connected to the first power supply terminal 2p.

[0045] When the power supply Ps is reverse-connected, the potential of the second power supply terminal 2n, that is, the P-type semiconductor substrate Psub (see FIG. 2A) becomes the highest potential in the load driving circuit 1. On the other hand, the potential of the first power supply terminal 2p becomes the lowest potential, and the source potential of the two transistors 3, that is, the potential of the first output terminal 21 of the transistor control circuit 10 becomes a potential lower than at least the potential of the P-type semiconductor substrate Psub. Therefore, from the P-type semiconductor substrate Psub, through the parasitic diode 4pd, the drain and source of the depletion-type transistor 41 constituting the current limiting circuit 4, and the load element 54 of the off-driving circuit 5, the control current Ic limited by the current limiting circuit 4 flows to the sources of the two transistors 3. The control current Ic flows from the sources of the two transistors 3 through the parasitic diode between the drain and source of the first transistor 31 to the negative electrode of the power supply Ps. That is, the control current Ic flows along the path indicated by the broken-line arrow shown in FIG. 3.

[0046] When the control current Ic flows through the load element 54 and the gate-source voltage of the first off transistor 51 increases and exceeds the threshold voltage of the first off transistor 51, the first off transistor 51 turns on. When the first off transistor 51 turns on, the first output terminal 21 and the second output terminal 22 of the transistor control circuit 10 are electrically connected, and the gates and sources of the two transistors 3 are substantially short-circuited. Therefore, the first transistor 31 and the second transistor 32 turn off. Accordingly, excessive voltage is prevented from being applied to the load L and the first transistor 31 and the second transistor 32, and abnormal operation is prevented from occurring.

[0047] When the power supply is reverse-connected, the first off transistor 51 is formed in the P-type semiconductor region Pw that sandwiches the N-type semiconductor region Na2 between the P-type semiconductor substrate Psub as shown in FIG. 2B. Therefore, current does not flow from the P-type semiconductor substrate Psub. Therefore, the two transistors 3 can be shifted to the off state by the first off transistor 51 without being affected by the current from the P-type semiconductor substrate at a high potential.

[0048] In addition, in the load driving circuit and the like of the embodiment, the control current Ic flowing through the off driving circuit 5 is limited by the current limiting circuit 4. Therefore, low power consumption can be achieved, and protection against reverse power supply connection and protection against GND disconnection described later can be realized. In particular, in an example such as FIG. 1, the current limiting circuit 4 is composed of a depletion type transistor 41 that functions as a constant current source by short-circuiting the gate-source or connecting through a fixed resistor. Therefore, the off driving circuit 5 can be stably operated. Further, the control current Ic flows only when the potential of the P-type semiconductor substrate Psub is higher than the potential of the sources of the two transistors 3 due to reverse power supply connection or the like. When the power supply Ps is properly connected, the control current Ic does not flow. Also in this respect, in the load driving circuit and the like of the embodiment, protection against reverse power supply connection and the like can be realized with low power consumption.

[0049] Furthermore, in examples such as FIG. 1, since the current limiting circuit 4 is constituted by the depletion type transistor 41, it is possible to have a high breakdown voltage with respect to the voltage applied to the load driving circuit etc. of the embodiment when the power supply is reversely connected. Specifically, for example, when current directly flows from the parasitic diode 4pd to the off driving circuit 5 without the current limiting circuit 4 being provided, the breakdown voltage with respect to the voltage applied to the load driving circuit etc. of the embodiment due to the reverse connection of the power supply is limited to the breakdown voltage between the gate and source of the first off transistor 51, and a breakdown voltage of only about 5V to 10V can be obtained, for example. On the other hand, by constituting the current limiting circuit 4 with a depletion type transistor 41 having a high drain-source breakdown voltage, it may be possible to obtain a breakdown voltage of 50V or more, for example.

[0050] <Protection operation when GND is disconnected> Next, the protection operation when the GND wiring is disconnected in the load driving circuit etc. of the embodiment will be described with reference to FIG. 4. In FIG. 4, the path of the current (control current Ic) flowing when the GND is disconnected in the load driving circuit etc. of the embodiment is indicated by the broken line arrow. In FIG. 4, the GND wiring from the negative electrode of the power supply Ps to the second power supply terminal 2n is disconnected at an arbitrary location X. Note that the connection between the negative electrode of the power supply Ps and the load L is maintained without being disconnected.

[0051] In an embodiment of a load driving circuit or the like having a current path Pi between the first power supply terminal 2p and the second power supply terminal 2n, when the GND wiring is disconnected, the potential of the second power supply terminal 2n, that is, the potential of the P-type semiconductor substrate Psub (see FIG. 2A), begins to be pulled up to the potential of the first power supply terminal 2p. Further, since the control circuit 6 cannot receive the normal power supply voltage, the control circuit 6 cannot output a gate signal sufficient to completely turn on the two transistors 3, and the drain-source voltage of the first transistor 31 increases. On the other hand, the gate-source of the second transistor 32 is connected by a parasitic diode between the drain-source biased in the forward direction, and the drain of the second transistor 32 is connected to the negative electrode of the power supply Ps via the load L. Therefore, the source potential of the two transistors 3, that is, the potential of the first output terminal 21 of the transistor control circuit 10 decreases.

[0052] In this way, the potential of the P-type semiconductor substrate Psub rises toward the potential of the first power supply terminal 2p (that is, the potential of the positive electrode of the power supply Ps), while the potential of the sources of the two transistors 3 decreases. Therefore, when the potential of the P-type semiconductor substrate Psub rises above the potential of the sources of the two transistors 3, similar to the case of reverse power supply connection, a control current Ic flows from the P-type semiconductor substrate Psub (the second power supply terminal 2n) to the current limiting circuit 4 and the off-driving circuit 5 through the parasitic diode 4pd. The control current Ic further flows to the sources of the two transistors 3, and flows into the negative electrode of the power supply Ps through the parasitic diode between the drain-source of the second transistor 32 and the load L.

[0053] Then, due to the control current Ic, similar to the case of reverse power supply connection, the first off-transistor 51 is turned on by the potential difference generated across the load element 54, the first output terminal 21 and the second output terminal 22 are electrically connected, and the first transistor 31 and the second transistor 32 are in a stable off state. Therefore, an excessive voltage is prevented from being applied to the load L, the first transistor 31, and the second transistor 32, and abnormal operation is prevented from occurring.

[0054] In the protection operation when the GND is disconnected, it is considered more preferable that the control circuit 6 has the above-described UVLO function. That is, when the GND is disconnected, a normal power supply voltage is not applied to the control circuit 6, so the UVLO function operates to lower the potential of the gates of the two transistors 3. Therefore, the two transistors 3 can be surely shifted to the off state, and the potential of the sources of the two transistors 3 can be made lower than the potential of the P-type semiconductor substrate Psub.

[0055] If the two transistors 3 are turned off by the UVLO function of the control circuit 6, it seems that the two transistors 3 and the load L can be protected even without the actions of the current limiting circuit 4 and the off driving circuit 5. However, when the second power supply terminal 2n is completely pulled up to the potential of the first power supply terminal 2p, the operation in the load driving circuit 1 becomes unstable, and it is also conceivable that the gates of the two transistors 3 become in a floating state. And due to the leakage current to the floating gates, the off state of the two transistors 3 may not be maintained. By inserting a pull-down resistor between the gates and sources of the two transistors 3, the floating state of the gates of the two transistors 3 can be prevented. However, in that case, even when the power supply Ps is properly connected, current flows through the pull-down resistor, the power consumption current increases, and the efficiency decreases. On the other hand, in the load driving circuit and the like of the embodiment, the control current Ic does not flow when the power supply Ps is properly connected. Therefore, the protection function can be stably realized without substantially reducing the efficiency.

[0056] As described above, the load driving circuit 1 of the embodiment is configured such that when the potential of the second power supply terminal 2n rises above the potential of the sources of the two transistors 3, the off driving circuit 5 shifts the two transistors 3 to the off state. The off driving circuit 5 shifts the two transistors 3 to the off state based on the control current Ic flowing through the parasitic diode 4pd between the P-type semiconductor substrate Psub and the current limiting circuit 4 and the current limiting circuit 4.

[0057] Further, in the transistor control circuit 10 of the embodiment, when the potential of the second power supply terminal 2nn rises above the potential of the first output terminal 21 with the P-type semiconductor substrate Psub and the second power supply terminal 2nn connected, the off-drive circuit 5 is configured to conduct between the first output terminal 21 and the second output terminal 22. The off-drive circuit 5 conducts between the first output terminal 21 and the second output terminal 22 based on the control current Ic flowing through the parasitic diode 4pd between the P-type semiconductor substrate Psub and the current limiting circuit 4 and the current limiting circuit 4.

[0058] According to the load drive circuit of the embodiment and the transistor control circuit of the embodiment configured as described above, in both the case of reverse power supply connection and GND disconnection, a common circuit turns off the transistor connected to the load, thereby protecting the transistor and the load from excessive voltage application and abnormal operation. Since there is no need to provide a protection circuit individually for each of the reverse power supply connection and GND disconnection, it is possible to protect the load and the like at the time of reverse power supply connection and GND disconnection with a smaller size and less power consumption compared to the prior art. Further, by configuring the current limiting circuit with a depletion-type transistor, the off-drive circuit can be stably operated with even less consumption current. Also, the breakdown voltage at the time of reverse power supply connection can be increased, and it can be used for a power supply with a larger voltage.

[0059] <Modification example of the load drive circuit etc. of the embodiment> FIG. 5 shows a load driving circuit 1a which is a first modification of the load driving circuit 1 of the first embodiment in FIG. 1, and a transistor control circuit 10a which is a first modification of the transistor control circuit 10 of the first embodiment. The load driving circuit 1a and the transistor control circuit 10a are different from the load driving circuit 1 and the transistor control circuit 10 in FIG. 1 in that they each include a load element 54a composed of a MOSFET instead of a resistance element in the off driving circuit 5. The functions of the components other than the load element 54a in the load driving circuit 1a and the transistor control circuit 10a and the connection forms between the components are the same as the functions of the components of the load driving circuit 1 and the transistor control circuit 10 in FIG. 1 and the connection forms between the components. Components similar to those shown in FIG. 1 are denoted by the same reference numerals as in FIG. 1 in FIG. 5 or are appropriately omitted, and repeated explanations thereof are omitted.

[0060] As shown in FIG. 5, the load element 54a is composed of an enhancement type N-MOSFET in which the drain and the gate are short-circuited. Since the drain and the gate are short-circuited, the load element 54a functions substantially as a diode. When the control current Ic flows from the current limiting circuit 4 to the load element 54a, a voltage equal to or higher than the threshold voltage of the N-MOSFET constituting the load element 54a is generated between both ends of the load element 54a. Therefore, when a control current Ic that generates a voltage equal to or higher than the threshold voltage of the first off transistor 51 flows between both ends of the load element 54a, the first off transistor 51 is turned on, and the two transistors 3 can be shifted to the off state. For example, the load element 54a may be composed of an N-MOSFET having substantially the same characteristics (particularly substantially the same threshold voltage) as the first off transistor 51. Thus, in the load driving circuit and the like of the embodiment, the load element may be composed of a MOSFET connected in diode form. When the load element is composed of a MOSFET connected in diode form, even if the threshold voltage of the first off transistor 51 fluctuates due to the temperature environment or manufacturing variations, the voltage generated across the load element 54a fluctuates in the same manner as the threshold voltage of the first off transistor 51. Therefore, there is an advantage that the influence on the temperature environment and manufacturing variations can be reduced.

[0061] FIG. 6A shows a load driving circuit 1b which is a second modification of the load driving circuit 1 of the first embodiment shown in FIG. 1, and a transistor control circuit 10b which is a second modification of the transistor control circuit 10 of the first embodiment. The load driving circuit 1b and the transistor control circuit 10b are different from the load driving circuit 1 and the transistor control circuit 10 of FIG. 1 in that they each include a current limiting circuit 4a composed of resistance elements instead of depletion type transistors. FIG. 6B shows an example of the structure of the current limiting circuit 4a in the second modification of FIG. 6A. The functions of the components other than the current limiting circuit 4a in the load driving circuit 1b and the transistor control circuit 10b and the connection form between the components are the same as the functions of the components of the load driving circuit 1 and the transistor control circuit 10 of FIG. 1 and the connection form between the components. Components similar to the components shown in FIG. 1 are given the same reference numerals as in FIG. 1 in FIG. 6A or are appropriately omitted, and repeated explanations thereof are omitted.

[0062] As shown in FIGS. 6A and 6B, one end of the resistor constituting the current limiting circuit 4a is connected to the cathode of the parasitic diode 4pd formed between the second power terminal 2n, that is, the P-type semiconductor substrate Psub and the current limiting circuit 4a. The other end of the resistor constituting the current limiting circuit 4a is connected to the gate of the first off transistor 51 constituting the off driving circuit 5 and one end 541 of the load element 54. Also in the modifications of FIGS. 6A and 6B, by appropriately selecting the resistance value of the resistance element constituting the current limiting circuit 4a according to the power supply voltage of the power supply Ps, the control current Ic flowing through the off driving circuit 5 can be limited to an appropriate current value. Note that in a state where the power supply Ps is appropriately connected to the load driving circuit 1, the P-type semiconductor substrate Psub is at a lower potential than the other end 542 of the load element 54, but the current flowing from the load element 54 side toward the P-type semiconductor substrate Psub is blocked by the parasitic diode 4pd biased in the reverse direction.

[0063] As shown in FIG. 6B, the current limiting circuit 4a composed of resistance elements is formed on the P-type semiconductor substrate Psub, similarly to the depletion type transistor 41 shown in FIG. 2A. That is, an N-type embedded layer Nb1 is formed in an appropriate region on the P-type semiconductor substrate Psub, and an N-type epitaxial layer Ne1 is formed so as to cover the surface of the P-type semiconductor substrate Psub around the N-type embedded layer Nb1. A P-type diffusion isolation layer Pp is formed around the N-type epitaxial layer Ne1. A P-type well 42pw is formed in the N-type epitaxial layer Ne1, and a P+ region 421p and a P+ region 422p are formed in the P-type well 42pw with a space therebetween. A diffusion resistor 42 is formed in the P-type well 42pw between the P+ region 421p and the P+ region 422p. The P+ region 412p is connected to the off-drive circuit 5.

[0064] On the other hand, an N+ region 42n is formed in the N-type epitaxial layer Ne1 at a distance from the P-type well 42pw and is connected to the P+ region 422p by a metal wiring W. The N+ region 42n is electrically connected to the cathode of a parasitic diode 4pd formed between the P-type semiconductor substrate Psub and the N-type semiconductor region Na1. For example, with such a structure, the current limiting circuit 4a can be constituted by the diffusion resistor 42. Thus, in the load drive circuit and the like of the embodiment, the current limiting circuit may be constituted by the diffusion resistor 42 provided between the cathode of the parasitic diode 4pd and the off-drive circuit 5. That is, the current limiting circuit is not limited to the depletion type transistor 41 as in the example of FIG. 1, and may be constituted by any electric element or electric circuit capable of limiting the current flowing through the off-drive circuit 5.

[0065] <Configuration of Load Drive Circuit and Transistor Control Circuit of Second Embodiment> Referring to FIGS. 7 and 8, the load driving circuit of the second embodiment and the transistor control circuit of the second embodiment will be described. FIG. 7 shows a load driving circuit 1α which is an example of the load driving circuit of the second embodiment, and a transistor control circuit 10α which is an example of the transistor control circuit of the second embodiment. FIG. 8 schematically shows an example of the cross-sectional structure of a second OFF transistor 52 included in the OFF driving circuit 5α in the embodiment shown in FIG. 7. In FIG. 7, for the components identical to those shown in FIG. 1, the same reference numerals as those given in FIG. 1 are assigned or appropriately omitted, and repeated descriptions are omitted.

[0066] As shown in FIG. 7, the load driving circuit 1α and the transistor control circuit 10α of the present embodiment include an OFF driving circuit 5α instead of the OFF driving circuit 5 of the load driving circuit 1 and the transistor control circuit 10 in FIG. 1. The OFF driving circuit 5α includes a second OFF transistor 52 and a third OFF transistor 53 for shifting the second OFF transistor 52 to the OFF state. Also, in the example of FIG. 7, the OFF driving circuit 5α includes a first OFF transistor 51 constituted by a plurality of transistors connected in series, and a plurality of load elements combined with each transistor of the first OFF transistor 51. The first OFF transistor 51 in the example of FIG. 7 includes two transistors (transistor 51α and transistor 51β), and therefore, the OFF driving circuit 5α includes two load elements 54α, 54β. Further, the load driving circuit 1α and the transistor control circuit 10α in FIG. 7 include two current limiting circuits 4 combined with the transistor 51α and the transistor 51β, respectively. Note that the load driving circuit 1α includes two transistors 3 as in the load driving circuit 1 of FIG. 1. Also, the load driving circuit 1α and the transistor control circuit 10α include a control circuit 6 as in the load driving circuit 1 and the transistor control circuit 10 of FIG. 1.

[0067] In the example of FIG. 7, the second turn-off transistor 52 is a so-called laterally diffused MOSFET (LDMOS). One of the two controlled terminals of the second turn-off transistor 52 (the source in the example of FIG. 7) is connected to the sources of the two transistors 3 via the first output terminal 21 of the transistor control circuit 10α. The other of the two controlled terminals of the second turn-off transistor 52 (the drain in the example of FIG. 7) is connected to the gates of the two transistors 3 via the second output terminal 22 of the transistor control circuit 10α. In the example of FIG. 7, the drain of the second turn-off transistor 52 is connected to the gates of the two transistors 3 via a reverse current prevention element 62 disposed between the second output terminal 22. In FIG. 7, the reverse current prevention element 62 is constituted by a diode. By the reverse current prevention element 62, for example, when the power supply Ps is reversely connected or when the GND is disconnected, the current flowing from the second turn-off transistor 52 to the two transistors 3 is blocked.

[0068] The control terminal of the second turn-off transistor 52 (the gate in the example of FIG. 7) is connected to the output port 6b of the control circuit 6 via a resistor 63 and is also connected to one of the two controlled terminals of the third turn-off transistor 53 (the drain in the example of FIG. 7). The gate of the second turn-off transistor 52 may be pulled up to the potential of the power supply terminal 6p in the control circuit 6 or may receive a gate signal for controlling the state of the second turn-off transistor 52 from the control circuit 6.

[0069] As shown in the cross-sectional view of FIG. 8, the second-off transistor 52 is formed on a P-type semiconductor substrate Psub. Specifically, the second-off transistor 52 is formed in an N-type semiconductor region Na3 including an N-type embedded layer Nb3 and an N-type epitaxial layer Ne3 formed on the P-type semiconductor substrate Psub. A P-type diffusion isolation layer Pp is formed around the N-type epitaxial layer Ne3. Specifically, a P+ region 521p is formed in a P-type well 52pw formed in the N-type epitaxial layer Ne3, and an N+ region 521n is formed on the side of the P+ region 521p. A source 52s is provided so as to contact the P+ region 521p and the N+ region 521n. On the other hand, an N+ region 522n is formed separately from the P-type well 52pw, and a drain 52d is provided on the N+ region 522n. An insulating layer 52i made of an oxide film is formed so as to contact the P-type well 52pw and the N-type epitaxial layer Ne3 between the drain 52d and the source 52s, and a gate 52g is provided on the insulating film 52i.

[0070] As can be understood from FIG. 8, as an example, the second-off transistor 52 having the structure shown in FIG. 8 can be the aforementioned LDMOS. When the second-off transistor 52 has the structure of the LDMOS as shown in FIG. 8, the second-off transistor 52 can have a larger drain-source breakdown voltage compared to a MOSFET in which a source, a drain, and a gate are formed in a P-type well as shown in FIG. 2B.

[0071] A parasitic diode 5pd is formed between the P-type semiconductor substrate Psub, the N-type buried layer Nb3, and the N-type epitaxial layer Ne3. Therefore, as shown in FIGS. 7 and 8, the drain 52d of the second turn-off transistor 52 is connected to the P-type semiconductor substrate Psub (the second power terminal 2n) via the parasitic diode 5pd. Accordingly, when the potential of the P-type semiconductor substrate Psub rises above the source potential of the two transistors 3, as in the case of reverse connection of the power supply Ps, the parasitic diode 5pd is forward-biased. When the second turn-off transistor 52 is in the on state during the forward bias, a current Ir flows from the P-type semiconductor substrate Psub, through the parasitic diode 5pd, to the drain and source of the second turn-off transistor 52, and further to the sources of the two transistors 3.

[0072] In the example of FIG. 7, the third turn-off transistor 53, and the transistors 51α and 51β that constitute the first turn-off transistor 51 are enhancement-type N-type MOSFETs and have the same structure as the structure of the first turn-off transistor 51 shown in FIG. 2B, for example. That is, the third turn-off transistor 53 is formed in a P-type semiconductor region Pw formed in an N-type semiconductor region Na2 on the P-type semiconductor substrate Psub and is insulated from the P-type semiconductor substrate Psub. Therefore, no current flows into the third turn-off transistor 53 from the P-type semiconductor substrate Psub when the power supply Ps is reversely connected. Accordingly, the third turn-off transistor 53 can operate appropriately to turn off the second turn-off transistor 52 when the power supply Ps is reversely connected.

[0073] One of the two controlled terminals of the third turn-off transistor 53, the drain, is connected to the gate of the second turn-off transistor 52 and the resistor 63, and the other controlled terminal (the source in the example of FIG. 7) is connected to the source of the second turn-off transistor 52 and to the sources of the two transistors 3, respectively. The control terminal (the gate in the example of FIG. 7) of the third turn-off transistor 53 is connected to one end 54α1 of the load element 54α together with the control terminal (the gate in the example of FIG. 7) of the transistor 51α.

[0074] One of the controlled terminals of transistor 51β (the drain in the example of FIG. 7) is connected to the gates of the two transistors 3 via the first output terminal 22 of the transistor control circuit 10α, and the other controlled terminal (the source in the example of FIG. 7) is connected to one of the controlled terminals of transistor 51α (the drain in the example of FIG. 7). The other controlled terminal of transistor 51α (the source in the example of FIG. 7) is connected to the sources of the two transistors 3 via the first output terminal 21 of the transistor control circuit 10α.

[0075] The two current control circuits 4 provided in the example of FIG. 7 are each composed of an N-channel depletion-type transistor 41 having its gate and source connected, and have the structure shown in FIG. 2A. That is, the two depletion-type transistors 41 are formed on a P-type semiconductor substrate Psub and each function as a constant current source. Also, a parasitic resistance 4pd is formed between the P-type semiconductor substrate Psub (i.e., the second power supply terminal 2n) and the drains of the two depletion-type transistors 41 respectively.

[0076] One of the gates and sources of the two depletion-type transistors 41 is connected to the control terminal of transistor 51α (the gate in the example of FIG. 7), the gate of the third turn-off transistor 53, and one end 54α1 of the load element 54α. The other gates and sources of the two depletion-type transistors 41 are connected to the control terminal of transistor 51β (the gate in the example of FIG. 7) and one end 54β1 of the load element 54β. The other end 54β2 of the load element 54β is connected to the source of transistor 51β and the drain of transistor 51α. And the other end 54α2 of the load element 54α is connected to the source of transistor 51α.

[0077] <Usefulness of this Embodiment> Next, the operations of the load driving circuit 1α and the transistor control circuit 10α of the present embodiment will be described. Generally, for transistors that drive a load such as two transistors 3, in order to transmit high power to the load, a high gate-source voltage of, for example, 15 V or higher may be applied. A protection circuit that shifts a driving transistor to which such a high gate-source voltage is applied to an off state is required to have a breakdown voltage corresponding to the high voltage applied to the driving transistor. For example, in the load driving circuit 1 of FIG. 1, a high breakdown voltage is required between the drain and source of the first off transistor 51. However, in a transistor having a structure as shown in FIG. 2B, it may be difficult to sufficiently increase the breakdown voltage between the drain and source while starting a significant increase in size. As in the example of FIG. 7, by configuring the first off transistor 51 with a plurality of transistors connected in series, the breakdown voltage can be increased, but using a plurality of transistors may cause an increase in on-resistance and an increase in the delay time until the driving transistor is turned off. Also, by increasing the gate width of the first off transistor 51, the operating speed can be increased, but this will lead to an increase in size and cost.

[0078] On the other hand, it may be necessary to rapidly shift the driving transistor to the off state not only during an abnormality such as reverse connection of the power supply but also during normal operation. In that case, the transistor that turns off the driving transistor is required to operate at high speed, and in the operation of the driving transistor by a plurality of connected off transistors, it may not be possible to turn off the driving transistor within the allowable delay time.

[0079] Therefore, in the present embodiment, in addition to the first turn-off transistor 51, a second turn-off transistor 52 preferably composed of a transistor that can have a high drain-source breakdown voltage alone is provided. In the present embodiment including the second turn-off transistor 52 in addition to the first turn-off transistor 51, for example, when a rapid transition to the off state of the two transistors 3 is required during normal operation, etc., the second turn-off transistor is shifted to the on state by a gate signal from the control circuit 6. Since the drain-source voltage of the two transistors 3 decreases, the two transistors 3 quickly shift to the off state. On the other hand, during reverse connection of the power supply Ps or disconnection of GND, similar to the load driving circuit 1 in FIG. 1, the two transistors 3 are shifted to the off state by the current limiting circuit 4 and the off driving circuit 5α, thereby protecting the load L and the two transistors 3.

[0080] Preferably, a transistor having a breakdown voltage between two controlled terminals higher than the breakdown voltage between two controlled terminals of each transistor (transistor 51α and transistor 51β in the example of FIG. 7) constituting the first turn-off transistor 51 is used as the second turn-off transistor. For example, an LDMOS as illustrated in FIG. 8 that can structurally have a high drain-source breakdown voltage is used as the second turn-off transistor 52. Also, preferably, as in the example of FIG. 7, the first turn-off transistor 51 is composed of a plurality of transistors connected in series to increase the drain-source voltage.

[0081] <Protection Operation of the Present Embodiment> In this embodiment, when the potential of the P-type semiconductor substrate Psub rises above the potential of the first output terminal 21 of the transistor control circuit 1α due to reverse connection of the power supply Ps or disconnection of GND, that is, when the potential of the sources of the two transistors 3 is lower than the potential of the second power supply terminal 2n, the protection operation will be described below. When the potential of the P-type semiconductor substrate Psub rises above the potential of the first output terminal 21, as described with reference to FIGS. 3 and 4, current flows from the P-type semiconductor substrate Psub, through the parasitic diode 4pd, to the two depletion-type transistors 41, and the load elements 54α and 54β respectively. Due to the potential difference generated across the load element 54α, the transistor 51α is turned on, and due to the potential difference generated across the load element 54β, the transistor 51β is turned on. As a result, the gate-source voltage of the two transistors 3 decreases, and the two transistors 3 transition to the off state. Therefore, the two transistors 3 and the load L are protected from excessive voltage application and abnormal operation.

[0082] Also, due to the potential difference generated across the load element 54α, the third turn-off transistor 53 transitions to the on state. Therefore, the potential of the gate of the second turn-off transistor 52 decreases to approximately the potential of the source of the second turn-off transistor 52, the second turn-off transistor 52 becomes off, and the current flowing from the drain to the source of the second turn-off transistor 52 is blocked. That is, as described above, when the second turn-off transistor 52 is in the on state when the potential of the P-type semiconductor substrate Psub rises above the potential of the first output terminal 21, current Ir flows from the P-type semiconductor substrate Psub, through the parasitic diode 5pd, the second turn-off transistor 52, and further to the sources of the two transistors 3. The current Ir will flow to the load L through the parasitic diode between the drain and source of the second transistor 32 even when the two transistors 3 are in the off state. In this embodiment, since the third turn-off transistor 53 causes the second turn-off transistor 52 to transition to the off state, it is possible to block a current such as Ir that attempts to flow from the P-type semiconductor substrate Psub to the load L during reverse connection of the power supply Ps or disconnection of GND.

[0083] In addition, the current Ir that can flow from the second power supply terminal 2nn to the second turn-off transistor 52 when the power supply Ps is reversely connected or the GND is disconnected does not flow to the gates of the two transistors 3 because the reverse current prevention element 62 is arranged as described above. If the reverse current prevention element 62 is not provided, the current Ir will flow to the gates of the two transistors 3, and thus the gate voltage can only drop to a voltage that is lower by the forward voltage drop of the parasitic diode 5pd from the second power supply terminal 2nn. Therefore, the two transistors 3 cannot transition to the off state. In the example of FIG. 7, since the reverse current prevention element 62 is arranged, the two transistors 3 can be transitioned to the off state.

[0084] As described above, the load driving circuit 1α and the transistor control circuit 10α of the present embodiment are configured to transition the two transistors 3 to the off state based on the potential of the control terminal of the second turn-off transistor 52 when the power supply Ps is properly connected. Then, for example, when the potential of the sources of the two transistors 3 becomes lower than the potential of the second power supply terminal 2n due to the reverse connection of the power supply Ps or the disconnection of the GND, the third turn-off transistor 53 is configured to turn off the second turn-off transistor 52 based on the potential difference generated between both ends of the load element 54α. By turning off the second turn-off transistor 52, the current flowing through the parasitic diode 5pd between the P-type semiconductor substrate Psub and the second turn-off transistor 52 is blocked.

[0085] In particular, the fact that the present embodiment includes the third off-transistor 53 can be particularly useful when the load L is an inductive load such as a coil. That is, when the load L is an inductive load, if the two transistors 3 transition to the off state during normal operation, the potential at the sources of the two transistors 3 may drop below the potential of the second power supply terminal 2n. At this time, if the second off-transistor 52 is in the on state, as described above, the current Ir will continue to flow through the parasitic diodes of the second off-transistor 52 and the second transistor 32, and depending on the current value, each component may be damaged. However, if the third off-transistor 53 is provided, when the potential at the sources of the two transistors 3 drops below the potential of the second power supply terminal 2n, the third off-transistor 53 causes the second off-transistor 52 to transition to the off state. Therefore, the current that would otherwise flow through the second off-transistor 52 is blocked, preventing damage to each component.

[0086] As described above, the load driving circuit and the transistor control circuit of the embodiment have been described with reference to the respective drawings. However, the load driving circuit and the transistor control circuit of the embodiment are not limited to those having the configurations shown in the respective drawings and those having the configurations described above. For example, the cross-sectional structures shown in FIGS. 2A, 2B, and 8 are merely examples. Each transistor can be composed of transistors of any conductivity type (N-type or P-type) unless otherwise particularly limited. Also, the first off-transistor 51 in FIG. 7 may be composed of three or more transistors.

Explanation of Reference Numerals

[0087] 1, 1a, 1b, 1α Load driving circuit 10, 10a, 10b, 10α Transistor control circuit 2p, 2pp First power supply terminal 2n, 2nn Second power supply terminal 21 First output terminal 22 Second output terminal 3 Two transistors 31 First transistor 32 Second transistor 4. 4a Current Limiting Circuit 41 Depletion-Type Transistor 4g Gate 4s Source 4d Drain 4pd Parasitic Diode 42 Diffusion Resistance 5. 5α Off-Drive Circuit 51, 51α, 51β First Off Transistor 51g Gate 51s Source 51d Drain 52 Second Off Transistor 52g Gate 52s Source 52d Drain 53 Third Off Transistor 54, 54a, 54α, 54β Load Element 541, 54α1, 54β1 One End of Load Element 542, 54α2, 54β2 The Other End of Load Element 5pd Parasitic Diode 6 Control Circuit 62 Backflow Prevention Element Ic Control Current L Load Na1~Na3 N-Type Semiconductor Region Psub P-Type Semiconductor Substrate Pw P-Type Semiconductor Region (P-Type Well) Pi Current Path Ps Power Supply

Claims

1. A load driving circuit for switching the supply and stop of power from a power source to a load, wherein the load driving circuit includes: two transistors connected in series with the load between the positive and negative electrodes of the power source; a first power terminal to be connected to the positive electrode of the power source; a second power terminal to be connected to the negative electrode of the power source; an off-driving circuit connected to the source and gate of each of the two transistors for shifting the two transistors to an off state; a current limiting circuit formed on a P-type semiconductor substrate connected to the second power terminal for limiting the current flowing through the off-driving circuit; a control circuit for generating driving signals for the two transistors; and is provided with: a current path is provided between the first power terminal and the second power terminal; one of the two transistors has a drain connected to the positive or negative electrode of the power source; the other of the two transistors has a drain connected to the load; in the two transistors, the sources are connected to each other and the gates are connected to each other; When the potential of the second power terminal rises above the potential of the sources of the two transistors, based on the control current flowing through the parasitic diode between the P-type semiconductor substrate and the current limiting circuit and the current limiting circuit, the off-driving circuit is configured to shift the two transistors to an off state. Load driving circuit.

2. The current limiting circuit is constituted by a depletion-type transistor formed in an N-type semiconductor region on the P-type semiconductor substrate, the P-type semiconductor substrate is connected to the drain of the depletion-type transistor via the parasitic diode, The load driving circuit according to claim 1, wherein the control current is configured to flow through the off-driving circuit based on the conductivity between the source and the gate of the depletion-type transistor.

3. The load driving circuit according to claim 1, wherein the current limiting circuit is constituted by a diffusion resistor provided between the cathode of the parasitic diode and the off-driving circuit.

4. The off-driving circuit includes a first off transistor for shifting each of the two transistors to an off state, and a load element for generating a potential difference based on the control current between both ends. The first off-transistor is formed within a P-type semiconductor region that is formed on the P-type semiconductor substrate and electrically insulated from the P-type semiconductor substrate. The source of the depletion-mode transistor is connected to the control terminal of the first off-transistor and one end of the load element. The load driving circuit according to claim 2, wherein the first off-transistor is configured to shift to an on state based on the potential difference.

5. The off-driving circuit further includes a second off-transistor. One of the two controlled terminals of the second off-transistor is connected to the source of each of the two transistors. The other of the two controlled terminals of the second off-transistor is connected to the gate of each of the two transistors via a reverse current prevention element. The load driving circuit according to claim 4, wherein the two transistors are configured to shift to an off state based on the potential of the control terminal of the second off-transistor.

6. The load driving circuit further includes a third off-transistor configured to shift the second off-transistor to an off state. The second off-transistor is formed on the P-type semiconductor substrate. When the potential of the source of the two transistors is lower than the potential of the second power supply terminal, the third off-transistor turns off the second off-transistor based on the potential difference, thereby blocking the current flowing through the parasitic diode between the P-type semiconductor substrate and the second off-transistor. The load driving circuit according to claim 5.

7. A transistor control circuit that controls two transistors whose sources are connected to each other and whose gates are connected to each other to switch the conduction state between a power supply and a load. The transistor control circuit includes: A first power supply terminal to be connected to the positive electrode of the power supply; A second power supply terminal to be connected to the negative electrode of the power supply; A first output terminal connected to the sources of the two transistors; A second output terminal connected to the gates of the two transistors; An off-driving circuit connected to the first output terminal and the second output terminal; A current limiting circuit formed on a P-type semiconductor substrate to limit the current flowing into the off-driving circuit; A control circuit that generates driving signals for the two transistors; And is provided with. A current path is provided between the first power terminal and the second power terminal. When the potential of the second power terminal rises above the potential of the first output terminal with the P-type semiconductor substrate and the second power terminal connected, based on the control current flowing through the parasitic diode between the P-type semiconductor substrate and the current limiting circuit and the current limiting circuit, the off-drive circuit is configured to conduct between the first output terminal and the second output terminal. A transistor control circuit.

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