Chip body and method for manufacturing the same

Abstract

To provide a method for manufacturing a chip body.SOLUTION: An active surface 120 of a chip 100 is attached to a carrier T2, and a heat dissipation layer 150 is formed on the back surface 110 of the chip 100. When the heat dissipation layer 150 is formed, a half groove 140a surrounding the active surface 120 prevents metal residues from accumulating in a gap between the active surface 120 and the carrier and contaminating the chip 100.SELECTED DRAWING: Figure 7D

Description

Technical Field

[0001] The present invention relates to a chip body and a manufacturing method thereof, and more particularly to a chip body for forming a heat dissipation layer on the back surface of a chip and a manufacturing method thereof.

Background Art

[0002] FIG. 9 shows that the active surfaces 11a of a plurality of chips 11 on a wafer 10 are adhered to the surface 21 of a tape 20, and there are groove portions 30 between adjacent chips 11, and the surface 21 is exposed in the groove portions 30. Next, a heat dissipation layer 12 is formed on the back surface 11b of each chip 11 by a sputtering process.

Summary of the Invention

Problems to be Solved by the Invention

[0003] However, in the above-described conventional technology, when the heat dissipation layer 12 is formed on the back surface 11b by the sputtering process, a gap 40 is generated between the active surface 11a and the tape 20 due to the physical properties of the chip 11 and the tape 20 or the process environment (temperature, etc.). By the accumulation of sputtering target atoms on the tape 20 and in the gap 40, a plurality of metal residues 50 are formed. When each metal residue 50 adheres to the active surface 11a, the quality and yield of the chip 11 are affected.

[0004] Therefore, the inventor of the present invention considered that the above-mentioned drawbacks can be improved, and as a result of intensive studies, the present invention was proposed to effectively improve the above-mentioned problems by a reasonable design.

[0005] The present invention has been made in view of such conventional problems. For solving the above problems, the main object of the present invention is to provide a chip body and a manufacturing method thereof. That is, when forming a heat dissipation layer on the back surface of a chip, it is possible to prevent a situation where metal residues accumulate in a gap between the active surface of the chip and the carrier, and to prevent the quality and yield of the chip from being affected.

Means for Solving the Problems

[0006] To solve the above problems, a chip body according to an aspect of the present invention includes a chip and a heat dissipation layer. The chip has a back surface, an active surface, a side surface, and a semi-groove. The heat dissipation layer covers the back surface. The semi-groove surrounds the active surface and is located between the active surface and the side surface. The semi-groove has a first edge adjacent to the active surface and a second edge adjacent to the side surface.

[0007] Another aspect of the present invention is a method for manufacturing a chip body. The method for manufacturing the chip body includes a step of attaching a plurality of chips to a second carrier, each of the chips having a back surface, an active surface, a side surface, and a semi-groove, and forming a heat dissipation layer on the back surface to constitute a plurality of chip bodies. The semi-groove surrounds the active surface and is located between the active surface and the side surface. The semi-groove has a first edge adjacent to the active surface and a second edge adjacent to the side surface. By attaching each of the chips to the second carrier with the active surface, the semi-groove is formed as a shielding space located between each of the chips and the second carrier.

[0008] The semi-groove surrounding the active surface is used as the shielding space located between the chip and the second carrier. In the process of forming the heat dissipation layer, a situation where sputtering target atoms accumulate in the gap between the second carrier and the active surface to form metal residues is prevented, so that the metal residues do not contaminate or damage the chip.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4A

Figure 4B

Figure 4C

Figure 4D

Figure 5A

Figure 5B

Figure 5C

Figure 5D

Figure 6A

Figure 6B

Figure 6C

Figure 6D

Figure 7A

Figure 7B

Figure 7C

Figure 7D

Figure 8A

Figure 8B

Figure 8C

Figure 8D

Figure 9

Mode for Carrying Out the Invention

[0010] Hereinafter, the present invention will be described through embodiments of the present invention. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution of the invention.

[0011] First, an embodiment of a method for manufacturing a chip body according to the present invention will be described in detail with reference to FIGS. 1 and 2.

[0012] First, a wafer 200 is provided. The wafer 200 has a plurality of unseparated chips 100, and each chip 100 has a back surface 110 and an active surface 120. In the present embodiment, a plurality of contact pads 121 are provided on the active surface 120, and each contact pad 121 is electrically connected to a redistribution layer (RDL, not shown). Next, the wafer 200 is attached to the first carrier T1, and the wafer 200 is attached to the first carrier T1 by the back surface 110 of each chip 100, and the active surface 120 of the chip 100 is exposed.

[0013] As shown in FIGS. 3 and 4A, next, a groove portion 140 is formed on the active surface 120, and the groove portion 140 surrounds the active surface 120. Preferably, the first tool K1 cuts the wafer 200 along the scribe line C to form a groove portion 140 surrounding the active surface 120. The groove portion 140 has a bottom surface 143 and two opposing first edge ends 141, and each first edge end 141 is adjacent to the active surface 120. The cross-sectional shape of the groove portion 140 varies depending on the shape of the first tool K1 (see FIGS. 4A to 4D).

[0014] As shown in FIGS. 4A to 4C, the groove portion 140 has two opposing groove side surfaces 144. Each first edge end 141 is located on each groove side surface 144. Each groove side surface 144 is coupled to the bottom surface 143. There is an included angle A between each groove side surface 144 and the bottom surface 143, and the included angle A is 90 degrees or more. As shown in FIG. 4A, the groove side surface 144 is perpendicular to the bottom surface 143, and the included angle A is 90 degrees. Referring to FIGS. 4B and 4C, the included angle A is greater than 90 degrees. Different from FIGS. 4A, 4B, and 4C, the groove side surface 144 shown in FIG. 4D presents an arc-shaped surface.

[0015] As shown in FIGS. 5A to 5D, after forming the groove portion 140, the second tool K2 cuts the wafer 200 along the bottom surface 143 of the groove portion 140 and the scribe line C to separate each chip 100. Each chip 100 has a side surface 130, and the groove portion 140 is divided into two half-groove portions 140a. The half-groove portion 140a surrounds the active surface 120 and is located between the active surface 120 and the side surface 130. The half-groove portion 140a has a first edge end 141 and a second edge end 142. The first edge end 141 is close to the active surface 120, and the second edge end 142 is close to the side surface 130.

[0016] As shown in FIGS. 5A to 5D, a first virtual line Y extending along the side surface 130 passes through the second edge end 142, and a second virtual line X extending along the active surface 120 passes through the first edge end 141. A first distance S1 between the first edge end 141 and the first virtual line Y is 3 μm or more and 10 μm or less (3 μm ≤ S1 ≤ 10 μm). A second distance S2 between the second edge end 142 and the second virtual line X is 5 μm or more and 120 μm or less (5 μm ≤ S2 ≤ 120 μm). A ratio (S2 / S1) of the second distance S2 to the first distance S1 is 0.5 or more and 40 or less (0.5 ≤ S2 / S1 ≤ 40).

[0017] As shown in FIGS. 5A and 5B, when separating each chip 100, the second tool K2 cuts the wafer 200 along the bottom surface 143 of the groove 140, divides the bottom surface 143 into two groove bottom surfaces 143a, the groove side surface 144 is joined to the groove bottom surface 143a, and there is an included angle A between the groove side surface 144 and the groove bottom surface 143a. In this embodiment, the second edge 142 is located on the groove bottom surface 143a, the groove side surface 144 is directed towards the first virtual line Y, and the groove bottom surface 143a is directed towards the second virtual line X. In other embodiments, the groove side surface 144 is an arc-shaped surface and is joined to the groove bottom surface 143a (see FIG. 5D).

[0018] In other embodiments, the second tool K2 cuts the wafer 200 along the bottom surface 143 of the groove 140 and removes the bottom surface 143 (see FIG. 5C). After each chip 100 is separated, the groove side surface 144 remains in the semi-groove 140a, the second edge 142 is located on the groove side surface 144, and the groove side surface 144 is directed towards the intersection point O of the first virtual line Y and the second virtual line X.

[0019] Next, the active surface 120 of each chip 100 is adhered to the second carrier T2, and the semi-groove 140a is made into a shielding space B located between the chip 100 and the second carrier T2 (see FIGS. 6A to 6D). There is a gap G between the side surfaces 130 of adjacent chips 100, and the gap G is 20 μm or more and 1 mm or less (20 μm ≤ G ≤ 1 mm). Next, the first carrier T1 is removed to expose the back surface 110. The first carrier T1 and the second carrier T2 may be selected from adhesive tapes, glass substrates, silicon substrates, etc.

[0020] Next, a heat dissipation layer 150 is formed on the back surface 110 to constitute a plurality of chip bodies 100A (see FIGS. 7A to 7D). Preferably, the heat dissipation layer 150 covers the back surface 110 and the side surface 130 to form a heat sink. The heat dissipation layer 150 is formed by a sputtering process. During the process of forming the heat dissipation layer 150, the shielding space B located between the chip 100 and the second carrier T2 prevents the sputtering target atoms from accumulating in the gap (not shown) between the second carrier T2 and the active surface 120, so as not to form metal residues that contaminate or damage the chip 100.

[0021] As shown in FIGS. 8A to 8D, finally, the device executes a pick and place process to detach each chip body 100A from the second carrier T2.

[0022] The difference between each chip body 100A shown in FIGS. 8A to 8D lies in the shape of the semi-groove 140a. Each chip body 100A includes a chip 100 and a heat dissipation layer 150. The semi-groove 140a surrounds the active surface 120, is located between the active surface 120 and the side surface 130, has a first edge 141 adjacent to the active surface 120 and a second edge 142 adjacent to the side surface 130, and the heat dissipation layer 150 covers the back surface 110. Preferably, the heat dissipation layer 150 also covers the side surface 130.

[0023] As shown in FIGS. 8A and 8B, the semi-groove 140a has a groove side surface 144 and a groove bottom surface 143a. The first edge 141 is located on the groove side surface 144, and the second edge 142 is located on the groove bottom surface 143a. The groove side surface 144 is directed towards the first virtual line Y, and the groove bottom surface 143a is directed towards the second virtual line X. The groove side surface 144 is connected to the groove bottom surface 143a, and there is an included angle A between the groove side surface 144 and the groove bottom surface 143a. The included angle A is 90 degrees or more. The groove side surface 144 is perpendicular to the groove bottom surface 143a, and the included angle A presents 90 degrees (see FIG. 8A). The included angle A is more than 90 degrees (see FIG. 8B). Referring to FIG. 8D, the groove side surface 144 is an arc-shaped surface and is connected to the groove bottom surface 143a.

[0024] As shown in FIG. 8C, the semi-groove portion 140a has only the groove side surface 144, the first edge 141 and the second edge 142 are located on the groove side surface 144, and the groove side surface 144 is directed toward the intersection point O of the first virtual line Y and the second virtual line X.

[0025] Before separating each chip 100, first, a groove portion 140 surrounding the active surface 120 is formed on the active surface 120. After separating each chip 100, the groove portion 140 is made into a semi-groove portion 140a surrounding the active surface 120, and each active surface 120 of each chip 100 is adhered to the second carrier T2, and the semi-groove portion 140a is used as a shielding space B. In the process of forming the heat dissipation layer 150 by sputtering, the shielding space B prevents the situation where sputtering target atoms accumulate in a gap (not shown) between the second carrier T2 and the active surface 120, so that metal residues that contaminate or damage the chip 100 are not formed.

[0026] The above embodiments are for facilitating the understanding of the present invention and are not for limiting the interpretation of the present invention. It goes without saying that the present invention can be changed and improved without departing from its gist, and equivalents of the present invention are included therein.

Explanation of Reference Numerals

[0027] 10 Wafer 11 Chip 11a Active surface 11b Back surface 12 Heat dissipation layer 20 Tape 21 Surface 30 Groove portion 40 Gap 50 Metal residue 100 Chip 100A Chip body 110 Back surface 120 Active surface 121 Contact pad 130 Side surface 140 Groove portion 140a Semi-groove part 141 First edge end 142 Second edge end 143 Bottom surface 143a Bottom surface of the groove part 144 Side surface of the groove part 150 Heat dissipation layer 200 Wafer A Included angle B Shielded space C Scribe line G Spacing K1 First tool K2 Second tool O Intersection point S1 First distance S2 Second distance T1 First carrier T2 Second carrier X Second virtual line Y First virtual line

Claims

1. A chip having a back surface, an active surface, a side surface, and a semi-groove portion, wherein the semi-groove portion surrounds the active surface and is located between the active surface and the side surface, and the semi-groove portion has a first edge adjacent to the active surface and a second edge adjacent to the side surface, and a heat dissipation layer covering the back surface, characterized in that it is a chip body provided with the above.

2. A first virtual line extending along the side surface passes through the second edge, a second virtual line extending along the active surface passes through the first edge, a first distance between the first edge and the first virtual line is 3 μm or more and 10 μm or less, a second distance between the second edge and the second virtual line is 5 μm or more and 120 μm or less, and a ratio of the second distance to the first distance is 0.5 or more and 40 or less. The chip body according to Claim 1, characterized in that.

3. The semi-groove portion has a groove side surface and a groove bottom surface, the first edge is located on the groove side surface, the second edge is located on the groove bottom surface, the groove side surface is directed toward the first virtual line, the groove bottom surface is directed toward the second virtual line, the groove side surface is joined to the groove bottom surface, and there is an included angle between the groove side surface and the groove bottom surface, and the included angle is 90 degrees or more. The chip body according to Claim 1, characterized in that.

4. The semi-groove portion has a groove side surface, the first edge and the second edge are located on the groove side surface, and the groove side surface is directed toward an intersection point of the first virtual line and the second virtual line. The chip body according to Claim 1, characterized in that.

5. The semi-groove portion has a groove side surface and a groove bottom surface, the groove side surface is an arcuate surface, the groove side surface is joined to the groove bottom surface, the groove side surface is located between the groove bottom surface and the active surface, and the second edge is located on the groove bottom surface. The chip body according to Claim 1, characterized in that.

6. The groove side surface is joined to the active surface, and the first edge is located on the groove side surface. The chip body according to Claim 5, characterized in that.

7. A step of attaching a plurality of chips to a second carrier, wherein each of the chips has a back surface, an active surface, a side surface, and a semi-groove portion. The semi-groove portion surrounds the active surface and is located between the active surface and the side surface. The semi-groove portion has a first edge adjacent to the active surface and a second edge adjacent to the side surface. By attaching each of the chips to the second carrier with the active surface, a shielding space is formed with the semi-groove portion located between each of the chips and the second carrier. A step of forming a heat dissipation layer on the back surface to form a plurality of chip bodies. A method for manufacturing a chip body, characterized by including the above steps.

8. Before attaching each of the chips to the second carrier, a wafer having a plurality of the unseparated chips is attached to a first carrier. The wafer is attached to the first carrier with the back surface of each of the chips and the active surface is exposed. A groove portion surrounding the active surface and having a bottom surface and two opposing first edges is formed on the active surface. The wafer is cut along the bottom surface of the groove portion to separate each of the chips, and the groove portion is divided into two semi-groove portions. After attaching the active surface of each of the chips having the side surface, the first edge, the second edge, and the semi-groove portion to the second carrier, the first carrier is removed to expose the back surface. The method for manufacturing a chip body according to claim 7, characterized by the above steps.

9. There is a gap between the side surfaces of each of the chips that are attached to the second carrier and adjacent to each other. The gap is 20 μm or more and 1 mm or less. The method for manufacturing a chip body according to claim 8, characterized by the above feature.

10. A first virtual line extending along the side surface passes through the second edge, and a second virtual line extending along the active surface passes through the first edge. A first distance between the first edge and the first virtual line is 3 μm or more and 10 μm or less, and a second distance between the second edge and the second virtual line is 5 μm or more and 120 μm or less. A ratio of the second distance to the first distance is 0.5 or more and 40 or less. The method for manufacturing a chip body according to claim 7 or 9, characterized by the above features.

11. The groove portion has two opposing groove side surfaces, each of the first edge ends is located on each of the groove side surfaces, each of the groove side surfaces is coupled to the bottom surface, and there is an included angle between each of the groove side surfaces and the bottom surface, the included angle being 90 degrees or more. After separating each of the chips, the bottom surface is taken as two groove bottom surfaces, each of the groove side surfaces is coupled to each of the groove bottom surfaces, the second edge end is located on each of the groove bottom surfaces, and there is the included angle between each of the groove side surfaces and each of the groove bottom surfaces. The method for manufacturing a chip body according to claim 8, characterized in that.

12. The groove portion has two opposing groove side surfaces, each of the first edge ends is located on each of the groove side surfaces, each of the groove side surfaces is coupled to the bottom surface, and there is an included angle between each of the groove side surfaces and the bottom surface, the included angle being greater than 90 degrees. When separating each of the chips, the bottom surface is removed. After separating each of the chips, each of the groove side surfaces is retained in each of the semi-groove portions, and the second edge end is located on each of the groove side surfaces. The method for manufacturing a chip body according to claim 8, characterized in that.

13. The groove portion has two opposing groove side surfaces, each of the groove side surfaces is an arcuate surface, each of the groove side surfaces is coupled to the bottom surface. After separating each of the chips, the bottom surface is taken as two groove bottom surfaces, the second edge end is located on each of the groove bottom surfaces, each of the groove side surfaces is coupled to each of the groove bottom surfaces, and each of the groove side surfaces is located between each of the groove bottom surfaces and the active surface. The method for manufacturing a chip body according to claim 8, characterized in that.

14. Each of the groove side surfaces is coupled to the active surface, and the first edge end is located on each of the groove side surfaces. The method for manufacturing a chip body according to claim 13, characterized in that.

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