Contact structure and method of forming the same

Abstract

To provide a contact structure and a method of forming the same.SOLUTION: A semiconductor device includes a first die including a stack of a first layer in a first region on the reverse side of the first die and a stack of a second layer in a second region on the reverse side of the first die. The stack of the first layer has different layers less in number than the stack of the second layer. A contact structure is formed in the first region on the reverse side of the first die. The contact structure extends through the stack of the first layer, and a first conductive structure on the top side of the first die and a second conductive structure on the reverse side of the first die are conductively connected. The top side and reverse side are the opposite sides.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This application generally describes embodiments related to semiconductor devices and fabrication processes for semiconductor devices.

Background Art

[0002] Memory devices typically include a memory cell array and peripheral circuits. In some examples, the memory cell array can be formed on a first die, referred to as an array die, and the peripheral circuits are formed on a second die, referred to as a peripheral die. The array die and the peripheral die can be bonded to connect the peripheral circuits to the memory cell array.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Aspects of the present disclosure provide a semiconductor device having a contact structure and a method of forming the same.

Means for Solving the Problems

[0005] According to a first aspect, a semiconductor device is provided. The semiconductor device includes a first die. The first die includes a first stack of layers in a first region on the back side of the first die and a second stack of layers in a second region on the back side of the first die. The first stack of layers has fewer different layers than the second stack of layers. A contact structure is formed in the first region on the back side of the first die. The contact structure is configured to extend through the first stack of layers and conductively connect a first conductive structure on the front side of the first die to a second conductive structure on the back side of the first die. The front side is opposite to the back side.

[0006] In some embodiments, the stack of the first layer includes, in order, a first layer, a replacement layer, and a first insulating layer. The stack of the second layer includes, in order, a first layer, a second layer, a conductive layer, a replacement layer, and a first insulating layer.

[0007] In some embodiments, the first layer and the replacement layer have equivalent etching characteristics. The second layer and the first layer have different etching characteristics. The conductive layer and the second layer have different etching characteristics. In some embodiments, the first layer and the replacement layer include the same conductive material. In some embodiments, the first layer includes doped silicon and the replacement layer includes doped silicon.

[0008] In some embodiments, the contact structure includes a conductive portion and a sidewall portion. The conductive portion is configured to be conductively connected to a first conductive structure. The sidewall portion is configured to insulate the conductive portion from the stack of the first layer.

[0009] In some embodiments, the conductive portion includes at least one of tungsten or aluminum. In some embodiments, the sidewall portion includes at least one of silicon oxide, silicon nitride, zirconium oxide, hafnium oxide, aluminum oxide, or tantalum oxide.

[0010] In some embodiments, the semiconductor device further includes a memory cell on a front side of a first die and a second die bonded face-to-face with the first die. The second die includes a substrate and a peripheral circuit network formed on a front side of the substrate for the memory cell. In some embodiments, the memory cell includes a third stack of alternating gate layers and a second insulating layer on a front side of the first die and a plurality of channel structures extending through the third stack.

[0011] In some embodiments, the semiconductor device further includes a second die bonded face-to-face with the first die. The second die includes a memory cell formed on a front side of the second die. A peripheral circuit network is formed on a front side of the first die for the memory cell.

[0012] According to a second aspect of the present disclosure, a method of fabricating a semiconductor device is provided. The method includes, in a first region and from the back side of a first die, replacing a multilayer within a stack of layers formed on the back side of the first die with a replacement layer. A buffer layer is formed on the replacement layer on the back side. A contact hole is formed in the first region by etching the buffer layer and the replacement layer. The contact hole exposes a first conductive structure formed on the front side of the first die. The front side is opposite to the back side.

[0013] In some embodiments, the step of replacing a multilayer within a stack of layers formed on the back side of the first die with a replacement layer further includes forming a recess in the stack of layers in the first region such that a first etch stop layer is at the bottom of the recess. The recess in the stack of layers is filled and a replacement layer covering the stack of layers from the back side of the first die is deposited.

[0014] In some embodiments, the multilayer within the stack of layers is replaced with a replacement layer having etching characteristics equivalent to those of a first etch stop layer within the stack of layers. In some embodiments, the replacement layer and the first etch stop layer are of the same material.

[0015] In some embodiments, an insulating portion of a contact structure is formed on a sidewall of the contact hole. A conductive portion of the contact structure is formed to fill the contact hole and connect to the first conductive structure.

[0016] In some embodiments, the step of forming an insulating portion of a contact structure on a sidewall of the contact hole further includes depositing an insulating material on the sidewall and the bottom of the contact hole. The insulating material is removed from the bottom of the contact hole.

[0017] In some embodiments, a second conductive structure is formed on the back side of the contact structure. The second conductive structure is electrically coupled to the first conductive structure through the contact structure.

[0018] In some embodiments, memory cells are formed on the front side of the first die. Peripheral circuitry for the memory cells is formed on the front side of the second die. The first die and the second die are joined face to face.

[0019] According to a third aspect, a memory system is provided. The memory system includes a semiconductor device and a controller configured to control the operation of the semiconductor device. The controller is connected to the semiconductor device. The semiconductor device includes a die including a contact structure provided on the back side of the die. A first conductive structure is provided on the front side of the die and is connected to the contact structure from the front side of the die. The front side is the side opposite to the back side. A second conductive structure is provided on the back side of the die and is connected to the contact structure from the back side of the die. The contact structure is configured to conductively connect the first conductive structure to the second conductive structure.

[0020] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that various features are not drawn to scale in accordance with standard practice in the industry. In fact, the dimensions of various features may be increased or decreased for clarity of discussion.

Brief Description of the Drawings

[0021]

Figure 1

Figure 2A

Figure 2B

Figure 2C

Figure 2D

Figure 2E

Figure 2F

Figure 3

Figure 4

[0022] The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are set forth below for the sake of brevity of this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are in direct contact, but may also include embodiments where additional features are formed between the first and second features, resulting in the first and second features not being in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations being described.

[0023] Further, to facilitate descriptions of the relationship of one element or feature to another element or feature as illustrated in the figures, spatial relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein. The spatial relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in a different direction (rotated 90 degrees or other orientation), and the spatial relative descriptors used herein may be interpreted accordingly.

[0024] A semiconductor device can include a plurality of dies that are joined together. In some fabrication techniques, the dies can be joined at the wafer level before the formation of the pad structure. For example, a first wafer including a plurality of first dies (e.g., array dies) and a second wafer including a plurality of second dies (peripheral dies) can be joined face to face. The joined wafers can then be further processed, for example, to form a pad structure on the back side of one of the wafers, and the pad structure is used to interface with an external circuit network. In some examples, after the formation of the pad structure, the joined wafers can be diced into chips, and each chip can include two dies (e.g., an array die and a peripheral die) that are joined together, and the pad structure is formed on the back side of one of the two dies.

[0025] While the pad structure is formed on the back side of one of the two dies, the pad structure can be connected to a circuit network formed on the front sides of the two dies by a conductive structure. Some conductive structures are formed by processing steps that act on the front side of the die before bonding, and some conductive structures are formed by processing steps that act on the back side of one of the two dies.

[0026] According to some aspects of the present disclosure, a contact structure can be formed from the back side of one of the two dies, and the contact structure can extend through various layers on the back of the die and can conductively connect to a conductive structure (e.g., the conductive structure is formed by a processing step that acts on the front side of the die) provided on the front side of the die. In some examples, one of the various layers is a silicon layer, and the contact structure extending through the various layers is referred to as a through-silicon contact (TSC) structure. In the following description, the TSC structure is used as an example to illustrate a technique for forming a contact structure, and that technique can be used to form a contact structure that extends through various layers without a silicon layer.

[0027] Note that generally, a circuit network such as a memory cell array, a peripheral circuit network, etc. is provided on the front side (also referred to as the front side in some examples) of the die, and the opposite side of the die is referred to as the back side. The front side and the back side are opposite sides of the die.

[0028] For ease of explanation, the end of the TSC structure connected to the pad structure on the back of the die is referred to as the back side of the TSC structure, and the end of the TSC structure connected to the conductive structure on the front side of the die is referred to as the front side of the TSC structure. The TSC structure can thus function as a connection structure.

[0029] To form the TSC structure, in some examples, through-silicon holes (TSHs) are formed by etching through a stack of layers from the back side of the die, typically before a conductive metal material is deposited on the TSHs. The stack of layers can include different materials with different etching characteristics such as different etch rates, etching directions, etc. During the etching process for forming the TSHs, due to differences in etching characteristics, the TSHs can have non-planar sidewalls, for example, at the interface of two materials with different etching characteristics.

[0030] In some examples, the TSHs typically have a high aspect ratio, and relatively smooth sidewalls may be desirable for the TSHs. The non-planar sidewalls of the TSHs can be a problem for further processing. In some examples, due to other processing requirements, the stack of layers can have quite different etching characteristics. In one example, the stack of layers includes an insulating layer (first layer), a conductive layer (second layer), a second etch stop layer (third layer) for etching the conductive layer, a first etch stop layer (fourth layer) for etching the second etch stop layer, etc. Generally, the etch stop layers are selected to have a relatively large difference in etching characteristics compared to the layer being etched. Therefore, the stack of layers includes three interfaces with relatively large differences in etching characteristics. Specifically, the first layer and the second layer have a relatively large difference in etching characteristics, the second layer and the third layer have a relatively large difference in etching characteristics, and the third layer and the fourth layer have a large difference in etching characteristics. Due to the differences in etching characteristics of the four different materials, it can be difficult to form a TSH with a smooth etching profile around the three interfaces of the sidewalls of the TSH.

[0031] Aspects of the present disclosure provide techniques for reducing the number of different materials in a stack of layers that would extend through a TSC structure, such that the TSC structure can be formed with a relatively smooth sidewall profile. In one example, the stack of layers that would extend through the TSC structure includes two different layers of material and involves one interface. As a result, in some examples, the etching process for forming the TSH is simplified, and more importantly, it becomes easier to obtain a smooth etching profile of the TSH.

[0032] FIG. 1 is a cross-sectional view of a semiconductor device 100 according to an illustrative embodiment of the present disclosure. As shown, the semiconductor device 100 can include a first die (or wafer) D1. The first die D1 has a back side and a front side opposite the back side. The first die D1 can include a first stack of layers 101 in a first region 108 on the back side of the first die D1. The first die D1 can also include a second stack of layers 102 in a second region 109 on the back side of the first die D1. In some examples, the second stack of layers 102 is adjacent to the first stack of layers 101, and the second stack of layers 102 includes more layers of different material properties than the first stack of layers 101. The first die D1 can further include at least one through-silicon contact (TSC) structure 120 formed in the first region 108 on the back side of the first die D1 and extending through the first stack of layers 101. The at least one TSC structure 120 is configured to conductively connect a first conductive structure 131 on the front side of the first die D1 to a second conductive structure 133 on the back side of the first die D1.

[0033] In some embodiments, the stack 101 of the first layer includes, in order, a first layer 111 (illustrated by 111a and also referred to as the first etch stop layer), a replacement layer 116 (illustrated by 116a), and a first insulating layer 117 (illustrated by 117a). The stack 102 of the second layer includes, in order, a first layer 111 (illustrated by 111b), a second layer 112 (also referred to as the second etch stop layer), a conductive layer 113, a replacement layer 116 (illustrated by 116b), and a first insulating layer 117 (illustrated by 117b). In some embodiments, the first layer 111 and the replacement layer 116 have equivalent (e.g., similar or identical) etching characteristics. The second layer 112 and the first layer 111 have different etching characteristics. The conductive layer 113 and the second layer 112 have different etching characteristics.

[0034] Referring further to FIG. 1, the TSC structure 120 can include a conductive portion 121 and a sidewall portion 123 (also referred to as an insulating portion). The conductive portion 121 is configured to be conductively connected to a first conductive structure 131 on the front side and a second conductive structure 133 on the back side. As a result, the second conductive structure 133 can be electrically coupled to the first conductive structure 131 via the TSC structure 120. In one example, the second conductive structure 133 is configured to be a pad-out structure, and the conductive portion 121 includes a conductive metal material such as tungsten, aluminum, etc. It should be noted that in some examples, the first conductive structure 131 can extend into the conductive portion 121 to increase the contact area between the first conductive structure 131 and the conductive portion 121.

[0035] The sidewall portion 123 of the TSC structure 120 is configured to isolate the conductive portion 121 from the stack 101 of the first layer. In one example, the sidewall portion 123 is provided between the conductive portion 121 and the stack 101 of the first layer. The sidewall portion 123 can thus function to electrically separate the conductive portion 121 from the stack 101 of the first layer. Accordingly, the sidewall portion 123 can include an insulating material such as silicon oxide, silicon nitride, zirconium oxide, hafnium oxide, aluminum oxide, tantalum oxide, etc.

[0036] As illustrated in FIG. 1, the TSC structure 120 extends through a stack 101 of the first layer including a first insulating layer 117, a replacement layer 116, and a first layer 111. In one embodiment, the replacement layer 116 and the first layer 111 include different materials and have an interface therebetween. Thus, the TSC structure 120 extends through three different materials and two interfaces. In another embodiment, the replacement layer 116 and the first layer 111 include the same conductive material without an etching difference, so that an uneven interface does not need to be caused by etching. Thus, the TSC structure 120 extends through two different materials and one interface. For example, the same conductive material can be a silicon material (e.g., doped polysilicon, doped amorphous silicon, or doped nanosilicon) or a conductive metal material.

[0037] Furthermore, in some embodiments, the semiconductor device 100 can include a shielding structure 125 formed on the back side of the first die D1. The shielding structure 125 extends through at least one of the first stack 101 or the second stack 102. In the example of FIG. 1, the shielding structure 125 is disposed at the boundary between the first region 108 and the second region 109. As illustrated, the shielding structure 125 can have a high aspect ratio. In particular, in one example, the TSC structure 120 is wider than the shielding structure 125 in the X-Y plane. In addition, the shielding structure 125 can include an insulating material to electrically isolate the second stack 102. In one example, the shielding structure 125 and the sidewall portion 123 of the TSC structure 120 can include the same insulating material.

[0038] Referring further to FIG. 1, the semiconductor device 100 can further include memory cells formed on the front side of the first die D1. In some embodiments, the memory cells include 3D NAND memory cells. By way of non-limiting example, a third stack 103 of alternating word line layers 141 (also referred to as gate layers) and second insulating layers 143 is provided on the front side of the first die D1. The third stack 103 of layers can include an array region in which at least one channel structure 150 is formed and extends through the third stack 103. The alternating word line layers 141, second insulating layers 143, and channel structure 150 can form a stack of transistors, such as a vertical memory cell string. The array of alternating word line layers 141, second insulating layers 143, and channel structure 150 can form an array of vertical memory cell strings. In some examples, the stack of transistors can include selection transistors, such as memory cells, and one or more lower select transistors, one or more upper select transistors, etc. In some examples, the stack of transistors can also include one or more dummy select transistors.

[0039] The second insulating layer 143 can include one or more insulating materials, such as silicon nitride, silicon oxide, etc. The word line layer 141 can include a gate stack of materials such as a high-k gate insulator layer, a metal gate electrode, etc. The channel structure 150 can include a channel layer 153 (e.g., polysilicon), and is surrounded by one or more third insulating layers 155, such as a tunneling layer (e.g., silicon oxide), a charge trapping layer (e.g., silicon nitride), and a barrier layer (e.g., silicon oxide) that can together form an oxide-nitride-oxide (ONO) structure surrounding the channel layer 153. The channel structure 150 can further include a space 151 within the channel layer 153. The space 151 may be void or filled with an insulating material.

[0040] In one embodiment, the first layer 111 (illustrated by 111b) in the second region 109 is configured to serve as a common source line or as a source connection layer that electrically connects the channel layer 153 to the source region of the semiconductor device 100. Accordingly, a portion of one or more third insulating layers 155 is removed such that the first layer 111 is in direct contact with the channel layer 153. For example, this can be achieved by the SWS technique as disclosed in the applicant's co-pending U.S. patent application Ser. No. 17 / 113,662, entitled "TWO-STEP L-SHAPED SELECTIVE EPITAXIAL GROWTH," filed on Dec. 7, 2020, the entire content of which is incorporated herein by reference.

[0041] Furthermore, the third stack 103 can have a stepped region where a plurality of gate contact structures 145 are formed. The gate contact structures 145 are connected to the word line layer 141.

[0042] Referring further to FIG. 1, the semiconductor device 100 can include a second die (or wafer) D2 that is bonded face-to-face (circuit network side is the front and substrate side is the back) to the first die D1 via a bonding interface 180. Accordingly, the second die D2 also has a front side and a back side opposite the front side. The second die D2 includes a substrate 188 and a peripheral circuit network (e.g., address decoder, drive circuit, sense amplifier, etc.) formed on the front side of the substrate 188 for memory cells. Note that the first die D1 initially includes a substrate, and memory cells are formed thereon. The substrate of the first die D1 is removed in some examples before the formation of the TSC structure 120.

[0043] The structure in the first die D1 can be electrically coupled to the structure in the second die D2 through the contact structure in the first die D1, the metal layers in the first die D1 (illustrated as 171 and 172, 171a, 171n, 172a, 172n, etc.), the bonding structure 181 (illustrated as 181a, 181n, etc.) at the bonding interface 180, the metal layers in the second die D2 (illustrated as 191, 191a, 191n, etc.), and the contact structure (not shown) in the second die D2. For example, the channel structure 150 can be electrically connected to the structure of the peripheral circuit network in the second D2 through the metal layers 171n and 172n, the bonding structure 181n, and the metal layer 191n. Similarly, the first conductive structure 131 can be electrically connected to another structure (such as an input / output circuit) of the peripheral circuit network in the second D2 through the metal layers 171a and 172a, the bonding structure 181a, and the metal layer 191a. As a result, in some examples, the second conductive structure 133 can be electrically connected to the input / output circuit through the TSC structure 120 and the first conductive structure 131.

[0044] In the example of FIG. 1, the first die D1 includes memory cells, and the second die D2 includes a peripheral circuit network. Generally, the peripheral circuit network of the second die D2 can interface the memory cells with an external circuit network. For example, the peripheral circuit network receives commands from the external circuit network through the second conductive structure 133, provides control signals to the memory cells, receives data from the memory cells, and outputs the data to the external circuit network through the second conductive structure 133.

[0045] In some embodiments, semiconductor device 100 can include a plurality of array dies (e.g., first die D1) and CMOS dies (e.g., second die D2). The plurality of array dies and CMOS dies can be stacked and bonded together. Each array die is coupled to the CMOS die, and the CMOS die can drive the array dies individually or collectively as well. Further, in some embodiments, semiconductor device 100 includes at least a first wafer and a second wafer that are bonded face-to-face. The first die D1 is provided on the first wafer together with other array dies such as D1, and the second die D2 is provided on the second wafer together with other CMOS dies such as D2. The first wafer and the second wafer are bonded together such that the array die on the first wafer is bonded to the corresponding CMOS die on the second wafer.

[0046] In an alternative embodiment, the second die D2 can include memory cells, and the first die D1 can include a peripheral circuit network (not shown) for the memory cells. Similarly, the peripheral circuit network is coupled to the memory cells via a contact structure in the first die, a bonding interface between the first die and the second die, and a contact structure in the second die. In particular, the second conductive structure 133 is also provided on the back side of the first die D1 and can be coupled to the input / output circuits of the peripheral circuit network via the first conductive structure 131.

[0047] FIGS. 2A, 2B, 2C, 2D, 2E, and 2F are cross-sectional views of semiconductor device 100' at various intermediate steps of manufacturing, according to illustrative embodiments of the present disclosure. In some embodiments, semiconductor device 100' can ultimately become semiconductor device 100.

[0048] As shown, the embodiment of the semiconductor device 100' in FIG. 2A is similar to the embodiment of the semiconductor device 100 in FIG. 1. The description has been provided above, and the description here will be given with an emphasis on the differences. For example, the semiconductor device 100' can include a fourth stack 104 of layers formed on the back side of the first die D1. The fourth stack of layers 104 includes a first etch stop layer 111, a second etch stop layer 112, and a conductive layer 113. The first conductive structure 131 can extend into the fourth stack 104 only by the penetration depth. Specifically, in the example of FIG. 2A, the first conductive structure 131 extends through the first etch stop layer 111 and the second etch stop layer 112 and extends into the conductive layer 113. Note that the penetration depth of the first conductive structure 131 is related to the contact area with a future TSC structure (e.g., the TSC structure 120 in FIG. 1), and thus may be different in other examples.

[0049] In some embodiments, a hard mask layer 114 can be formed on the back side of the fourth stack 104. A photoresist layer 115 can be formed on the back side of the hard mask layer 114. The photoresist layer 115 is patterned such that a portion of the hard mask layer 114 is exposed in the first region 108. In one example, the hard mask layer 114 includes at least one of silicon oxide, silicon nitride, or carbon.

[0050] FIG. 2B illustrates the semiconductor device 100' after the pattern is transferred from the photoresist layer 115 to the hard mask layer 114. This pattern transfer can be achieved by using the photoresist layer 115 as an etching mask to etch a portion of the hard mask layer 114 exposed in the first region 108. The photoresist layer 115 is then removed. As a result, a portion of the conductive layer 113 is exposed in the first region 108.

[0051] FIG. 2C illustrates the semiconductor device 100' after a portion of the conductive layer 113 exposed in the first region 108 is removed. This can be achieved by using the hard mask layer 114 as an etching mask and etching a portion of the conductive layer 113 using the second etch stop layer 112 to determine the end point of the etching. As a result, a portion of the second etch stop layer 112 is exposed in the first region 108, and a recess 107 is formed in the fourth stack 104. In the example of FIG. 2C, the first conductive structure 131 is also exposed from the back side. As described in FIG. 2A, the penetration depth of the first conductive structure 131 can be different in other examples. Therefore, the first conductive structure 131 may or may not be exposed in other examples.

[0052] In FIG. 2D, a portion of the second etch stop layer 112 exposed in the first region 108 is etched and removed using the hard mask layer 114 as an etching mask, and the hard mask layer 114 is also removed. Note that the hard mask layer 114 can be etched during or after a portion of the second etch stop layer 112 is etched. For example, the second etch stop layer 112 can include silicon oxide, silicon nitride, etc. The hard mask layer 114 can include at least one of silicon oxide, silicon nitride, or carbon. In one embodiment, the hard mask layer 114 and the second etch stop layer 112 are both made of silicon oxide so that a portion of the hard mask layer 114 and the second etch stop layer 112 can be etched in the same etching process. In another embodiment, the hard mask layer 114 includes silicon oxide while the second etch stop layer 112 includes silicon nitride. In one example, a portion of the second etch stop layer 112 is etched before the hard mask layer 114 is etched.

[0053] Note that FIGS. 2A-2D illustrate an example of forming a recess 107 in the fourth stack 104 in the first region 108. It should be understood that other patterning and / or etching processes can be designed and implemented to form the recess 107 in the first region 108.

[0054] In FIG. 2E, a replacement layer 116 is formed from the back side of the first die D1. The replacement layer 116 fills the recess 107 and covers the fourth stack 104 from the back side of the first die D1. In one example, the replacement layer 116 can be planarized by chemical mechanical polishing (CMP) from the back side of the first die D1. In some embodiments, the replacement layer 116 includes a conductive material. For example, the conductive material can be selected such that the replacement layer 116 and the first etch stop layer 111 have equivalent (e.g., similar or the same) etching characteristics. During a future etching process, a smooth etching profile can be obtained around the interface between the replacement layer 116 and the first etch stop layer 111. In some embodiments, the replacement layer 116 and the first etch stop layer 111 include the same conductive material and are formed without an interface therebetween. For example, the replacement layer 116 and the first etch stop layer 111 can include a silicon material (e.g., doped polysilicon, doped amorphous silicon, or doped nanosilicon) or a conductive metal material.

[0055] Referring further to FIG. 2E, a first insulating layer 117 (also referred to as a buffer layer) is formed on the back side of the replacement layer 116. The first insulating layer 117 can include an insulating material such as silicon oxide. The first insulating layer 117 can be used to function as a buffer layer during a future etching process to stabilize the etching conditions.

[0056] In FIG. 2F, at least one silicon through-hole (TSH) 126 (also known as a contact hole) is formed in the first region 108. At least one TSH 126 extends through the first insulating layer 117, the replacement layer 116, and the first etch stop layer 111 of the fourth layer stack 104. The TSH 126 exposes the first conductive structure 131 from the back side of the first die D1. In some embodiments, an opening 127 may also be formed in the first region 108. The TSH 126 and the opening 127 have a depth H. The TSH 126 has a width D1, and the opening 127 has a width D2. In some examples, D1 can be larger than D2. The TSH 126 and the opening 127 can be formed in the same patterning process using the photoresist layer 118 as a mask. Further, the opening 127 can have a high aspect ratio in cross-section in the xz plane. The opening 127 can be a trench extending in the y direction.

[0057] Although not shown, in some embodiments, a silicon through contact (TSC) structure, such as the TSC structure 120 in FIG. 1, can be formed in the TSH 126 to contact the first conductive structure 131. In some embodiments, a sidewall portion 123 of the TSC structure 120 is formed on the sidewall 126' of the TSH 126, and a conductive portion 121 of the TSC structure 120 is formed to fill the TSH 126. For example, an insulating material can be deposited on the sidewall 126' and the bottom 126'' of the TSH 126. Then, the insulating material is removed from the bottom 126'' of the TSH 126 such that the insulating material on the sidewall 126' of the TSH 126 forms the sidewall portion 123 of the TSC structure 120. Note that the insulating material may cover and then be removed from a portion of the first conductive structure 131. Thereafter, a conductive material is deposited to fill the TSH 126 and form the conductive portion 121 of the TSC structure 120. The conductive material may overfill the TSH 126, and a CMP process can be used to remove the overfilled portion of the conductive material.

[0058] Furthermore, in some embodiments, a shielding structure such as the shielding structure 125 in FIG. 1 can be formed in the opening 127. In one embodiment, the sidewall portion 123 of the shielding structure 125 and the TSC structure 120 includes the same insulating material and is formed in the same deposition process (note that D1 can be larger than D2). In another embodiment, the sidewall portion 123 of the shielding structure 125 and the TSC structure 120 are formed in separate processes and may or may not include the same material.

[0059] Note that in the example of FIG. 2F, the opening 127 is formed in the first region 108, or more precisely, at the boundary between the first region 108 and the second region 109. In another example, the opening 127 can be formed in the first region 108 without being at the boundary. In another example, the opening 127 can be formed in the second region 109 whether or not there is a boundary. Accordingly, the TSH 126 and the opening 127 can be formed in separate etching processes.

[0060] FIG. 3 is a flowchart of a process 300 for manufacturing an exemplary semiconductor device such as the semiconductor device 100 in FIG. 1 according to an embodiment of the present disclosure.

[0061] The process 300 begins at step S310, where in the first region and from the back side of the first die, the multilayer in the stack of layers formed on the back side of the first die is replaced with a replacement layer. In some embodiments, in order to replace the multilayer with the replacement layer, a recess is formed in the stack of layers in the first region (e.g., FIGS. 2A-2D). The first etch stop layer of the stack of layers can be the bottom of the recess. Then, the recess in the stack of layers is filled and a replacement layer is deposited to cover the stack of layers from the back side of the first die (e.g., FIG. 2E).

[0062] In some embodiments, the stack of layers includes a first etch stop layer, a second etch stop layer, and a conductive layer. In some embodiments, forming the recess includes etching a portion of the conductive layer and a portion of the second etch stop layer from the back side of the first die based on a mask such that the first etch stop layer is exposed. In some embodiments, the back side of the replacement layer can be planarized, for example, by CMP. In some embodiments, the multiple layers within the stack of layers are replaced with a replacement layer having etch characteristics equivalent (e.g., similar or identical) to the first layer within the stack of layers. In one example, the replacement layer and the first etch stop layer are of the same material (e.g., doped silicon).

[0063] Process 300 then proceeds to step S320 by forming a buffer layer on the replacement layer on the back side (e.g., FIG. 2E). The buffer layer can include an insulating material. The buffer layer can be used to function as a buffer layer during future etching processes to stabilize the etching conditions.

[0064] In step S330, contact holes are formed in the first region by etching the buffer layer and the replacement layer. The contact holes expose a first conductive structure formed on the front side of the first die. The front side is opposite the back side. For example, a TSH can be formed in the first region (e.g., FIG. 2F).

[0065] In some embodiments, a contact structure (e.g., a TSC structure) is formed in the contact holes. Specifically, an insulating portion (also referred to as a sidewall portion) of the contact structure is formed on the sidewalls of the TSH, and a conductive portion of the contact structure that fills the TSH and contacts the first conductive structure is formed.

[0066] In some embodiments, an insulating material is deposited on the sidewalls and the bottom of the TSH. The insulating material is then removed from the bottom of the TSH such that the insulating material on the sidewalls of the TSH forms the sidewall portion of the TSC structure. Thereafter, a conductive material is deposited to fill the TSH and form the conductive portion of the TSC structure.

[0067] In some embodiments, a second conductive structure is formed on the back side of the TSC structure. The second conductive structure is electrically coupled to the first conductive structure via the TSC structure. The second conductive structure can be configured to include, for example, a pad-out structure.

[0068] In some embodiments, a shielding structure is formed that extends through the buffer layer, the replacement layer, and the first etch stop layer. The shielding structure can include an insulating material.

[0069] In some embodiments, memory cells are formed on the front side of the first die. Peripheral circuitry for the memory cells is formed on the front side of the second die. In one example, the first die and the second die are face-to-face bonded such that a first bonding structure connected to the first conductive structure in the first die is bonded to a second bonding structure connected to the input / output circuitry of the peripheral circuitry in the second die.

[0070] Note that the semiconductor device 100 can be suitably used in a memory system.

[0071] FIG. 4 shows a block diagram of a memory system device 400 according to some examples of the present disclosure. The memory system device 400 includes one or more semiconductor memory devices, such as illustrated by semiconductor memory devices 411, 412, 413, and 414, each configured similarly to the semiconductor device 100. In some examples, the memory system device 400 is a solid state drive (SSD).

[0072] The memory system device 400 can include other suitable components. For example, the memory system device 400 includes an interface 401 and a master controller 402 that are coupled together as shown in FIG. 4. The memory system device 400 can include a bus 420 that couples the master controller 402 to semiconductor memory devices 411-414. In addition, the master controller 402 is connected to the semiconductor memory devices 411-414 respectively, as illustrated by respective control lines 421, 422, 423, and 424.

[0073] The interface 401 is mechanically and electrically appropriately configured to connect between the memory system device 400 and the host device and can be used to transfer data between the memory system device 400 and the host device.

[0074] The master controller 402 is configured to connect the respective semiconductor memory devices 411-414 to the interface 401 for data transfer. For example, the master controller 402 is configured to provide enable / disable signals to the semiconductor memory devices 411-414 respectively to operate one or more of the semiconductor memory devices 411-414 for data transfer.

[0075] The master controller 402 is responsible for the completion of various instructions within the memory system device 400. For example, the master controller 402 can perform bad block management, error checking and correction, garbage collection, etc.

[0076] In some embodiments, the master controller 402 is implemented using a processor chip. In some examples, the master controller 402 is implemented using multiple microcontroller units (MCUs).

[0077] As used herein, "device" or "semiconductor device" generally refers to any suitable device, such as a memory circuit, a semiconductor chip in which a memory circuit is formed on a semiconductor chip (or die), a semiconductor wafer in which a plurality of semiconductor dies are formed on a semiconductor wafer, a stack of semiconductor chips, a semiconductor package including one or more semiconductor chips assembled on a package substrate, and the like.

[0078] As used herein, "substrate" generally refers to an object being processed in accordance with the present invention. The substrate may include any material part or structure of a device, particularly a semiconductor or other electronics device, such as a semiconductor wafer, a basic substrate structure such as a reticle, or a thin film, etc., which may be on or above the basic substrate structure. Therefore, the substrate is not limited to any particular patterned or unpatterned basic structure, lower layer or upper layer, but rather is intended to include any such layer or basic structure, as well as any combination of layers and / or basic structures. Although a particular type of substrate may be referred to in the description, this is for illustrative purposes only.

[0079] The substrate can be any suitable substrate such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, and / or a silicon on insulator (SOI) substrate. The substrate may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. The Group IV semiconductor may include Si, Ge, or SiGe. The substrate may be a bulk wafer or an epitaxial layer.

[0080] The above outlines the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should recognize that they can immediately use the present disclosure as a basis for designing or modifying other processes and structures that implement the same objectives and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Explanation of Reference Numerals

[0081] 100 Semiconductor device 100’ Semiconductor device 101 First stack 102 Second stack 103 Third stack 104 Fourth stack 107 Recess 108 First region 109 Second region 111, 111a, 111b First etch stop layer 112 Second etch stop layer 113 Conductive layer 114 Hard mask layer 115 Photoresist layer 116, 116a, 116b Replacement layer 117, 117a, 117b First insulating layer 118 Photoresist layer 120 Through-silicon contact (TSC) structure 121 Conductive portion 123 Sidewall portion 125 Shielding structure 126 Through-silicon hole (TSH) 126’ Sidewall 126’’ Bottom 127 Opening 131 First conductive structure 133 Second conductive structure 141 Word line layer 143 Second insulating layer 145 Gate contact structure 150 Channel structure 151 Space 153 Channel layer 155 Third insulating layer 171, 171a, 171n, 172, 172a, 172n Metal layer 180 Bonding interface 181, 181a, 181n Bonding structure 188 Substrate 191, 191a, 191n Metal layer 400 Memory system device 401 Interface 402 Master controller 411, 412, 413, 414 Semiconductor memory devices 420 Bus 421, 422, 423, 424 Control lines D1 First die D2 Second die

Claims

1. A semiconductor device comprising a first die, wherein the first die has: A stack of a first layer in a first region on the back side of the first die and a stack of a second layer in a second region on the back side of the first die, the stack of the first layer having fewer different layers than the stack of the second layer, the stack of the first layer and the stack of the second layer; A contact structure formed in the first region on the back side of the first die, the contact structure being configured to extend through the stack of the first layer and conductively connect a first conductive structure on the front side of the first die to a second conductive structure on the back side of the first die, the front side being the opposite side of the back side, the contact structure; A semiconductor device comprising the above.

2. The stack of the first layer sequentially includes a first layer, a replacement layer, and a first insulating layer. The stack of the second layer sequentially includes the first layer, a second layer, a conductive layer, the replacement layer, and the first insulating layer. The semiconductor device according to Claim 1.

3. The first layer and the replacement layer have equivalent etching characteristics. The second layer and the first layer have different etching characteristics. The conductive layer and the second layer have different etching characteristics. The semiconductor device according to Claim 2.

4. The first layer and the replacement layer contain the same conductive material. The semiconductor device according to Claim 2.

5. The first layer contains doped silicon. The replacement layer contains doped silicon. The semiconductor device according to Claim 2.

6. The contact structure includes a conductive portion and a sidewall portion. The conductive portion is configured to be conductively connected to the first conductive structure. The sidewall portion is configured to insulate the conductive portion from the stack of the first layer. The semiconductor device according to Claim 1.

7. The conductive portion contains at least one of tungsten or aluminum. The semiconductor device according to Claim 6.

8. The sidewall portion contains at least one of silicon oxide, silicon nitride, zirconium oxide, hafnium oxide, aluminum oxide, or tantalum oxide. The semiconductor device according to Claim 6.

9. The memory cell on the front side of the first die; A second die that is joined face-to-face with the first die, the second die including a substrate and a peripheral circuit network formed on a front side of the substrate for the memory cell The semiconductor device according to claim 1, further comprising.

10. wherein the memory cell a third stack of alternating gate layers and a second insulating layer on the front side of the first die; a plurality of channel structures extending through the third stack The semiconductor device according to claim 9, comprising.

11. A second die that is joined face-to-face with the first die, the second die including a memory cell formed on a front side of the second die, a peripheral circuit network formed on the front side of the first die for the memory cell The semiconductor device according to claim 1, further comprising.

12. A method of fabricating a semiconductor device, comprising: In a first region and from a back side of the first die, replacing a plurality of layers in a stack of layers formed on the back side of the first die with a replacement layer; Forming a buffer layer on the back side over the replacement layer; In the first region, forming a contact hole by etching the buffer layer and the replacement layer, the contact hole exposing a first conductive structure formed on a front side of the first die, the front side being opposite the back side; A method comprising.

13. The step of replacing the plurality of layers in the stack of layers formed on the back side of the first die with the replacement layer comprises: In the first region, forming a recess in the stack of layers such that a first etch stop layer is at a bottom of the recess; Depositing the replacement layer that fills the recess in the stack of layers and covers the stack of layers from the back side of the first die The method according to claim 12, further comprising.

14. Replacing the plurality of layers in the stack of layers with a replacement layer having etching characteristics equivalent to those of the first etch stop layer in the stack of layers The method according to claim 13, further comprising.

15. The replacement layer and the first etch stop layer are of the same material, The method according to claim 14.

16. Forming an insulating portion of a contact structure on sidewalls of the contact hole Forming a conductive portion of the contact structure that fills the contact hole and connects to the first conductive structure The method according to claim 12, further comprising.

17. The step of forming the insulating portion of the contact structure on the sidewall of the contact hole, Depositing an insulating material on the sidewall and bottom of the contact hole, Removing the insulating material from the bottom of the contact hole The method according to claim 16, further comprising.

18. Forming a second conductive structure on the back side of the contact structure, wherein the second conductive structure is electrically coupled to the first conductive structure via the contact structure, the step The method according to claim 16, further comprising.

19. Forming a memory cell on the front side of the first die, Forming a peripheral circuit network for the memory cell on the front side of the second die, Face-to-face, joining the first die and the second die The method according to claim 12, further comprising.

20. A die including a contact structure provided on the back side of the die, A first conductive structure provided on the front side of the die and connected to the contact structure from the front side of the die, wherein the front side is opposite to the back side, and A second conductive structure provided on the back side of the die and connected to the contact structure from the back side of the die, wherein the contact structure is configured to conductively connect the first conductive structure to the second conductive structure, the second conductive structure A semiconductor device comprising; A controller configured to control the operation of the semiconductor device and connected to the semiconductor device A memory system comprising.

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