Semiconductor integrated circuit

Abstract

To provide a semiconductor integrated circuit having a level shift circuit with erroneous operation prevented.SOLUTION: In a level shift circuit 200, a first end of a first resistor R1 is connected to a first line L1 which generates a first voltage VDD1. A first transistor M1 has a gate connected to a second end of the first resistor R1 and a source connected to the first line L1. A second resistor R2 is connected between a drain of the first transistor M1 and a second line L2 which generates a second voltage VSS1. A second transistor M2 has a source connected to the second end of the first resistor R1 and a gate connected to the second line L2. A third transistor M3 has a drain connected to a drain of the second transistor M2. A capacitor C1 is connected to the first resistor R1 in parallel.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor integrated circuit including a level shift circuit. [Background technology]

[0002] A semiconductor integrated circuit includes multiple circuit blocks that operate on different power supply voltages. A level shift circuit (level shift-up circuit) is used to transmit binary signals from a circuit block that operates on a lower power supply voltage to a circuit block that operates on a higher power supply voltage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-169029

[0004] DC / DC converter controller ICs (Integrated Circuits), power management integrated circuits (PMICs), motor drivers, and other ICs generate switching noise. If this switching noise gets mixed into a level shift circuit, it can cause the circuit to malfunction, adversely affecting the entire circuit system.

[0005] [overview] The present disclosure has been made in light of the above-mentioned circumstances, and an exemplary purpose of an embodiment thereof is to provide a semiconductor integrated circuit including a level shift circuit that prevents malfunctions.

[0006] A semiconductor integrated circuit according to an aspect of the present disclosure includes a first circuit block that operates with a first voltage as an upper power supply voltage and a second voltage as a lower power supply voltage, a second circuit block that operates with a third voltage lower than the first voltage as an upper power supply voltage and a ground voltage as a lower power supply voltage, and a level shift circuit that level-shifts up an output signal of the second circuit block and supplies it to the first circuit block. The level shift circuit includes a first resistor having a first end connected to a first line where the first voltage is generated, a first P-channel transistor having a gate connected to a second end of the first resistor and a source connected to the first line, a second resistor connected between a drain of the first transistor and a second line where the second voltage is generated, a second P-channel transistor having a source connected to the second end of the first resistor and a gate connected to the second line, a third N-channel transistor having a drain connected to a drain of the second transistor, a driver that controls the third transistor according to an output signal of the second circuit block, and a capacitor connected between a gate and a source of the first transistor.

[0007] In addition, combinations of the above components arbitrarily, and components and expressions mutually replaced between methods, apparatuses, systems, etc. are also effective as aspects of the present invention or the present disclosure. Furthermore, the description of this item (means for solving the problem) does not explain all the essential features of the present invention, and therefore, sub-combinations of these described features can also be the present invention.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

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Figure 5

Figure 6

[0009] [Detailed Description] (Overview of Embodiment) An overview of some exemplary embodiments of the present disclosure will be described. This overview is provided as a prelude to the detailed description below and is for the purpose of providing a basic understanding of the embodiments by simplifying and explaining some concepts of one or more embodiments. It does not limit the scope of the invention or the disclosure. This overview is not an exhaustive overview of all possible embodiments, nor is it intended to identify all important elements of all embodiments or to delineate the scope of some or all aspects. For convenience, "one embodiment" may be used to refer to one embodiment (example or modification) or a plurality of embodiments (examples or modifications) disclosed in this specification.

[0010] A semiconductor integrated circuit according to one embodiment includes a first circuit block that operates with a first voltage as an upper power supply voltage and a second voltage as a lower power supply voltage, a second circuit block that operates with a third voltage lower than the first voltage as an upper power supply voltage and a ground voltage as a lower power supply voltage, and a level shift circuit that level-shifts up an output signal of the second circuit block and supplies it to the first circuit block. The level shift circuit includes a first resistor having a first end connected to a first line where the first voltage is generated, a first P-channel transistor having a gate connected to a second end of the first resistor and a source connected to the first line, a second resistor connected between a drain of the first transistor and a second line where the second voltage is generated, a second P-channel transistor having a source connected to the second end of the first resistor and a gate connected to the second line, a third N-channel transistor having a drain connected to the drain of the second transistor, a driver that controls the third transistor in response to an output signal of the second circuit block, and a capacitor connected between the gate and the source of the first transistor.

[0011] When noise is mixed into the first line, the source voltage of the first transistor, that is, the voltage between the gate and the source, fluctuates. In the above configuration, the capacitor connected between the gate and the source of the first transistor can suppress the fluctuation of the voltage between the gate and the source, and prevent the malfunction of the level shift circuit.

[0012] In one embodiment, the level shift circuit may further include a third resistor connected between the second end of the first resistor and the source of the second transistor. By adding the third resistor, a high-pass filter is formed. This high-pass filter can disconnect the parasitic capacitance of the source of the second transistor, and further realize a more stable operation.

[0013] In one embodiment, the second transistor may be a DMOS (Double Diffusion Meta-Oxide-Semiconductor) transistor.

[0014] In one embodiment, the gate of the third transistor may be connected to a third line to which a third voltage is supplied, and the output node of the driver may be connected to the source of the third transistor.

[0015] In one embodiment, the source of the third transistor may be connected to the ground line, and the output node of the driver may be connected to the gate of the third transistor.

[0016] In one embodiment, the level shift circuit may further include an inverter that receives the drain voltage of the first transistor.

[0017] (Embodiment) Hereinafter, preferred embodiments will be described with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing are denoted by the same reference numerals, and repeated explanations will be omitted as appropriate. Further, the embodiments are illustrative and not restrictive of the disclosure and the invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and the invention.

[0018] In this specification, the phrase "member A is in a state of being connected to member B" includes not only the case where member A and member B are physically directly connected, but also the case where member A and member B are indirectly connected via other members without substantially affecting their electrical connection states or impairing the functions and effects achieved by their connection.

[0019] Similarly, the phrase "member C is in a state of being connected (provided) between member A and member B" includes not only the case where member A and member C, or member B and member C are directly connected, but also the case where they are indirectly connected via other members without substantially affecting their electrical connection states or impairing the functions and effects achieved by their connection.

[0020] (Embodiment) FIG. 1 is a block diagram of a semiconductor integrated circuit 100 according to an embodiment. The semiconductor integrated circuit 100 includes a first circuit block 110, a second circuit block 120, and a level shift circuit 200.

[0021] A power supply voltage V SYS is supplied to the power supply pin VIN of the semiconductor integrated circuit 100. The power supply voltage V SYS can be a voltage such as 40V, 24V, 12V, or higher than 100V. The power supply voltage V SYS is supplied to the first circuit block 110 as a first voltage V DD1 via the first line L1.

[0022] The first circuit block 110 operates with the first voltage V DD1 as the upper power supply voltage and the second voltage V SS1 as the lower power supply voltage. The second voltage V SS1 is a voltage lower than the first voltage V DD1 by a predetermined voltage range (e.g., 5V). The second voltage V SS1 is stabilized by a voltage source (not shown) and supplied to the first circuit block 110 via the second line L2.

[0023] The second circuit block 120 operates with a third voltage V DD1 lower than the first voltage V DD2 as the upper power supply voltage and the ground voltage V SS2 (= 0V) as the lower power supply voltage. The third voltage V DD2 is, for example, 5V, 3.5V, or 1.5V and is supplied to the second circuit block 120 via the third line L3.

[0024] The level shift circuit 200 level-shifts up the output signal (first signal) S1 of the second circuit block 120 and supplies the level-shifted second signal S2 to the first circuit block 110. The first signal S1 and the second signal S2 are digital signals taking binary values of high and low.

[0025] FIG. 2 is a circuit diagram of the level shift circuit 200. The level shift circuit 200 includes a first transistor M1, a second transistor M2, a third transistor M3, a first resistor R1, a second resistor R2, a capacitor C1, a driver 210, and an inverter 220.

[0026] The first end of the first resistor R1 is connected to the first line L1 where the first voltage V DD1 is generated. The first transistor M1 is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the gate of which is connected to the second end of the first resistor R1, and the source of which is connected to the first line L1.

[0027] The second resistor R2 is connected between the drain of the first transistor M1 and the second line L2 where the second voltage V SS1 is generated.

[0028] The second transistor M2 is a P-channel MOSFET, the source of which is connected to the second end of the first resistor R1, and the gate of which is connected to the second line L2.

[0029] The third transistor M3 is an N-channel MOSFET, the drain of which is connected to the drain of the second transistor M2.

[0030] Power supply voltage V SYS In an application where the power supply voltage V exceeds several tens of volts, it is preferable that the second transistor M2 is a high breakdown voltage DMOS (Double Diffusion Meta-Oxide-Semiconductor) transistor. In addition to the second transistor M2, the third transistor M3 may also be a DMOS transistor.

[0031] The driver 210 controls the on and off of the third transistor M3 according to the first signal S1 which is the output of the second circuit block 120. Specifically, when the first signal S1 is at the first level, the driver 210 turns on the third transistor M3 and conducts between the source of the second transistor M2 and the ground line L4. When the first signal S1 is at the second level, the driver 210 turns off the third transistor M3 and sets the source of the second transistor M2 to high impedance.

[0032] In the present embodiment, the gate of the third transistor M3 is connected to the third line L3, and the source of the third transistor M3 is connected to the output node of the driver 210. In this configuration, when the first signal S1 is low, the third transistor M3 turns on, and when the first signal S1 is high, the third transistor M3 turns off.

[0033] The inverter 220 inverts the voltage Vd1 at the drain of the first transistor M1 and outputs the second signal S2.

[0034] The capacitor C1 is connected in parallel with the first resistor R1 between the gate and source of the first transistor M1.

[0035] The above is the configuration of the level shift circuit 200. The advantages of the level shift circuit 200 will become clear by comparison with the comparative technology. Therefore, the configuration and operation of the comparative technology will be described.

[0036] Figure 3 is a waveform diagram for explaining the operation of a level shift circuit according to a comparative technique. The level shift circuit according to the comparative technique is obtained by omitting the capacitor C1 from the level shift circuit 200 in FIG. 2. Before time t0, the first signal S1 is low. At this time, the third transistor M3 is turned on, and a current flows through the current path including the first resistor R1 and the second transistor M2, a voltage drop occurs across the first resistor R1, and the gate voltage Vg1 of the first transistor M1 becomes a certain voltage level V SS1 +Vgs2. The second transistor M2 functions as a clamp circuit. Vgs2 is the gate-source voltage of the second transistor M2. At this time, the gate-source voltage Vgs1 of the first transistor M1 is higher than the threshold voltage Vgs (th) , and the first transistor M1 is on. Therefore, the voltage Vd1 is high (V DD1 ), and the second signal S2 is low (V SS1 ).

[0037] At time t0, the first signal S1 goes high and the third transistor M3 turns off. Then, no current flows through the current path including the first resistor R1 and the second transistor M2, the voltage drop across the first resistor R1 becomes zero, and the gate voltage Vg1 of the first transistor M1 rises to near the first voltage V DD1 . At this time, the gate-source voltage Vgs1 of the first transistor M1 is lower than the threshold voltage Vgs (th) , and the first transistor M1 is off. Therefore, the voltage Vd1 is low (V SS1 ), and the second signal S2 is high (V DD1 ).

[0038] Assume that at time t1, noise is mixed into the power supply pin VIN and the first voltage V DD1 (i.e., the source voltage of the first transistor M1) jumps to the high potential side. At this time, the gate voltage Vg1 of the first transistor M1 hardly changes. Therefore, the gate-source voltage Vgs1 of the first transistor M1 increases, and the first transistor M1 that should be off turns on, causing the level shift circuit to malfunction.

[0039] After the first signal S1 returns low at time t2, at time t3, noise is mixed into the power supply pin VIN, and the first voltage V DD1 (that is, the source voltage of the first transistor M1) is assumed to change to the low potential side. At this time, the gate voltage Vg1 of the first transistor M1 hardly changes. Therefore, the gate-source voltage Vgs1 of the first transistor M1 becomes small, and the first transistor M1 that should be on turns off, causing the level shift circuit to malfunction.

[0040] The above are the problems that occur in the level shift circuit according to the comparative technique. Next, the operation of the level shift circuit 200 according to the embodiment will be described.

[0041] FIG. 4 is a waveform diagram for explaining the operation of the level shift circuit 200 according to the embodiment. At time t1, noise is mixed into the power supply pin VIN, and the first voltage V DD1 (that is, the source voltage of the first transistor M1) is assumed to jump to the high potential side. In the embodiment, the noise propagates to the gate of the first transistor M1 through the capacitor C1 connected between the gate and the source of the first transistor M1. As a result, the gate voltage Vg1 of the first transistor M1 follows the first voltage V DD1 , and the gate-source voltage Vgs1 of the first transistor M1 maintains around 0 V, which is lower than the threshold voltage Vgs (th) . Thereby, the turn-on of the first transistor M1 can be prevented.

[0042] After the first signal S1 returns low at time t2, at time t3, noise is mixed into the power supply pin VIN, and the first voltage V DD1 (that is, the source voltage of the first transistor M1) is assumed to change to the low potential side. In the embodiment, the noise propagates to the gate of the first transistor M1 through the capacitor C1 connected between the gate and the source of the first transistor M1. As a result, the gate voltage Vg1 of the first transistor M1 follows the first voltage V DD1 , and the gate-source voltage Vgs1 of the first transistor M1 follows the threshold voltage Vgs (th)Maintain a higher voltage. This can prevent the turn-off of the first transistor M1.

[0043] Next, a modified example of the level shift circuit 200 will be described.

[0044] (Modified Example 1) FIG. 5 is a circuit diagram of a level shift circuit 200A according to Modified Example 1. The level shift circuit 200A further includes a third resistor R3 in addition to the level shift circuit 200 of FIG. 2. The third resistor R3 is connected between the second end of the first resistor R1 and the source of the second transistor M2.

[0045] A parasitic capacitance Cp exists at the drain of the second transistor M2. In the level shift circuit 200 of FIG. 2 where the third resistor R3 does not exist, the parasitic capacitance Cp will be directly connected to the gate of the first transistor M1.

[0046] The parasitic capacitance Cp reduces the followability of the gate voltage of the first transistor M1 to noise when noise is mixed in. When this parasitic capacitance Cp is small, its influence can be ignored, but in a design where the second transistor M2 is composed of a DMOS transistor, the influence of the parasitic capacitance Cp cannot be ignored.

[0047] According to Modified Example 1 of FIG. 5, by adding the third resistor R3, the gate of the first transistor M1 can be separated from the parasitic capacitance Cp. Therefore, when noise is mixed into the first voltage V DD1 the followability of the gate voltage Vg of the first transistor M1 to the first voltage V DD1 can be enhanced, and malfunction can be more reliably prevented.

[0048] (Modified Example 2) FIG. 6 is a circuit diagram of a level shift circuit 200B according to Modified Example 2. In the level shift circuit 200B, the source of the third transistor M3 is grounded, and the gate of the third transistor M3 is connected to the output node of an inverter which is the driver 210.

[0049] When the first signal S1 is high, the gate voltage of the third transistor M3 becomes 0V, and the third transistor M3 turns off. When the second signal S2 is low, the gate voltage of the third transistor M3 becomes V DD2 and the third transistor M3 turns on.

[0050] According to Modification 2, the same operation as the level shift circuit 200 in FIGS. 2 and 5 can be realized.

[0051] (Modification 3) When the input impedance of the first circuit block 110 connected to the subsequent stage of the level shift circuit 200 is sufficiently high, the inverter 220 can be omitted. Alternatively, the inverter 220 may be replaced with a buffer. In these cases, the circuit forms of the driver 210 and the third transistor M3 may be changed so that the third transistor M3 turns on when the first signal S1 is high and the third transistor M3 turns off when the first signal S1 is low.

[0052] (Supplementary Note) The following techniques are disclosed in this specification.

[0053] (Item 1) A first circuit block operating with a first voltage as the upper power supply voltage and a second voltage as the lower power supply voltage, A second circuit block operating with a third voltage lower than the first voltage as the upper power supply voltage and the ground voltage as the lower power supply voltage, A level shift circuit that level shifts up the output signal of the second circuit block and supplies it to the first circuit block, comprising the level shift circuit a first resistor having a first end connected to a first line where the first voltage is generated, a P-channel first transistor having a gate connected to a second end of the first resistor and a source connected to the first line, a second resistor connected between the drain of the first transistor and a second line where the second voltage is generated, A P-channel second transistor having a source connected to the second end of the first resistor and a gate connected to the second line, and an N-channel third transistor having a drain connected to the drain of the second transistor, and a driver that controls the third transistor in response to the output signal of the second circuit block, and a capacitor connected between the gate and source of the first transistor, and A semiconductor integrated circuit comprising.

[0054] (Item 2) The semiconductor integrated circuit according to item 1, wherein the level shift circuit further includes a third resistor connected between the second end of the first resistor and the source of the second transistor.

[0055] (Item 3) The semiconductor integrated circuit according to item 1 or 2, wherein the second transistor is a DMOS (Double Diffusion Meta-Oxide-Semiconductor) transistor.

[0056] (Item 4) The gate of the third transistor is connected to a third line to which the third voltage is supplied, The output node of the driver is connected to the source of the third transistor. The semiconductor integrated circuit according to any one of items 1 to 3.

[0057] (Item 5) The source of the third transistor is connected to a ground line, The output node of the driver is connected to the gate of the third transistor. The semiconductor integrated circuit according to any one of items 1 to 3.

[0058] (Item 6) The semiconductor integrated circuit according to any one of items 1 to 5, wherein the level shift circuit further includes an inverter that receives the drain voltage of the first transistor.

[0059] Although embodiments according to the present disclosure have been described using specific terms, this description is merely illustrative for facilitating understanding and does not limit the present disclosure or the scope of the claims. The scope of the present invention is defined by the scope of the claims. Also, not only embodiments but also embodiments, examples, and modifications not described herein are included in the scope of the present invention.

Explanation of Reference Numerals

[0060] 100 Semiconductor integrated circuit 110 First circuit block 120 Second circuit block 200 Level shift circuit L1 First line L2 Second line L3 Third line L4 Ground line M1 First transistor M2 Second transistor M3 Third transistor R1 First resistor R2 Second resistor R3 Third resistor C1 Capacitor 210 Driver 220 Inverter

Claims

1. A first circuit block that operates with the first voltage as the upper power supply voltage and the second voltage as the lower power supply voltage; A second circuit block that operates with a third voltage lower than the first voltage as the upper power supply voltage and the ground voltage as the lower power supply voltage; A level shift circuit that level shifts up the output signal of the second circuit block and supplies it to the first circuit block; Comprising: The level shift circuit is: A first resistor having a first terminal connected to a first line where the first voltage is generated; A P-channel first transistor having a gate connected to a second terminal of the first resistor and a source connected to the first line; A second resistor connected between the drain of the first transistor and a second line where the second voltage is generated; A P-channel second transistor having a source connected to the second terminal of the first resistor and a gate connected to the second line; An N-channel third transistor having a drain connected to the drain of the second transistor; A driver that controls the third transistor according to the output signal of the second circuit block; A capacitor connected between the gate and source of the first transistor; A semiconductor integrated circuit comprising:

2. The semiconductor integrated circuit according to claim 1, wherein the level shift circuit further comprises a third resistor connected between the second terminal of the first resistor and the source of the second transistor.

3. The semiconductor integrated circuit according to claim 1 or 2, wherein the second transistor is a DMOS (Double Diffusion Meta-Oxide-Semiconductor) transistor.

4. The gate of the third transistor is connected to a third line to which the third voltage is supplied, The semiconductor integrated circuit according to claim 1 or 2, wherein the output node of the driver is connected to the source of the third transistor.

5. The source of the third transistor is connected to a ground line, The semiconductor integrated circuit according to claim 1 or 2, wherein the output node of the driver is connected to the gate of the third transistor.

6. The semiconductor integrated circuit according to claim 1 or 2, wherein the level shift circuit further comprises an inverter that receives the drain voltage of the first transistor.

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