Semiconductor device

Abstract

To further expand a die pad area per device area, thereby providing a semiconductor device which allows improvement in heat dissipation.SOLUTION: A semiconductor device 101 comprises: at least three first die pads 11; at least three first semiconductor elements 21 each of which is mounted on each of the first die pads 11; a first wire 31 which electrically connects the first semiconductor elements 21 to one another; at least three second die pads 12 which are arranged alternately with the first die pads 11; at least three second semiconductor elements 22 each of which is mounted on each of the second die pads 12; and a second wire 32 which electrically connects the second semiconductor elements 22 to one another.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Conventionally, as a semiconductor device in which multiple semiconductor elements and a control integrated circuit are mounted in a single package, a device in which multiple semiconductor elements are mounted on a single die pad is known. For example, in Patent Document 1, multiple pairs of semiconductor elements, each consisting of an IGBT chip and a free-haul diode, are mounted on a single die pad portion of a lead frame. In detail, three pairs of IGBT chips and free-haul diodes on the high-potential side are mounted on one die pad portion, and three pairs of IGBT chips and free-haul diodes on the low-potential side are mounted on three die pad portions, respectively. The IGBT chips and free-haul diodes are electrically connected to a predetermined lead frame by bonding wires. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-111154 Summary of the Invention [Problem to be solved by the invention]

[0004] In the device of Patent Document 1, three sets of high-potential side IGBT chips and free-hole diodes are mounted on one die pad, so the high-potential side semiconductor element and the low-potential side semiconductor element, which need to be electrically connected to each other, are arranged at positions apart. Therefore, the lead terminals connected to the die pad on which the low-potential side semiconductor element is mounted are bent and arranged so as to approach the high-potential side semiconductor element, and the bent parts of the lead terminals are used to electrically connect the high-potential side semiconductor element and the low-potential side semiconductor element by wire bonding.

[0005] Therefore, in the device of Patent Document 1, space is required to place the bent lead terminals, and therefore the area of the die pad portion relative to the area of the entire device cannot be increased by the amount of space required to place the bent lead terminals, resulting in the problem that it is not possible to improve the heat dissipation of the semiconductor element by increasing the area of the die pad portion.

[0006] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a semiconductor device that enables the die pad area relative to the device area to be expanded more than conventionally, thereby improving heat dissipation. [Means for solving the problem]

[0007] The semiconductor device according to the present disclosure comprises at least three first die pads, at least three first semiconductor elements mounted on the first die pads, first wires electrically connecting the first semiconductor elements, at least three second die pads arranged alternately with the first die pads, at least three second semiconductor elements mounted on the second die pads, and second wires electrically connecting the second semiconductor elements. [Effects of the Invention]

[0008] According to the semiconductor device according to the present disclosure, the area of the die pad relative to the device area can be increased, thereby improving heat dissipation. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] 1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present disclosure. [Figure 3] FIG. 10 is a plan view showing a semiconductor device according to a second embodiment of the present disclosure. [Figure 4] FIG. 10 is a cross-sectional view showing a semiconductor device according to a second embodiment of the present disclosure. [Figure 5]FIG. 10 is a cross-sectional view showing a semiconductor device according to a second embodiment of the present disclosure. [Figure 6] FIG. 10 is a plan view showing a semiconductor device according to a third embodiment of the present disclosure. [Figure 7] FIG. 10 is a plan view showing a semiconductor device according to a fourth embodiment of the present disclosure. [Figure 8] FIG. 11 is a plan view showing a semiconductor device according to a fifth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] An example of a semiconductor device according to the present disclosure will be described below with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference numerals, and descriptions thereof will not be repeated.

[0011] In this specification, a semiconductor device equipped with a three-phase inverter circuit will be described as an example of a semiconductor device in which multiple semiconductor elements and a control integrated circuit are mounted in a single package. Here, the three-phase inverter circuit is a circuit that converts DC power into three-phase (U-phase, V-phase, and W-phase) AC power.

[0012] Embodiment 1 A first embodiment of the present disclosure relates to a semiconductor device 101 having at least three first die pads, at least three first semiconductor elements mounted on the first die pads, first wires electrically connecting the first semiconductor elements, at least three second die pads arranged alternately with the first die pads, at least three second semiconductor elements mounted on the second die pads, and second wires electrically connecting the second semiconductor elements.

[0013] <Configuration of First Embodiment> The configuration of a semiconductor device 101 according to a first embodiment of the present disclosure will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view showing the semiconductor device 101, and FIG. 2 is a cross-sectional view taken along line AA in FIG. 1. Note that FIGS. 1 and 2 omit the sealing resin 70 in order to show the internal structure of the sealing resin 70. In FIGS. 1 and 2, the outline of the sealing resin 70 when it is present is indicated by a dotted line.

[0014] 1 and 2, the semiconductor device 101 includes die pads (11, 12, 51), semiconductor elements (21, 22), a control integrated circuit 52, wires (31, 32, 33, 34, 53), terminals (41, 42, 43, 54), and an insulating sheet 60 inside a sealing resin 70 that has a rectangular shape in a plan view. Note that portions of the terminals (41, 42, 43, 54) and at least a portion of the lower surface of the insulating sheet 60 are sealed so as to be exposed to the outside of the sealing resin 70. Each component will be described in detail below.

[0015] The semiconductor device 101 includes three first die pads 11 and three second die pads 12. The three first die pads 11 and three second die pads 12 have a rectangular shape in a plan view and are arranged alternately. In detail, the three first die pads 11 and three second die pads 12 are arranged alternately along a direction in which a first side 71 in a plan view of a sealing resin 70 having a rectangular shape in a plan view extends. In other words, in a plan view, the first side 71 of the sealing resin 70 is a side that extends in the direction in which the first die pads 11 and second die pads 12 are arranged alternately.

[0016] 1 shows an example in which the first side 71, which is the side of the sealing resin 70 in a plan view and extends in a direction in which the first die pads 11 and the second die pads 12 are alternately arranged, is the long side of the sealing resin 70 in a plan view, but the first die pads 11 and the second die pads 12 may be arranged alternately along the direction of one of the four sides of the sealing resin 70 in a plan view. That is, in FIG. 1, three first die pads 11 and three second die pads 12 may be arranged along, for example, one short side of the sealing resin 70 (the second side 72 or the third side 73 in FIG. 1).

[0017] The first die pad 11 and the second die pad 12 are plate-like members having an upper surface and a lower surface, and are made of a material having electrical conductivity and good thermal conductivity, such as copper.

[0018] Three first semiconductor elements 21 are mounted on the upper surfaces of the three first die pads 11, respectively. Furthermore, three second semiconductor elements 22 are mounted on the upper surfaces of the three second die pads 12, respectively.

[0019] The first semiconductor element 21 and the second semiconductor element 22 are components for configuring a three-phase inverter circuit that converts DC power into three-phase (U-phase, V-phase, and W-phase) AC power, and are elements that perform switching operations. The first semiconductor element 21 is electrically connected between a first main terminal 41 (described later) and an output terminal 43 (described later) to configure the three-phase inverter circuit. The second semiconductor element 22 is connected between the output terminal 43 (described later) and a second main terminal 42 (described later) to configure the three-phase inverter circuit. The first semiconductor element 21 is connected to an external substrate (not shown) on the high-potential side of the DC power in the three-phase inverter circuit. The second semiconductor element 22 is connected to an external substrate (not shown) on the low-potential side of the DC power in the three-phase inverter circuit. In other words, a relatively higher potential is supplied to the first semiconductor element 21 compared to the second semiconductor element 22. A relatively lower potential is supplied to the second semiconductor element 22 compared to the first semiconductor element 21.

[0020] The first semiconductor element 21 and the second semiconductor element 22 are, for example, RC (Reverse Conducting)-IGBTs (Insulated Gate Bipolar Transistors). The RC-IGBT is an element in which an IGBT and a freewheeling diode are configured on a single chip, and performs both switching and freewheeling operations. Note that the first semiconductor element 21 and the second semiconductor element 22 may be a combination of two or more elements as long as they are capable of switching operations. That is, the first semiconductor element 21 or the second semiconductor element 22 may be a combination of a switching element and a diode connected in anti-parallel. For example, the first semiconductor element 21 or the second semiconductor element 22 may be a combination of an IGBT or a MOS (Metal Oxide Semiconductor) transistor and a freewheeling diode.

[0021] Three first semiconductor elements 21 and three second semiconductor elements 22 are provided corresponding to the three-phase AC power to be output. The configuration of a three-phase inverter circuit formed by the first semiconductor elements 21 and the second semiconductor elements 22 will be described later.

[0022] The semiconductor device 101 includes a first main terminal 41, a second main terminal 42, and three output terminals 43. The first main terminal 41 extends from one of the three first die pads 11, which is located at one end in the direction in which the first die pads 11 and the second die pads 12 are alternately arranged. The second main terminal 42 is located at the other end in the direction in which the first die pads 11 and the second die pads 12 are alternately arranged. Here, in FIG. 1 , the one end in the direction in which the first die pads 11 and the second die pads 12 are alternately arranged is the left end, and the other end in the direction in which the first die pads 11 and the second die pads 12 are alternately arranged is the right end. The three output terminals extend from at least three of the second die pads.

[0023] The first main terminal 41, the second main terminal 42, and the output terminal 43 protrude to the outside from a first side surface of the sealing resin 70, which includes a first edge 71, which is one of the edges of the sealing resin 70 in a planar view and extends in the direction in which the first die pads 11 and the second die pads 12 are alternately arranged.

[0024] 1 shows an example in which the first side 71 included in the first side surface of the sealing resin 70 is a long side of the sealing resin 70 in a plan view, but the first side surface may be a side surface that includes one of the four sides of the sealing resin 70 that has a rectangular shape in a plan view. That is, the first side surface may be a side surface that includes a short side of the sealing resin 70 in a plan view (the second side 72 or the third side 73 in FIG. 1). As shown in FIG. 1, when the first side 71 included in the first side surface of the sealing resin 70 is a long side of the sealing resin 70 in a plan view, the first main terminal 41, the second main terminal 42, and the output terminal 43 are disposed farther away from each other terminal than when the first side 71 is a short side, and therefore, the creepage distance between the terminals can be reliably secured.

[0025] 1 shows an example in which the portions of the first main terminal 41, the second main terminal 42, and the output terminal 43 protruding from the sealing resin 70 have a rectangular shape in a plan view, but this is not limiting. The portions of the first main terminal 41, the second main terminal 42, and the output terminal 43 protruding from the sealing resin 70 may be, for example, polygonal or rounded plate-like members.

[0026] The first main terminal 41 and the second main terminal 42 are electrically connected to an external substrate (not shown) and are provided for inputting DC power. The output terminal 43 is electrically connected to an external substrate (not shown) and is provided for outputting AC power. Like the first die pad 11 and the second die pad 12, the first main terminal 41, the second main terminal 42, and the output terminal 43 are made of a material that has electrical conductivity and good thermal conductivity, such as copper.

[0027] 1, the semiconductor device 101 may include inner leads 41a that extend from two of the three first die pads 11 and are entirely sealed within the sealing resin 70. In particular, the inner leads 41a extend from the two first die pads 11 that are arranged on the other end side in the direction in which the first die pads 11 and the second die pads 12 are alternately arranged. Although the inner leads 41a are members that extend from the first die pads 11, unlike the first main terminals 41, they do not protrude outside the sealing resin 70. The inner leads 41a are formed for electrical connection within the semiconductor device 101.

[0028] The semiconductor device 101 includes a plurality of wires for electrically connecting the three first semiconductor elements 21 and the three second semiconductor elements 22. In particular, the semiconductor device 101 includes a first wire 31, a second wire 32, a third wire 33, and a fourth wire 34.

[0029] The first wires 31 are wires that electrically connect the three first semiconductor elements 21 to one another, and are provided so as to connect two adjacent first die pads 11 that sandwich the second die pad 12. Specifically, the first wires 31 include a first wire 31a that connects two first die pads 11 at one end in the direction in which the first die pads 11 and the second die pads 12 are alternately arranged, and a first wire 31b that connects two first die pads 11 at the other end in the direction in which the first die pads 11 and the second die pads 12 are alternately arranged. Here, the two first die pads 11 at one end refer to the two first die pads 11 arranged at the left end in FIG. 1 , and the two first die pads 11 at the other end refer to the two first die pads 11 arranged at the right end in FIG. 1 . In other words, the first wires 31 are a general term for wires that connect the first die pads 11. The first wire 31 may be configured using a plurality of wires, or may be provided so as to be connected by a single wire.

[0030] The second wires 32 are wires that electrically connect the three second semiconductor elements 22 to one another, and are provided so as to connect two second semiconductor elements 22 mounted on two adjacent first die pads 11 that sandwich the first die pad 11. Specifically, the second wires 32 include a second wire 32a that connects two second semiconductor elements 22 on the other end side in the direction in which the first die pads 11 and the second die pads 12 are alternately arranged, and a second wire 32b that connects two second semiconductor elements 22 on one end side in the direction in which the first die pads 11 and the second die pads 12 are alternately arranged. Here, the two second semiconductor elements 22 on one end side refer to the two second semiconductor elements 22 arranged on the left end side in FIG. 1, and the two second semiconductor elements 22 on the other end side refer to the two second semiconductor elements 22 arranged on the right end side in FIG. 1. In other words, the second wires 32 are a general term for wires that are provided so as to connect the second semiconductor elements 22. The second wire 32 may be configured using a plurality of wires, or may be provided so as to be connected by a single wire.

[0031] The third wire 33 is a wire that electrically connects the second main terminal 42 and the second semiconductor element 22. The third wire 33 is provided so as to connect the second main terminal 42 and the second semiconductor element 22 that is arranged on the other end side in the direction in which the first die pads 11 and the second die pads 12 are alternately arranged.

[0032] The fourth wire 34 is a wire that electrically connects the first semiconductor element 21 and the second semiconductor element 22, and is provided so as to connect the first semiconductor element 21 and the second die pad 12 that are adjacent to each other.

[0033] The first wire 31, the second wire 32, the third wire 33, and the fourth wire 34 are, for example, bonding wires made of aluminum wires.

[0034] The semiconductor device 101 also includes three control integrated circuits 52 for controlling the first semiconductor element 21 and the second semiconductor element 22. In detail, the control integrated circuits 52 receive an external operation command and generate and output control signals for the first semiconductor element 21 and the second semiconductor element 22. The three control integrated circuits 52 are each mounted on the upper surface of one third die pad 51.

[0035] Although an example in which three control integrated circuits 52 are provided is shown in FIGS. 1 and 2, the number of control integrated circuits 52 is not limited to this, and for example, two control integrated circuits 52 may be provided.

[0036] The semiconductor device 101 also includes a plurality of control terminals 54 electrically connected to the control integrated circuit 52. The control terminals 54 protrude to the outside of the sealing resin 70 from a fourth side surface including a fourth side 74 that faces the first side 71 in a plan view of the sealing resin 70. The plurality of control terminals 54 are electrically connected to an external board (not shown) and are provided to receive operation commands to the semiconductor element 21 and the second semiconductor element 22.

[0037] Furthermore, the semiconductor device 101 includes a plurality of fifth wires 53 provided to connect between the first semiconductor element 21 and the control integrated circuit 52, between the second semiconductor element 22 and the control integrated circuit 52, and between the control terminal 54 and the control integrated circuit 52. The plurality of fifth wires 53 are provided, for example, to transmit control signals from the control integrated circuit 52 to the first semiconductor element 21 and the second semiconductor element 22 to command ON or OFF in a switching operation, or to allow the control integrated circuit 52 to receive operation commands to the first semiconductor element 21 and the second semiconductor element 22 from the outside. The fifth wires 53 are, for example, bonding wires made of gold wires.

[0038] 2, the semiconductor device 101 further includes an insulating sheet 60. The insulating sheet 60 is disposed so that the upper surface of the insulating sheet 60 faces the lower surfaces of the first die pad 11 and the second die pad 12, i.e., the surfaces of the first die pad 11 and the second die pad opposite the mounting surfaces of the first semiconductor element 21 and the second semiconductor element 22.

[0039] The insulating sheet 60 is made of a material having insulating properties and good thermal conductivity, such as an epoxy resin containing any of BN, SiO2, Si3N4, Al2O3, and AlN as a filler.

[0040] The semiconductor device 101 has each component sealed with a sealing resin 70 that is rectangular in plan view. Specifically, the sealing resin 70 seals the first die pad 11, the second die pad 12, the third die pad 51, the first semiconductor element 21, the second semiconductor element 22, the control integrated circuit 52, the first wire 31, the second wire 32, the third wire 33, the fourth wire 34, the fifth wire 53, a portion of the first main terminal 41, a portion of the second main terminal 42, a portion of the output terminal 43, a portion of the control terminal 54, and a portion of the insulating sheet 60. That is, a portion of the first main terminal 41, a portion of the second main terminal 42, a portion of the output terminal 43, a portion of the control terminal 54, and at least a portion of the lower surface of the insulating sheet 60 are exposed to the outside of the sealing resin 70.

[0041] With the above configuration, the heat generated by the first semiconductor element 21 and the second semiconductor element 22 is dissipated to the outside of the semiconductor device 101 via the first die pad 11 or the second die pad 12 with which they are in contact and the insulating sheet 60.

[0042] The semiconductor device 101 may also include a heat sink (not shown). The heat sink is disposed on the lower surface of the insulating sheet 60. By further including the heat sink, it is possible to improve the dissipation of heat generated by the first semiconductor element 21 and the second semiconductor element.

[0043] As described above, the semiconductor device 101 has a configuration in which three first semiconductor elements 21, three second semiconductor elements 22, and three control integrated circuits 52 for controlling the first semiconductor elements 21 and the second semiconductor elements 22 are mounted in one package. The semiconductor device 101 has a three-phase inverter circuit configured by the three first semiconductor elements 21 and the three second semiconductor elements 22, and a drive circuit configured by the three control integrated circuits 52. Here, the circuit configuration of the semiconductor device 101 will be described.

[0044] The three-phase inverter circuit included in the semiconductor device 101 is a circuit that converts DC power into three-phase AC power and outputs it through the switching operation of the first semiconductor element 21 and the second semiconductor element 22. The three-phase inverter circuit is configured such that the first semiconductor element 21 on the high potential side and the second semiconductor element 22 on the low potential side are electrically connected between a first main terminal 41 connected to a high potential side external substrate (not shown) and a second main terminal 42 connected to a low potential side external substrate (not shown), and a connection node connecting the AC power output sides of both semiconductor elements serves as an output terminal 43. That is, to configure the three-phase inverter circuit, the first semiconductor element 21 on the high potential side and the second semiconductor element 22 on the low potential side must be electrically connected. Furthermore, the three first semiconductor elements 21 must be electrically connected in parallel. Similarly, the three second semiconductor elements 22 must be electrically connected in parallel.

[0045] As described above, three first semiconductor elements 21 and three second semiconductor elements 22 are provided corresponding to the three phases. That is, one first semiconductor element 21 and one second semiconductor element 22 are provided for each phase, and three first semiconductor elements 21 and three second semiconductor elements 22 are provided for the three phases. Three output terminals 33 are provided corresponding to each of the three phases.

[0046] The drive circuit included in the semiconductor device 101 is a circuit that controls the switching operations of the first semiconductor element 21 and the second semiconductor element 22. The drive circuit is configured so that one control integrated circuit 52 controls the switching operations of a pair of the first semiconductor element 21 and the second semiconductor element 22 that constitute one of the three phases. That is, one control integrated circuit 52 is provided for each phase, and three control integrated circuits 52 are provided for the three phases.

[0047] In this way, the semiconductor device 101 controls the switching operations of the three first semiconductor elements 21 and the three second semiconductor elements 22 using a three-phase inverter circuit and a drive circuit, converts DC power into three-phase AC power, and outputs it.

[0048] Although the example in which the semiconductor device 101 includes three each of the first semiconductor elements 21 and the second semiconductor elements 22 has been described, the semiconductor device 101 may include three or more each of the first semiconductor elements 21 and the second semiconductor elements 22. The semiconductor device 101 may include at least three each of the first semiconductor elements 21 and the second semiconductor elements 22, and may configure a three-phase voltage-type three-level inverter circuit by including, for example, six each of the first semiconductor elements 21 and the second semiconductor elements 22. Depending on the number of the first semiconductor elements 21 and the second semiconductor elements 22, the semiconductor device 101 may also include three or more each of the first die pads 11 and the second die pads 12.

[0049] <Manufacturing Method of First Embodiment> Next, a method for manufacturing the semiconductor device 101 according to the first embodiment of the present disclosure will be described. In this embodiment, among the manufacturing steps of the semiconductor device 101, steps other than the step of forming the three first die pads 11 can be realized by appropriately applying known techniques, and therefore only the step of forming the three first die pads 11 will be described here.

[0050] The three first die pads 11 are formed by punching a copper plate having electrical conductivity and good thermal conductivity. The three first die pads 11 are formed, for example, by using a die to punch the copper plate into a predetermined shape.

[0051] <Effects of the First Embodiment> Next, the operation and effect of the semiconductor device 101 according to the first embodiment of the present disclosure will be described by comparing a conventional semiconductor device with the semiconductor device 101 according to the present disclosure.

[0052] In conventional semiconductor devices, such as the device disclosed in Patent Document 1, three sets of high-potential side IGBT chips and free-hole diodes are mounted on one die pad. Therefore, in the device disclosed in Patent Document 1, the high-potential side semiconductor element and the low-potential side semiconductor element, which need to be electrically connected to each other to form a three-phase inverter circuit, are arranged at separate locations, and in order to connect the high-potential side semiconductor element and the low-potential side semiconductor element, the terminals extending from the die pad on which the low-potential side semiconductor element is mounted are formed in a shape having one or more bent portions. Therefore, in the device of Patent Document 1, the area of the die pad relative to the area of the entire device could not be increased by the amount of space required to place the bent portion of the terminal, and it was not possible to improve the heat dissipation of the semiconductor element by increasing the area of the die pad.

[0053] The semiconductor device 101 in embodiment 1 of the present disclosure comprises at least three first die pads 11, at least three first semiconductor elements 21 mounted on the first die pads 11, first wires 31 electrically connecting the first semiconductor elements 21, at least three second die pads 12 arranged alternately with the first die pads 11, at least three second semiconductor elements 22 mounted on the second die pads 12, and second wires 32 electrically connecting the second semiconductor elements 22.

[0054] According to semiconductor device 101 of the first embodiment of the present disclosure, first die pad 11 carrying first semiconductor element 21 corresponding to the semiconductor element on the high potential side is separated into three parts, and second die pad 12 carrying second semiconductor element 22 corresponding to the semiconductor element on the low potential side is alternately arranged, thereby enabling first semiconductor element 21 and second semiconductor element 22, which need to be electrically connected to each other, to be arranged side by side. Arranging first semiconductor element 21 and second semiconductor element 22 side by side eliminates the need to bend output terminal 43, which corresponds to a terminal extending from the second die pad, so as to approach first semiconductor element 21. In other words, first semiconductor element 21 and second semiconductor element 22 can be electrically connected without bending output terminal 43. Therefore, according to semiconductor device 101 of the first embodiment of the present disclosure, output terminal 43 can be arranged without bending, and therefore the area of first die pad 11 and second die pad 12 relative to the area of semiconductor device 101 can be increased by the space occupied by the bent terminal in conventional devices.

[0055] Heat generated by first semiconductor element 21 and second semiconductor element 22 is dissipated to the outside of semiconductor device 101 via first die pad 11 and second die pad 12. Therefore, according to semiconductor device 101 of embodiment 1 of the present disclosure, the areas of first die pad 11 and second die pad 12 can be increased compared to conventional devices, thereby improving the heat dissipation performance of semiconductor device 101 compared to conventional devices. Furthermore, according to semiconductor device 101 of embodiment 1 of the present disclosure, the improved heat dissipation performance of semiconductor device 101 allows the current flowing through semiconductor device 101 to be increased compared to conventional devices.

[0056] Embodiment 2 In the first embodiment of the present disclosure, a semiconductor device 101 was described that includes a first main terminal 41, a second main terminal 42, and an output terminal 43 that are provided to protrude from a first side surface of the sealing resin 70, the first side 71 being a side that extends in the direction in which the first die pads 11 and the second die pads 12 are alternately arranged among the sides of the sealing resin 70 in a plan view. In the second embodiment of the present disclosure, a semiconductor device 102 will be described that includes an output terminal 43 that is provided to protrude from the first side surface of the sealing resin 70, a first main terminal 241 that is provided to protrude from a second side surface of the sealing resin 70 that includes a second side 72 that is a side on one end side of the sealing resin 70 in the direction in which the first die pads 11 and the second die pads 12 are alternately arranged among the sides of the sealing resin 70 in a plan view, and a second main terminal 242 that is provided to protrude from a third side surface of the sealing resin 70 that includes a third side 73 that is a side on the other end side of the sealing resin 70 in the direction in which the first die pads 11 and the second die pads 12 are alternately arranged among the sides of the sealing resin 70 in a plan view. In the second embodiment, the same components as those in the first embodiment of the present disclosure are designated by the same reference numerals, and descriptions of the same or corresponding parts will be omitted. Hereinafter, a semiconductor device 102 according to the second embodiment will be described with reference to the drawings.

[0057] <Configuration of Second Embodiment> The configuration of a semiconductor device 102 according to a second embodiment of the present disclosure will be described with reference to FIGS. 3, 4, and 5. FIG. 3 is a plan view showing the semiconductor device 102. FIG. 4 is a cross-sectional view taken along line AA in FIG. 3, and FIG. 5 is a cross-sectional view taken along line BB in FIG. 3. Note that in FIGS. 3, 4, and 5, the sealing resin 70 is omitted in order to show the internal structure of the sealing resin 70. In addition, in FIGS. 3, 4, and 5, the outline of the sealing resin 70 when it is present is shown by a dotted line.

[0058] As shown in Figures 3, 4 and 5, the semiconductor device 102 includes an output terminal 43 arranged to protrude from a first side surface of the sealing resin 70, including a first side 71 which is a side that extends in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged among the sides of the sealing resin 70 in a planar view, a first main terminal 241 arranged to protrude from a second side surface of the sealing resin 70 which is a second side 72 which is a side on one end side of the sealing resin 70 in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged among the sides of the sealing resin 70 in a planar view, and a second main terminal 242 arranged to protrude from a third side surface of the sealing resin 70 which is a third side 73 which is a side on the other end side of the sealing resin 70 in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged among the sides of the sealing resin 70 in a planar view.

[0059] As described above, by providing each terminal so that it protrudes from a different side surface of the sealing resin 70, the first main terminal 241, the second main terminal 242, and the output terminal 43 are each positioned apart from the other terminals.

[0060] Note that, in addition to providing each terminal so as to protrude from a different side surface of the sealing resin 70, the area of the portion of each terminal protruding from the sealing resin 70 may be increased. In particular, as shown in Figures 3, 4 and 5, each terminal may be provided so as to protrude from a different side surface of the sealing resin 70, and further, the width of the portion of each terminal protruding from the sealing resin 70 in a direction perpendicular to the protruding direction in a plan view may be increased. A configuration in which the width of the portion of each terminal protruding from the sealing resin 70 is increased will be described with reference to Figures 3, 4 and 5.

[0061] As shown in FIGS. 3 , 4 , and 5 , the first main terminal 241, the second main terminal 242, and the output terminal 43 are provided so as to protrude from different side surfaces of the sealing resin 70, and therefore the width of the portion of each terminal protruding from the sealing resin 70 can be increased in a direction perpendicular to the protruding direction in a plan view. Specifically, in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged, the width of the portion of the output terminal 43 protruding from the sealing resin 70 is longer than the width of the second die pad 12. Furthermore, in the direction perpendicular to the direction in which the first die pad 11 and the second die pad 12 are alternately arranged, the width of the portion of the first main terminal 241 protruding from the sealing resin 70 is longer than the width of the first die pad 11. In the direction perpendicular to the direction in which the first die pad 11 and the second die pad 12 are alternately arranged, the width of the portion of the second main terminal 242 protruding from the sealing resin 70 is longer than the width of the second die pad 12.

[0062] As described above, the area of each terminal is increased by increasing the width of the portion of each terminal that protrudes from the sealing resin 70 in a direction perpendicular to the direction in which the terminal protrudes from the side surface of the sealing resin 70 in a planar view.

[0063] 3 shows an example in which the portions of the first main terminal 241, the second main terminal 242, and the output terminal 43 protruding from the sealing resin 70 have a rectangular shape in a plan view, but this is not limiting. The portions of the first main terminal 241, the second main terminal 242, and the output terminal 43 protruding from the sealing resin 70 may be, for example, polygonal or rounded plate-like members.

[0064] <Manufacturing Method of Second Embodiment> The method for manufacturing the semiconductor device 102 according to the second embodiment of the present disclosure is the same as the method for manufacturing the semiconductor device 101 according to the first embodiment, and therefore a description thereof will be omitted.

[0065] <Effects of the Second Embodiment> Next, the operation and effects of the semiconductor device 102 according to the second embodiment of the present disclosure will be described.

[0066] The semiconductor device 102 in the second embodiment of the present disclosure includes an output terminal 43 that is arranged to protrude from a first side surface of the sealing resin 70, which has a rectangular shape when viewed from above, and includes a first side 71 that is a side that extends in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged, among the sides of the sealing resin 70 when viewed from above, and includes a second side 72 that is a side on one end side of the sealing resin 70 in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged, among the sides of the sealing resin 70 when viewed from above, and a second main terminal 242 that is arranged to protrude from a third side surface of the sealing resin 70 that is a third side 73 that is a side on the other end side of the sealing resin 70 in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged, among the sides of the sealing resin 70 when viewed from above, and includes

[0067] According to the semiconductor device 102 of the second embodiment of the present disclosure, the first main terminal 241, the second main terminal 242, and the output terminal 43 are arranged to protrude from different sides of the sealing resin 70, namely the first side, the second side, and the third side, respectively. Therefore, the first main terminal 241, the second main terminal 242, and the output terminal 43 are each positioned apart from the other terminals, and the creepage distance between the terminals can be reliably secured.

[0068] Furthermore, in semiconductor device 102 according to the second embodiment of the present disclosure, the width of the portion of output terminal 43 protruding from sealing resin 70 is longer than the width of second die pad 12 in the direction in which first die pad 11 and second die pad 12 are alternately arranged. In a direction perpendicular to the direction in which first die pad 11 and second die pad 12 are alternately arranged, the width of the portion of first main terminal 241 protruding from sealing resin 70 is longer than the width of first die pad 11. In a direction perpendicular to the direction in which first die pad 11 and second die pad 12 are alternately arranged, the width of the portion of second main terminal 242 protruding from sealing resin 70 is longer than the width of second die pad 12.

[0069] As described above, according to semiconductor device 102 of the second embodiment of the present disclosure, the areas of first main terminal 241, second main terminal 242, and output terminal 43 relative to the area of semiconductor device 102 can be increased compared to the first embodiment, while reliably ensuring the creepage distance between terminals. Heat generated by first semiconductor element 21 and second semiconductor element 22 is dissipated to the outside of semiconductor device 102 via first main terminal 241, second main terminal 242, and output terminal 43. Therefore, according to semiconductor device 102 of the second embodiment of the present disclosure, the areas of first main terminal 241, second main terminal 242, and output terminal 43 can be increased, thereby further improving the heat dissipation performance of semiconductor device 102. Furthermore, according to semiconductor device 102 of the second embodiment of the present disclosure, the improved heat dissipation performance of semiconductor device 102 can further increase the current flowing through semiconductor device 102.

[0070] Embodiment 3 In the second embodiment of the present disclosure, a semiconductor device 102 has been described that includes an output terminal 43 provided to protrude from a first side surface of the sealing resin 70, a first main terminal 241 provided to protrude from a second side surface of the sealing resin 70, and a second main terminal 242 provided to protrude from a third side surface of the sealing resin 70. In the third embodiment of the present disclosure, a semiconductor device 103 will be described that includes a first main terminal 341, a second main terminal 342, and an output terminal 343, at least a portion of which protrudes from the sealing resin 70 and is formed in a comb-tooth shape. In the third embodiment, the same components as those in the first and second embodiments of the present disclosure are designated by the same reference numerals, and descriptions of the same or corresponding parts will be omitted. Hereinafter, a semiconductor device 103 according to the third embodiment will be described with reference to the drawings.

[0071] <Configuration of Third Embodiment> The configuration of a semiconductor device 103 according to a third embodiment of the present disclosure will be described with reference to Fig. 6. Fig. 6 is a plan view showing the semiconductor device 103. Note that Fig. 6 does not show the sealing resin 70 in order to show the internal structure of the sealing resin 70. In Fig. 6, the outline of the sealing resin 70 when it is present is shown by a dotted line.

[0072] 6, semiconductor device 103 includes first main terminal 341, second main terminal 342, and output terminal 343, each of which has a comb-tooth shape among its portions protruding from sealing resin 70. For example, as shown in FIG. 6, the portions of first main terminal 341, second main terminal 342, and output terminal 343 protruding from sealing resin 70 have a polygonal shape with one side formed into a comb-tooth shape in plan view. That is, the portions of first main terminal 341, second main terminal 342, and output terminal 343 protruding from sealing resin 70 have a quadrangular shape in plan view before being formed into the comb-tooth shape, and one side of a plate-like member having a quadrangular shape in plan view has been formed into the comb-tooth shape.

[0073] The first main terminal 341, the second main terminal 342, and the output terminal 343 may have a comb-tooth shape at a portion protruding from the sealing resin 70. The first main terminal 341, the second main terminal 342, and the output terminal 343 are not limited to being plate-like members having a rectangular shape in a plan view at a portion protruding from the sealing resin 70, and one entire side of the plate-like member may be formed into a comb-tooth shape, but may also be one side of which is formed into a comb-tooth shape at a portion. The first main terminal 341, the second main terminal 342, and the output terminal 343 may also be plate-like members having a rectangular shape in a plan view at a portion protruding from the sealing resin 70, and two or more sides of the plate-like member may be formed into a comb-tooth shape. Furthermore, the first main terminal 341, the second main terminal 342, and the output terminal 343 do not have to have a rectangular planar shape in the parts that protrude from the sealing resin 70 before being formed into a comb-tooth shape, and may be polygonal or rounded plate-shaped members with a part that protrudes from the sealing resin 70 formed into a comb-tooth shape.

[0074] 6 shows an example in which the first main terminal 341, the second main terminal 342, and the output terminal 343, each having a comb-tooth-shaped portion protruding from the sealing resin 70, protrude from the second side surface, the third side surface, and the first side surface of the sealing resin 70, as in embodiment 2. However, the present invention is not limited to this, and the first main terminal 341, the second main terminal 342, and the output terminal 343, each having a comb-tooth-shaped portion protruding from the sealing resin 70, may be provided so as to protrude from the first side surface, as in embodiment 1, for example.

[0075] As described above, by forming a part of the portion of each terminal protruding from the sealing resin 70 in a comb-tooth shape, the area of each terminal that comes into contact with an external substrate (not shown) or the external air is increased.

[0076] <Manufacturing Method of Third Embodiment> Next, a method for manufacturing semiconductor device 103 according to embodiment 3 of the present disclosure will be described. Note that in this embodiment, among the manufacturing steps of semiconductor device 103, steps other than the steps of forming first main terminal 341, second main terminal 342, and output terminal 343 can be realized by appropriately applying known techniques, and therefore only the steps of forming first main terminal 341, second main terminal 342, and output terminal 343 will be described here.

[0077] The first main terminal 341, the second main terminal 342, and the output terminal 343 are formed by stamping a copper plate having electrical conductivity and good thermal conductivity. The first main terminal 341, the second main terminal 342, and the output terminal 343 are formed, for example, by stamping the copper plate into a predetermined shape using a die. Here, the predetermined shape is, for example, a polygonal shape with one side formed in a comb-like shape.

[0078] <Effects of the Third Embodiment> Next, the operation and effects of the semiconductor device 103 according to the third embodiment of the present disclosure will be described.

[0079] Semiconductor device 103 according to the third embodiment of the present disclosure includes first main terminal 341, second main terminal 342, and output terminal 343, each of which has a comb-tooth shape among its portions protruding from sealing resin .

[0080] According to semiconductor device 103 of the third embodiment of the present disclosure, first main terminal 341, second main terminal 342, and output terminal 343 have at least a portion of their protruding portions from sealing resin 70 formed in a comb-tooth shape, thereby enabling the contact areas of first main terminal 341, second main terminal 342, and output terminal 343 with an external substrate (not shown) or external air to be larger than those of the first and second embodiments. Heat generated by first semiconductor element 21 and second semiconductor element 22 is transferred to the external substrate (not shown) or external air via first main terminal 341, second main terminal 342, and output terminal 343, and is thereby dissipated to the outside of semiconductor device 103. Therefore, according to semiconductor device 103 of the third embodiment of the present disclosure, first main terminal 341, second main terminal 342, and output terminal 343 have at least a portion of their protruding portions from sealing resin 70 formed in a comb-tooth shape, thereby further improving the heat dissipation performance of semiconductor device 103. Furthermore, according to semiconductor device 103 of the third embodiment of the present disclosure, the heat dissipation properties of semiconductor device 103 are improved, thereby making it possible to further increase the current flowing through semiconductor device 103.

[0081] Embodiment 4 In the first embodiment of the present disclosure, a semiconductor device 101 including the first wire 31, the second wire 32, and the third wire 33 has been described. In the fourth embodiment of the present disclosure, a semiconductor device 104 will be described in which the number of wires through which current frequently flows among the first wire 31, the second wire 32, and the third wire 33 is multiple.

[0082] <Configuration of Fourth Embodiment> The configuration of a semiconductor device 104 according to a fourth embodiment of the present disclosure will be described with reference to Fig. 7. Fig. 7 is a plan view showing the semiconductor device 104. Note that Fig. 7 does not show the sealing resin 70 in order to show the internal structure of the sealing resin 70. In Fig. 7, the outline of the sealing resin 70 when it is present is shown by a dotted line.

[0083] As shown in FIG. 7, in the semiconductor device 104, the first wires 31 include a first wire 31a that is arranged to connect two first die pads 11 at one end in the direction in which the first die pads 11 and second die pads 12 are alternately arranged, the second wires 32a that is arranged to connect two second semiconductor elements 22 at the other end in the direction in which the first die pads 11 and second die pads 12 are alternately arranged, and the third wire 33, all of which have a plurality of wires.

[0084] The first wire 31a, the second wire 32a, and the third wire 33 are wires through which current flows more frequently than the first wire 31b provided to connect two first die pads 11 at the other end in the direction in which the first die pads 11 and second die pads 12 are alternately arranged, and the second wire 32b provided to connect two second semiconductor elements 22 at one end in the direction in which the first die pads 11 and second die pads 12 are alternately arranged. Therefore, by increasing the number of the first wires 31a, the second wires 32a, and the third wires 33, the density of the current flowing in each wire can be reduced, and the load caused by the current can be reduced.

[0085] <Manufacturing Method of Fourth Embodiment> The method for manufacturing the semiconductor device 104 according to the fourth embodiment of the present disclosure is similar to the method for manufacturing the semiconductor device 101 according to the first embodiment, and therefore a description thereof will be omitted.

[0086] <Effects of the Fourth Embodiment> Next, the operation and effects of the semiconductor device 104 according to the fourth embodiment of the present disclosure will be described.

[0087] The semiconductor device 104 in embodiment 4 of the present disclosure has, among the first wires 31, a first wire 31a arranged to connect two first die pads 11 at one end in the direction in which the first die pads 11 and second die pads 12 are alternately arranged, among the second wires 32, a second wire 32a arranged to connect two second semiconductor elements 22 at the other end in the direction in which the first die pads 11 and second die pads 12 are alternately arranged, and the third wire 33, each of which has a plurality of wires.

[0088] According to semiconductor device 104 of the fourth embodiment of the present disclosure, it is possible to reduce the density of current flowing through first wire 31 a, second wire 32 a, and third wire 33, which are wires through which current frequently flows, and thereby reduce the load caused by the current flowing through each wire. Therefore, according to semiconductor device 104 of the fourth embodiment of the present disclosure, by reducing the load caused by the current flowing through each wire, it is possible to suppress deterioration of the wires and improve the power cycle life of semiconductor device 104.

[0089] Embodiment 5. In the fourth embodiment of the present disclosure, a semiconductor device 104 has been described in which the number of first wires 31 a, second wires 32 a, and third wires 33, which are wires through which current frequently flows, is plural. In the fifth embodiment of the present disclosure, a semiconductor device 105 will be described in which the wire diameters of first wires 31 a, second wires 32 a, and third wires 33 are increased.

[0090] <Configuration of Fifth Embodiment> The configuration of a semiconductor device 105 according to a fifth embodiment of the present disclosure will be described with reference to Fig. 8. Fig. 8 is a plan view showing the semiconductor device 105. Note that Fig. 8 omits the sealing resin 70 in order to show the internal structure of the sealing resin 70. In Fig. 8, the outline of the sealing resin 70 when it is present is indicated by a dotted line.

[0091] As shown in FIG. 8, in the semiconductor device 105, the first wire 31a of the first wire 31 is arranged to connect the two first die pads 11 at one end in the direction in which the first die pads 11 and the second die pads 12 are alternately arranged, the second wire 32a of the second wire 32 is arranged to connect the two second semiconductor elements 22 at the other end in the direction in which the first die pads 11 and the second die pads 12 are alternately arranged, and the third wire 33 have a larger wire diameter than the first wire 31b arranged to connect the two first die pads 11 at the other end in the direction in which the first die pads 11 and the second die pads 12 are alternately arranged and the second wire 32b arranged to connect the two second semiconductor elements 22 at one end in the direction in which the first die pads 11 and the second die pads 12 are alternately arranged.

[0092] As described in the fourth embodiment, the first wire 31a, the second wire 32a, and the third wire 33 are wires through which current flows more frequently than the first wire 31b and the second wire 32b. Therefore, by increasing the wire diameter of the first wire 31a, the second wire 32a, and the third wire 33, the density of the current flowing through the wires can be reduced, and the load caused by the current can be reduced.

[0093] <Manufacturing Method of Fifth Embodiment> The method for manufacturing the semiconductor device 105 according to the fifth embodiment of the present disclosure is similar to the method for manufacturing the semiconductor device 101 according to the first embodiment, and therefore a description thereof will be omitted.

[0094] <Effects of the Fifth Embodiment> Next, the operation and effects of the semiconductor device 105 according to the fifth embodiment of the present disclosure will be described.

[0095] Among the first wires 31 provided in the semiconductor device 105 in embodiment 5 of the present disclosure, the first wire 31a is arranged to connect two first die pads 11 at one end in the direction in which the first die pads 11 and second die pads 12 are alternately arranged, and among the second wires 32, the second wire 32a is arranged to connect two second semiconductor elements 22 at the other end in the direction in which the first die pads 11 and second die pads 12 are alternately arranged, and the third wire 33 have a wire diameter larger than the first wire 31b is arranged to connect two first die pads 11 at the other end in the direction in which the first die pads 11 and second die pads 12 are alternately arranged, and the second wire 32b is arranged to connect two second semiconductor elements 22 at one end in the direction in which the first die pads 11 and second die pads 12 are alternately arranged.

[0096] According to semiconductor device 105 of the fifth embodiment of the present disclosure, it is possible to reduce the density of current flowing through first wire 31 a, second wire 32 a, and third wire 33, which are wires through which current frequently flows, and thereby reduce the load caused by the current flowing through each wire. Therefore, according to semiconductor device 105 of the fifth embodiment of the present disclosure, by reducing the load caused by the current flowing through each wire, it is possible to suppress deterioration of the wires and improve the power cycle life of semiconductor device 105.

[0097] Although the present disclosure has been described above based on the embodiments, the present disclosure is not limited to the embodiments. Furthermore, appropriate combinations, modifications, omissions, etc. of the embodiments are also included within the scope of the technical idea of the present disclosure. [Explanation of symbols]

[0098] 11 First die pad 12 Second die pad 21 First semiconductor element 22 second semiconductor element 31 First Wire 32 Second Wire 33 Third Wire 34 4th Wire 41 1st main terminal 42 2nd main terminal 43 Output terminal 51 Third die pad 52 Control integrated circuits 53 5th Wire 54 Control terminal 60 Insulation Sheet 70 Sealing resin

Claims

1. at least three first die pads; At least three first semiconductor elements mounted on the first die pads, respectively; First wires electrically connecting the first semiconductor elements to each other; at least three second die pads arranged alternately with the first die pads; at least three second semiconductor elements mounted on the second die pads, respectively; second wires electrically connecting the second semiconductor elements; A semiconductor device comprising:

2. a first main terminal extending from the first die pad arranged on one end side in a direction in which the first die pads and the second die pads are alternately arranged; a second main terminal disposed on the other end side in the direction in which the first die pads and the second die pads are alternately arranged; at least three output terminals extending from the at least three second die pads; a sealing resin that seals the first die pad, the second die pad, the first semiconductor element, the second semiconductor element, the first wire, the second wire, a portion of the first main terminal, a portion of the second main terminal, and a portion of the output terminal; Furthermore, The semiconductor device according to claim 1 .

3. the sealing resin has a quadrangular shape in a plan view, the first main terminal, the second main terminal, and the output terminal are provided so as to protrude from a first side surface of the sealing resin, the first side being a side extending in a direction in which the first die pads and the second die pads are alternately arranged, among sides of the sealing resin in a plan view; The semiconductor device according to claim 2 .

4. the sealing resin has a quadrangular shape in a plan view, the output terminal is provided to protrude from a first side surface of the sealing resin, the first side being a side of the sealing resin in a plan view that extends in a direction in which the first die pads and the second die pads are alternately arranged, the first main terminal is provided to protrude from a second side surface of the sealing resin, the second side being a side of the sealing resin in a plan view, the second side being a side on the one end side in a direction in which the first die pads and the second die pads are alternately arranged, the second main terminal is provided to protrude from a third side surface of the sealing resin, the third side being a side of the sealing resin in a plan view, the third side being a side on the other end side in a direction in which the first die pads and the second die pads are alternately arranged, The semiconductor device according to claim 2 .

5. a width of a portion of the output terminal protruding from the sealing resin in a direction in which the first die pad and the second die pad are alternately arranged is longer than a width of the second die pad; a width of a portion of the first main terminal protruding from the sealing resin in a direction perpendicular to a direction in which the first die pad and the second die pad are alternately arranged is longer than a width of the first die pad; a width of a portion of the second main terminal protruding from the sealing resin in a direction perpendicular to a direction in which the first die pads and the second die pads are alternately arranged is greater than a width of the second die pad; The semiconductor device according to claim 4 .

6. At least a part of the first main terminal, the second main terminal, and the output terminal protruding from the sealing resin is formed in a comb-teeth shape. The semiconductor device according to claim 2 .

7. a third wire electrically connecting the second main terminal and the second semiconductor element; the first wires are provided so as to connect two adjacent first die pads with the second die pad interposed therebetween, the second wires are provided so as to connect two of the second semiconductor elements mounted on two of the second die pads adjacent to each other with the first die pad interposed therebetween, the third wire is provided to connect the second semiconductor element mounted on the second die pad arranged on the other end side in the direction in which the first die pad and the second die pad are alternately arranged, and the second main terminal; The semiconductor device according to claim 2 .

8. the first wire, which is provided to connect two first die pads at one end in a direction in which the first die pads and the second die pads are alternately arranged, the second wire, which is provided to connect two second semiconductor elements at the other end in a direction in which the first die pads and the second die pads are alternately arranged, and the third wire are each a plurality of wires; The semiconductor device according to claim 7 .

9. the first wire provided to connect two first die pads on one end in a direction in which the first die pads and the second die pads are alternately arranged, the second wire provided to connect two second semiconductor elements on the other end in a direction in which the first die pads and the second die pads are alternately arranged, and the third wire have a wire diameter larger than the first wire provided to connect two first die pads on the other end and the second wire provided to connect two second semiconductor elements on the one end; The semiconductor device according to claim 7 .

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