Semiconductor device and method of manufacturing semiconductor device

Abstract

To provide a semiconductor device and a method of manufacturing the semiconductor device which can suppress a triple point of three layers including a plating layer, a resin layer, and a solder layer from being formed on an electrode layer, and prevent the electrode layer from cracking.SOLUTION: A semiconductor device is sealed by a sealing resin, and includes: a semiconductor substrate; an electrode layer formed on an upper surface of the semiconductor substrate; a plating layer formed on an upper surface of the electrode layer, the plating layer including a first region and a second region outside the first region in a plan view; a solder layer formed on the first region of the plating layer; and a solder blocking portion formed on the plating layer, for blocking solder from flowing on the second region from the first region.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor module having a semiconductor chip having a semiconductor substrate and an electrode layer formed on the semiconductor substrate, a plating layer formed on the electrode layer, a solder layer formed on the plating layer, and a sealing resin that seals the semiconductor chip. Furthermore, the document shows a configuration in which the entire side surface of the plating layer is covered with a solder layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-178755 Summary of the Invention [Problem to be solved by the invention]

[0004] The semiconductor device described in Patent Document 1 has a triple junction on the electrode layer where three layers, a plating layer, a resin layer, and a solder layer, meet, and therefore has the problem that strain concentrates at the triple junction due to the difference in stress among the three layers, causing cracks in the electrode layer.

[0005] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a semiconductor device and a method for manufacturing a semiconductor device that can suppress the occurrence of triple points formed by the three layers of a plating layer, a resin layer, and a solder layer on an electrode layer, and prevent cracks from occurring in the electrode layer. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure is a semiconductor device sealed with a sealing resin, and includes a semiconductor substrate, an electrode layer provided on the upper surface of the semiconductor substrate, a plating layer provided on the upper surface of the electrode layer and having a first region and a second region outside the first region in a planar view, a solder layer provided on the first region of the plating layer, and a solder blocking portion formed on the plating layer that blocks solder from flowing from above the first region to above the second region.

[0007] The method for manufacturing a semiconductor device according to the present disclosure is a method for manufacturing a semiconductor device sealed with a sealing resin, and includes an electrode layer formation process for forming an electrode layer on the upper surface of a semiconductor substrate, a plating layer formation process for forming a plating layer having a first region on the upper surface of the electrode layer and a second region outside the first region in a planar view, a solder blocking portion formation process for forming a solder blocking portion in the plating layer that blocks solder so that solder does not flow from above the first region to above the second region, and a solder layer formation process for supplying solder onto the first region to form a solder layer. [Effects of the Invention]

[0008] According to the semiconductor device and the method for manufacturing the semiconductor device of the present disclosure, it is possible to suppress the occurrence of triple points of the plating layer, the resin layer, and the solder layer on the electrode layer, thereby preventing the occurrence of cracks in the electrode layer. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic top view of a semiconductor device according to a first embodiment. [Figure 2] 2 is a schematic cross-sectional view of the semiconductor device according to the first embodiment taken along line XX in FIG. 1. [Figure 3] 3 is a schematic plan view of the semiconductor device according to the first embodiment taken along line YY in FIG. 2. [Figure 4] FIG. 1 is a schematic plan view of a semiconductor device according to a first modification of the first embodiment. [Figure 5] 5 is a schematic cross-sectional view of the semiconductor device according to Modification 1 of Embodiment 1, taken along the line XX in FIG. 4. [Figure 6] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a second modification of the first embodiment. [Figure 7] FIG. 10 is a schematic plan view of a semiconductor device according to a third modification of the first embodiment. [Figure 8] FIG. 10 is a schematic plan view of a semiconductor device according to a third modification of the first embodiment. [Figure 9] FIG. 10 is a schematic plan view of a semiconductor device according to a fourth modification of the first embodiment. [Figure 10] 10 is a schematic cross-sectional view of the semiconductor device according to the fourth modification of the first embodiment, taken along the line XX in FIG. 9. FIG. [Figure 11] FIG. 10 is a schematic plan view of a semiconductor device according to a modification of the first embodiment. [Figure 12] FIG. 10 is a schematic plan view of a semiconductor device according to a modification of the first embodiment. [Figure 13] FIG. 10 is a schematic plan view of a semiconductor device according to a second embodiment. [Figure 14] 14 is a schematic cross-sectional view of the semiconductor device according to the second embodiment taken along line XX in FIG. 13. [Figure 15] FIG. 10 is a schematic plan view of a semiconductor device according to a first modification of the second embodiment. [Figure 16] 16 is a schematic cross-sectional view of the semiconductor device according to the first modification of the second embodiment, taken along the line XX in FIG. 15. [Figure 17] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a second modification of the second embodiment. [Figure 18] FIG. 10 is a schematic plan view of a semiconductor device according to a third modification of the second embodiment. [Figure 19] FIG. 10 is a schematic plan view of a semiconductor device according to a third modification of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] <Introduction> One side in a direction parallel to the depth direction of a semiconductor device is referred to as "top" and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the top surface and the other surface is referred to as the bottom surface. The directions of "top" and "bottom" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0011] For ease of explanation, the width direction of the semiconductor device will be referred to as the x direction, the depth direction of the semiconductor device that intersects with the x direction as the y direction, and the thickness direction or depth direction of the semiconductor device, i.e., the normal direction to the xy plane, as the z direction.

[0012] Furthermore, the drawings are schematic, and the relative sizes and positions of images shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. In the following description, similar components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions thereof may be omitted.

[0013] Embodiment 1 The first embodiment will be described below with reference to the drawings. Fig. 1 is a schematic top view of a semiconductor device 100 according to the first embodiment. Fig. 2 is a schematic cross-sectional view of the semiconductor device 100 according to the first embodiment. Note that Fig. 2 shows a cross section taken along the dashed dotted line X-X shown in Fig. 1.

[0014] In the following description, a semiconductor device sealed with a sealing resin and a semiconductor device that is expected to be sealed with a sealing resin in the future will be described.

[0015] 1 to 3, the configuration of the semiconductor device 100 will be described. As shown in FIG. 2, the semiconductor device 100 includes a semiconductor substrate 1, an electrode layer 2, a plating layer 3, a solder layer 4, and a solder blocking portion 5.

[0016] The semiconductor substrate 1 is made of various semiconductor materials such as silicon (Si), silicon carbide (SiC), or gallium nitride (GaN).

[0017] 2, the electrode layer 2 is provided on the upper surface side of the semiconductor substrate 1. An interlayer insulating film, which will be described later, may be provided between the electrode layer 2 and the semiconductor substrate 1. The electrode layer 2 may be made of an aluminum alloy. For example, the electrode layer 2 is made of an aluminum-silicon alloy (Al—Si alloy).

[0018] As shown in FIG. 2, the plating layer 3 is provided on the upper surface of the electrode layer 2. Next, the plating layer 3 will be described in more detail using FIG. 3. FIG. 3 is a horizontal cross-sectional view taken along the dashed-dotted line Y-Y in FIG. 2. That is, it is a horizontal cross-sectional view taken along the upper surface of the plating layer 3, with the solder layer 4 omitted. The horizontal cross-sectional view described above will be referred to as a plan view. In the following description of the present invention, a "plan view" will be defined as a horizontal cross-sectional view taken along the upper surface of the plating layer 3 of the semiconductor device, as in FIG. 3. As shown in FIG. 3, the plating layer 3 is composed of a first region 3a located at the center of the plating layer 3 and a second region 3b located outside the first region 3a in a plan view. Here, the "plan view" refers to a view from the perspective shown in FIG. 3. In the following description of the present invention, the "plan view" will be defined as a view from above of a cross-section of the upper surface of the plating layer 3 of the semiconductor device, as shown in FIG. 3. The plating layer 3 may be composed of, for example, Au, nickel, or a nickel alloy. The plating layer 3 may have a laminated structure including two or more metal layers, for example. The laminated structure may be composed of, for example, a NiP layer and an Au layer. The plating layer 3 improves the wettability between the electrode layer 2 and the solder layer 4, which is the bonding member, and can enhance the bonding to, for example, a lead frame.

[0019] 1 to 3, the solder layer 4 is provided on the first region 3a of the plating layer 3. In this embodiment, the solder layer 4 is provided over the entire upper surface of the first region 3a, but it may also be provided on a part of the upper surface of the first region 3a.

[0020] As shown in FIGS. 2 and 3 , the solder blocking portion 5 is formed in the plating layer 3. In this embodiment, the solder blocking portion 5 is a gap between the first region 3a and the second region 3b of the plating layer 3. As shown in FIG. 3 , the gap may be formed to surround the outer periphery of the first region 3a of the plating layer 3. Although the width of the gap is exaggerated in FIGS. 2 and 3 compared to the actual width, as described below, the width of the gap may be approximately the width of a crack dividing the first region 3a and the second region 3b. As shown in FIG. 2 , among the side surfaces of the first region 3a and the second region 3b that form the gap, the side surface of the first region 3a is preferably perpendicular to the upper surface of the electrode layer 2. The reason for this will be described later. As shown in FIG. 2 , the gap may extend from the upper surface of the plating layer 3 to the lower surface of the plating layer 3. Note that the gap need only be formed on the upper surface of the plating layer 3; it does not have to reach the lower surface of the plating layer 3.

[0021] As shown in Fig. 3, it is preferable to form the gap so that the center of the first region 3a coincides with the center of the entire plating layer 3. In Fig. 3, the gap is provided symmetrically with respect to the center of the entire plating layer 3, but it does not necessarily have to be provided symmetrically. As long as a gap is formed between the first region 3a and the second region 3b, the position and shape of the gap are arbitrary.

[0022] The semiconductor device 100 of this embodiment is configured as described above. By providing the plating layer 3 with a gap that serves as the solder blocking portion 5, it is possible to suppress the occurrence of a triple point between the plating layer 3, the resin layer, and the solder layer 4 on the electrode layer 2, thereby preventing cracks from occurring in the electrode layer 2. The reason for this will be explained below.

[0023] By providing the gap, solder supplied onto the first region 3a can be prevented from flowing from the first region 3a to the second region 3b. The surface tension of the solder keeps the solder on the first region 3a, preventing it from flowing onto the second region 3b and the electrode layer 2. Furthermore, adjusting the width of the gap, taking into account the viscosity of the solder, can prevent the solder from penetrating into the gap. Therefore, even when the semiconductor device 100 is sealed with a sealing resin, triple junctions formed by the plating layer 3, the resin layer made of the sealing resin, and the solder layer 4 can be prevented from occurring on the electrode layer 2. This prevents cracks from occurring on the electrode layer 2. Furthermore, if a crack occurs in the electrode layer 2 and reaches the interlayer insulating film 7, it will no longer function as an insulating film, leading to device destruction. By applying the present invention, cracks caused by triple junctions on the electrode layer 2 can be prevented, preventing device destruction.

[0024] The width of the gap serving as the solder blocking portion 5 is preferably narrow. By forming the gap narrow, it is possible to more effectively prevent solder from flowing into the gap and onto the electrode layer 2. Furthermore, of the side surfaces of the first region 3a and second region 3b that form the gap, it is preferable that the side surface of the first region 3a is perpendicular to the upper surface of the electrode layer 2. Normally, when the plating layer 3 is formed on the electrode layer 2, the end of the plating layer 3 has a gentle shape relative to the electrode layer 2. With a gentle shape, the solder is more likely to flow onto the electrode layer 2. Therefore, by forming the side surface of the first region 3a that forms the gap perpendicular to the upper surface of the electrode layer 2, it is possible to more effectively prevent solder from flowing into the gap and onto the electrode layer 2.

[0025] Furthermore, when the semiconductor substrate 1 is made of SiC, the breakdown voltage is higher than that of Si, and therefore a higher voltage is applied when the semiconductor device is in use. Therefore, in a SiC substrate, cracks are more likely to occur in the electrode layer 2. By applying the present invention, it is possible to prevent cracks from occurring due to triple points on the electrode layer 2 and suppress the occurrence of cracks in the electrode layer 2.

[0026] Furthermore, when the electrode layer 2 is made of an aluminum alloy, for example, Al—Si, the strength is relatively low compared to when the electrode layer 2 is made of other materials, and therefore cracks are more likely to occur in the electrode layer 2. By applying the present invention, when the electrode layer 2 is made of an aluminum alloy that is prone to cracking, it is possible to prevent cracks from occurring at triple points on the electrode layer 2.

[0027] Next, a description will be given of a manufacturing method of the semiconductor device 100 of this embodiment. The manufacturing method of the semiconductor device 100 of this embodiment is basically the same as the manufacturing method of a conventional semiconductor device except for the solder blocking portion forming step, and therefore some parts will not be described.

[0028] The method for manufacturing the semiconductor device 100 includes an electrode layer forming step, a plating layer forming step, a solder blocking portion forming step, and a solder layer forming step.

[0029] First, the electrode layer forming step will be described. A semiconductor substrate 1 is formed, and an electrode layer 2 is formed on the upper surface of the semiconductor substrate 1. The electrode layer 2 may be formed by a PVD method such as sputtering or vapor deposition.

[0030] Next, the plating layer formation step will be described. A plating layer 3 having a first region 3a and a second region 3b outside the first region 3a in a plan view is formed on the upper surface of the electrode layer 2. The plating layer 3 may be formed by electroless plating or electrolytic plating.

[0031] Next, the solder blocking portion forming step will be described. In this embodiment, a method for forming a gap between the first region 3a and the second region 3b of the plating layer 3 by using the solder blocking portion 5 as a gap will be described.

[0032] As an example of a method for forming the gap, it is preferable to form the gap by passing a current to divide the plating layer 3 into a first region 3a and a second region 3b. For example, the plating layer 3 may be divided by passing a larger-than-normal main current using the main current that flows between an upper electrode and a lower electrode provided in a semiconductor device. If the gap is formed by the above-described method, the width of the gap can be set to approximately the width of the crack that divides the first region 3a and the second region 3b, and the side surface of the first region 3a that forms the gap can be formed perpendicular to the upper surface of the electrode layer 2.

[0033] Therefore, by dividing the plating layer 3 into a first region 3a and a second region 3b to form a gap, the width of the gap can be narrowed, and the side surface of the first region 3a that forms the gap can be formed so as to be perpendicular to the upper surface of the electrode layer 2. Note that the method of forming the gap is not limited to the method using an electric current described above. For example, the gap may be formed by providing a groove in the plating layer 3 by grinding, etching, or the like.

[0034] Next, the solder layer forming step will be described. Solder is supplied onto the first region 3a of the plating layer 3 to form the solder layer 4.

[0035] The semiconductor device 100 is fabricated through the above-described steps. As described above, the manufacturing method for the semiconductor device 100 of this embodiment further includes a solder blocking portion forming step, and the solder blocking portion 5 is a gap. By forming the gap, the solder supplied onto the first region 3a can be prevented from flowing from the first region 3a onto the second region 3b in the solder layer forming step. The surface tension of the solder keeps the solder on the first region 3a, preventing it from flowing onto the second region 3b and onto the electrode layer 2. Furthermore, adjusting the width of the gap in consideration of the viscosity of the solder can prevent the solder from entering the gap. Therefore, even when the semiconductor device 100 is sealed with a sealing resin, the triple point formed by the three layers of the plating layer 3, the resin layer made of the sealing resin, and the solder layer 4 can be prevented from occurring on the electrode layer 2. This prevents cracks from occurring in the electrode layer 2.

[0036] Furthermore, by forming the gap to be narrow, it is possible to further prevent the solder from flowing into the gap and onto the electrode layer 2. Furthermore, by forming the side surface of the first region 3a that forms the gap so as to be perpendicular to the upper surface of the electrode layer 2, it is possible to further prevent the solder from flowing into the gap and onto the electrode layer 2.

[0037] Next, modifications of the first embodiment will be described with reference to FIGS. 4 to 12. In FIGS. 4 to 12, the width of the gap is exaggerated compared to the actual width of the gap. First, the first modification will be described with reference to FIGS. 4 and 5. FIG. 4 is a schematic plan view of a semiconductor device according to the first modification. FIG. 5 is a schematic cross-sectional view of the semiconductor device according to the first modification. In addition, FIG. 5 shows a cross section taken along the dashed dotted line X-X shown in FIG. 4.

[0038] 4 and 5, a protective film 8 that surrounds the outer periphery of the plating layer 3 may be further formed on the upper surface side of the electrode layer 2. As shown in Fig. 5, the protective film 8 may be in contact with the upper surface of the electrode layer 2. Furthermore, as shown in Fig. 4, the protective film 8 may be formed so as to surround the outer periphery of the second region 3b of the plating layer 3. The protective film 8 may be made of, for example, polyimide.

[0039] Next, Modification 2 will be described with reference to FIG. 6 . FIG. 6 is a schematic cross-sectional view of a semiconductor device according to Modification 2. Modification 2 assumes that the semiconductor device is encapsulated with an encapsulating resin. As shown in FIG. 6 , an encapsulating resin 9 may be formed to encapsulate at least the electrode layer 2. Furthermore, as shown in FIG. 6 , the encapsulating resin 9 does not need to fill the gap. As described above, the width of the gap is exaggerated, and the actual width of the gap is narrow. By narrowing the gap, the encapsulating resin 9, like the solder, can be prevented from entering the gap. Note that voids may be formed in the gap. Preventing the solder and the encapsulating resin 9 from entering the gap can form voids in the gap. By forming voids, the solder on the first region 3 a does not enter the gap, thereby further suppressing the occurrence of triple points on the electrode layer 2. Note that the encapsulating resin 9 can be prevented from entering the gap by optimizing the viscosity, material, or encapsulation process of the encapsulating resin. Note that the encapsulating resin 9 may be filled in the gap. By filling the gaps with sealing resin 9, the solder on first region 3a does not enter the gaps, and therefore the occurrence of triple points on electrode layer 2 can be further suppressed.

[0040] Next, Modification 3 will be described with reference to FIGS. 7 and 8. FIGS. 7 and 8 are schematic plan views of a semiconductor device according to Modification 3. The cross-sectional view taken along dashed-dotted line X-X in FIG. 7 is the same as the cross-sectional view shown in FIG. 2. The cross-sectional view taken along dashed-dotted line X-X in FIG. 8 is the same as the cross-sectional view shown in FIG. 5. The semiconductor chip 10 includes a semiconductor substrate 1 and an electrode layer 2. As shown in FIG. 7, when the semiconductor chip 10 is rectangular in plan view, gaps may be formed only in the areas of the plating layer 3 located on the short sides of the semiconductor chip 10. It has been found that when the semiconductor chip 10 is rectangular, cracks are more likely to occur in the electrode layer 2 when solder flows along the short sides of the semiconductor chip 10 than along the long sides of the semiconductor chip 10. Therefore, by forming gaps only in the areas of the plating layer 3 located on the short sides of the semiconductor chip 10, triple points on the short sides of the semiconductor chip 10, where cracks are more likely to occur, can be suppressed, thereby preventing cracks from occurring in the electrode layer 2. Furthermore, the configuration of Modification 3 makes the area of the first region 3a larger than that of Embodiment 1. This makes it possible to widen the area on which the solder can be applied, thereby improving the bonding strength.

[0041] 8, in addition to the configuration of Modification 3, a protective film 8 may be formed as in Modification 1. Also, as shown in FIG. 8, the protective film 8 may be formed so as to surround the entire outer periphery of the plating layer 3 including the gaps.

[0042] In addition to the configuration of the third modification, a sealing resin 9 may be formed in the same manner as the second modification.

[0043] Next, Modification 4 will be described using FIGS. 9 and 10 . FIG. 9 is a schematic plan view of a semiconductor device according to Modification 3. FIG. 10 is a schematic cross-sectional view of a semiconductor device according to Modification 4. Note that FIG. 10 shows a cross section taken along dashed line X-X in FIG. 9 . As shown in FIGS. 9 and 10 , the width and depth of the first region 3a of the plating layer 3 and the width of one side of the second region 3b may be greater than or equal to the thickness of the protective film 8. As shown in FIG. 9 , the width of the first region 3a is B1, and the depth is B2. Furthermore, the widths of one side of the second region 3b are C1 and C2, and the width of one side of the second region 3b adjacent to B1 is C1, and the width of one side of the second region 3b adjacent to B2 is C2. As shown in FIGS. 9 and 10 , when the thickness of the protective film 8 is A, A≦B1, B2, C1, C2 may be satisfied. 9 and 10, the width and depth of the first region 3a of the plating layer 3 are preferably wider than the width of one side of the adjacent second region 3b. By configuring the first region 3a so that C1≦B1 and C2≦B2, the size of the first region 3a on which the solder is placed can be ensured. The thickness of the protective film 8 is, for example, about 10 μm.

[0044] Furthermore, a gap may be formed as shown in Fig. 11. As shown in Fig. 11, the shape of the second region 3b may change depending on the shape of the gap.

[0045] A gate electrode 6 may also be provided on the upper surface of the semiconductor substrate 1. As shown in FIG. 12, it is preferable to provide the gate electrode 6 directly below the first region 3a on the upper surface of the semiconductor substrate 1, and not provide the gate electrode 6 directly below the second region 3b. By not providing the gate electrode 6 directly below the second region 3b, it is possible to ensure that the main current flows only directly below the first region 3a on which the solder is placed. Also, while FIG. 12 shows a gate electrode 6 with a trench structure, a gate electrode with a planar structure may also be used. Also, as shown in FIG. 12, an interlayer insulating film 7 may be provided on the upper surface of the gate electrode 6.

[0046] Embodiment 2 A semiconductor device 200 according to the second embodiment will be described with reference to FIGS. 13 and 14. FIG. 13 is a schematic plan view of the semiconductor device 200 according to the second embodiment. FIG. 14 is a schematic cross-sectional view of the semiconductor device 200 according to the second embodiment. FIG. 14 shows a cross section taken along the dashed-dotted line X-X in FIG. 13. FIG. 14 is a horizontal cross-sectional view taken along the dashed-dotted line Y-Y in FIG. 13, with the solder stopping portion 5 added for ease of explanation, and the solder layer 4 omitted.

[0047] In the semiconductor device 200 of the second embodiment, the solder stopping portion 5 is an oxide film. As shown in FIGS. 13 and 14, the oxide film is formed on the second region 3b of the plating layer 3. This embodiment differs from the first embodiment in that the solder stopping portion 5 is an oxide film and is provided on the second region 3b. In the second embodiment, as shown in FIGS. 13 and 14, the oxide film is provided over the entire second region 3b. However, the oxide film may be provided only on the region of the second region 3b that is close to the first region 3a. For example, the oxide film may be provided only on the region of the second region 3b that is close to the first region 3a, so as to surround the first region 3a.

[0048] As shown in Figure 13, it is preferable to form the oxide film so that the center of the first region 3a coincides with the center of the entire plating layer 3. In Figure 13, the oxide film is provided symmetrically with respect to the center of the entire plating layer 3, but this does not necessarily have to be the case. As long as the oxide film is formed on the second region 3b, the position and shape of the oxide film are arbitrary. Furthermore, the width of the oxide film may vary from side to side.

[0049] The semiconductor device 200 of the second embodiment is configured as described above. By providing the plating layer 3 with an oxide film, which is the solder blocking portion 5, it is possible to suppress the occurrence of triple points between the plating layer 3, the resin layer, and the solder layer 4 on the electrode layer 2, thereby preventing cracks from occurring in the electrode layer 2. The reason for this will be explained below.

[0050] By providing the oxide film, it is possible to prevent the solder supplied onto the first region 3a from flowing from the first region 3a onto the second region 3b. Because the solder does not wet the oxide film, the solder remains on the first region 3a without flowing onto the second region 3b. Therefore, the solder does not flow onto the electrode layer 2. Therefore, even when the semiconductor device 200 is sealed with a sealing resin, it is possible to prevent the occurrence of a triple point on the electrode layer 2 due to the three layers of the plating layer 3, the resin layer made of the sealing resin, and the solder layer 4. This makes it possible to prevent cracks from occurring in the electrode layer 2.

[0051] Next, a method for manufacturing the semiconductor device 200 of the second embodiment will be described. The method for manufacturing the semiconductor device 200 of the second embodiment differs from the method of the first embodiment in the solder stopping portion forming step. The solder stopping portion forming step will be described below, and the other steps are the same as those of the first embodiment.

[0052] In the second embodiment, an example of a method for forming an oxide film on the second region 3b of the plating layer 3 as the solder blocking portion 5 will be described.

[0053] An example of a method for forming an oxide film will be described. First, a metal having a higher ionization tendency than the metal constituting the plating layer 3 is applied to the second region 3b. Here, the metal constituting the plating layer 3 is referred to as the first metal, and the metal having a higher ionization tendency than the metal constituting the plating layer 3 is referred to as the second metal. If the first metal is Au, it is preferable to use Li, Cu, or the like, which is oxidized in air, as the second metal; for example, the second metal is composed of Al.

[0054] Next, the second metal is oxidized to form an oxide film, for example, by exposing the second metal to air.

[0055] Furthermore, when the second metal is applied onto the second region 3b, it is preferable that the second metal remain on the second region 3b without flowing onto the electrode layer 2. If the second metal flows onto the electrode layer 2, a triple point will occur on the electrode layer 2 due to the three layers of the oxide film formed by the oxidation of the second metal, the plating layer 3, and the sealing resin. By applying the second metal onto the second region 3b and preventing it from flowing onto the electrode layer 2, it is possible to prevent the triple point caused by the three layers of the oxide film, the plating layer 3, and the sealing resin from occurring on the electrode layer 2.

[0056] The semiconductor device 200 is fabricated through the above-described steps. As described above, the manufacturing method for the semiconductor device 200 of the second embodiment includes a solder blocking portion forming step, and the solder blocking portion 5 is an oxide film. By forming an oxide film on the plating layer 3, the solder supplied onto the first region 3a can be blocked from flowing from the first region 3a to the second region 3b in the solder layer forming step, as in the first embodiment. Because solder does not wet the oxide film, the solder remains on the first region 3a without flowing onto the second region 3b. Therefore, the solder does not flow onto the electrode layer 2. Therefore, even when the semiconductor device 200 is sealed with a sealing resin, the triple point formed by the three layers of the plating layer 3, the resin layer made of the sealing resin, and the solder layer 4 can be prevented from occurring on the electrode layer 2. This prevents cracks from occurring in the electrode layer 2.

[0057] Furthermore, when the solder blocking portion 5 is an oxide film, it is possible to form the solder blocking portion 5 relatively easily compared to the first embodiment in which the solder blocking portion 5 is a gap.

[0058] Next, modifications of the second embodiment will be described with reference to FIGS. 15 to 19. First, modification 1 will be described with reference to FIGS. 15 and 16. FIG. 15 is a schematic plan view of a semiconductor device according to modification 1. FIG. 16 is a schematic cross-sectional view of the semiconductor device according to modification 1. FIG. 16 is a cross-sectional view taken along the line X-X indicated by the dashed dotted line in FIG. 15. Similarly to FIG. 13, the plan views of FIGS. 15, 18, and 19 are horizontal cross-sectional views taken along the dashed dotted line Y-Y in the cross-sectional views corresponding to the respective plan views, with the solder blocking portion 5 added.

[0059] 15 and 16, a protective film 8 that surrounds the outer periphery of the plating layer 3 may be further formed on the upper surface side of the electrode layer 2. Furthermore, as shown in FIG. 15, the protective film 8 may be formed so as to surround the outer periphery of the second region 3b of the plating layer 3.

[0060] Next, Modification 2 will be described with reference to Fig. 17. Fig. 17 is a schematic cross-sectional view of a semiconductor device according to Modification 2. Modification 2 assumes that the semiconductor device is sealed with a sealing resin. As in Modification 2 of Embodiment 1, the semiconductor device may be sealed with a sealing resin 9 as shown in Fig. 17.

[0061] Next, Modification 3 will be described with reference to FIGS. 18 and 19. FIGS. 18 and 19 are schematic plan views of a semiconductor device according to Modification 3. The cross-sectional view taken along dashed line X-X in FIG. 18 is the same as that in FIG. 14. The cross-sectional view taken along dashed line X-X in FIG. 19 is the same as that in FIG. 16. As shown in FIG. 18, when the semiconductor chip 10 is rectangular in plan view, an oxide film may be formed only on the region of the plating layer 3 located on the short sides of the semiconductor chip 10. It has been found that when the semiconductor chip 10 is rectangular, cracks are more likely to occur in the electrode layer 2 when solder flows along the short sides of the semiconductor chip 10 than along the long sides of the semiconductor chip 10. Therefore, by forming an oxide film only on the region of the plating layer 3 located on the short sides of the semiconductor chip 10, triple points on the electrode layer 2 on the short sides of the semiconductor chip 10, which are prone to cracking, can be suppressed, thereby preventing cracks from occurring in the electrode layer 2. Furthermore, the configuration of Modification 3 provides a larger area for the first region 3a than the configuration of Embodiment 2. Therefore, the area on which the solder can be applied can be expanded, and the bonding strength can be improved.

[0062] 19, in addition to the configuration of Modification 3, a protective film 8 may be formed as in Modification 1. As shown in FIG. 18, the protective film 8 may be formed so as to surround the entire outer periphery of the plating layer 3 including the oxide film.

[0063] In addition to the configuration of the third modification, a sealing resin 9 may be formed in the same manner as the second modification.

[0064] Furthermore, similar to the fourth modification of the first embodiment, the width and depth of the first region 3a of the plating layer 3 and the width of one side of the second region 3b may be equal to or greater than the thickness of the protective film 8. Furthermore, it is preferable that the width and depth of the first region 3a of the plating layer 3 are greater than the width of one side of the adjacent second region 3b. This ensures the size of the first region 3a on which the solder is placed.

[0065] The configurations shown in the above embodiments are merely examples of the contents of the present disclosure and may be combined with other known technologies. Furthermore, it is also possible to combine the embodiments with each other and the modified examples with each other. Furthermore, it is also possible to omit or modify part of the configurations without departing from the scope of the present disclosure. [Explanation of symbols]

[0066] REFERENCE SIGNS LIST 1 semiconductor substrate, 2 electrode layer, 3 plating layer, 4 solder layer, 5 solder stop portion, 6 gate electrode, 8 protective film, 9 sealing resin, 10 semiconductor chip, 100 200 semiconductor device

Claims

1. A semiconductor device sealed with a sealing resin, a semiconductor substrate; an electrode layer provided on the upper surface side of the semiconductor substrate; a plating layer provided on an upper surface of the electrode layer, the plating layer having a first region and a second region outside the first region in a plan view; a solder layer provided on the first region of the plating layer; a solder blocking portion formed on the plating layer for blocking solder so that the solder does not flow from above the first region onto the second region.

2. The semiconductor device according to claim 1 , wherein the solder blocking portion is a gap between the first region and the second region.

3. The semiconductor device according to claim 1 , wherein the solder stopping portion is an oxide film formed on the second region of the plating layer.

4. The semiconductor chip is rectangular in plan view, 4. The semiconductor device according to claim 1, wherein the solder stopping portion is formed only in an area of the plating layer that is located on a short side of the semiconductor chip.

5. 4. The semiconductor device according to claim 1, further comprising a protective film formed on the upper surface of the electrode layer to surround the outer periphery of the plating layer.

6. The semiconductor device according to claim 5 , wherein, in a plan view, the width and depth of the first region of the plating layer and the width of one side of the second region are equal to or greater than the thickness of the protective film.

7. 3. The semiconductor device according to claim 2, wherein the gap is a crack that separates the first region and the second region.

8. 8. The semiconductor device according to claim 2, wherein the side surface of the first region, of the side surfaces of the first region and the second region that form the gap, is perpendicular to the upper surface of the electrode layer.

9. 8. The semiconductor device according to claim 2, wherein the sealing resin does not fill the gap.

10. 4. The semiconductor device according to claim 1, wherein a gate electrode is provided on the upper surface of the semiconductor substrate directly below the first region, and the gate electrode is not provided directly below the second region.

11. 4. The semiconductor device according to claim 1, wherein the electrode layer is made of an aluminum alloy.

12. 4. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of SiC.

13. A method for manufacturing a semiconductor device sealed with a sealing resin, comprising: an electrode layer forming step of forming an electrode layer on the upper surface side of the semiconductor substrate; a plating layer forming step of forming a plating layer having a first region on the upper surface of the electrode layer and a second region outside the first region in a plan view; a solder blocking portion forming step of forming a solder blocking portion in the plating layer to block solder so that the solder does not flow from above the first region to above the second region; and a solder layer forming step of supplying solder onto the first region to form a solder layer.

14. the solder blocking portion is a gap, The method for manufacturing a semiconductor device according to claim 13 , wherein the solder blocking portion forming step forms the gap between the first region and the second region.

15. The method for manufacturing a semiconductor device according to claim 14 , wherein the solder stopping portion forming step forms the gap by dividing the plating layer into the first region and the second region.

16. the solder stopping portion is an oxide film, The method for manufacturing a semiconductor device according to claim 13 , wherein the solder stopping portion forming step forms the oxide film on the second region.

17. 17. The method for manufacturing a semiconductor device according to claim 16, wherein the solder stopping portion forming process applies a metal having a higher ionization tendency than the metal constituting the plating layer onto the second region, and oxidizes the metal having a higher ionization tendency to form the oxide film.

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