Semiconductor apparatus, vibration device, and method of manufacturing semiconductor apparatus

Abstract

To provide a semiconductor apparatus, a vibration device, and a method of manufacturing the semiconductor apparatus capable of suppressing disconnection of wiring in through holes.SOLUTION: In a vibration device 1, a semiconductor apparatus 2 comprises: a semiconductor substrate 5 which has an upper surface 5a and a lower surface 5b in front-and-back relation and is provided with through holes 51, 52 penetrating the upper surface and the lower surface; a semiconductor circuit 7 (oscillation circuit 70) which is disposed on the lower surface side of the semiconductor substrate and provided with electrode pads 721, 722 exposed in the through holes; and first wirings 811, 812 which are disposed on inner peripheral surfaces of the through holes, and have a film thickness at central portions greater than a film thickness at edge portions of the through holes.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, a vibration device, and a method for manufacturing a semiconductor device. [Background technology]

[0002] For example, the semiconductor device described in Patent Document 1 includes a semiconductor substrate having upper and lower surfaces that are opposite each other and having a through hole formed therethrough, a first conductive layer disposed on the lower surface of the semiconductor substrate and exposed in the through hole, an insulating layer disposed on the inner wall of the through hole, an organic insulating layer disposed on the insulating layer, and a wiring disposed on the organic insulating layer and electrically connected to the first conductive layer through a second opening in the organic insulating layer. The wiring is also formed to extend from the through hole onto the upper surface of the semiconductor substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2018-113466 Summary of the Invention [Problem to be solved by the invention]

[0004] However, with such a configuration, it is difficult to ensure the thickness of the wiring within the through-hole, and the wiring is prone to breakage within the through-hole. [Means for solving the problem]

[0005] The semiconductor device of the present invention includes a semiconductor substrate having a first surface and a second surface that are opposite surfaces to each other, and having a through hole formed therein that penetrates the first surface and the second surface; a semiconductor circuit disposed on the second surface side of the semiconductor substrate and including a conductive layer exposed in the through hole; The through hole has a first wiring disposed on an inner peripheral surface thereof, the first wiring having a thickness greater at a center portion than at an edge portion of the through hole.

[0006] The resonation device of the present invention comprises the semiconductor device described above and and a vibration element bonded to the semiconductor device and electrically connected to the semiconductor circuit.

[0007] The method for manufacturing a semiconductor device of the present invention includes the steps of: preparing a base material including: a semiconductor substrate having a first surface and a second surface that are opposite surfaces to each other, and a through hole that penetrates the first surface and the second surface; and a semiconductor circuit that is disposed on the second surface side of the semiconductor substrate and has a conductive layer exposed in the through hole; and a first wiring formation process for forming, by plating, a first wiring in the through hole that is electrically connected to the conductive layer and has a thickness greater at the center than at the edge of the through hole. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view showing a vibration device according to a first embodiment. [Figure 2] 1 is an enlarged cross-sectional view of a through hole formed in a semiconductor substrate. [Figure 3] 1 is an enlarged cross-sectional view of a through hole formed in a semiconductor substrate. [Figure 4] 1 is an enlarged cross-sectional view of a through hole formed in a semiconductor substrate. [Figure 5] FIG. 2 is a plan view showing the top surface of the semiconductor device. [Figure 6] FIG. 1 is a cross-sectional view of a semiconductor device. [Figure 7] FIG. 2 is a plan view showing a vibration element. [Figure 8] 10A to 10C are cross-sectional views illustrating a method for forming a joining member. [Figure 9] FIG. 10 is a cross-sectional view for explaining a problem in plating processing. [Figure 10] 1 is a flowchart showing a manufacturing process of a vibration device. [Figure 11] 10A to 10C are cross-sectional views illustrating a method for manufacturing a vibration device. [Figure 12]10A to 10C are cross-sectional views illustrating a method for manufacturing a vibration device. [Figure 13] 10A to 10C are cross-sectional views illustrating a method for manufacturing a vibration device. [Figure 14] 10A to 10C are cross-sectional views illustrating a method for manufacturing a vibration device. [Figure 15] 10A to 10C are cross-sectional views illustrating a method for manufacturing a vibration device. [Figure 16] 10A to 10C are cross-sectional views illustrating a method for manufacturing a vibration device. [Figure 17] 10A to 10C are cross-sectional views illustrating a method for manufacturing a vibration device. [Figure 18] 10A to 10C are cross-sectional views illustrating a method for manufacturing a vibration device. [Figure 19] 10A to 10C are cross-sectional views illustrating a method for manufacturing a vibration device. [Figure 20] 10A to 10C are cross-sectional views illustrating a method for manufacturing a vibration device. [Figure 21] FIG. 4 is a cross-sectional view showing a vibration device according to a second embodiment. [Figure 22] 22 is a cross-sectional view showing a state in which the vibration device shown in FIG. 21 is mounted on a mounting substrate. DETAILED DESCRIPTION OF THE INVENTION

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device, a resonator device, and a method for manufacturing a semiconductor device according to the present invention will be described in detail below with reference to the embodiments shown in the accompanying drawings.

[0010] First Embodiment FIG. 1 is a cross-sectional view showing a resonator device according to a first embodiment. FIGS. 2 to 4 are enlarged cross-sectional views of through holes formed in a semiconductor substrate. FIG. 5 is a plan view showing the top surface of a semiconductor device. FIG. 6 is a cross-sectional view of the semiconductor device. FIG. 7 is a plan view showing a resonator element. FIG. 8 is a cross-sectional view for explaining a method for forming a bonding member. FIG. 9 is a cross-sectional view for explaining problems in a plating process. FIG. 10 is a flowchart showing the manufacturing process of a resonator device. FIGS. 11 to 20 are cross-sectional views for explaining a method for manufacturing a resonator device. For ease of explanation, each figure illustrates three mutually orthogonal axes as the X-axis, Y-axis, and Z-axis. The side toward which the arrow in the Z-axis direction points is also referred to as "upper," and the opposite side is also referred to as "lower." A planar view from the Z-axis direction is also simply referred to as a "planar view."

[0011] 1, the resonator device 1 includes a semiconductor device 2, a resonator element 3 disposed on the upper surface of the semiconductor device 2, and a lid 4 that covers the resonator element 3 and is bonded to the upper surface of the semiconductor device 2. In such a resonator device 1, the semiconductor device 2 and the lid 4 form a package P, and the resonator element 3 is housed in a housing space S of the package P.

[0012] <Semiconductor device 2> As shown in FIG. 1, the semiconductor device 2 has a semiconductor substrate 5. The semiconductor substrate 5 is a silicon substrate. However, the semiconductor substrate 5 is not particularly limited, and a substrate made of a semiconductor material other than silicon, such as Ge, GaP, GaAs, or InP, may be used. The semiconductor substrate 5 has an upper surface 5a as a first surface and a lower surface 5b as a second surface, which are opposite surfaces. The semiconductor substrate 5 has a pair of through holes 51 and 52 formed therein, penetrating the upper surface 5a and the lower surface 5b. The through holes 51 and 52 can be formed by, for example, RIE (reactive ion etching). This allows the through holes 51 and 52 to have a high aspect ratio. However, the method for forming the through holes 51 and 52 is not particularly limited.

[0013] The semiconductor device 2 also has an insulating film 60 formed on the upper surface 5a and the lower surface 5b of the semiconductor substrate 5. The insulating film 60 formed on the upper surface 5a also extends into the through holes 51 and 52 and is also formed on the upper ends of the through holes 51 and 52. The insulating film 60 is made of, for example, silicon oxide (SiO2). The insulating film 60 can be formed by, for example, sputtering. However, the constituent material and forming method of the insulating film 60 are not particularly limited.

[0014] The semiconductor device 2 also has a semiconductor circuit 7 formed on the lower surface 5b of the semiconductor substrate 5 and electrically connected to the vibration element 3. The semiconductor circuit 7 includes an oscillation circuit 70 that oscillates the vibration element 3 to generate the frequency of a reference signal such as a clock signal. This makes the vibration device 1 an oscillator, which is expected to be highly versatile and in demand.

[0015] The semiconductor circuit 7 has a plurality of elements 700 formed on the lower surface 5b of the semiconductor substrate 5 and a laminated body 71 laminated on the lower surface 5b of the semiconductor substrate 5. The laminated body 71 has a wiring layer 72 formed on the lower surface 5b of the semiconductor substrate 5, an insulating layer 73 formed on the lower surface of the wiring layer 72, a passivation film 74 formed on the lower surface of the insulating layer 73, and a terminal layer 75 formed on the lower surface of the passivation film 74. The plurality of elements 700 are electrically connected to each other via wiring included in the wiring layer 72 and through electrodes penetrating between layers, thereby forming an oscillator circuit 70. The elements 700 are, for example, transistors, resistors, capacitors, etc.

[0016] In this way, by forming the semiconductor circuit 7 on the semiconductor substrate 5, the space of the semiconductor substrate 5 can be effectively utilized. Furthermore, since the semiconductor circuit 7 can be integrally formed with the resonator device 1, the overall size of the device can be reduced. In particular, by forming the semiconductor circuit 7 on the lower surface 5b side, the area in which the semiconductor circuit 7 can be formed is wider compared to when the semiconductor circuit 7 is formed on the upper surface 5a side, since there is no bonding area with the lid 4. Therefore, the degree of freedom in designing the semiconductor circuit 7 is increased.

[0017] In this embodiment, the laminate 71 includes one wiring layer 72, but the present invention is not limited to this, and multiple wiring layers 72 may be laminated with insulating layers 73 interposed therebetween. In other words, the wiring layers 72 and the insulating layers 73 may be alternately laminated multiple times between the semiconductor substrate 5 and the passivation film 74. This improves the degree of freedom in routing the wiring and facilitates circuit design.

[0018] The wiring layer 72 also has an electrode pad 721 as a conductive layer that overlaps the through hole 51 and is exposed in the through hole 51, and an electrode pad 722 as a conductive layer that overlaps the through hole 52 and is exposed in the through hole 52. The terminal layer 75 also has a plurality of external terminals 751 for connecting the semiconductor circuit 7 to an exterior device. Each external terminal 751 penetrates the insulating layer 73 and the passivation film 74 and is electrically connected to the wiring layer 72.

[0019] 1 to 3, the semiconductor device 2 further includes first organic resin films 611 and 612 disposed in the through holes 51 and 52. The first organic resin films 611 and 612 each have insulating properties. The first organic resin film 611 is disposed on the inner circumferential surface of the through hole 51, covering the inner circumferential surface of the through hole 51. Similarly, the first organic resin film 612 is disposed on the inner circumferential surface of the through hole 52, covering the inner circumferential surface of the through hole 52. By covering the inner circumferential surfaces of the through holes 51 and 52 with the first organic resin films 611 and 612 in this manner, first wirings 811 and 812 (described later) can be more reliably insulated from the semiconductor substrate 5.

[0020] The first organic resin films 611, 612 extend from the upper openings of the through holes 51, 52 onto the upper surface 5a, covering the boundary portions 5c between the through holes 51, 52 and the upper surface 5a. The portions of the first organic resin films 611, 612 that cover the boundary portions 5c have rounded surfaces. Furthermore, within the through holes 51, 52, the inner circumferential surfaces of the first organic resin films 611, 612 are tapered such that the inner diameter gradually decreases from the top to the bottom.

[0021] The material for forming such first organic resin films 611 and 612 is not particularly limited, and may be, for example, polyimide resin, epoxy resin, or the like.

[0022] As shown in FIGS. 1 to 3 , the semiconductor device 2 further includes first wirings 811 and 812 disposed in the through holes 51 and 52 and electrically connected to the electrode pads 721 and 722. The first wiring 811 is disposed on the inner circumferential surface of the first organic resin film 611 within the through hole 51 and electrically connected to the electrode pad 721 via the lower opening of the through hole 51. The first wiring 811 is disposed within the inner circumferential surface of the through hole 51. The first organic resin film 611 is disposed within the through hole 51 between the inner circumferential surface of the through hole 51 and the first wiring 811. Similarly, the first wiring 812 is disposed on the inner circumferential surface of the first organic resin film 612 within the through hole 52 and electrically connected to the electrode pad 722 via the lower opening of the through hole 52. The first wiring 812 is disposed within the inner circumferential surface of the through hole 52. A first organic resin film 612 is disposed in the through-hole 52 between the inner circumferential surface of the through-hole 52 and the first wiring 812 .

[0023] The first wirings 811, 812 are filled in the through holes 51, 52 and are arranged so as to fill the bottoms of the through holes 51, 52. In the through holes 51, 52, the first wirings 811, 812 have a thickness T2 at the center that is thicker than the thickness T1 at the edges of the through holes 51, 52. In other words, T2 > T1. By configuring the first wirings 811, 812 in this way, the first wirings 811, 812 can be formed sufficiently thick in the through holes 51, 52, and breakage of the first wirings 811, 812 in the through holes 51, 52 can be effectively suppressed.

[0024] Also, on the upper surfaces of the first wirings 811 and 812, recesses 811a and 812a recessed into the through-holes 51 and 52 are formed. Therefore, the film thickness T2 at the central portions of the through-holes 51 and 52 of the first wirings 811 and 812 is thinner than the depth D of the through-holes 51 and 52. That is, T2 < D. Thereby, it is possible to avoid the through-holes 51 and 52 being completely filled by the first wirings 811 and 812. For example, as shown in FIG. 4, if T2 ≧ D and the through-holes 51 and 52 are completely filled by the first wirings 811 and 812, the thermal stress applied to the semiconductor substrate 5 due to the thermal expansion of the first wirings 811 and 812 in the through-holes 51 and 52 becomes too large, and the semiconductor substrate 5 may be damaged depending on the strength of the semiconductor substrate 5. Therefore, in the present embodiment, by forming the recesses 811a and 812a and setting T2 < D, the thermal stress applied to the semiconductor substrate 5 is suppressed to be small. Thereby, breakage of the semiconductor substrate 5 is effectively suppressed, and a highly reliable vibration device 1 is obtained.

[0025] The film thickness T2 is not particularly limited, but for example, it is preferably 50% or more and 90% or less of the depth D, and more preferably 60% or more and 80% or less. That is, it is preferably 0.5D ≦ T2 ≦ 0.9D, and more preferably 0.6D ≦ T2 ≦ 0.8D. By adopting such a configuration, while the first wirings 811 and 812 in the through-holes 51 and 52 are formed thick enough, the thermal stress applied to the semiconductor substrate 5 due to the thermal expansion of the first wirings 811 and 812 in the through-holes 51 and 52 can be suppressed to be sufficiently small.

[0026] The recesses 811a and 812a are shallower than the through-holes 51 and 52 and have a gentler slope than the inner peripheral surfaces of the through-holes 51 and 52. Therefore, it is possible to ensure the sputtering coverage when forming the second wirings 821 and 822 described later, and the second wirings 821 and 822 can be formed with high precision.

[0027] The first wirings 811, 812 protrude from the upper openings of the through holes 51, 52 onto the upper surface 5a and extend beyond the first organic resin films 611, 612. As described above, the portions of the first organic resin films 611, 612 covering the boundary portion 5c are rounded, which makes it easier to form the first wirings 811, 812 on the boundary portion 5c and effectively prevents poor formation, damage, breakage, and the like of the first wirings 811, 812 at these locations. The first wirings 811, 812 also cover the through holes 51, 52. The portions of the first wirings 811, 812 protruding onto the upper surface 5a surround the through holes 51, 52 in a plan view.

[0028] The first wirings 811, 812 are plated wirings formed by electrolytic plating. By forming the first wirings 811, 812 by electrolytic plating in this way, it becomes easier to form the first wirings 811, 812 thick, and disconnection of the first wirings 811, 812 inside the through holes 51, 52 can be effectively suppressed. In addition, high interlayer adhesion can be achieved. However, the plating process is not limited to electrolytic plating, and the first wirings 811, 812 may also be formed by electroless plating.

[0029] Here, in the electrolytic plating process, a seed layer for growing plating inside the through holes 51, 52 and on the upper surface 5a is formed by sputtering. Therefore, in this embodiment, as described above, the inner surfaces of the first organic resin films 611, 612 are tapered to ensure sputtering coverage when forming the seed layer. Therefore, the seed layer can be formed with a desired thickness over its entire area, and as a result, the first wirings 811, 812 can be formed with high precision.

[0030] The constituent material of such first wirings 811, 812 is not particularly limited, but for example, copper (Cu) can be used. Note that the constituent material being copper (Cu) means that copper (Cu) is used as the main material, and as long as copper (Cu) is used as the main material, other materials may be added. In addition, the configuration of the seed layer is not particularly limited, but for example, it can be a laminate of an underlayer made of a titanium / tungsten alloy (TiW) and a surface layer made of copper (Cu).

[0031] 1 to 3, the semiconductor device 2 further includes second wirings 821 and 822 arranged on the upper surface 5a of the semiconductor substrate 5. The second wiring 821 overlaps the first wiring 811 from above, thereby being electrically connected to the first wiring 811. The first wiring 811 and the second wiring 821 form a single wiring 8A. Similarly, the second wiring 822 overlaps the first wiring 812 from above, thereby being electrically connected to the first wiring 812. The first wiring 812 and the second wiring 822 form a single wiring 8B.

[0032] As shown in FIG. 5, the second wirings 821 and 822 have internal terminals 821a and 822a that are disposed at one end thereof and to which the vibration element 3 is joined.

[0033] The second wirings 821 and 822 are also disposed on the through holes 51 and 52, and cover the first wirings 811 and 812. This allows the second wirings 821 and 822 to confine outgassing from the first wirings 811 and 812 within the through holes 51 and 52. This makes it possible to suppress environmental changes in the accommodation space S due to outgassing, particularly an increase in pressure. This stabilizes the vibration characteristics of the vibration element 3, resulting in a highly reliable vibration device 1. In particular, in this embodiment, the second wirings 821 and 822 cover the entire first wirings 811 and 812, making the above-mentioned effect more pronounced. Furthermore, the first wirings 811 and 812, which are plated wirings, contain a relatively large amount of moisture and are prone to outgassing, making the above-mentioned effect more pronounced in this respect as well.

[0034] The second wirings 821 and 822 are sputtered wirings formed by sputtering. The second wirings 821 and 822 have smaller surface roughness and are thinner than the first wirings 811 and 812. Forming the second wirings 821 and 822 by sputtering can suppress outgassing from the second wirings 821 and 822. This can suppress environmental changes in the accommodation space S, particularly increases in pressure. The second wirings 821 and 822 form dense films, which can more reliably confine outgassing from the first wirings 811 and 812 within the through holes 51 and 52. As described above, the through holes 51 and 52 are partially filled with the first wirings 811 and 812, and recesses 811a and 812a that are shallower and gentler than the through holes 51 and 52 are formed on the surfaces of the second wirings 821 and 822. This ensures sputtering coverage and enables accurate formation of the second wirings 821 and 822. Therefore, the second wirings 821 and 822 can cover the entire area of the first wirings 811 and 812 more reliably.

[0035] 2 and 3, the second wirings 821 and 822 are formed by a laminate of wiring layers 821b and 822b and coating layers 821c and 822c arranged to cover the wiring layers 821b and 822b. The wiring layers 821b and 821b are formed by a laminate of a base layer made of a titanium / tungsten alloy (TiW) and a wiring layer made of copper (Cu), although not shown. The coating layers 821c and 822c are formed by a laminate of a base layer made of titanium (Ti) and a surface layer made of gold (Au), although not shown. By covering the outermost layers of the second wirings 821 and 822 with a surface layer made of gold (Au), degradation of the electrical characteristics of the second wirings 821 and 822 due to oxidation can be effectively suppressed.

[0036] As shown in FIG. 6 , the semiconductor device 2 further includes second organic resin films 621 and 622 disposed on the upper surface 5 a of the semiconductor substrate 5. The second organic resin films 621 and 622 each have insulating properties. The second organic resin film 621 is interposed between the upper surface 5 a and an internal terminal 821 a of the second wiring 821. In other words, the internal terminal 821 a is formed on the second organic resin film 621 and covers the second organic resin film 621. Similarly, the second organic resin film 622 is interposed between the upper surface 5 a and an internal terminal 822 a of the second wiring 822. In other words, the internal terminal 822 a is formed on the second organic resin film 622 and covers the second organic resin film 622.

[0037] The material for forming such second organic resin films 621 and 622 is not particularly limited, and for example, like the first organic resin films 611 and 612 described above, polyimide resin, epoxy resin, etc. may be used.

[0038] <Lid 4> As shown in FIG. 1, the lid 4 has an opening on its lower surface and a bottomed recess 41 for accommodating the vibration element 3 therein. The lid 4 is bonded at its lower surface to the upper surface of the semiconductor device 2, i.e., the upper surface 5a of the semiconductor substrate 5, via a bonding member 40. This forms an accommodating space S for accommodating the vibration element 3 between the lid 4 and the semiconductor device 2. The accommodating space S is airtight and in a reduced pressure state, preferably closer to a vacuum. This reduces viscous resistance and improves the oscillation characteristics of the vibration element 3. However, the atmosphere in the accommodating space S is not particularly limited.

[0039] The lid 4 is a silicon substrate, similar to the semiconductor substrate 5. This makes the linear expansion coefficients of the semiconductor substrate 5 and the lid 4 equal, suppressing the generation of thermal stress due to thermal expansion, resulting in a resonator device 1 with excellent vibration characteristics. Furthermore, since the resonator device 1 can be formed by a semiconductor process, the resonator device 1 can be manufactured with high precision and can be made smaller. However, the lid 4 is not particularly limited, and a substrate made of a semiconductor material other than silicon, such as Ge, GaP, GaAs, or InP, may also be used.

[0040] <Vibration element 3> As shown in FIG. 7 , the vibration element 3 includes a vibration substrate 31 and electrodes arranged on the surface of the vibration substrate 31. The vibration substrate 31 has a thickness-shear vibration mode and is formed of an AT-cut quartz crystal substrate in this embodiment. The AT-cut quartz crystal substrate has a third-order frequency-temperature characteristic, which provides the vibration element 3 with excellent temperature characteristics. The electrodes include an excitation electrode 321 arranged on the upper surface of the vibration substrate 31 and an excitation electrode 322 arranged on the lower surface opposite the excitation electrode 321. The electrodes also include a pair of terminals 323 and 324 arranged on the lower surface of the vibration substrate 31, a wiring 325 electrically connecting the terminal 323 and the excitation electrode 321, and a wiring 326 electrically connecting the terminal 324 and the excitation electrode 322.

[0041] The configuration of the vibration element 3 is not limited to the above-described configuration. For example, the vibration element 3 may be a mesa type in which the vibration region sandwiched between the excitation electrodes 321 and 322 protrudes from its surroundings, or conversely, may be an inverted mesa type in which the vibration region is recessed from its surroundings. In addition, the vibration substrate 31 may be subjected to bevel processing, in which the periphery is ground, or convex processing, in which the upper and lower surfaces are made convex.

[0042] Furthermore, the vibration element 3 is not limited to one that vibrates in a thickness-shear vibration mode, and may be, for example, a vibration element in which multiple vibrating arms vibrate in an in-plane direction. That is, the vibration substrate 31 is not limited to one formed from an AT-cut quartz substrate, and may be formed from a quartz substrate other than an AT-cut quartz substrate, such as an X-cut quartz substrate, a Y-cut quartz substrate, a Z-cut quartz substrate, a BT-cut quartz substrate, an SC-cut quartz substrate, or an ST-cut quartz substrate. In this embodiment, the vibration substrate 31 is made of quartz, but is not limited thereto. For example, the vibration substrate 31 may be made of a piezoelectric single crystal such as lithium niobate, lithium tantalate, lithium tetraborate, langasite, potassium niobate, or gallium phosphate, or may be made of other piezoelectric single crystals. Furthermore, the vibration element 3 is not limited to a piezoelectrically driven vibration element, and may be an electrostatically driven vibration element using electrostatic force.

[0043] 6, the vibration element 3 is joined to internal terminals 821a and 822a by conductive joining members B1 and B2. The joining member B1 electrically connects the internal terminal 821a to the terminal 323, and the joining member B2 electrically connects the internal terminal 822a to the terminal 324. This electrically connects the vibration element 3 and the semiconductor circuit 7 via the joining members B1 and B2 and the wiring 8A and 8B.

[0044] Such bonding members B1 and B2 are microbumps formed by electrolytic plating. By forming the bonding members B1 and B2 by electrolytic plating in this way, it is possible to form minute bonding members B1 and B2. This allows the vibration device 1 to be miniaturized. However, the plating process is not limited to electrolytic plating, and the bonding members B1 and B2 may be formed by electroless plating. In addition, the constituent material of the bonding members B1 and B2 is not particularly limited, but in this embodiment, gold (Au) is used. This results in bonding members B1 and B2 that have excellent conductivity while suppressing deterioration of electrical properties due to oxidation.

[0045] 8, the bonding members B1 and B2 are formed by forming a mask M having openings corresponding to the positions where the bonding members B1 and B2 are to be formed, and then applying a voltage while the semiconductor device 2 is immersed in a plating solution L. Here, as shown in FIG. 9, if the wiring layers 821b and 822b of the second wirings 821 and 822 have large surface roughness, the coating layers 821c and 822c may not be formed uniformly on the surfaces, resulting in the formation of abnormalities Q, such as thin film thicknesses or through holes, in the coating layers 821c and 822c. If the abnormalities Q are formed in the coating layers 821c and 822c, when the semiconductor device 2 is immersed in the plating solution L, the wiring layers 821b and 822b will dissolve into the plating solution L through the abnormalities Q, resulting in copper (Cu), the material of the wiring layers 821b and 822b, being mixed into the bonding members B1 and B2. In this way, if copper (Cu) is mixed into the bonding members B1 and B2, the purity of the gold (Au) decreases, thereby reducing the bonding strength between the bonding members B1 and B2 and the vibration element 3, and as a result, reducing the mechanical strength of the vibration device 1. For example, when the wiring layers 821b and 822b are formed by plating, such a problem is likely to occur.

[0046] In contrast, by forming the wiring layers 821b and 822b by sputtering as in this embodiment, the surface roughness of the wiring layers 821b and 822b can be made smaller than the surface roughness of the first wirings 811 and 812, which are plated wirings. Therefore, the surface roughness of the wiring layers 821b and 822b can be kept sufficiently small, making it difficult for abnormalities Q to form in the coating layers 821c and 822c. This effectively alleviates the above-mentioned problem. In other words, the resonation device 1 of this embodiment prevents copper (Cu) from being mixed into the bonding members B1 and B2, effectively preventing a decrease in the bonding strength between the bonding members B1 and B2 and the resonator element 3. Therefore, a decrease in the mechanical strength of the resonation device 1 can be prevented.

[0047] The above describes the configuration of the resonator device 1. In such a resonator device 1, the wirings 8A and 8B electrically connecting the resonator element 3 and the semiconductor circuit 7 are composed of separately formed first wirings 811 and 812 and second wirings 821 and 822. Therefore, the first wirings 811 and 812 are plated wirings with a sufficiently large film thickness within the through holes 51 and 52, thereby preventing disconnection within the through holes 51 and 52, and the second wirings 821 and 822 are sputtered wirings that can provide good bonding with the resonator element 3. Therefore, the resonator device 1 can effectively prevent disconnection of the wirings 8A and 8B within the through holes 51 and 52 and poor bonding between the resonator element 3 and the wirings 8A and 8B, thereby demonstrating high reliability.

[0048] Next, we will explain the manufacturing method of the resonator device 1. As shown in Fig. 10, the manufacturing method of the resonator device 1 includes a preparation step S1 of preparing a base material of the semiconductor device 2, a first wiring formation step S2 of forming first wirings 811 and 812 by plating, a second wiring formation step S3 of forming second wirings 821 and 822 by sputtering, a bonding member formation step S4 of forming bonding members B1 and B2 by plating, a resonator element bonding step S5 of bonding the resonator element 3 to the semiconductor device 2 via the bonding members B1 and B2, and a lid bonding step S6 of bonding the lid 4 to the semiconductor device 2.

[0049] ≪Preparation process S1≫ First, as shown in FIG. 11, a semiconductor substrate 5 is prepared, and a semiconductor circuit 7 is formed on the lower surface 5b side. This results in a base material for the semiconductor device 2. Next, as necessary, the semiconductor substrate 5 is ground and polished from the upper surface 5a side to thin the semiconductor substrate 5 to a predetermined thickness. Next, as shown in FIG. 12, through holes 51 and 52 are formed in the semiconductor substrate 5, reaching the electrode pads 721 and 722. The through holes 51 and 52 can be formed by, for example, RIE (reactive ion etching). Next, an insulating film 60 is formed from the upper surface 5a side of the semiconductor substrate 5 by, for example, sputtering, and unnecessary portions of the insulating film 60 are removed by etching to expose the electrode pads 721 and 722 in the through holes 51 and 52, as shown in FIG.

[0050] ≪First wiring formation step S2≫ Next, an organic resin is applied to the inner circumferential surfaces of the through holes 51 and 52 and the upper surface 5a. The applied organic resin is heated and cured (baked), and then patterned to form first organic resin films 611 and 612, as shown in FIG. 14. When applied, the organic resin drips downward due to its own weight, so the inner circumferential surfaces of the formed first organic resin films 611 and 612 have a tapered shape. Next, an organic resin is applied to the upper surface 5a. The applied organic resin is heated and cured (baked), and then patterned to form second organic resin films 621 and 622, as shown in FIG. 15. However, the second organic resin film 622 is not shown in FIG. However, without being limited thereto, the second organic resin films 621 and 622 may be formed first, followed by the first organic resin films 611 and 612, or these may be formed simultaneously.

[0051] Next, as shown in FIG. 16 , first wirings 811 and 812 are formed on the inner circumferential surfaces and upper surface 5a of through holes 51 and 52 by electrolytic plating on first organic resin films 611 and 612. By forming first wirings 811 and 812 thick, disconnection of first wirings 811 and 812 within through holes 51 and 52 can be effectively prevented. Although not shown, the process of forming first wirings 811 and 812 includes, for example, the steps of forming a seed layer on the surface of semiconductor substrate 5 by sputtering, forming a mask on the seed layer with openings corresponding to first wirings 811 and 812, growing plating in the openings of the mask to form first wirings 811 and 812, and removing the mask and then etching away unnecessary portions of the seed layer. As described above, the tapered inner circumferential surfaces of first organic resin films 611 and 612 ensure sputtering coverage, enabling the seed layer to be formed with precision.

[0052] ≪Second wiring formation step S3≫ 17, second wirings 821 and 822 are formed on the upper surface 5a by sputtering from above the first wirings 811 and 812, and the first wirings 811 and 812 are covered with the second wirings 821 and 822. This makes it possible to confine outgassing from the first wirings 811 and 812 in the through holes 51 and 52. Note that, because the through holes 51 and 52 are partially filled with the first wirings 811 and 812, sputtering coverage is ensured in this step, and the second wirings 821 and 822 can be formed with high precision.

[0053] Although not shown, the process of forming the second wirings 821 and 822 includes the steps of forming an underlayer for the wiring layers 821b and 822b by sputtering and then patterning it, forming the wiring layers for the wiring layers 821b and 822b by sputtering and then patterning it, forming an underlayer for the coating layers 821c and 822c by sputtering and then patterning it, and forming a surface layer for the coating layers 821c and 822c by sputtering and then patterning it.

[0054] <Joint member forming process S4> Next, as shown in FIG. 18, bonding members B1 and B2 are formed on the internal terminals 821a and 822a of the second wirings 821 and 822 by electrolytic plating. However, FIG. 18 does not show the bonding members B2 and other components. The method for forming the bonding members B1 and B2 is as described above. As described above, the wiring layers 821b and 822b of the second wirings 821 and 822 are formed by sputtering, which allows the surface roughness of the wiring layers 821b and 822b to be sufficiently reduced. Therefore, abnormalities Q are unlikely to form in the coating layers 821c and 822c on the wiring layers 821b and 822b, effectively preventing the wiring layers 821b and 822b from dissolving in the plating solution L. Therefore, copper (Cu), the material of the second wirings 821 and 822, is unlikely to mix with the bonding members B1 and B2, allowing the bonding members B1 and B2 to be formed of high-purity gold (Au).

[0055] <Vibration element bonding process S5> 19, the vibration element 3 is pressed against the bonding members B1 and B2 to bond the vibration element 3 to the internal terminals 821a and 822a. At this time, the second organic resin films 621 and 622 formed directly below the internal terminals 821a and 822a function as stress relief layers that relieve stress generated during pressing. Therefore, the stress applied to the semiconductor device 2 during this process can be reduced, and damage to the semiconductor device 2 can be effectively suppressed.

[0056] ≪Lid joining process S6≫ Next, as shown in FIG. 20, the lid 4 is bonded to the upper surface 5a of the semiconductor substrate 5 in a reduced pressure state.

[0057] In this way, the vibration device 1 is obtained. According to this method for manufacturing the vibration device 1, the outgassing generated from the first wirings 811 and 812 can be confined within the through holes 51 and 52 by the second wirings 821 and 822. This makes it possible to suppress environmental changes in the accommodation space S due to the outgassing, particularly an increase in pressure. This stabilizes the vibration characteristics of the vibration element 3, resulting in a vibration device 1 with high reliability.

[0058] The above describes the resonation device 1. As described above, the resonation device 1 includes a semiconductor substrate 5 having an upper surface 5a (first surface) and a lower surface 5b (second surface) that are opposite surfaces, with through holes 51 and 52 formed therethrough, a semiconductor circuit 7 disposed on the lower surface 5b of the semiconductor substrate 5 and including electrode pads 721 and 722 that are conductive layers exposed in the through holes 51 and 52, and first wirings 811 and 812 disposed on the inner peripheries of the through holes 51 and 52, with a thickness T2 at the center of the through holes 51 and 52 being thicker than a thickness T1 at the edges of the through holes 51 and 52. This configuration allows the first wirings 811 and 812 to be formed sufficiently thick within the through holes 51 and 52, effectively preventing disconnection of the first wirings 811 and 812 within the through holes 51 and 52.

[0059] As described above, recesses 811a, 812a that are recessed into through holes 51, 52 are formed on the surfaces of first wirings 811, 812. This makes it possible to prevent through holes 51, 52 from being completely filled with first wirings 811, 812, and reduces the thermal stress applied to semiconductor substrate 5. Therefore, damage to semiconductor substrate 5 is effectively suppressed, resulting in a highly reliable semiconductor device 2.

[0060] Furthermore, as described above, the film thickness T2 of the first wirings 811, 812 at the center of the through holes 51, 52 is 50% to 90% of the depth D of the through holes 51, 52. With this configuration, the film thickness of the first wirings 811, 812 in the through holes 51, 52 can be ensured to be sufficiently thick, while the thermal stress applied to the semiconductor substrate 5 due to the thermal expansion of the first wirings 811, 812 in the through holes 51, 52 can be kept sufficiently small.

[0061] As described above, the second wirings 821 and 822 are disposed on the upper surface 5a and electrically connected to the first wirings 811 and 812. With this configuration, the wiring can be easily drawn out to the upper surface 5a.

[0062] As described above, the first wirings 811 and 812 extend onto the upper surface 5a, and the second wirings 821 and 822 contact the first wirings 811 and 812 on the upper surface 5a. With this configuration, the first wirings 811 and 812 and the second wirings 821 and 822 can be easily connected to each other.

[0063] As described above, the second wirings 821 and 822 cover the first wirings 811 and 812. With this configuration, outgassing generated from the first wirings 811 and 812 can be confined within the through holes 51 and 52 by the second wirings 821 and 822.

[0064] As described above, the first wirings 811 and 812 are plated wirings, and the second wirings 821 and 822 are sputtered wirings. This configuration makes it easier to form the first wirings 811 and 812 thick. Also, the surface roughness of the second wirings 821 and 822 can be reduced.

[0065] As described above, the first organic resin films 611, 612 are provided between the inner circumferential surfaces of the through holes 51, 52 and the first wirings 811, 812. With this configuration, the first wirings 811, 812 can be more reliably insulated from the semiconductor substrate 5.

[0066] As described above, the resonator device 1 includes the semiconductor device 2 and the resonator element 3 bonded to the semiconductor device 2 and electrically connected to the semiconductor circuit 7. Such a resonator device 1 can provide the effects of the semiconductor device 2 described above, resulting in a highly reliable resonator device 1.

[0067] As described above, the semiconductor circuit 7 has the oscillation circuit 70 that oscillates the vibration element 3. With this configuration, the vibration device 1 becomes an oscillator, which is expected to be highly versatile and in demand.

[0068] As described above, the manufacturing method of the semiconductor device 2 includes a preparation step S1 of preparing a base material including: a semiconductor substrate 5 having an upper surface 5a as a first surface and a lower surface 5b as a second surface that are opposite surfaces to each other, and having through holes 51, 52 formed therethrough; and a semiconductor circuit 7 disposed on the lower surface 5b of the semiconductor substrate 5 and having electrode pads 721, 722 that are conductive layers exposed in the through holes 51, 52; and a first wiring formation step S2 of forming, by plating, first wirings 811, 812 in the through holes 51, 52, the first wirings being electrically connected to the electrode pads 721, 722 and having a thickness T2 at the center of the through holes 51, 52 that is thicker than a thickness T1 at the edges of the through holes 51, 52. This manufacturing method allows the first wirings 811, 812 to be formed sufficiently thick in the through holes 51, 52, effectively preventing disconnection of the first wirings 811, 812 in the through holes 51, 52.

[0069] Second Embodiment Fig. 21 is a cross-sectional view showing a resonation device according to a second embodiment Fig. 22 is a cross-sectional view showing a state in which the resonation device shown in Fig. 21 is mounted on a mounting substrate.

[0070] The resonator device 1 according to this embodiment is similar to the resonator device 1 according to the first embodiment, except for the configuration of the semiconductor device 2. In the following description, the resonator device 1 according to this embodiment will be described focusing on the differences from the first embodiment, and a description of similar points will be omitted. In addition, in each drawing of this embodiment, the same reference numerals are used to designate the same components as those in the above-described embodiment.

[0071] As shown in FIG. 21 , the semiconductor device 2 of this embodiment is upside down compared to the first embodiment, and a semiconductor circuit 7 is formed on the upper surface 5a of a semiconductor substrate 5. Specifically, the semiconductor substrate 5 has a lower surface 5b as a first surface and an upper surface 5a as a second surface, which are opposite surfaces. The semiconductor circuit 7 is formed on the upper surface 5a of the semiconductor substrate 5, excluding the bonding area with the lid 4. The semiconductor circuit 7 includes multiple elements 700, such as transistors, formed on the upper surface 5a of the semiconductor substrate 5, and a laminated body 71 laminated on the upper surface 5a of the semiconductor substrate 5. The laminated body 71 includes a wiring layer 72 formed on the upper surface 5a of the semiconductor substrate 5, an insulating layer 73 formed on the upper surface of the wiring layer 72, a passivation film 74 formed on the upper surface of the insulating layer 73, and a terminal layer 75 formed on the upper surface of the passivation film 74. By forming the semiconductor circuit 7 on the upper surface 5a of the semiconductor substrate 5 in this manner, the semiconductor circuit 7 is housed in a package P and protected.

[0072] The terminal layer 75 also has two internal terminals 752 and 753 for electrically connecting the semiconductor circuit 7 to the vibration element 3. The internal terminals 752 and 753 are electrically connected to the wiring layer 72 by penetrating the insulating layer 73 and the passivation film 74, respectively. The internal terminals 752 and 753 are also electrically connected to the terminals 323 and 324 of the vibration element 3 via the bonding members B1 and B2. This electrically connects the vibration element 3 and the semiconductor circuit 7 via the bonding members B1 and B2 and the internal terminals 752 and 753. The electrode pads 721 and 722 are output signal pads for outputting oscillation signals and the like from the semiconductor circuit 7 to the outside, and input signal pads for supplying a power supply voltage or a ground potential to the semiconductor circuit 7 from the outside, etc.

[0073] Then, first wirings 811 and 812 are arranged and filled in the through holes 51 and 52, and wiring is drawn out from the semiconductor circuit 7 to the outside by the first wirings 811 and 812. Note that the configuration of the first wirings 811 and 812 is the same as that of the first embodiment described above, and therefore description thereof will be omitted.

[0074] The resonator device 1 configured as described above is mounted on the mounting substrate 100 by solder reflow or the like, as shown in FIG. 22 . At this time, the portions of the first wirings 811, 812 that protrude onto the lower surface 5b function as terminals. Furthermore, by forming the first wirings 811, 812 thick in the through holes 51, 52, the gap G between the mounting substrate 100 and the through holes 51, 52 is reduced, thereby reducing voids accordingly. This improves the connection reliability between the resonator device 1 and the mounting substrate 100.

[0075] The second embodiment as described above can also achieve the same effects as the first embodiment.

[0076] The semiconductor device, resonator device, and semiconductor device manufacturing method of the present invention have been described above based on the illustrated embodiments, but the present invention is not limited to these, and the configurations and steps of each part can be replaced with any configurations and steps having similar functions. Furthermore, other arbitrary configurations and steps may be added to the present invention. Furthermore, the present invention may be a combination of two or more embodiments.

[0077] In the above-described embodiment, an example in which the vibration device 1 is applied to an oscillator has been described, but the application of the vibration device 1 is not particularly limited, and the vibration device 1 can be applied to, for example, an inertial sensor such as an acceleration sensor, an angular velocity sensor, etc. Furthermore, the vibration device 1 can be applied to any other equipment. [Explanation of symbols]

[0078] 1... resonator device, 100... mounting substrate, 2... semiconductor device, 3... resonator element, 31... resonator substrate, 321... excitation electrode, 322... excitation electrode, 323... terminal, 324... terminal, 325... wiring, 326... wiring, 4... lid, 40... bonding member, 41... recess, 5... semiconductor substrate, 5a... upper surface, 5b... lower surface, 5c... boundary portion, 51... through hole, 52... through hole, 60... insulating film, 611... first organic resin film, 612... first organic resin film, 621... second organic resin film, 622... second organic resin film, 7... semiconductor circuit, 70... oscillation circuit, 700... element, 71... laminate, 72... wiring layer, 721... electrode pad, 722... electrode pad, 73... insulating layer, 74... passivation film, 75... terminal layer , 751...external terminal, 752...internal terminal, 753...internal terminal, 8A...wiring, 8B...wiring, 811...first wiring, 811a...recess, 812...first wiring, 812a...recess, 821...second wiring, 821a...internal terminal, 821b...wiring layer, 821c...covering layer, 822...second wiring, 822a...internal terminal, 822b...wiring layer, 822c...covering layer, B1...bonding member, B2...bonding member, D...depth, G...gap, L...plating solution, M...mask, P...package, Q...abnormal area, S...accommodation space, S1...preparation step, S2...first wiring formation step, S3...second wiring formation step, S4...bonding member formation step, S5...vibration element bonding step, S6...lid body bonding step, T1...film thickness, T2...film thickness

Claims

1. a semiconductor substrate having a first surface and a second surface that are opposite surfaces to each other, and having a through hole formed therein that penetrates the first surface and the second surface; a semiconductor circuit disposed on the second surface side of the semiconductor substrate and including a conductive layer exposed in the through hole; a first wiring disposed on an inner peripheral surface of the through hole, the first wiring having a thickness greater at a center portion of the through hole than at an edge portion of the through hole.

2. The semiconductor device according to claim 1 , wherein a recess that is recessed into the through hole is formed on the surface of the first wiring.

3. 3. The semiconductor device according to claim 2, wherein the thickness of the first wiring at the center of the through hole is 50% to 90% of the depth of the through hole.

4. 2. The semiconductor device according to claim 1, further comprising a second wiring disposed on the first surface and electrically connected to the first wiring.

5. the first wiring extends onto the first surface; The semiconductor device according to claim 4 , wherein the second wiring is in contact with the first wiring on the first surface.

6. The semiconductor device according to claim 4 , wherein the second wiring covers the first wiring.

7. the first wiring is a plated wiring, 5. The semiconductor device according to claim 4, wherein the second wiring is a sputtering wiring.

8. 2. The semiconductor device according to claim 1, further comprising a first organic resin film interposed between an inner periphery of the through hole and the first wiring.

9. A semiconductor device according to any one of claims 1 to 8, a vibration element bonded to the semiconductor device and electrically connected to the semiconductor circuit.

10. The vibrating device according to claim 9 , wherein the semiconductor circuit includes an oscillation circuit that causes the vibrating element to oscillate.

11. a preparation step of preparing a base material including: a semiconductor substrate having a first surface and a second surface that are opposite surfaces to each other, with a through hole formed therethrough that penetrates the first surface and the second surface; and a semiconductor circuit disposed on the second surface side of the semiconductor substrate and including a conductive layer exposed in the through hole; a first wiring formation process for forming, by plating, a first wiring in the through hole, the first wiring being electrically connected to the conductive layer and having a thickness greater at the center than at the edge of the through hole.

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