Semiconductor device

Abstract

To provide a semiconductor device with a new structure in which the storage content can be held even in circumstances with no power supply and the number of times of writing is not limited.SOLUTION: A semiconductor device has a structure in which a plurality of memory cells are arranged in matrix, each memory cell including a first transistor 160, a second transistor 162, and a capacitor element 164, a wire (also called a bit line) 156 connecting one memory cell and another memory cell and a source electrode or drain electrode 142a, 142b of the first transistor are electrically connected through the source electrode or drain electrode 142a, 142b of the second transistor. Thus, the number of wires can be reduced compared to a case in which the source electrode or the drain electrode of the first transistor and the source electrode or the drain electrode of the second transistor are connected to different wires, thereby improving the degree of integration of the semiconductor device.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The disclosed invention relates to a semiconductor device using a semiconductor element and a manufacturing method thereof. do. [Background technology]

[0002] Memory devices that use semiconductor elements are volatile memory devices that lose their contents when the power supply is cut off. and non-volatile memory devices, which retain their contents even when the power supply is cut off. can be.

[0003] A typical example of a volatile memory device is a DRAM (Dynamic Random Access Memory). DRAM is a memory element that can be selected from transistors. By storing charge in the capacitor, information is stored.

[0004] According to the above principle, in DRAM, when information is read, the charge in the capacitor is lost. Every time information is read, a write operation is required again. In a transistor, leakage current (off-state current) between the source and drain in the off state causes transistor Data retention is achieved because charges flow in and out even when the transistor is not selected. Therefore, a write operation (refresh operation) is required at regular intervals. Therefore, it is difficult to sufficiently reduce power consumption. Because the contents are lost, other storage methods using magnetic or optical materials are used for long-term memory retention. Equipment is required.

[0005] Another example of a volatile memory device is SRAM (Static Random Access Memory). SRAM uses circuits such as flip-flops to store the memory contents. In order to retain data, no refresh operation is required, which is an advantage over DRAM. However, because it uses circuits such as flip-flops, the cost per unit of memory capacity is high. In addition, there is a problem that the memory contents are lost when the power supply is cut off. In this regard, it is no different from DRAM.

[0006] A typical example of a nonvolatile memory device is flash memory. A floating gate is provided between the gate electrode of the transistor and the channel forming region, Since memory is stored by holding an electric charge in the floating gate, the data retention period is extremely long. The advantage is that it lasts for a very long time (semi-permanent) and does not require the refresh operations required for volatile storage devices. The point is as follows (see, for example, Patent Document 1).

[0007] However, the gate insulating layer that constitutes the memory element is damaged by the tunnel current that occurs during writing. The memory element deteriorates, and repeated writing causes it to stop functioning. To avoid this problem, for example, the number of write operations to each memory element may be made uniform. However, to achieve this, complex peripheral circuits are required. However, even if such a method is adopted, the fundamental problem of lifespan will not be resolved. Therefore, flash memory is not suitable for applications where information needs to be rewritten frequently.

[0008] In addition, to inject or remove charges into or from the floating gate, high A high voltage is required, and a circuit for this is also required. It takes a relatively long time to erase the data, and it is not easy to speed up writing and erasing. There is also an issue. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Publication No. 57-105889 Summary of the Invention [Problem to be solved by the invention]

[0010] In view of the above-mentioned problems, one embodiment of the disclosed invention provides a method for storing stored contents even when power is not supplied. To provide a semiconductor device having a new structure that can retain data and has no limit on the number of times it can be written. This is one of the purposes of the organization. [Means for solving the problem]

[0011] In the disclosed invention, a semiconductor device is formed using a highly purified oxide semiconductor. Since transistors using oxide semiconductors with SiO2 have extremely low leakage current, , it is possible to retain information for a long period of time.

[0012] One embodiment of the disclosed invention is, for example, a wiring ( a source electrode or a drain electrode of the first transistor; is electrically connected to the source electrode or the drain electrode of the second transistor. This structure allows the source electrode or the drain electrode of the first transistor to and the source electrode or the drain electrode of the second transistor are connected to different wirings. The number of wirings can be reduced compared to when a semiconductor device is used, thereby improving the integration degree of the semiconductor device. It can be done.

[0013] Another embodiment of the disclosed invention is, for example, a wiring for connecting one memory cell to another memory cell. One of the lines (also called source lines) is connected to multiple memory cells (at least connected to different bit lines). a source electrode or a second electrode of a first transistor included in each of the first and second memory cells (including the memory cell having the first and second transistors) The number of source lines is set to be greater than the number of bit lines. This allows the number of source lines to be reduced sufficiently, The integration degree of the device can be improved.

[0014] More specifically, for example, the following configuration can be adopted.

[0015] A semiconductor device according to one embodiment of the present invention includes a first transistor and a second transistor. The memory cell includes a first transistor having a first channel forming region and a first transistor having a first channel forming region. a first gate insulating layer provided on the channel forming region and a second insulating layer overlapping the first channel forming region; a first gate electrode provided on the first gate insulating layer; and a first channel forming region. a first source electrode and a first drain electrode electrically connected to each other; The first gate electrode has a second channel forming region and a second gate electrode electrically connected to the second channel forming region. a source electrode, a second drain electrode, and a second channel forming region; a second gate electrode and a second channel forming region provided between the second gate electrode and the second channel forming region; and a gate insulating layer, wherein the first channel forming region and the second channel forming region are different. The first transistor and the second transistor are configured to include a semiconductor material A wiring for connecting one memory cell to another memory cell is provided so as to overlap with the first memory cell. One of the first source electrode or the first drain electrode and the second source electrode and the second drain electrode. Electrical connection is made via one of the input electrodes.

[0016] In the semiconductor device, one of the first source electrode and the first drain electrode; The region in contact with one of the second source electrode and the second drain electrode is the second source electrode. and one of the second drain electrodes and a wiring connecting one of the memory cells to another memory cell. , preferably overlap with the area they contact.

[0017] Alternatively, in the semiconductor device, one of the second source electrode and the second drain electrode is , and either the first source electrode or the first drain electrode are preferably the same. In this case, one of the second source electrode and the second drain electrode and the first source electrode and The region where the first drain electrode contacts the second source electrode and the second drain electrode and a wiring connecting one of the memory cells to another memory cell. It is more preferable to have

[0018] Furthermore, a semiconductor device according to another embodiment of the present invention includes m signal lines (m is an integer of 2 or more) and m signal lines. n word lines, n bit lines (n is an integer equal to or greater than 2), and k bit lines (k is a natural number less than n). The source line, the (m×n) memory cells arranged in a matrix, the bit line, and the a first driving circuit electrically connected to the source line; a second driving circuit electrically connected to the signal line; a third driving circuit electrically connected to the word line; and a fourth driving circuit electrically connected to the word line. and a gate electrode, a first source electrode, a first drain electrode, and a second gate electrode. a first transistor including a gate electrode and a first channel forming region; a second gate electrode; a second transistor including a second source electrode, a second drain electrode, and a second channel forming region; a first channel forming region and a second channel forming region; and one of the second source electrode and the second drain electrode, each of which includes a different semiconductor material. One of the electrodes of the capacitor element is electrically connected to the first gate electrode, and one of the source lines is connected to the first gate electrode. The first source electrode is electrically connected to one of the bit lines, and the second source electrode is electrically connected to the second The other of the drain electrodes is electrically connected to the first drain electrode, and is connected to one of the word lines. The other electrode of the capacitor element is electrically connected to one of the signal lines and the second gate electrode. are electrically connected, and one of the source lines is connected to j (j is (m+1) or more) memory cells including one of the memory cells. (m×n) (an integer not greater than m×n) is connected to.

[0019] Furthermore, a semiconductor device according to another embodiment of the present invention includes m signal lines (m is an integer of 2 or more) and m signal lines. n word lines, n bit lines (n is an integer of 2 or more), and k bit lines (k is a natural number less than n). The source line, the (m×n) memory cells arranged in a matrix, the bit line, and the a first driving circuit electrically connected to the source line; a second driving circuit electrically connected to the signal line; a third driving circuit electrically connected to the word line; and a fourth driving circuit electrically connected to the word line. and a gate electrode, a first source electrode, a first drain electrode, and a second gate electrode. a first transistor including a gate electrode and a first channel forming region; a second gate electrode; a second transistor including a second source electrode, a second drain electrode, and a second channel forming region; a first channel forming region and a second channel forming region; and one of the second source electrode and the second drain electrode, each of which includes a different semiconductor material. One of the electrodes of the capacitor element is electrically connected to the first gate electrode, and one of the source lines is connected to the first gate electrode. The first source electrode is electrically connected to one of the bit lines, and the second source electrode is electrically connected to the second The other of the drain electrodes is electrically connected to the first drain electrode, and is connected to one of the word lines. The other electrode of the capacitor element is electrically connected to one of the signal lines and the second gate electrode, are electrically connected, and one of the source lines is connected to one of the (m×n / k) memory cells including one of the memory cells. It is electrically connected to all of the first source electrodes that the cells have.

[0020] In the semiconductor device, the first transistor has a first channel forming region therebetween. It is preferable that the impurity region is provided so as to surround the semiconductor substrate.

[0021] In the semiconductor device, the second channel formation region of the second transistor is formed of an oxide. It is preferable that the layer is made up of a nitride semiconductor.

[0022] In the above description, the transistor is formed using an oxide semiconductor material. The present invention is not limited to this. materials, such as wide-gap materials including silicon carbide (more specifically, e.g. , a semiconductor material having an energy gap Eg of greater than 3 eV) may be applied.

[0023] In this specification, the terms "above" and "below" refer to the positional relationship of a component, such as "directly above" or "below." For example, the term "gate electrode on a gate insulating layer" is not limited to "directly under" the gate insulating layer. If the expression "electrode" is used, it excludes those that include other components between the gate insulating layer and the gate electrode. Furthermore, the terms "upper" and "lower" are used merely for the convenience of explanation.

[0024] In addition, the terms "electrode" and "wiring" used in this specification refer to these components functionally. This is not a limitation. For example, an "electrode" may be used as part of a "wiring." , and vice versa. Furthermore, the terms "electrode" and "wiring" are used interchangeably to refer to the plural "electrodes." This also includes cases where the wiring is formed as a single unit.

[0025] Also, the functions of "source" and "drain" may differ depending on whether transistors with different polarities are used or not. However, they may be swapped when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" are used interchangeably. It is assumed that this is possible.

[0026] In this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a wire. is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between the connection objects.

[0027] For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. These include switching elements, resistor elements, inductors, capacitors, and other various functions. This includes elements such as [Effects of the Invention]

[0028] Since a transistor using an oxide semiconductor has an extremely small off-state current, It is possible to retain the stored contents for a much longer period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations to an extremely low level. Therefore, power consumption can be reduced sufficiently. , it is possible to retain the stored contents for a long period of time.

[0029] In addition, the semiconductor device according to the disclosed invention does not require a high voltage for writing information. There is no problem of degradation of the electrons in the floating gate as in conventional non-volatile memory. Since there is no need to inject or extract electrons from the floating gate, there is no degradation of the gate insulating layer. In other words, the semiconductor device according to the present invention does not have the same problems as the conventional nonvolatile semiconductor memory device. There is no limit to the number of times it can be rewritten, which is a problem with non-volatile memory, and reliability is dramatically improved. Furthermore, information can be written by switching the transistor between on and off. Since the data is erased, high-speed operation can be easily realized. There is also the advantage that

[0030] In addition, a transistor using a material other than an oxide semiconductor is Compared to transistors, this allows for even higher speed operation. By using it in combination with a transistor, the operation of a semiconductor device (for example, reading out information) can be improved. Furthermore, it is possible to ensure sufficient high speed of the semiconductor device (operation). These transistors are ideal for various circuits (logic circuits, driver circuits, etc.) that require high-speed operation. It is possible to achieve this appropriately.

[0031] In this way, transistors using materials other than oxide semiconductors (more broadly speaking, transistors that can operate satisfactorily) and transistors that use oxide semiconductors (or, more broadly, transistors that can operate satisfactorily) By integrating a transistor with a particularly low off-state current, It is possible to realize a semiconductor device that

[0032] Furthermore, in one embodiment of the disclosed invention, the number of wirings is reduced by sharing wirings, and the number of wirings is reduced. It is possible to provide a semiconductor device with improved integration density. [Brief explanation of the drawings]

[0033] [Figure 1] 1A and 1B are a cross-sectional view and a plan view of a semiconductor device; [Figure 2] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 3] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 4] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 5] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 6] 1A and 1B are a cross-sectional view and a plan view of a semiconductor device; [Figure 7] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor substrate used for manufacturing a semiconductor device. [Figure 8] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 9] 1A and 1B are a cross-sectional view and a plan view of a semiconductor device; [Figure 10] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 11] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 12] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 13]FIG. [Figure 14] Timing chart. [Figure 15] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 16] Timing chart. [Figure 17] 1A to 1C illustrate electronic devices using semiconductor devices. [Figure 18] 10A to 10C show characteristics of a transistor including an oxide semiconductor. [Figure 19] FIG. 10 is a circuit diagram for evaluating the characteristics of a transistor including an oxide semiconductor. [Figure 20] 10 is a timing chart for evaluating characteristics of a transistor including an oxide semiconductor. [Figure 21] 10A to 10C show characteristics of a transistor including an oxide semiconductor. [Figure 22] 10A to 10C show characteristics of a transistor including an oxide semiconductor. [Figure 23] 10A to 10C show characteristics of a transistor including an oxide semiconductor. [Figure 24] A diagram showing the results of a memory window width survey. DETAILED DESCRIPTION OF THE INVENTION

[0034] An example of an embodiment of the present invention will be described below with reference to the drawings. and the present invention is not limited to the above description, and may be modified in various forms and forms without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. The present invention is not to be construed as being limited to the description of the embodiment shown in the accompanying drawings.

[0035] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily accurate to facilitate understanding. It may not represent the actual position, size, range, etc. Therefore, the disclosed invention The position, size, range, etc. are not necessarily limited to those disclosed in the drawings.

[0036] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components. It should be noted that the numbers are added to avoid confusion and are not intended to limit the number.

[0037] (Embodiment 1) In this embodiment, a structure of a semiconductor device according to one embodiment of the disclosed invention and a manufacturing method thereof will be described. This will be described with reference to FIGS.

[0038] <Cross-sectional and planar configurations of semiconductor device> FIG. 1 shows an example of the configuration of a semiconductor device. FIG. 1(A) shows a cross section of the semiconductor device. 1B) shows a plan view of the semiconductor device. Here, FIG. 1A shows the A of FIG. 1B. The cross sections shown in Fig. 1(A) and Fig. 1(B) correspond to the cross sections taken along lines 1-A2 and B1-B2. The semiconductor device has a transistor 160 using a first semiconductor material in the lower part and a The transistor 162 is made of a second semiconductor material. It is desirable that the first semiconductor material and the second semiconductor material are different materials. The first semiconductor material is a semiconductor material other than an oxide semiconductor, and the second semiconductor material is an oxide semiconductor. Examples of semiconductor materials other than oxide semiconductors include silicon, germanium, Silicon germanium, silicon carbide, or gallium arsenide can be used. It is preferable to use a crystalline semiconductor. Alternatively, an organic semiconductor material may be used. Transistors using semiconductor materials with high conductivity can easily operate at high speed. The characteristics of the transistor allow it to retain charge for a long period of time.

[0039] It should be noted that the above transistors are all n-channel transistors. However, it goes without saying that a p-channel transistor can also be used. The technical essence of the invention is to develop a semiconductor device that can sufficiently reduce the off-state current, such as an oxide semiconductor, to retain data. The advantage of this method is that the transistor 162 is made of a semiconductor material that can be reduced to The specific configuration of the semiconductor device, such as the materials used in the device and the structure of the semiconductor device, is shown here. There is no need to limit it to anything.

[0040] The transistor 160 in FIG. 1 is formed on a substrate 100 that includes a semiconductor material (e.g., silicon). 00 and the channel forming region 116 provided in between. The impurity region 120 is formed by the metal compound region 124 in contact with the impurity region 120, and the channel A gate insulating layer 108 is provided on the gate forming region 116, and a gate insulating layer 109 is provided on the gate insulating layer 108. The figure does not explicitly show the source electrode or the drain electrode. However, for convenience, this state is also referred to as a transistor. In this case, the source region and the drain region are not shown in order to explain the connection relationship of the transistor. The source electrode and the drain electrode may include the drain region. In the above, the source electrode may include the source region. The description may include a drain region.

[0041] An electrode 126 is connected to a portion of the metal compound region 124 of the transistor 160 . Here, the electrode 126 functions as a source electrode or a drain electrode of the transistor 160. In addition, an element isolation insulating layer 106 is provided on the substrate 100 so as to surround the transistor 160. and an insulating layer 128 and an insulating layer 130 are provided over the transistor 160. In order to achieve high integration, the transistor 160 is preferably a sidewall transistor as shown in FIG. On the other hand, it is preferable to use a structure without a wall insulating layer. When this is important, a sidewall insulating layer is provided on the side of the gate electrode 110, and the side The impurity region includes a region with a different impurity concentration formed in the region overlapping the wall insulating layer. 120 may be set.

[0042] The transistor 162 in FIG. 1 has a source electrode or drain electrode provided on the insulating layer 130. a source or drain electrode 142a, and a source or drain electrode 142b. The drain electrode 142a and the source or drain electrode 142b are electrically connected to each other. The oxide semiconductor layer 144 is connected to the source electrode or drain electrode 142a. Alternatively, the drain electrode 142b and the gate insulating layer 146 covering the oxide semiconductor layer 144 and the gate insulating layer 146 are A gate electrode 148 is provided on the oxide insulating layer 146 so as to overlap with the oxide semiconductor layer 144. a, and a gate electrode between the source electrode or drain electrode 142a and the oxide semiconductor layer 144. The insulating layer 143a provided in a region overlapping with the electrode 148a and the source electrode or the drain electrode The electrode 142b is provided in a region between the electrode 142b and the oxide semiconductor layer 144, and overlaps with the gate electrode 148a. The source electrode or the drain electrode and the gate electrode are formed on the insulating layer 143b. In order to reduce the capacitance between the electrodes, insulating layers 143a and 143b are provided. However, it is also possible to adopt a structure in which the insulating layer 143a and the insulating layer 143b are not provided. is.

[0043] Here, impurities such as hydrogen are sufficiently removed from the oxide semiconductor layer 144. It is desirable that the gas be highly purified by supplying sufficient oxygen. Specifically, for example, the hydrogen concentration in the oxide semiconductor layer 144 is 5×10 19 atoms / cm 3 Below 5×10 18 atoms / cm 3 Less than or equal to 5×10 17 a toms / cm 3 Note that the hydrogen concentration in the oxide semiconductor layer 144 is determined as follows: Secondary Ion Mass Spectrometry (SIMS) In this way, the hydrogen concentration in the oxide semiconductor layer 144 is measured by spectroscopy. The oxide semiconductor layer 144 is highly purified by sufficiently reducing the amount of oxygen. In the oxide semiconductor layer 144 in which the defect level in the energy gap due to deficiency is reduced, , the carrier concentration is 1×10 12 / cm 3 Less than 1×10 11 / cm 3 less than, More preferably 1.45 x 10 10 / cm 3 For example, at room temperature (25°C), The current (here, the value per unit channel width (1 μm)) is 100 zA (1 zA (Zep amperes) is 1 x 10 -21 A) or less, preferably 10zA or less. By using an i-type (intrinsic) or substantially i-type oxide semiconductor, extremely excellent Therefore, the transistor 162 having the same off-state current characteristics can be obtained.

[0044] In the transistor 162 of FIG. 1, leakage current that occurs between elements due to miniaturization is suppressed. In order to achieve this, the oxide semiconductor layer 144 is processed into an island shape. In the case where the oxide semiconductor layer is not processed into an island shape, the oxide semiconductor layer may be processed without any etching. This can prevent contamination of the oxide semiconductor layer 144 due to etching.

[0045] The capacitor 164 in FIG. 1 includes a source electrode or a drain electrode 142a, an oxide semiconductor The gate insulating layer 144, the gate insulating layer 146, and the electrode 148b are the source electrodes. The drain electrode 142a functions as one electrode of the capacitor 164. The electrode 8 b functions as the other electrode of the capacitor element 164 .

[0046] In the capacitor 164 in FIG. 1, the oxide semiconductor layer 144 and the gate insulating layer 146 are stacked. By doing so, the insulation between the source electrode or drain electrode 142a and the electrode 148b is reduced. Of course, in order to ensure sufficient capacity, oxide semiconductor The capacitor element 164 may be configured without the insulating layer 143a. A capacitor element 164 having an insulating layer formed in the same manner may be used. If the capacitor 164 is not required, the capacitor 164 may not be provided.

[0047] Note that in the transistor 162 and the capacitor 164, the source electrode or the drain electrode The ends of the electrode 142a and the source or drain electrode 142b are tapered. It is preferable that the source electrode or drain electrode 142a, the source electrode or drain electrode The tapered end of the electrode 142b improves the coverage of the oxide semiconductor layer 144. This is because the taper angle can be improved and step disconnection can be prevented. The taper angle is 0° or more and 60° or less. The taper angle is the angle at which the layer having a tapered shape (for example, The source electrode or drain electrode 142a) is perpendicular to the cross section (plane perpendicular to the surface of the substrate). This indicates the inclination angle between the side and bottom surfaces of the layer when observed from a perpendicular direction.

[0048] In this embodiment, the transistor 162 and the capacitor 164 are By adopting such a planar layout, For example, if the minimum processing dimension is F and the area occupied by the memory cell is 15 F 2 ~25F 2 It is possible to do so.

[0049] An insulating layer 150 is provided over the transistor 162 and the capacitor 164. An insulating layer 152 is provided on the edge layer 150. The gate insulating layer 146 and the insulating layer An electrode 154 is provided in an opening formed in the insulating layer 152. On the top of the electrode 154, a wiring 156 is formed to connect to the electrode 154. and electrode 154 to form a metal compound region 124, a source electrode or a drain electrode 142b. , and wiring 156 are connected, but the disclosed invention is not limited to this. The source or drain electrode 142b may be in direct contact with the metal compound region 124. Alternatively, the wiring 156 may be directly in contact with the source electrode or the drain electrode 142b. stomach.

[0050] In FIG. 1, the metal compound region 124 and the source electrode or drain electrode 142b are The electrode 126 to be connected is connected to the source electrode or drain electrode 142b and the wiring 156. The source electrode and the drain electrode of the transistor 160 are overlapped with each other. Electrode 126 serves as a drain electrode, and the source or drain electrode of transistor 162. The area where the gate electrode 142b contacts the source electrode or drain electrode of the transistor 162. The area where the electrode 142b and the wiring 156 connecting one memory cell to another memory cell contact each other. By adopting this layout, high integration can be achieved. do.

[0051] <Method for manufacturing semiconductor device> Next, an example of a method for manufacturing the semiconductor device will be described. A method for fabricating the transistor 160 will be described with reference to FIGS. 2 and 3. A method for manufacturing the transistor 162 and the capacitor 164 will be described with reference to FIGS. 4 and 5. explain.

[0052] <Method for manufacturing the lower transistor> First, a substrate 100 containing a semiconductor material is prepared (see FIG. 2(A)). The plate 100 may be a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. Compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be used. Here, the substrate 100 containing a semiconductor material is a single crystal silicon substrate. An example will be shown below. Generally, an "SOI substrate" is a substrate that has a silicon layer on an insulating surface. However, in this specification, it refers to a substrate having a structure in which a material other than silicon is provided on an insulating surface. This also includes substrates with a structure in which a semiconductor layer made of a material is provided. The semiconductor layer of the SOI substrate is not limited to a silicon layer. This includes a configuration in which a semiconductor layer is provided on an insulating substrate via an insulating layer. .

[0053] In particular, when a single crystal semiconductor substrate such as silicon is used as the substrate 100 containing a semiconductor material, In this case, it is preferable because the read operation of the semiconductor device can be performed at high speed.

[0054] A protective layer 102 is formed on the substrate 100 to serve as a mask for forming an element isolation insulating layer. (See FIG. 2(A)). The protective layer 102 may be made of, for example, silicon oxide or silicon nitride. An insulating layer made of silicon oxynitride or the like can be used. In order to control the threshold voltage of the transistor, an impurity that gives n-type conductivity is added. An element or an impurity element that imparts p-type conductivity may be added to the substrate 100. In the case of capacitors, impurities that give n-type conductivity include phosphorus and arsenic. In addition, impurities that impart p-type conductivity include, for example, boron and aluminum. Sodium, gallium, etc. can be used.

[0055] Next, etching is performed using the protective layer 102 as a mask, and the This removes a portion of the substrate 100 from the exposed area. A semiconductor region 104 separated from the region is formed (see FIG. 2(B)). Although dry etching is preferably used for this purpose, wet etching may also be used. The etching gas and etching solution should be selected appropriately depending on the material to be etched. can.

[0056] Next, an insulating layer is formed so as to cover the semiconductor region 104, and the region overlapping the semiconductor region 104 is The insulating layer is selectively removed to form an element isolation insulating layer 106 (see FIG. 2(C)). The insulating layer is formed using silicon oxide, silicon nitride, silicon oxynitride, etc. The insulating layer can be removed by polishing such as CMP (chemical mechanical polishing) or etching. After the semiconductor region 104 is formed, Alternatively, after the element isolation insulating layer 106 is formed, the protective layer 102 is removed.

[0057] The element isolation insulating layer 106 can be formed by selectively removing the insulating layer, or by using an acid. Alternatively, a method of forming an insulating region by implanting an element may be used.

[0058] Next, an insulating layer is formed on the surface of the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. Complete.

[0059] The insulating layer is to be a gate insulating layer later, and is formed by, for example, heat treatment of the surface of the semiconductor region 104. Instead of heat treatment, high density High density plasma treatment may be applied. For example, high density plasma treatment may be applied using He, Ar, Kr, A mixture of rare gases such as Xe, oxygen, nitrogen oxide, ammonia, nitrogen, hydrogen, etc. It can be done using gas. Of course, it is also possible to use CVD or sputtering methods to create insulation. The insulating layer may be formed of silicon oxide, silicon oxynitride, silicon nitride, or silicon oxide. Hafnium oxide, aluminum oxide, tantalum oxide, yttrium oxide, hafnium silicate HfSi x O y(x>0, y>0)), nitrogen-doped hafnium silicate ( HfSi x O y (x>0, y>0)), nitrogen-doped hafnium aluminate (Hf Al x O y It is desirable to have a single layer structure or a laminated structure including (x>0, y>0) The thickness of the insulating layer is, for example, 1 nm or more and 100 nm or less, preferably 10 nm or more. It can be 50 nm or less.

[0060] The layer containing the conductive material is made of a metal material such as aluminum, copper, titanium, tantalum, or tungsten. Also, a conductive material such as polycrystalline silicon can be used to form the conductive layer. The method for forming the layer is not particularly limited, and may be a vapor deposition method, a CVD method, a sputtering method, or the like. Various film forming methods such as talc coating and spin coating can be used. In this embodiment, an example in which a layer containing a conductive material is formed using a metal material is shown. Let's say.

[0061] Thereafter, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108. Then, a gate electrode 110 is formed (see FIG. 2(C)).

[0062] Next, phosphorus (P) or arsenic (As) is added to the semiconductor region 104 to form a channel forming region. 116 and impurity region 120 are formed (see FIG. 2(D)). Phosphorus and arsenic are added to form p-type transistors. In this case, impurity elements such as boron (B) and aluminum (Al) can be added. The concentration of the added impurities can be set appropriately, but as semiconductor elements become highly miniaturized, In this case, it is desirable to increase the concentration of the added impurity.

[0063] A sidewall insulating layer is formed around the gate electrode 110 to form a gate insulating film containing different impurity elements. An impurity region doped with a certain concentration may be formed.

[0064] Next, a metal layer 122 is formed so as to cover the gate electrode 110, the impurity region 120, etc. (FIG. 3(A)). The metal layer 122 can be formed by vacuum deposition, sputtering, spin coating, or the like. The metal layer 122 can be formed by using various film formation methods such as the above. The metal material reacts with the semiconductor material that makes up the semiconductor to form a low-resistance metal compound. Such metal materials include, for example, titanium, tantalum, Examples include tungsten, nickel, cobalt, and platinum.

[0065] Next, a heat treatment is performed to bond the metal layer 122 and the semiconductor material that constitutes the semiconductor region 104. This causes a reaction, forming a metal compound region 124 in contact with the impurity region 120. (See FIG. 3(A)). When polycrystalline silicon or the like is used as the gate electrode 110, In addition, a metal compound region is also formed in the portion of the gate electrode 110 that is in contact with the metal layer 122. This will happen.

[0066] The heat treatment may be, for example, a heat treatment by irradiation with a flash lamp. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds In order to improve the controllability of the heat treatment, it is desirable to use a method that can realize heat treatment in a very short time. The metal compound region is preferably formed by a reaction between a metal material and a semiconductor material. The metal compound region is formed in a region where the conductivity is sufficiently increased. This can sufficiently reduce the electrical resistance and improve the device characteristics. After forming region 124, metal layer 122 is removed.

[0067] Next, an electrode 126 is formed in a region that contacts a part of the metal compound region 124 (FIG. 3(B) The electrode 126 is formed by, for example, forming a layer containing a conductive material and then depositing a conductive material containing the conductive material. The conductive material layer is formed by selectively etching the conductive material. The insulating layer 11 can be formed using a metal material such as titanium, tantalum, or tungsten. A layer containing a conductive material may be formed using a semiconductor material such as polycrystalline silicon. The method is not particularly limited, and various methods such as vapor deposition, CVD, sputtering, and spin coating can be used. A film forming method can be used.

[0068] The electrode 126 is formed by forming the insulating layer 128 and the insulating layer 130. An opening is formed in the insulating layer 130 so as to reach the metal compound region 124, and the opening is filled with It is also possible to form it so that it is enclosed.

[0069] In this case, for example, a thin titanium film is formed in the area including the opening by the PVD method, and then a thin titanium film is formed by the CVD method. After forming a thinner titanium nitride film, a tungsten film is formed to fill the opening. Here, the titanium film formed by the PVD method is The oxide film (such as a natural oxide film) of the lower electrode (here, the metal compound region 124) is reduced. The titanium nitride film formed afterwards has the function of reducing the contact resistance with the conductive material. It also has a barrier function that suppresses the diffusion of conductive materials. After forming the barrier film, a copper film may be formed by plating.

[0070] Next, insulating layers 128 and 130 are formed to cover the respective components formed by the above-described steps. The insulating layer 128 and the insulating layer 130 are formed of silicon oxide, silicon oxynitride, or the like. It is formed using a material containing an inorganic insulating material such as silicon, silicon nitride, or aluminum oxide. In particular, the insulating layer 128 and the insulating layer 130 may be made of a low-k material. By using this, it is possible to sufficiently reduce the capacitance caused by overlapping of various electrodes and wiring. It is preferable that the insulating layer 128 and the insulating layer 130 are made of porous materials. A porous insulating layer may have a higher dielectric constant than a dense insulating layer. This reduces the capacitance caused by the electrodes and wiring, making it possible to further reduce the capacitance. The edge layer 128 and the insulating layer 130 are formed using organic insulating materials such as polyimide and acrylic. It is also possible to form the insulating layer 128 and the insulating layer 130 in a laminated structure. However, one embodiment of the disclosed invention is not limited to this. It may also be a structure.

[0071] As a result of the above, a transistor 160 using the substrate 100 containing a semiconductor material is formed (see FIG. 3(C)). Such a transistor 160 has the advantage of being capable of high-speed operation. Therefore, by using the transistor as a read transistor, Information can be read at high speed.

[0072] Then, as a process before forming the transistor 162 and the capacitor element 164, the insulating layer 128 The insulating layer 130 is subjected to CMP processing to expose the upper surfaces of the gate electrode 110 and the electrode 126. (See FIG. 3(D)). As the process, etching or the like can be applied in addition to CMP (etching (The CMP process may be combined with the CMP process.) To achieve this, the surfaces of the insulating layer 128 and the insulating layer 130 should be as flat as possible. desirable.

[0073] Before and after each of the above steps, further steps may be performed to form electrodes, wiring, semiconductor layers, insulating layers, etc. For example, the wiring structure may be a laminated structure of an insulating layer and a conductive layer. It is also possible to realize a highly integrated semiconductor device by adopting a multi-layer wiring structure.

[0074] <Method of manufacturing the upper transistor> Next, a conductive layer is formed on the gate electrode 110, the electrode 126, the insulating layer 128, the insulating layer 130, etc. The conductive layer is selectively etched to form a source electrode or a drain electrode 142a. The source or drain electrode 142b is formed so as to be in electrical contact with the electrode 126. (See Figure 4(A)).

[0075] The conductive layer is formed using PVD methods such as sputtering, or CVD methods such as plasma CVD. The conductive layer can be formed using a material such as aluminum, chromium, copper, Elements selected from tantalum, titanium, molybdenum, and tungsten, or the above elements Alloys containing manganese, magnesium, zirconium, beryllium, etc. can be used. Using either aluminum, neodymium, or scandium, or a combination of these materials Good too.

[0076] The conductive layer may have a single layer structure or a laminated structure of two or more layers. single-layer structure of silicon film or titanium nitride film, single-layer structure of aluminum film containing silicon, Two-layer structure with titanium film laminated on titanium nitride film, two-layer structure with titanium film laminated on titanium nitride film Examples include a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated. In addition, when the conductive layer has a single layer structure of a titanium film or a titanium nitride film, a tapered shape is The source or drain electrode 142a and the source or drain electrode 142 It has the advantage of being easy to process into b.

[0077] The conductive layer may be formed using a conductive metal oxide. Indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), Indium tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO), oxide Indium-zinc oxide alloy (In2O3-ZnO), or these metal oxide materials It is possible to use a material containing silicon or silicon oxide.

[0078] The etching of the conductive layer is performed to form the source or drain electrode 142a and the source It is preferable to perform this process so that the end of the source or drain electrode 142b has a tapered shape. Here, the taper angle is preferably, for example, 30° or more and 60° or less. The ends of the source or drain electrodes 142a and 142b are By etching to form a tapered shape, the gate insulating layer 14 to be formed later can be This improves the covering property of 6 and prevents breakage.

[0079] The channel length (L) of the upper transistor is determined by the source or drain electrode 142a and and the distance between the bottom ends of the source electrode or drain electrode 142b. Exposure for forming a mask used when forming a transistor with a channel length (L) of less than 25 nm When using light, extreme ultraviolet rays with a wavelength of several nanometers to several tens of nanometers are used. It is preferable to use ultraviolet light. Extreme ultraviolet light exposure provides high resolution and a wide depth of focus. Therefore, the channel length (L) of the transistor to be formed later should be set to 10 nm or more. It is possible to make it 000nm (1μm) or less, which enables the operating speed of the circuit to be increased. Furthermore, miniaturization also makes it possible to reduce the power consumption of semiconductor devices.

[0080] An insulating layer that functions as a base may be provided on the insulating layer 128 or the insulating layer 130. The insulating layer can be formed by using a PVD method, a CVD method, or the like.

[0081] Next, an insulating layer 143a is formed on the source or drain electrode 142a. An insulating layer 143b is formed on each of the drain electrodes 142b (see FIG. 4(B)). The insulating layer 143a and the insulating layer 143b are formed on the source electrode or the drain electrode 142a and the After forming an insulating layer covering the source electrode or the drain electrode 142b, the insulating layer is selectively The insulating layer 143a and the insulating layer 143b can be formed by etching. The insulating layer is formed so as to overlap with a part of the gate electrode to be formed later. By doing so, the capacitance between the gate electrode and the source electrode or the drain electrode can be reduced. It is possible to do this.

[0082] The insulating layer 143a and the insulating layer 143b are made of silicon oxide, silicon oxynitride, silicon nitride, or silicon oxide. The insulating layer can be formed using a material containing an inorganic insulating material such as aluminum chloride. By using a low-k material for the layer 143a and the insulating layer 143b, It becomes possible to sufficiently reduce the capacitance between the electrode and the source electrode or the drain electrode. It is preferable that the insulating layer 143a and the insulating layer 143b are made of porous materials. A porous insulating layer may be applied. A porous insulating layer has a lower dielectric constant than a dense insulating layer. This reduces the capacitance between the gate electrode and the source or drain electrode. It is possible to reduce it.

[0083] In addition, in order to reduce the capacitance between the gate electrode and the source electrode or the drain electrode, In this case, it is preferable to form the insulating layer 143a and the insulating layer 143b. It is also possible to configure it without providing it.

[0084] Next, the source or drain electrode 142a and the source or drain electrode 142b are After forming an oxide semiconductor layer so as to cover 42b, the oxide semiconductor layer is selectively etched. The oxide semiconductor layer 144 is formed by etching (see FIG. 4C).

[0085] The oxide semiconductor layer 144 may be a quaternary metal oxide such as In—Sn—Ga—Zn—O, or a ternary metal oxide such as In—Sn—Ga—Zn—O. The metal oxides In-Ga-Zn-O, In-Sn-Zn-O, and In-Al- Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn-O and binary metal oxides such as In-Zn-O, Sn-Zn-O, and Al-Zn-O. Zn-Mg-O, Sn-Mg-O, In-Mg-O, and single-component metal oxides It can be formed using an In-O system, an Sn-O system, a Zn-O system, or the like.

[0086] Among these, In-Ga-Zn-O oxide semiconductor materials have a sufficiently high resistance in the absence of an electric field. It is possible to sufficiently reduce the electron current and the field effect mobility is high, so it is It is suitable as a semiconductor material for use in devices.

[0087] A typical example of an In-Ga-Zn-O oxide semiconductor material is InGaO3(ZnO). m (m>0). Also, M is used instead of Ga, and InMO3(Zn O) m There are oxide semiconductor materials that are written as (m>0), where M is gallium. (Ga), aluminum (Al), iron (Fe), nickel (Ni), manganese (Mn), It refers to one or more metal elements selected from the group consisting of cobalt (Co), etc. For example, M includes Ga, Ga and Al, Ga and Fe, Ga and Ni, and Ga and Mn. The above composition is derived from the crystal structure. Please note that these are merely examples.

[0088] The target for forming the oxide semiconductor layer by sputtering is In:Ga:Zn= It is recommended to use a material expressed in the composition ratio of 1:x:y (x is 0 or more, y is 0.5 or more and 5 or less). For example, In2O3:Ga2O3:ZnO=1:1:2 [molar ratio] (x= 1, y=1) can be used. :Ga2O3:ZnO=1:1:1 [molar ratio] (x=1, y=0.5) and targets such as In2O3:Ga2O3:ZnO=1:1:4 [molar ratio] (x=1, y=2), or a target having a composition ratio of In2O3:Ga2O3:ZnO=1:0:2 A target having a composition ratio of [molar ratio] (x=0, y=1) can also be used.

[0089] In this embodiment, the oxide semiconductor layer is formed using an In—Ga—Zn—O-based oxide semiconductor film forming tank. The film is formed by sputtering using a target.

[0090] The relative density of the metal oxide in the oxide semiconductor film formation target is 80% or more, preferably 95% or more. % or more, and more preferably 99.9% or more. By using a target, it is possible to form an oxide semiconductor layer with a dense structure. .

[0091] The oxide semiconductor layer is formed in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or Alternatively, it is preferable to use a mixed atmosphere of rare gas (typically argon) and oxygen. In practice, the concentration of impurities such as hydrogen, water, hydroxyl groups, and hydrides is preferably 1 ppm or less. It is preferable to use a high-purity gas atmosphere in which the concentration has been reduced to 10 ppb or less.

[0092] When forming the oxide semiconductor layer, for example, the object to be processed is kept in a processing chamber maintained in a reduced pressure state. The temperature of the workpiece is maintained at 100°C or higher and lower than 550°C, preferably 200°C or higher and 400°C or higher. Alternatively, the temperature of the object to be treated is adjusted to the temperature of the object to be treated when the oxide semiconductor layer is formed. The temperature may be room temperature (25°C ± 10°C). Then, while removing moisture from the processing chamber, hydrogen A sputtering gas from which silicon dioxide and water have been removed is introduced, and an oxide semiconductor layer is formed using the target. The oxide semiconductor layer is formed while heating the object to be treated. In addition, damage to the oxide semiconductor layer due to sputtering can be reduced. To remove moisture from the processing chamber, an adsorption type vacuum pump is used. For example, cryopumps, ion pumps, titanium sublimation pumps, etc. A pump or the like can be used. A turbo pump with a cold trap added can also be used. By using a cryopump or the like to evacuate the processing chamber, hydrogen, water, etc. can be removed. Since the impurity concentration in the oxide semiconductor layer can be reduced, the impurity concentration in the oxide semiconductor layer can be reduced.

[0093] The oxide semiconductor layer is formed under the conditions, for example, when the distance between the object to be treated and the target is 1 70 mm, pressure 0.4 Pa, direct current (DC) power 0.5 kW, atmosphere oxygen (oxygen 10 0%) atmosphere, or argon (100% argon) atmosphere, or a mixture of oxygen and argon It is possible to apply conditions such as a mixed atmosphere. This reduces the amount of powdery material (also called particles or dust) that is generated during film formation, and improves film thickness distribution. The thickness of the oxide semiconductor layer is preferably 1 nm or more and 50 nm or less. The thickness is preferably 1 nm or more and 30 nm or less, and more preferably 1 nm or more and 10 nm or less. By using an oxide semiconductor layer with a sufficient thickness, it is possible to suppress the short channel effect that accompanies miniaturization. However, it is possible to select an appropriate oxide semiconductor material depending on the application of the semiconductor device. The thickness varies and can be selected depending on the material used and the intended use.

[0094] Before forming the oxide semiconductor layer by sputtering, argon gas was introduced to Reverse sputtering is performed to generate a smear, and deposits on the formation surface (for example, the surface of the insulating layer 130) are removed. Here, the reverse sputtering is a method of removing the sputtered material. Instead of bombarding the target with ions, the ions are bombarded on the processing surface of the substrate. This refers to a method of modifying the surface by bombarding the surface with ions. The method is to apply a high frequency voltage to the surface to be treated in an argon atmosphere, and then place a plasma near the workpiece. In addition, instead of an argon atmosphere, a nitrogen atmosphere or a helium atmosphere can be used. An atmosphere such as an oxygen atmosphere may be used.

[0095] After that, the oxide semiconductor layer is preferably subjected to heat treatment (first heat treatment). Excess hydrogen (including water and a hydroxyl group) in the oxide semiconductor layer is removed by first heat treatment; The structure of the oxide semiconductor layer can be adjusted to reduce defect levels in the energy gap. The temperature of the first heat treatment is, for example, 300°C or higher and lower than 550°C, or 400°C or higher and lower than 50°C. Keep below 0℃.

[0096] The heat treatment is carried out by, for example, placing the object to be treated in an electric furnace using a resistance heating element, and heating the object in a nitrogen atmosphere. The process can be carried out at 450°C for 1 hour. During this time, the oxide semiconductor layer is not exposed to the air. This will prevent water and hydrogen from getting mixed in.

[0097] The heat treatment device is not limited to an electric furnace, and may be any device that uses heat conduction or heat radiation from a medium such as a heated gas. For example, a device that heats the object to be treated by irradiation may be used. Rapid Thermal Anneal (GRTA) equipment, Gas Rapid Th RTA (Rapid Thermal Anneal) equipment l) The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps It is a device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp such as a The GRTA device is a device that performs heat treatment using high-temperature gas. Inert gases that do not react with the material to be treated by heat treatment, such as rare gases such as fluorine or nitrogen. is used.

[0098] For example, in the first heat treatment, the workpiece is placed in a heated inert gas atmosphere and heated for several minutes. After the heating, the object to be treated may be taken out of the inert gas atmosphere and subjected to GRTA treatment. GRTA treatment allows high-temperature heat treatment in a short time. It is possible to apply this method even under temperature conditions exceeding 100°C. During the treatment, an inert gas is used instead of oxygen. By performing the first heat treatment in an atmosphere containing oxygen, This is because the defect level in the energy gap caused by oxygen vacancies can be reduced. .

[0099] The inert gas atmosphere is nitrogen or a rare gas (helium, neon, argon, etc.). It is desirable to use an atmosphere containing ) as the main component and not containing water, hydrogen, etc. For example, nitrogen and rare gases such as helium, neon, and argon introduced into a heat treatment device Purity should be 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher ( That is, the impurity concentration is set to 1 ppm or less, preferably 0.1 ppm or less.

[0100] In either case, the first heat treatment reduces impurities and produces an i-type (intrinsic semiconductor) or i-type By forming an oxide semiconductor layer that is as close to the original thickness as possible, a transistor with extremely excellent characteristics can be realized. It can be realized.

[0101] By the way, the above-mentioned heat treatment (first heat treatment) has the effect of removing hydrogen, water, etc. This heat treatment can also be called a dehydration treatment or a dehydrogenation treatment. The dehydrogenation treatment is performed after the formation of an oxide semiconductor layer, after the formation of a gate insulating layer, or after the formation of a gate electrode. It is also possible to carry out the dehydration treatment at a timing such as after the dehydration treatment. The hydrogenation treatment may be carried out not only once but also multiple times.

[0102] The oxide semiconductor layer may be etched either before or after the heat treatment. From the viewpoint of miniaturization of elements, it is preferable to use dry etching. However, wet etching may also be used. The thickness can be appropriately selected depending on the material to be etched. If this does not pose a problem, the oxide semiconductor layer may be used without being processed into an island shape.

[0103] Next, a gate insulating layer 146 is formed in contact with the oxide semiconductor layer 144, and then a gate insulating layer 146 is formed. A gate electrode 148a is formed over the layer 146 in a region overlapping with the oxide semiconductor layer 144. Then, an electrode 148b is formed in a region overlapping with the source or drain electrode 142a (FIG. 4(D)).

[0104] The gate insulating layer 146 can be formed by using a CVD method, a sputtering method, or the like. The gate insulating layer 146 may be made of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like. tantalum oxide, hafnium oxide, yttrium oxide, hafnium silicate (HfS i x O y (x>0, y>0)), nitrogen-doped hafnium silicate (HfSi x O y (x>0, y>0)), nitrogen-doped hafnium aluminate (HfAl x O y ( Preferably, the gate insulating layer 146 is formed so as to include x>0, y>0). The thickness of the layer may be either a single layer or a multilayer structure. However, when miniaturizing semiconductor devices, the thickness must be reduced to ensure the operation of the transistor. For example, when silicon oxide is used, the thickness is preferably 1 nm or more and 100 nm or less. Alternatively, it can be 10 nm or more and 50 nm or less.

[0105] As mentioned above, when the gate insulating layer is made thin, the gate leakage caused by the tunnel effect etc. To solve the gate leakage problem, the gate insulating layer 146 is doped with hafnium oxide. tantalum oxide, yttrium oxide, hafnium silicate (HfSi x O y (x>0 , y>0), nitrogen-doped hafnium silicate (HfSi x O y (x>0, y> 0)), nitrogen-doped hafnium aluminate (HfAl x O y (x>0, y>0) It is recommended to use high-k materials such as By using the insulating layer 146, a film is formed to suppress gate leakage while maintaining electrical properties. It is possible to increase the thickness. Silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, etc. Alternatively, the film may have a laminated structure with a film containing the above.

[0106] After the gate insulating layer 146 is formed, a second thermal treatment is performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is 200°C or higher and 450°C or lower, preferably 25 The temperature is between 0°C and 350°C. For example, heat treatment can be performed at 250°C for 1 hour in a nitrogen atmosphere. By performing the second heat treatment, the variation in the electrical characteristics of the transistors can be reduced. When the gate insulating layer 146 contains oxygen, the oxide semiconductor layer 144 Oxygen is supplied to the oxide semiconductor layer 144 to compensate for oxygen vacancies in the oxide semiconductor layer 144, thereby forming an i-type (intrinsic) or Alternatively, an oxide semiconductor layer that is as close to i-type as possible can be formed.

[0107] In this embodiment, the second heat treatment is performed after the gate insulating layer 146 is formed. The timing of the second heat treatment is not limited to this. For example, the second heat treatment may be performed after the formation of the gate electrode. A heat treatment may be performed. In addition, a second heat treatment may be performed after the first heat treatment, or The first heat treatment may also serve as the second heat treatment, or the second heat treatment may also serve as the first heat treatment. It's okay to do that.

[0108] As described above, by applying at least one of the first heat treatment and the second heat treatment, the oxide The semiconductor layer 144 is highly purified so that it contains as few impurities as possible other than its main components. can.

[0109] The gate electrode 148a and the electrode 148b are formed by forming a conductive layer on the gate insulating layer 146. The gate electrode can be formed by selectively etching the conductive layer. The conductive layers that become the electrodes 148a and 148b can be formed by PVD methods such as sputtering, It can be formed by using a CVD method such as a plasma CVD method. The same applies to the case of the drain electrode 142a, etc., and the descriptions therefor can be taken into consideration.

[0110] Next, an insulating layer 15 is formed on the gate insulating layer 146, the gate electrode 148a, and the electrode 148b. 5A. The insulating layer 150 and the insulating layer 152 are formed. can be formed by using a PVD method, a CVD method, etc. Also, silicon oxide, oxynitride, etc. Inorganic insulating materials such as silicon dioxide, silicon nitride, hafnium oxide, and aluminum oxide It can be formed using materials.

[0111] The insulating layer 150 and the insulating layer 152 may be made of a material with a low dielectric constant or a structure with a low dielectric constant (porous It is desirable to use a structure with low dielectric constants for the insulating layer 150 and the insulating layer 152. This reduces the capacitance that occurs between wiring and electrodes, making it possible to speed up operation. This is because

[0112] In this embodiment, the insulating layer 150 and the insulating layer 152 are stacked. The present invention is not limited to this embodiment. It may be a single layer or a laminated structure of two or more layers. It is also possible to have a configuration in which no insulating layer is provided.

[0113] It is desirable that the insulating layer 152 be formed so that its surface is flat. By forming the insulating layer 152 so that the surface is flat, it is possible to This is because electrodes, wiring, and the like can be suitably formed on the insulating layer 152. The insulating layer 152 is planarized using a method such as CMP (chemical mechanical polishing). It is possible.

[0114] Next, a source electrode or a drain electrode is formed on the gate insulating layer 146, the insulating layer 150, and the insulating layer 152. An opening is formed that reaches the electrode 142b (see FIG. 5(B)). This is done by selective etching using a metal such as a silicon dioxide.

[0115] Here, it is desirable that the opening be formed in a region that overlaps with the electrode 126. By forming openings in the appropriate areas, the increase in element area due to the electrode contact area is suppressed. In other words, the degree of integration of the semiconductor device can be increased.

[0116] Thereafter, an electrode 154 is formed in the opening, and a wiring 15 in contact with the electrode 154 is formed on the insulating layer 152. 6 is formed (see FIG. 5(C)).

[0117] The electrode 154 is formed by forming a conductive layer in the region including the opening using, for example, a PVD method or a CVD method. Then, a part of the conductive layer is removed by a method such as etching or CMP. It can be formed by the following.

[0118] More specifically, for example, a thin titanium film is formed in the area including the opening by the PVD method, and then CV After forming a thin titanium nitride film by the D method, a tungsten film is formed to fill the opening. Here, the titanium film formed by the PVD method is The oxide film (such as the native oxide film) on the surface is reduced, and the lower electrode (here, the source electrode or It has the function of reducing the contact resistance with the drain electrode 142b. The titanium nitride film has a barrier function that suppresses the diffusion of conductive materials. After forming a barrier film such as titanium nitride film, a copper film may be formed by plating. stomach.

[0119] When forming the electrode 154 by removing a part of the conductive layer, the surface of the electrode 154 becomes flat. For example, a thin titanium film or titanium nitride film is formed in the area including the opening. When a tungsten film is formed so as to fill the opening after the formation of the tungsten film, By MP treatment, unnecessary tungsten film, titanium film, titanium nitride film, etc. are removed. In this way, the surface including the electrode 154 can be made flat. By flattening the surface, it is possible to form good electrodes, wiring, insulating layers, semiconductor layers, etc. in subsequent processes. It becomes possible to form.

[0120] The wiring 156 is formed by a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. After forming a conductive layer using the above, the conductive layer is patterned to form the conductive layer. The conductive layer may be made of aluminum, chromium, copper, tantalum, titanium, or molybdenum. It is possible to use an element selected from the group consisting of tungsten and tungsten, or an alloy containing the above-mentioned elements. Manganese, magnesium, zirconium, beryllium, neodymium, scandium The source electrode may be made of any one of the following materials or a combination of these materials. Or it is similar to the drain electrode 142a.

[0121] As a result of the above, the transistor 162 including the highly purified oxide semiconductor layer 144 and The capacitor element 164 is completed (see FIG. 5C).

[0122] In the transistor 162 described in this embodiment, the oxide semiconductor layer 144 is highly purified. Therefore, the hydrogen concentration is 5×10 19 atoms / cm 3 Below, preferably 5x 10 18 atoms / cm 3 Less than or equal to 5×10 17 atoms / cm 3 below The carrier density of the oxide semiconductor layer 144 is 100% of that of a general silicon wafer (phosphor The carrier density ( 1×10 14 / cm 3 A sufficiently small value (e.g., 1×10 12 / cm 3 less than 1.45 x 10 10 / cm 3 (less than 100%). For example, the off-state current of the transistor 162 at room temperature (25° C.) is The current (here, the value per unit channel width (1 μm)) is 100 zA (1 zA (Zep amperes) is 1 x 10 -21 A) or less, preferably 10zA or less.

[0123] By using the oxide semiconductor layer 144 that has been highly purified and made intrinsic, The off-state current of the transistor can be sufficiently reduced. This makes it possible to obtain a semiconductor device that can retain stored data for an extremely long period of time.

[0124] In addition, by forming the electrode 126 and the electrode 154 so as to overlap each other, the contact area of the electrodes This suppresses the increase in element area due to the region, and realizes even higher integration. In the semiconductor device shown in this embodiment, it is possible to share wiring, and the degree of integration is sufficient. Therefore, a semiconductor device with a significantly improved performance can be realized.

[0125] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0126] (Embodiment 2) In this embodiment, a structure of a semiconductor device according to another embodiment of the disclosed invention and a manufacturing method thereof will be described. The method will be described with reference to FIGS.

[0127] <Cross-sectional and planar configurations of semiconductor device> 6A and 6B show an example of the configuration of a semiconductor device according to this embodiment. FIG. 6(A) shows a cross section of the device, and FIG. 6(B) shows a plan view of the semiconductor device. ) corresponds to the cross section taken along lines C1-C2 and D1-D2 in FIG. 6(B). The semiconductor device shown in FIG. 6B has a transistor using the first semiconductor material in the lower part. 560 and a transistor 562 made of a second semiconductor material on top. Here, it is desirable that the first semiconductor material and the second semiconductor material are different materials. For example, the first semiconductor material may be a material other than an oxide semiconductor (such as silicon), and the second semiconductor may be a material other than an oxide semiconductor (such as silicon). The transistor material can be an oxide semiconductor. On the other hand, transistors using oxide semiconductors have the following drawbacks: Its characteristics allow it to retain charge for a long period of time.

[0128] It should be noted that the above transistors are all n-channel transistors. However, it goes without saying that a p-channel transistor can also be used. The technical essence of the invention is to develop a semiconductor device that can sufficiently reduce the off-state current, such as an oxide semiconductor, to retain data. The advantage of using a material that can be reduced to a low level for the transistor 562 is that it can be used in a semiconductor device. The specific configuration of the semiconductor device, such as the materials used and the structure of the semiconductor device, is shown here. There is no need to limit it.

[0129] The transistor 560 in FIG. 6 is a channel provided in a semiconductor layer on a base wafer 500. A channel forming region 526 and impurity regions 52 provided to sandwich the channel forming region 526 8, a gate insulating layer 522a provided on the channel forming region 526, and a gate insulating layer 5 6 and a gate electrode 524a provided on the transistor 22a. One difference between transistor 560 and transistor 160 in FIG. 1 is the channel The difference lies in whether the hole formation region is formed in the semiconductor layer on the base substrate 500. The difference is whether a silicon substrate is used or an SOI substrate is used. In practice, there are cases where the semiconductor device does not have a source electrode or a drain electrode, but for convenience, this is included. Sometimes they are simply called transistors.

[0130] An electrode 530 is connected to a part of the impurity region 528 of the transistor. The electrode 530 functions as a source electrode and a drain electrode of the transistor 560. Insulating layers 532 and 534 are provided to cover the transistor 560. In order to achieve high integration, the transistor 560 is formed on the sidewall as shown in FIG. It is preferable to use a structure without an insulating layer. In this case, a sidewall insulating layer is provided on the side surface of the gate electrode 524a, and the impurity concentration is An impurity region 528 including a region such as

[0131] Transistor 562 in FIG. 6 is similar to transistor 162 in FIG. That is, the transistor 562 in FIG. 6 has a source electrode or a drain electrode provided on the insulating layer 534. a source or drain electrode 542a, and a source or drain electrode 542b; and a source or drain electrode 542b. the oxide semiconductor layer 544 connected to the source or drain electrode 542a, A gate insulating layer 546 covers the source or drain electrode 542b and the oxide semiconductor layer 544. A gate electrode layer 546 is provided over the gate insulating layer 546 to overlap with the oxide semiconductor layer 544. The electrode 548a and the source or drain electrode 542a and the oxide semiconductor layer 544 , an insulating layer 543a provided in a region overlapping with the gate electrode 548a, and a source electrode or A portion between the drain electrode 542b and the oxide semiconductor layer 544, overlapping with the gate electrode 548a, and an insulating layer 543b provided in the source or drain electrode. In order to reduce the capacitance between the gate electrode and the insulating layer 543a and the insulating layer 543b, Although it is desirable to provide the insulating layer 543a and the insulating layer 543b, it is also possible to provide neither the insulating layer 543a nor the insulating layer 543b. For other details, the above-described embodiment can be referred to.

[0132] 6 is the same as the capacitance element 164 in FIG. That is, the capacitance element 564 in FIG. 6 includes a source electrode or a drain electrode 542a, an oxide It is composed of a semiconductor layer 544, a gate insulating layer 546, and an electrode 548b. The source or drain electrode 542a functions as one electrode of the capacitor 564. The electrode 548b serves as the other electrode of the capacitor 564. The above embodiment can be referred to for this.

[0133] An insulating layer 550 is provided over the transistor 562 and the capacitor 564. An insulating layer 552 is provided on the top, and a gate insulating layer 546, an insulating layer 550, an insulating layer 552, etc. An electrode 554 is provided in an opening formed in the insulating layer 552, and a wiring connected to the electrode 554 is provided on the insulating layer 552. The line 556 is provided in the same manner as in FIG.

[0134] <Method for manufacturing SOI substrate> Next, an example of a method for manufacturing an SOI substrate used in manufacturing the above semiconductor device will be described with reference to FIG. Please refer to the following for explanation.

[0135] First, a base substrate 500 is prepared (see FIG. 7A). A substrate made of an insulating material can be used. Specifically, aluminosilicate glass, aluminum Various glasses used in the electronics industry, such as borosilicate glass and barium borosilicate glass Examples of substrates include silicon substrates, quartz substrates, ceramic substrates, and sapphire substrates. and a ceramic substrate with a thermal expansion coefficient close to that of silicon, mainly composed of aluminum oxide. Good too.

[0136] The base substrate 500 may be a semiconductor substrate such as a single crystal silicon substrate or a single crystal germanium substrate. When a semiconductor substrate is used as the base substrate 500, a glass substrate is used. Compared to using a substrate, the temperature conditions for heat treatment are more mitigated, making it possible to obtain high-quality SOI substrates. Here, the semiconductor substrate is solar cell grade silicon (SOG-Si A solar grade silicon substrate may also be used. A conductive substrate may also be used. When using solar cell grade silicon or polycrystalline semiconductor substrate, This allows for lower manufacturing costs compared to using a single crystal silicon substrate. do.

[0137] In this embodiment mode, a case where a glass substrate is used as the base substrate 500 will be described. By using an inexpensive glass substrate that can be made large-area as the base substrate 500, low cost It is possible to achieve this.

[0138] It is preferable that the surface of the base substrate 500 be cleaned in advance. Specifically, the base substrate 500 is treated with a mixture of hydrochloric acid and hydrogen peroxide (HPM), sulfuric acid, and hydrogen peroxide. Hydrogen peroxide solution mixture (SPM), ammonia hydrogen peroxide solution mixture (APM), dilute hydrofluoric acid (DHF), FPM (a mixture of hydrofluoric acid, hydrogen peroxide, and pure water), etc. By carrying out such a cleaning process, the flatness of the surface of the base substrate 500 can be improved and the base This allows removal of abrasive particles remaining on the surface of the base substrate 500, etc.

[0139] Next, a nitrogen-containing layer 502 (for example, a silicon nitride film (SiN x ) and silicon oxynitride film (SiN x O y ) (x>y) and other nitrogen-containing insulating films The nitrogen-containing layer 502 is formed by a CVD method, a sputtering method, or the like (see FIG. 7B). It can be formed using the above.

[0140] The nitrogen-containing layer 502 formed in this embodiment is formed by bonding a single-crystal semiconductor layer to the nitrogen-containing layer 502 later. The nitrogen-containing layer 502 is a layer (bonding layer) for bonding the nitrogen-containing layer 502 to the sodium contained in the base substrate. It also acts as a barrier layer to prevent impurities such as sodium from diffusing into the single-crystal semiconductor layer. It works.

[0141] As described above, in this embodiment, the nitrogen-containing layer 502 is used as a bonding layer. It is preferable to form the nitrogen-containing layer 502 so that the surface has a predetermined flatness. , the average surface roughness (Ra, also known as the arithmetic mean roughness) is 0.5 nm or less, and the root mean square roughness ( Rms) is 0.60 nm or less, more preferably, the average surface roughness is 0.35 nm or less, The nitrogen-containing layer 502 is formed so that the average roughness is 0.45 nm or less. For surface roughness and root mean square roughness, values measured in an area of 10 μm x 10 μm are used. The film thickness is 10 nm or more and 200 nm or less, preferably 50 nm or more and 10 In this way, by increasing the flatness of the surface, it is possible to Poor bonding of the layers can be prevented.

[0142] Next, a bond substrate is prepared. Here, a single crystal semiconductor substrate 510 is used as the bond substrate. (See FIG. 7(C)). In this example, a single crystal substrate is used as the bond substrate. The crystallinity of the bond substrate does not need to be limited to single crystal.

[0143] The single crystal semiconductor substrate 510 may be, for example, a single crystal silicon substrate or a single crystal germanium-based A single crystal semiconductor substrate made of a group 14 element, such as a single crystal silicon germanium substrate, is used. In addition, compound semiconductor substrates such as gallium arsenide and indium phosphide can be used. Commercially available silicon substrates are 5 inch (approximately 125 mm) in diameter and 6 inch (approximately 125 mm) in diameter. (approx. 150 mm), 8 inch diameter (approx. 200 mm), 12 inch diameter (approx. 300 mm) The typical size is a circle with a diameter of 16 inches (about 400 mm). The shape of the conductive substrate 510 is not limited to a circle, but may be, for example, a rectangle or the like. The single crystal semiconductor substrate 510 can be grown by a CZ (Czochralski) method or an FZ (floating zone) method. It can be produced using the zone method.

[0144] An oxide film 512 is formed on the surface of the single crystal semiconductor substrate 510 (see FIG. 7(D)). From the viewpoint of removing contaminants, before forming the oxide film 512, a hydrochloric acid hydrogen peroxide solution (HPM) , sulfuric acid hydrogen peroxide solution mixture (SPM), ammonia hydrogen peroxide solution mixture (APM), Single crystals are grown using dilute hydrofluoric acid (DHF), FPM (a mixture of hydrofluoric acid, hydrogen peroxide, and pure water), etc. It is preferable to clean the surface of the semiconductor substrate 510. You can take it out and wash it.

[0145] The oxide film 512 is, for example, a single layer of a silicon oxide film, a silicon oxynitride film, or the like, or a laminated layer. The oxide film 512 can be formed by a method such as thermal oxidation, CVD, or the like. In addition, when the oxide film 512 is formed by the CVD method, To achieve good bonding, tetraethoxysilane (abbreviated as TEOS) is used. It is preferred to form a silicon oxide film using an organosilane such as Si(OC2H5)4). It's nice.

[0146] In this embodiment, the single crystal semiconductor substrate 510 is subjected to thermal oxidation treatment to form an oxide film 512 (Here, SiO x Thermal oxidation is performed by adding halogen to an oxidizing atmosphere. It is preferable to carry out the above steps.

[0147] For example, the single crystal semiconductor substrate 510 is subjected to thermal oxidation in an oxidizing atmosphere containing chlorine (Cl). By carrying out this process, an oxide film 512 that has been oxidized with chlorine can be formed. The oxide film 512 becomes a film containing chlorine atoms. Captures pure heavy metals (e.g., Fe, Cr, Ni, Mo, etc.) and forms metal chlorides By removing the etched portion to the outside, contamination of the single crystal semiconductor substrate 510 can be reduced. After bonding with the base substrate 500, impurities such as Na from the base substrate are fixed. Therefore, contamination of the single crystal semiconductor substrate 510 can be prevented.

[0148] The halogen atoms contained in the oxide film 512 are not limited to chlorine atoms. The surface of the single crystal semiconductor substrate 510 may be fluorine-oxidized. For example, immersion in a HF solution followed by thermal oxidation in an oxidizing atmosphere is used. There is a method in which the material is added to an oxidizing atmosphere and subjected to thermal oxidation treatment.

[0149] Next, ions are accelerated by an electric field and irradiated onto the single crystal semiconductor substrate 510. An embrittlement region 514 in which the crystal structure is damaged is formed at a predetermined depth in the crystalline semiconductor substrate 510 (FIG. 7). (See (E)).

[0150] The depth of the region where the embrittlement region 514 is formed depends on the kinetic energy, mass and charge of the ions, and the The embrittlement region 514 can be adjusted by adjusting the incident angle of the ions. It is formed in a region with a depth almost equal to the penetration depth. The thickness of the single-crystal semiconductor layer separated from the single-crystal semiconductor substrate 510 can be adjusted. For example, the thickness of the single crystal semiconductor layer is 10 nm or more and 500 nm or less, preferably 50 nm or more and 200 nm or less. The average penetration depth may be adjusted to about 00 nm or less.

[0151] The ion irradiation process can be performed using an ion doping device or an ion implantation device. A typical example of an ion doping device is a device that uses plasma generated by exciting a process gas. There is a non-mass separation type device in which all the ion species generated are irradiated onto the object to be processed. The ion species in the plasma are irradiated onto the object to be processed without being mass-separated. The ion implanter is a mass separation type device. In the ion implanter, the ion species in the plasma The ions are mass-separated, and the object to be processed is irradiated with ion species having a specific mass.

[0152] In this embodiment mode, hydrogen is added to the single crystal semiconductor substrate 510 using an ion doping apparatus. A gas containing hydrogen is used as the source gas. Regarding the H3 + It is better to increase the ratio of H + , H2 + , H3 + Total of H3 for the amount + The ratio of is set to 50% or more (more preferably 80% or more). H3 + By increasing the ratio, the efficiency of ion irradiation can be improved.

[0153] The ions to be added are not limited to hydrogen, and ions such as helium ions may also be added. The type of ions to be added is not limited to one type, and multiple types of ions may be added. For example, when hydrogen and helium are irradiated simultaneously using an ion doping device, different The number of steps can be reduced compared to when irradiation is performed in a single step, and the single crystal semiconductor It is possible to suppress the surface roughness of the layer.

[0154] When the embrittlement region 514 is formed using an ion doping apparatus, heavy metals are also simultaneously doped. However, the ions are irradiated through the oxide film 512 containing halogen atoms. By performing irradiation, contamination of the single crystal semiconductor substrate 510 by these heavy metals can be prevented. can.

[0155] Next, the base substrate 500 and the single-crystal semiconductor substrate 510 are placed opposite to each other, and the nitrogen-containing layer 502 is The surface is brought into close contact with the oxide film 512. This allows the base substrate 500 and the single-crystal semiconductor substrate The plate 510 is attached to the substrate 510 (see FIG. 7(F)).

[0156] When bonding, a 0. 001N / cm 2 More than 100N / cm 2 For example, 1N / cm2 More than 20N / cm 2 It is recommended to apply the following pressure. By applying pressure, the bonding surfaces will come closer and become tightly attached. At the contacted portion, the nitrogen-containing layer 502 and the oxide film 512 are bonded together, and the nitrogen-containing layer 502 and the oxide film 512 are bonded together. The spontaneous bonding occurs over almost the entire surface. This bonding is caused by van der Waals forces and hydrogen The bond is active and can be carried out at room temperature.

[0157] Before the single crystal semiconductor substrate 510 and the base substrate 500 are bonded to each other, It is preferable to perform a surface treatment on the surface of the single crystal semiconductor. The bonding strength at the interface between the main substrate 510 and the base substrate 500 can be improved.

[0158] Surface treatment can be wet treatment, dry treatment, or a combination of wet and dry treatment. Also, different wet treatments can be used in combination. Alternatively, different dry processes may be used in combination.

[0159] After bonding, a heat treatment may be carried out to increase the bonding strength. The treatment temperature is a temperature at which separation does not occur in the embrittlement region 514 (for example, a temperature above room temperature and 400°C). The nitrogen-containing layer 502 and the oxide film 512 are heated in this temperature range. The heat treatment may be carried out in a heating furnace such as a diffusion furnace or a resistance heating furnace, or in an RTA (instantaneous thermal annealing) furnace. Thermal annealing, Rapid Thermal Anneal equipment, microwave heating equipment, etc. The above temperature conditions are merely examples and may be used in the present invention. This is not to be construed as limiting one embodiment.

[0160] Next, heat treatment is performed to separate the single crystal semiconductor substrate 510 at the embrittlement region. A single-crystal semiconductor layer 502 is formed on a base substrate 500 via a nitrogen-containing layer 502 and an oxide film 512. 16 (see FIG. 7(G)).

[0161] It is desirable that the heat treatment temperature during the separation be as low as possible. This is because the lower the actual temperature is, the more the surface roughness of the single crystal semiconductor layer 516 can be suppressed. For example, the heat treatment temperature during the separation may be set to 300°C or higher and 600°C or lower. A temperature of 400°C or higher and 500°C or lower is more effective.

[0162] After the single crystal semiconductor substrate 510 is separated, the single crystal semiconductor layer 516 is Heat treatment is performed at a temperature of 0° C. or higher to reduce the concentration of hydrogen remaining in the single crystal semiconductor layer 516. It may be possible.

[0163] Next, the surface of the single crystal semiconductor layer 516 is irradiated with laser light to improve the flatness of the surface. A single crystal semiconductor layer 518 having improved conductivity and reduced defects is formed (see FIG. 7(H)). ) Note that heat treatment may be performed instead of the laser light irradiation treatment.

[0164] In this embodiment mode, immediately after the heat treatment for separating the single crystal semiconductor layer 516, However, one embodiment of the disclosed invention should not be construed as being limited thereto. After the heat treatment for separating the single crystal semiconductor layer 516, etching treatment is performed to separate the single crystal semiconductor layer 516. After removing the area with many defects on the surface of the conductor layer 516, the laser light irradiation treatment may be performed. Alternatively, the laser irradiation treatment is performed after improving the flatness of the surface of the single crystal semiconductor layer 516. The etching process may be wet etching or dry etching. In this embodiment, the laser beam is used as described above. After the irradiation, a thinning step may be performed to reduce the thickness of the single crystal semiconductor layer 516. The thinning of the crystalline semiconductor layer 516 can be achieved by dry etching or wet etching. Or both may be used.

[0165] Through the above steps, an SOI substrate having a single-crystal semiconductor layer 518 with good characteristics can be obtained. This is possible (see Figure 7(H)).

[0166] <Method for manufacturing semiconductor device> Next, a method for manufacturing a semiconductor device using the above-described SOI substrate, particularly, a method for manufacturing the transistor 560 will be described. The manufacturing method will be described with reference to FIG. 8. FIG. 8 shows the S manufactured by the method shown in FIG. This is a method for producing a semiconductor device using a part of an OI substrate.

[0167] First, the single crystal semiconductor layer 518 is processed into an island shape to form a semiconductor layer 520 (FIG. 8(A) Before and after this process, in order to control the threshold voltage of the transistor, The semiconductor layer is doped with impurity elements that give n-type conductivity or impurity elements that give p-type conductivity. When the semiconductor is silicon, it can be added as an impurity element to give n-type conductivity. For example, phosphorus or arsenic can be used as the impurity for imparting p-type conductivity. Examples of the metal element that can be used include boron, aluminum, and gallium.

[0168] Next, an insulating layer 522 is formed to cover the semiconductor layer 520, and at least A conductive layer 524 is formed in a region overlapping with the semiconductor layer 520 (see FIG. 8B).

[0169] The insulating layer 522 will later become a gate insulating layer. The insulating layer 522 is, for example, a semiconductor It can be formed by heat treatment (thermal oxidation treatment, thermal nitridation treatment, etc.) of the surface of layer 520. Instead of the heat treatment, a high density plasma treatment may be applied. , rare gases such as He, Ar, Kr, and Xe, oxygen, nitrogen oxide, ammonia, nitrogen, hydrogen, etc. Of course, CVD and sputtering methods can also be used. The insulating layer may be formed by a deposition method or the like. The insulating layer may be formed of silicon oxide or silicon oxynitride. , silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, yttrium oxide , hafnium silicate (HfSi x O y (x>0, y>0)), nitrogen-doped Huff HfSi x O y (x>0, y>0)), nitrogen-doped hafnium Aluminate (HfAl x O y (x>0, y>0)) and a single layer structure or a laminated structure The thickness of the insulating layer is preferably, for example, 1 nm or more and 100 nm or less. Alternatively, the thickness can be set to 10 nm or more and 50 nm or less. In this case, an insulating layer containing silicon oxide is formed as a single layer.

[0170] The conductive layer 524 will later become a gate electrode. The conductive layer 524 is made of aluminum or copper. The insulating layer 11 can be formed using a metal material such as titanium, tantalum, or tungsten. A layer containing a conductive material may be formed using a semiconductor material such as polycrystalline silicon. The method is not particularly limited, and various methods such as vapor deposition, CVD, sputtering, and spin coating can be used. In this embodiment, the layer containing the conductive material is formed by a metal film forming method. An example of forming the material is shown below.

[0171] Next, the insulating layer 522 and the conductive layer 524 are selectively etched to remove the upper surface of the semiconductor layer 520. On the other hand, a gate insulating layer 522a and a gate electrode 524a are formed (see FIG. 8C). For this etching, dry etching is preferably used, but wet etching is also suitable. The etching gas and etching solution are selected depending on the material to be etched. You can choose as you like.

[0172] Next, using the gate electrode 524a as a mask, an impurity element that imparts one conductivity type is introduced into the semiconductor layer 5 20 to form a channel forming region 526 and an impurity region 528 (FIG. 8(D) )). In this case, phosphorus (P) and arsenic (A) are used to form n-type transistors. s), but when forming a p-type transistor, boron (B) or aluminum The concentration of the added impurity element can be set appropriately. After the impurity element is added, a heat treatment is performed for activation. .

[0173] When the semiconductor layer 520 is made of a material containing silicon, the source region and the drain region To further reduce the resistance of the region, a portion of the semiconductor layer 520 is silicided. The silicide region may be formed by contacting a metal with a semiconductor layer and then performing a heat treatment. (For example, GRTA method, LRTA method, laser light irradiation, etc.) The silicide is formed by reacting silicide with metal. For example, cobalt silicide or nickel silicide is used. If the semiconductor layer 520 is thin, the bottom of the semiconductor layer 520 may be formed as a silicide. The silicidation reaction may proceed up to the portion. In addition to cobalt and nickel, titanium, tungsten, molybdenum, zirconium, Examples include fluorine, tantalum, vanadium, neodymium, chromium, platinum, and palladium. can be done.

[0174] Next, an electrode 530 is formed in a region in contact with a part of the impurity region 528, and then the formed Insulating layers 532 and 534 are formed to cover the above components (see FIG. 8(E)).

[0175] The electrode 530 is formed by, for example, forming a layer containing a conductive material and then selectively etching the layer. The conductive material layer is formed by applying a conductive material such as aluminum, copper, titanium, tantalum, or tantalum. It can be formed by using a metal material such as tungsten. A layer containing a conductive material may be formed using a conductive material. Various film formation methods such as deposition, CVD, sputtering, and spin coating can be used. can.

[0176] After the insulating layers 532 and 534 are formed, the electrode 530 is An opening is formed in the insulating layer 534 so as to reach the impurity region 528, and a conductive layer is formed in the insulating layer 534 so as to fill the opening. It is also possible to form it as follows.

[0177] The insulating layer 532 and the insulating layer 534 may be made of silicon oxide, silicon oxynitride, silicon nitride, or silicon oxide. The insulating layer 5 can be formed using a material containing an inorganic insulating material such as aluminum. By using a low-k material for the insulating layer 534 and the insulating layer 532, various electrodes and wiring This is preferable because it is possible to sufficiently reduce the capacitance caused by the overlap of the insulating layer. Porous insulating layers using these materials may be used for the insulating layer 532 and the insulating layer 534. In a porous insulating layer, the dielectric constant is lower than in a dense insulating layer, so there is no risk of damage to the electrodes or wiring. Furthermore, the insulating layer 532 and the insulating layer 534 are It is also possible to form the insulating layer using an organic insulating material such as polyimide or acrylic. In the example shown in FIG. 1, the insulating layer 532 and the insulating layer 534 are stacked. The present invention is not limited to the above, and may be a single layer or a laminated structure of two or more layers.

[0178] Through the above steps, a transistor 560 using an SOI substrate is formed (see FIG. 8E). The transistor 560 using a material other than an oxide semiconductor can operate at high speed. By using this transistor as a read transistor, the read operation can be performed at high speed. In addition, the transistor 560 can be used to implement other logic circuits (also known as arithmetic circuits). It is also possible to configure the following:

[0179] Thereafter, the insulating layer 532 and the insulating layer 534 are subjected to CMP processing to form the gate electrode 524a and The upper surface of the electrode 530 is exposed (not shown). In addition to CMP, etching can also be used to expose the top surface. It is possible to combine etching and CMP processes. In order to improve the characteristics of the transistor 562 to be formed, the surface of the insulating layer 532 or the insulating layer 534 is It is desirable to keep the surface as flat as possible.

[0180] Before and after each of the above steps, further steps may be performed to form electrodes, wiring, semiconductor layers, insulating layers, etc. For example, the wiring structure may be a laminated structure of an insulating layer and a conductive layer. It is also possible to realize a highly integrated semiconductor device by adopting a multi-layer wiring structure.

[0181] Then, the transistor 562 and the capacitor 56 4 is formed (see FIG. 6A). Since this is the same as the case of the transistor 162 and the capacitance element 164, it will not be explained here. For details of the manufacturing method, the above embodiment can be referred to.

[0182] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0183] (Embodiment 3) In this embodiment, a structure of a semiconductor device according to another embodiment of the disclosed invention and a manufacturing method thereof will be described. The method will be described with reference to FIGS.

[0184] <Cross-sectional and planar configurations of semiconductor device> 9A and 9B are diagrams showing an example of the configuration of a semiconductor device according to this embodiment. 9(A) shows a cross section of the device, and FIG. 9(B) shows a plan view of the semiconductor device. ) corresponds to the cross section taken along lines E1-E2 and F1-F2 in FIG. 9(B). 9B has a first insulating film at the bottom, similar to the semiconductor device shown in FIG. A transistor 560 made of one semiconductor material is provided on top of a transistor made of a second semiconductor material. The first semiconductor material and the second semiconductor material are For example, the first semiconductor material may be a material other than an oxide semiconductor. The first semiconductor material can be a semiconductor (e.g., silicon) and the second semiconductor material can be an oxide semiconductor. Transistors using semiconductor materials other than conductors can easily operate at high speeds. The characteristics of a transistor using a conductor enable it to retain charge for a long period of time.

[0185] One of the differences between the semiconductor device in FIG. 9 and the semiconductor device in FIG. 6 is the transistor 560 The semiconductor device in FIG. An electrode 530 is formed in the region in contact with a part of the transistor The impurity region 528 of 560 and the source or drain electrode of the upper transistor 562 9. The upper transistor 542b is electrically connected to the semiconductor device shown in FIG. The source electrode or drain electrode 542b of the lower transistor 560 is directly connected to the The impurity region 528 is in contact with the impurity region 528.

[0186] Another difference between the semiconductor device in FIG. 9 and the semiconductor device in FIG. 6 is that the transistor The semiconductor device in FIG. An electrode 554 is formed in contact with the drain electrode 542b, and the transfer electrode 542 is connected to the drain electrode 542b. The source electrode or drain electrode 542b of the transistor 562 and the wiring 556 are electrically connected. 9, the wiring 556 is directly connected to the transistor 562. The source electrode or drain electrode 542b is in contact with the transistor 5 in FIG. 62 and the source or drain electrode 542b of the transistor 560. In other words, the electrode 530 that functions as the rain electrode is the same as the electrode 530. .

[0187] 9, the source or drain electrode 542b and the The region in contact with either the source region or the drain region is the source electrode or the drain electrode. The area where 542b and the wiring 556 connecting one memory cell to another memory cell contact each other. By adopting this layout, high integration can be achieved. .

[0188] 9 is the same as the transistor 560 in FIG. 9 is the same as the transistor 562 in FIG. 9 is the same as the capacitance element 564 in FIG. For details, the previous embodiment can be referred to.

[0189] (Method for manufacturing a semiconductor device) The manufacturing method of the semiconductor device shown in FIG. 9, particularly the source electrode or drain electrode of the upper transistor 562 The method for fabricating the rain electrode will be described with reference to FIG. 10. Note that FIG. 10 is similar to the method shown in FIG. This is a method for fabricating a semiconductor device using a part of an SOI substrate fabricated by the above method.

[0190] First, in the same manner as in the steps shown in FIGS. 8A to 8D, a channel The semiconductor layer having the formation region 526 and the impurity region 528, the gate insulating layer 522a and the gate Then, an insulating layer 532, a gate electrode 524a, and a gate electrode 524b are formed to cover the formed components. An insulating layer 534 is deposited to form a transistor 560 .

[0191] Next, the insulating layer 532 and the insulating layer 534 are subjected to CMP treatment to form a gate electrode 524a on the upper surface thereof. The upper surface of the gate electrode 524a is exposed by a process such as C In addition to MP processing, etching processing etc. can also be applied (etching processing etc. (This may be combined with CMP processing.) The characteristics of the transistor 562 to be formed later are To improve the performance, the surfaces of the insulating layer 532 and the insulating layer 534 should be as flat as possible. is desirable.

[0192] Next, the insulating layer 532 and the insulating layer 534 are doped with a material that reaches the impurity region 528 of the transistor 560. The opening is formed by selective etching using a mask or the like. It will be held.

[0193] After that, a conductive layer is formed in the area including the opening by using a PVD method or a CVD method, and then etching is performed. By selectively removing a portion of the conductive layer using a method such as etching or CMP, The source or drain electrode 542a and the source or drain electrode 542b are (See FIG. 10(A)). By forming a conductive layer so as to fill the opening, impurities Region 528 can be in direct contact with source or drain electrode 542b.

[0194] Next, in the same manner as the steps shown in FIGS. 4B to 5A in the first embodiment, the source electrode An insulating layer 543a is formed on the source or drain electrode 542a, and 2b, and then the source electrode or drain electrode 54 2a and the source or drain electrode 542b, and an oxide semiconductor layer 544 provided over the The gate insulating layer 546 is in contact with the oxide semiconductor layer 544. A gate electrode 548a and an electrode 548b are formed on the gate electrode 548a and the electrode 548b. An insulating layer 550 is formed on the insulating layer 552 (see FIG. 10B).

[0195] Thereafter, an insulating layer 552 is formed on the insulating layer 550. The insulating layer 552 is the same as the insulating layer of the first embodiment. The insulating layer 552 can be formed using the same material and film formation method as the insulating layer 152. After the deposition, the insulating layer 552, the insulating layer 550 and the gate insulating layer 546 are connected to a source electrode or a drain electrode. An opening is formed that reaches the inner electrode 542b. The opening is formed by a selection method using a mask or the like. This is done by selective etching.

[0196] After that, a conductive layer is formed in the area including the opening by using a PVD method or a CVD method, and then etching is performed. The etching process is carried out by selectively removing a portion of the conductive layer using a method such as CMP. Thus, wiring 556 is formed.

[0197] Through the above steps, the semiconductor device described in this embodiment mode can be formed. The semiconductor device shown in the figure has a connection between a lower transistor 560 and an upper transistor 562. The connection between the upper transistor 562 and the wiring 556 is formed by forming electrodes. The source electrode or drain electrode 542b of the upper transistor 562 is directly connected to the Since the process is performed in contact with the substrate, the process of forming the electrodes can be omitted. The semiconductor device shown in the embodiment can be manufactured at low cost.

[0198] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0199] (Fourth embodiment) In this embodiment, a circuit configuration and operation of a semiconductor device according to one embodiment of the disclosed invention will be described. This will be described with reference to FIG. 11. Note that in the circuit diagram, To indicate that it is a transistor, the symbol OS may also be added.

[0200] In the semiconductor device shown in FIG. 11(A), the first wiring (1st Line) and the transistor The source electrode of the transistor 160 (or the transistor 560) is electrically connected to the second Line (2nd Line) and the drain of transistor 160 (or transistor 560) The electrodes are electrically connected. The other of the source electrode or the drain electrode of the transistor 162 (or the transistor 562) is The fourth line and the transistor 162 (or the transistor The gate electrode of the transistor 562 is electrically connected to the The gate electrode of transistor 160 (or transistor 560) and the gate electrode of transistor 162 (or transistor One of the source electrode or the drain electrode of the capacitor 164 (or capacitor 562) is connected to the capacitor 164. A fifth line (5th Line) is electrically connected to one of the electrodes of the capacitor element 564. The other electrode of the capacitor 164 (or the capacitor 564) is electrically connected.

[0201] Here, the transistor 162 (or the transistor 562) is, for example, the oxide A transistor using an oxide semiconductor is applied. Therefore, the transistor 162 (or transistor By turning off the transistor 160 (or the transistor 562), 560) can maintain the potential of the gate electrode for an extremely long period of time. By including the capacitor 164 (or the capacitor 564), the transistor 160 (or transistor 560) gate electrode to be easily retained, and , the stored information can be easily read.

[0202] The transistor 160 (or the transistor 560) is not particularly limited. From the viewpoint of improving the speed of reading information, for example, a transistor using single crystal silicon is It is preferable to use a transistor with a high switching speed, such as a transistor.

[0203] As shown in FIG. 11B, the capacitor 164 (or the capacitor 564) is not provided. It is also possible to configure it as follows.

[0204] In the semiconductor device shown in FIG. 11A, the transistor 160 (or the transistor 560) By utilizing the feature that the potential of the gate electrode can be maintained, information can be written as follows: , can be stored and read out.

[0205] First, writing and holding of information will be explained. First, the potential of the fourth wiring is set to The transistor 162 (or the transistor 562) is set to a potential at which it is turned on. The transistor 162 (or the transistor 562) is turned on. The potential is applied to the gate electrode of the transistor 160 (or the transistor 560) and the capacitor That is, the voltage is applied to the transistor 160 (or the capacitor 564). A predetermined charge is applied to the gate electrode of the transistor 560 (write). Now, let us consider two charges that give different potentials (hereafter, the charge that gives the lower potential is called charge Q L , high potential The charge to be given is charge Q H In addition, three different A charge that provides a potential of 100 or more may be applied to increase the storage capacity. The potential of the wiring 4 is turned off by the transistor 162 (or the transistor 562). By setting the potential, the transistor 162 (or the transistor 562) is turned off. As a result, the charge applied to the gate electrode of transistor 160 (or transistor 560) is retained (retained).

[0206] Since the off-state current of the transistor 162 (or the transistor 562) is extremely small, The charge on the gate electrode of transistor 160 (or transistor 560) is maintained for a long time. It will be held.

[0207] Next, the reading of information will be described. In this state, when an appropriate potential (read potential) is applied to the fifth wiring, the transistor 160 (or The second wiring is different depending on the amount of charge held in the gate electrode of the transistor 560. Generally, the transistor 160 (or the transistor 560) is an n-channel Then, the gate electrode of the transistor 160 (or the transistor 560) is connected to Q H is given The apparent threshold V th_H is a transistor 160 (or transistor Q is connected to the gate electrode of the L The apparent threshold V given th_L Yo Here, the apparent threshold voltage is the voltage at which the transistor 160 (or refers to the potential of the fifth wiring required to turn on the transistor 560. Therefore, the potential of the fifth wire is V th_H and V th_L The intermediate potential V0 is By this, the voltage applied to the gate electrode of the transistor 160 (or the transistor 560) For example, in writing, Q H If given, The potential of the wire 5 is V0 (> V th_H ), then transistor 160 (or transistor Q L is given, the potential of the fifth wire is V0( <V th_L ), transistor 160 (or transistor 560) Therefore, by observing the potential of the second wiring, The information can be read out.

[0208] When memory cells are arranged in an array, only the information of the desired memory cell is read. In this way, it is necessary to read the information of a specific memory cell and To prevent the information in other memory cells from being read, a transistor 1 is placed between each memory cell. 60 (or transistor 560) are connected in parallel, The fifth wiring of the memory cell that is not the target of the transistor is turned on regardless of the state of the gate electrode. The potential at which the resistor 160 (or the transistor 560) is in the "off state," i.e., V th_H In addition, a transistor 160 is provided between each memory cell. (or transistor 560) are connected in series, the read pair The fifth wiring of the non-elementary memory cell is connected to the transistor regardless of the state of the gate electrode. The potential at which the transistor 160 (or transistor 560) is in the "ON" state, i.e., V t h_L A larger potential may be applied to the fifth wiring.

[0209] Next, the rewriting of information will be described. That is, the potential of the fourth wiring is applied to the transistor 162 (or the transistor The transistor 162 (or transistor 562) is set to a potential at which it is turned on. This causes the potential of the third wiring (potential related to new information) However, the gate electrode of the transistor 160 (or the transistor 560) and the capacitance element 16 4 (or the capacitor 564). 162 (or transistor 562) to a potential that turns off the transistor 162 (or transistor 562) is turned off, The gate electrode of the transistor 560 is now in a state where a charge related to the new information is given. .

[0210] In this way, the semiconductor device according to the disclosed invention can directly write information again. It is possible to rewrite information. This is why it is necessary for flash memory etc. This eliminates the need to extract charge from the floating gate using a high voltage, and the erase operation In other words, it is possible to suppress the decrease in operating speed caused by the above. It will be revealed.

[0211] The source electrode or drain electrode of the transistor 162 (or the transistor 562) The electrode is electrically connected to the gate electrode of transistor 160 (or transistor 560). By using this, floating gate transistors used as nonvolatile memory elements can be Therefore, in the figure, transistor 16 2 (or transistor 562) and the source or drain electrode of transistor 160 (or the transistor 560) is electrically connected to the gate electrode of the floating It may be called the gate part FG. In this case, the floating gate portion FG can be seen as being buried in an insulator. The floating gate FG holds charge. The off-state current of the transistor 162 (or the transistor 562) is a transistor formed of silicon or the like. Transistor 162 (or transistor 562) It is possible to ignore the loss of charge stored in the floating gate FG due to leakage. That is, the transistor 162 (or the transistor 5) using an oxide semiconductor can be 62) realizes a non-volatile memory device that can retain information even without power supply. It is possible.

[0212] For example, the off-state current of the transistor 162 (or the transistor 562) at room temperature (25° C.) The current is 10zA (1zA (zeptoampere) is 1 x 10 -21 A) or less, and the capacitance element 1 If the capacitance value of 64 (or the capacitance element 564) is about 10 fF, then at least 10 4 It is possible to hold data for more than 10 ... It goes without saying that this will vary depending on the

[0213] In this case, the gate electrode, which has been pointed out in the conventional floating gate type transistor, There is no problem of deterioration of the gate insulating film (tunnel insulating film). This eliminates the degradation of the gate insulating film that occurs when electrons are injected into the floating gate. This means that there is no theoretical limit to the number of times you can write to it. In addition, the conventional floating gate transistor requires The high voltage that was previously required is no longer necessary.

[0214] The semiconductor device shown in FIG. 11A includes elements such as transistors constituting the semiconductor device. It can be considered as including resistance and capacitance as shown in Figure 11(C). In FIG. 11C, the transistor 160 (or the transistor 560) and the capacitor The capacitor 164 (or the capacitor 564) is configured to include a resistor and a capacitor. R1 and C1 are the capacitance elements 164 (or capacitance elements 564), and the resistance value R1 is the resistance and capacitance value of the capacitive element 164 (or the capacitive element 564) and R2 and C2 correspond to the resistance of the insulating layer that constitutes the , the resistance and capacitance values of the transistor 160 (or the transistor 560), and the resistance The value R2 is the gate insulation when transistor 160 (or transistor 560) is in the on state. The capacitance C2 corresponds to the resistance due to the gate electrode and the source electrode. or a capacitance formed between the drain electrode and the gate electrode, and a capacitance formed between the gate electrode and the channel forming region. This corresponds to the capacitance value of the capacitance formed between the

[0215] The source electrode when the transistor 162 (or the transistor 562) is in the off state If the resistance between the drain electrodes (also called the effective resistance) is ROS, then the transistor 162 (or transistor 562) is sufficiently small, R1 and When R2 satisfies R1 ≥ ROS and R2 ≥ ROS, the charge retention period (information retention period) is The transistor 162 (or transistor 562) is mainly The off-state current is determined by the

[0216] Conversely, if the condition is not met, transistor 162 (or transistor 562 Even if the off-state current of the transistor is sufficiently small, it becomes difficult to ensure a sufficient retention period. Leakage current (for example, source current) other than the off-state current of the resistor 162 (or the transistor 562) This is because the leakage current between the source electrode and the gate electrode is large. Therefore, the semiconductor device disclosed in this embodiment satisfies the above-mentioned relationship. This can be said to be desirable.

[0217] On the other hand, it is desirable that C1 and C2 satisfy the relationship C1≧C2. When the potential of the floating gate portion FG is controlled by the fifth wiring, This allows the potential of the floating gate FG to be efficiently applied, The potential difference between the potentials applied to the wiring (for example, the read potential and the non-read potential) is kept low. This is because it can be done.

[0218] By satisfying the above-mentioned relationship, it is possible to realize a more suitable semiconductor device. R1 and R2 are the gate insulating layer of transistor 160 (or transistor 560) Controlled by the insulating layer of the capacitive element 164 (or capacitive element 564). C1 and C2 Therefore, the material and thickness of the gate insulating layer are appropriately set, and the above-mentioned relationship is It is desirable to satisfy the requirements.

[0219] In the semiconductor device shown in this embodiment, the floating gate portion FG is It has the same effect as the floating gate of a floating gate type transistor such as a memory. However, the floating gate portion FG of this embodiment is a floating gate of a flash memory or the like. In flash memory, the control gate has fundamentally different characteristics from the The voltage applied to the floating gate of the adjacent cell is high, so the potential influence is To prevent this from happening, it is necessary to maintain a certain amount of space between cells. This is one of the factors that hinder the high integration of semiconductor devices. This is due to the fundamental principle of flash memory, which is to generate a tunnel current by applying a voltage. That is why.

[0220] On the other hand, the semiconductor device according to this embodiment is a switch of a transistor using an oxide semiconductor. It operates by tunneling and does not use the principle of charge injection by tunnel current as described above. In other words, unlike flash memory, a high electric field for injecting charges is not required. Therefore, there is no need to consider the influence of the high electric field caused by the control gate on the adjacent cells. This makes it easier to achieve high integration.

[0221] In addition, the fact that a high electric field is not required and large peripheral circuits (such as a boost circuit) are not required is also an advantage of flash memory. For example, when the voltage applied to the memory cell according to this embodiment is The maximum and minimum voltages applied simultaneously to each terminal of the memory cell The maximum value of the difference) is the maximum value of the difference in one memory cell when writing two-level (1-bit) information. , 5V or less, preferably 3V or less.

[0222] The relative dielectric constant εr1 of the insulating layer constituting the capacitance element 164 (or capacitance element 564) and the The relative dielectric constant εr2 of the insulating layer constituting the transistor 160 (or the transistor 560) is different. In this case, the area S1 of the insulating layer that constitutes the capacitance element 164 (or the capacitance element 564) is and the insulator constituting the gate capacitance in the transistor 160 (or the transistor 560) The area S2 of the edge layer satisfies 2·S2≧S1 (preferably S2≧S1), and C1≧C 2. That is, the capacitance element 164 (or the capacitance element 564) can be easily realized. It is easy to realize C1≧C2 while reducing the area of the insulating layer that constitutes it. For example, in the insulating layer that forms the capacitor element 164 (or the capacitor element 564), Films made of high-k materials such as hafnium oxide or high A laminated structure of a film made of -k material and a film made of oxide semiconductor is adopted to make εr1 10 or more, preferably Preferably, it is 15 or more, and silicon oxide is used for the insulating layer that constitutes the gate capacitance. Therefore, εr2 can be set to 3 to 4.

[0223] By using such a configuration in combination, the semiconductor device according to the disclosed invention can be further improved. Integration is possible.

[0224] In order to increase the memory capacity of a semiconductor device, in addition to increasing the integration density, a method of multi-level data storage is also being adopted. For example, it is possible to write three or more levels of information into one memory cell. This allows for a larger memory capacity than when writing information in two stages. , as mentioned above, the charge Q L , a charge Q that gives a high potential H In addition to the other potentials By providing the charge Q to the gate electrode of the first transistor, multi-values can be realized. In this case, F 2 Even if a circuit configuration is adopted in which can be secured.

[0225] The above explanation is for n-type transistors (n-channel transistors) in which electrons are the majority carriers. This is about using a large number of hole-capacitors instead of n-type transistors. It goes without saying that a p-type transistor can be used as a carrier.

[0226] As described above, the semiconductor device according to the present embodiment is suitable for high integration. The degree of integration has been further increased by sharing wiring according to one aspect of the present invention and reducing the contact area. It is possible to provide a semiconductor device.

[0227] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0228] (Embodiment 5) In this embodiment, one application example of the semiconductor device described in the previous embodiment will be described. Specifically, the semiconductor devices described in the previous embodiments are arranged in a matrix. An example of such a semiconductor device will be described below.

[0229] FIG. 12 shows an example of a circuit diagram of a semiconductor device having a storage capacity of (m×n) bits.

[0230] A semiconductor device according to one aspect of the present invention includes m signal lines S (m is an integer of 2 or more) and m signal lines S. A number of the gate lines WL, n number of the bit lines BL (n is an integer of 2 or more), and k number of the gate lines WL (k is a natural number less than n) are included. ) source lines SL and memory cells 1100 are arranged in a matrix of m rows by n columns. a memory cell array arranged in the first driving circuit 1111, a second driving circuit 1112, The third driving circuit 1113 and the fourth driving circuit 1114 are peripheral circuits. Here, the memory cell 1100 has the configuration described in the previous embodiment (see FIG. 11(A)) applies.

[0231] Each memory cell 1100 includes a first transistor, a second transistor, and a capacitance element. Each memory cell 1100 has a gate electrode of a first transistor and a One of the source electrode or drain electrode of the transistor in 2 and one of the electrodes of the capacitor element , electrically connected to the source line SL and the source electrode (source region) of the first transistor Furthermore, the bit line BL and the source of the second transistor are electrically connected. The other of the electrode and the drain electrode of the first transistor is electrically connected. The word line WL and the other electrode of the capacitor element are electrically connected, and the signal line S and the first The source line SL is electrically connected to the gate electrode of the transistor 2. The first wiring (1st Line) in the configuration shown in FIG. 11(A) is connected to the bit line BL is the second wiring (2nd Line) and the third wiring (3rd Line), and the signal line S is The fourth line (4th Line) and the word line WL are connected to the fifth line (5th Line). Equivalent.

[0232] In the memory cell array shown in FIG. 12, the bit lines BL, the source lines SL, the word lines The bit lines WL and the signal lines S form a matrix. Also, m memory cells 1100 are connected to one of the word lines WL and the signal line Each of the S's is connected to n memory cells 1100 arranged in the same row. In addition, since the number of source lines SL is smaller than the number of bit lines BL, one of the source lines SL is a plurality of memory cells including at least memory cells 1100 connected to different bit lines BL. That is, one of the source lines SL has j (j is (m+1) or more) cells. The memory cells 1100 of the upper (m×n) (an integer not larger than m×n) are connected. The source region of the first transistor of the plurality of memory cells 1100 connected to one of the The source lines SL are arranged at a ratio of one line to multiple bit lines BL. In this case, each source line S If the number of memory cells 1100 connected to the source line SL is equal, one of the source lines SL has (m ×n / k) memory cells 1100 are connected. The source line SL can be arranged as follows in FIG. The metal compound region 1 is provided in a region corresponding to the region 180, and 24 is electrically connected to the

[0233] As in the memory cell arrays shown in FIGS. 12 and 13, one of the memory cells 1100 and another memory cell One of the source lines SL connecting the memory cells is connected to at least a different bit line BL. In the configuration in which a plurality of memory cells 1100 including source lines are connected, the number of source lines SL is By making the number of source lines smaller than the number of bit lines BL, the number of source lines can be reduced sufficiently. Therefore, the degree of integration of the semiconductor device can be improved.

[0234] The bit line BL is electrically connected to the first drive circuit 1111, and the source line SL is The signal line S is electrically connected to the second driving circuit 1112. 3, and the word line WL is electrically connected to the fourth drive circuit 1114. In this example, a first driver circuit 1111, a second driver circuit 1112, a third driver circuit 1113, and a The first driver circuit 1113 and the fourth driver circuit 1114 are provided independently. The invention is not limited to this. is also good.

[0235] Next, the write and read operations will be described. 10 is an example of a timing chart of a write operation and a read operation of the device.

[0236] For simplicity, the semiconductor device is configured with a memory cell array of 2 rows x 2 columns. Although the operation will be described, the disclosed invention is not limited thereto.

[0237] Write to the memory cell 1100(1,1) and memory cell 1100(1,2) in the first row. When writing, the memory cell 1100(1,1) in the first row and the memory cell 11 The following explains how to read from 00(1,2). The data to be written to memory cell (1,1) is "1", and the data to be written to memory cell (1,2) is "0". The case where it is set to "0" will be explained.

[0238] First, a write operation will be described. First, a potential V1 is applied to the signal line S(1) of the first row. Then, the second transistor in the first row is turned on. A potential of 0 V is applied to turn off the second transistor in the second row.

[0239] A potential V2 is applied to the bit line BL(1) in the first column, and a potential V3 is applied to the bit line BL(2) in the second column. gives a potential of 0V.

[0240] As a result, the potential V2 is applied to the floating gate FG of the memory cell (1,1), A potential of 0V is applied to the floating gate portion FG of cell (1, 2). The potential V2 is set to a potential higher than the threshold voltage of the first transistor. The potential of S(1) is set to 0 V, and the second transistor in the first row is turned off. The potential V2 should be set to the same level as the potential V1 or lower. preferable.

[0241] During the write operation, the first word line WL(1) and the second word line WL( 2) is set to a potential of 0V. Also, at the end of writing, the first column bit line BL(1) Before changing the potential of the signal line S(1), the potential of the first signal line S(1) is set to 0V. The threshold voltage of the memory cell is Vw0 when data is "0" and Vw1 when data is "1". Here, the threshold voltage of the memory cell is Vw1. The resistance between the drain electrode and the word line WL changes when the voltage at the terminal connected to the word line WL is applied. Here, Vw0>0>Vw1.

[0242] Next, the read operation will be described. Here, the bit line BL is connected to the read circuit shown in FIG. The paths are electrically connected.

[0243] First, a potential of 0V is applied to the word line WL(1) in the first row, and a potential of 0V is applied to the word line WL(2) in the second row. A potential VL is applied to WL(1). The potential VL is set to a potential lower than the threshold value Vw1. When the potential is set to 0V, the first bit of the memory cell in the first row that stores data “0” The transistor is in the off state, and the first transistor of the memory cell in which data "1" is stored When the word line WL(2) is set to a potential VL, the data Whether the memory cell holds a data "0" or "1", the first transistor is in the off state.

[0244] As a result, the first transistor of the memory cell (1,1) is connected between the bit line BL(1) and the source line SL. Since the transistor is in the on state, the resistance is low, and the bit line BL(2)-source line SL(1) During this time, the first transistor of the memory cell (1, 2) is in the off state, and therefore has a high resistance. The read circuit connected to the bit line BL(1) and the bit line BL(2) is The data can be read out from the difference in resistance.

[0245] During the read operation, the signal line S(1) is set to a potential of 0V, and the signal line S(2) is set to a potential of VL The floating gate of the first row is turned on. Since the potential of the output part FG is 0V or V2, the signal line S(1) is set to a potential of 0V. All the transistors in row 2 can be turned off. When the potential VL is applied to the word line WL(2), the potential of the gate section FG becomes the potential VL immediately after writing. This causes the second transistor to be turned on. To prevent this, the signal line S(2) is set to the same low potential (potential VL) as the word line WL(2). That is, in the rows where no readout is performed, the signal line S and the word line WL are set to the same low potential (potential VL) As a result, all of the second transistors can be turned off.

[0246] The output potential when the circuit shown in FIG. 15 is used as the readout circuit will be described. In the read circuit shown in FIG. 5, the bit line BL is set to The clocked inverter and the array with the potential V1 are connected via the controlled switch. The source line SL is connected to a diode-connected transistor. For example, 0V is applied. Since the resistance between the bit line BL(1) and the source line SL is low, A low potential is input to the clocked inverter, and the output D(1) becomes high. Since the resistance between BL(2) and the source line SL is high, a high potential is input to the clocked inverter. The output D(2) becomes Low.

[0247] The operating potentials are, for example, V1=2V, V2=1.5V, VH=2V, and VL=-2V. This can be done.

[0248] Next, a write operation different from the above will be described. This is the same as the write operation described above. Figure 16 shows the timing of the write operation and the read operation. 1 is an example of a timing chart.

[0249] In the write operation (writing the first row) using the timing chart shown in FIG. The potential of the word line WL(2) at this time is set to 0V. For example, the memory cell (2,1) Or, if the data written in memory cell (2,2) is data "1", A steady current flows between the bit lines BL(1) and BL(2). At the time of writing, the first transistors of the memory cells in the second row are turned on. The bit line BL(1) and the bit line BL(2) are connected with low resistance via the source line. The write operation shown in FIG. 16 is a method for preventing the occurrence of such a steady current. .

[0250] First, a potential V1 is applied to the signal line S(1) in the first row to turn on the second transistor in the first row. In addition, a potential of 0V is applied to the signal line S(2) in the second row, and the second transistor in the second row is set to the The resistor is turned off.

[0251] A potential V2 is applied to the bit line BL(1) in the first column, and a potential V3 is applied to the bit line BL(2) in the second column. gives a potential of 0V.

[0252] As a result, the potential V2 is applied to the floating gate FG of the memory cell (1,1), A potential of 0V is applied to the floating gate portion FG of cell (1, 2). The potential V2 is set to a potential higher than the threshold voltage of the first transistor. The potential of S(1) is set to 0 V, and the second transistor in the first row is turned off. End writing.

[0253] During the write operation, the potential of the word line WL(1) in the first row is set to 0V, and the potential of the word line WL(2) in the second row is set to 0V. The potential of the word line WL(2) in the second row is set to the potential VL. By setting the value to VL, it is possible to determine whether the data "0" or "1" is held in the second row. Even if the memory cell is in a write operation, the first transistor is turned off. During this time, a potential V2 is applied to the source line SL. The potential of the wire may be 0V.

[0254] Also, when writing is completed, the first bit line BL(1) is changed before the potential of the first bit line BL(1) is changed. The signal line S(1) of the 1st row is set to a potential of 0 V. After writing, the threshold value of the memory cell is , Vw0 when data is "0", and Vw1 when data is "1". Let w0>0>Vw1.

[0255] In this write operation, the memory cells in the row where no write is performed (in this case, the second row) Since the first transistor in the buffer is off, the steady-state current between the bit line and the source line is not an issue. The only thing that matters is the memory cells in the row being written. When writing data "0" to a memory cell, the first transistor of the memory cell is turned off. On the other hand, if the memory cells in the row to be written are When writing data "1", the first transistor of the memory cell is turned on. Therefore, a voltage is applied between the source line SL and the bit line BL (in this case, the bit line BL(1)). If there is a potential difference, a steady current is generated. By making the potential V2 the same as that of the line BL(1), a steady current is prevented between the bit line and the source line. can.

[0256] As described above, the write operation can prevent the generation of a steady current during writing. In other words, the power consumption during the write operation is sufficiently suppressed. It is possible.

[0257] The read operation is the same as the read operation described above.

[0258] The semiconductor device shown in FIG. 12 is a semiconductor device including an oxide semiconductor with extremely low off-state current. This allows the memory contents to be retained for an extremely long period of time. Refresh operations are unnecessary or the frequency of refresh operations is extremely low. This allows for a sufficient reduction in power consumption. Even in this case, the stored contents can be retained for a long period of time.

[0259] Furthermore, the semiconductor device shown in FIG. 12 does not require a high voltage to write information, and the deterioration of the element is prevented. Therefore, the semiconductor device shown in FIG. 12 does not have the problem of the conventional nonvolatile memory. There is no limit to the number of times it can be rewritten, which dramatically improves reliability. Information is written by switching the transistor between on and off, so high It is also possible to easily realize fast operation. In addition, there is an advantage that no operation is required to erase information. There is also a .

[0260] In addition, a transistor using a material other than an oxide semiconductor is Compared to transistors, this allows for even higher speed operation. By using it in combination with a transistor, the operation of a semiconductor device (for example, reading out information) can be improved. Furthermore, it is possible to ensure sufficient high speed of the semiconductor device (operation). These transistors are ideal for various circuits (logic circuits, driver circuits, etc.) that require high-speed operation. It is possible to achieve this appropriately.

[0261] In this way, transistors using materials other than oxide semiconductors and transistors using oxide semiconductors By integrating a transistor, a semiconductor device with unprecedented features can be realized. It is possible.

[0262] Furthermore, in the semiconductor device shown in FIG. 12, the number of wirings per memory cell can be reduced. This reduces the area occupied by the memory cells, and the memory capacity per unit area of the semiconductor device can be increased. The memory capacity can be increased.

[0263] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0264] (Sixth embodiment) In this embodiment, when the semiconductor device described in the above embodiment is applied to an electronic device, This will be described with reference to FIG. 17. In this embodiment, telephones, mobile phone devices), portable information terminals (including portable game consoles and audio playback devices) digital cameras, digital video cameras, electronic paper, television equipment (television The semiconductor device described above is applied to electronic devices such as a television receiver. This section explains the case where

[0265] FIG. 17A shows a notebook personal computer, which includes a housing 701, a housing 702, The display unit 703, the keyboard 704, etc. At least one of the semiconductor devices is provided with the semiconductor device described in the above embodiment. It has high speed writing and reading of information, long-term storage, and low power consumption. This realizes a notebook-type personal computer with reduced processing power.

[0266] FIG. 17B shows a personal digital assistant (PDA), and a main body 711 includes a display unit 713 and an external An external interface 715, operation buttons 714, etc. are provided. The main body 711 is provided with a stylus 712 for operating the terminal. Therefore, writing and reading of information can be performed at high speed. A portable information terminal capable of long-term memory retention and sufficiently reduced power consumption is realized. .

[0267] FIG. 17C shows an electronic book 720 in which electronic paper is mounted, and the electronic book 720 is made up of a housing 721 and a housing 722. The display unit 721 and the display unit 723 are configured as two housings. 25 and a display unit 727 are provided. The housing 721 and the housing 723 are connected by a shaft portion 737. The housing 7 is connected to the shaft 737, and can be opened and closed around the shaft 737. 21 includes a power supply 731, operation keys 733, a speaker 735, etc. At least one of the housings 723 is provided with the semiconductor device described in the above embodiment. Therefore, information can be written and read at high speed, can be stored for a long period of time, and can be erased. This allows for the realization of an electronic book with significantly reduced power consumption.

[0268] FIG. 17D shows a mobile phone that is composed of two housings, a housing 740 and a housing 741. Furthermore, the housing 740 and the housing 741 slide and unfold as shown in FIG. 17(D). The two can be folded into an overlapping state, making them compact and suitable for portability. The housing 741 also includes a display panel 742, a speaker 743, a microphone 744, an operation panel 745, and a keyboard 746. Key 745, pointing device 746, camera lens 747, external connection terminal 74 The housing 740 also includes a solar cell 749 for charging the mobile phone. , an external memory slot 750, etc. The antenna is built into the housing 741. At least one of the housing 740 and the housing 741 is provided with the semiconductor device shown in the previous embodiment. This allows for high speed writing and reading of information and long-term storage. Thus, a portable telephone that can be held and consumes a sufficient amount of power is realized.

[0269] FIG. 17(E) shows a digital camera, which includes a main body 761, a display unit 767, an eyepiece unit 763, and an operation unit. It is composed of an operation switch 764, a display unit 765, a battery 766, etc. The semiconductor device described in the above embodiment is provided in the memory 761. High speed writing and reading, long-term memory retention, and low power consumption A digital camera having such a configuration is realized.

[0270] FIG. 17F shows a television device 770, which includes a housing 771, a display portion 773, a stand, and the like. The television device 770 is operated by a switch provided in the housing 771. This can be done using a switch or a remote control 780. The semiconductor device described in the above embodiment is mounted on the device 780. High speed writing and reading, long-term memory retention, and low power consumption A reduced television set is realized.

[0271] As described above, the electronic device described in this embodiment mode is equipped with the semiconductor device according to the above embodiment. This allows for the realization of electronic devices with reduced power consumption. [Example]

[0272] In this example, the off-state current of a transistor including a highly purified oxide semiconductor was measured. Explain the results.

[0273] First, the off-state current of a transistor using a highly purified oxide semiconductor must be sufficiently small. Considering this, we prepared a transistor with a sufficiently large channel width W of 1 m and measured the off-state current. The results of measuring the off-state current of a transistor with a channel width W of 1 m are shown in Figure 18. In FIG. 18, the horizontal axis represents the gate voltage VG, and the vertical axis represents the drain current ID. When the voltage VD is +1V or +10V, if the gate voltage VG is in the range of -5V to -20V, , the off-current of the transistor is 1×10, which is the detection limit. -12 It turns out that it is below A. In addition, the off-state current of the transistor (here, the value per unit channel width (1 μm)) is 1aA / μm (1×10 -18 A / μm or less.

[0274] Next, we aimed to more accurately determine the off-state current of a transistor using a highly purified oxide semiconductor. As described above, the transistor using the highly purified oxide semiconductor The off-state current of the transistor is 1×10, which is the detection limit of the measuring instrument. -12 It turns out that it is below A. Therefore, we fabricated a device for characteristic evaluation to obtain a more accurate value of the off-state current (measured in the above measurement). The results of the calculation (values below the detection limit of the detector) are explained below.

[0275] First, the characteristic evaluation element used in the current measurement method will be described with reference to FIG.

[0276] The characteristic evaluation element shown in FIG. 19 has three measurement systems 800 connected in parallel. 0 represents the capacitor element 802, the transistor 804, the transistor 805, and the transistor 806. , and transistor 808. A transistor including a highly purified oxide semiconductor was used for the capacitor 806.

[0277] In the measurement system 800, one of the source terminal and the drain terminal of the transistor 804, One of the terminals of the capacitor 802 and the source terminal and drain terminal of the transistor 805 One end is connected to a power supply (the power supply that provides V2). the other of the source and drain terminals of the transistor 808 One of the terminals of the capacitor 802, the other terminal of the capacitor 802, and the gate terminal of the transistor 805 are connected to each other. The other of the source terminal and the drain terminal of the transistor 808 is connected to the One of the source terminal and the drain terminal of the transistor 806 and the gate of the transistor 806 The output terminal of the transistor 805 is connected to a power supply (the power supply that provides V1). the other of the source and drain terminals of the transistor 806 The other terminal is connected to form an output terminal Vout.

[0278] The gate terminal of the transistor 804 is connected to a resistor R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R59, R59, R59, R50, R50 A potential Vext_b2 that controls the state of the transistor 808 is supplied to the gate terminal of the transistor 808. A potential Vext_b1 that controls the on and off states of the transistor 808 is supplied. Furthermore, the potential Vout is output from the output terminal.

[0279] Next, a current measurement method using the above characteristic evaluation element will be described.

[0280] First, an outline of the initialization period during which a potential difference is applied to measure the off-state current will be described. During the initialization period, the gate terminal of the transistor 808 is connected to the transistor 808. A potential Vext_b1 is input to the source terminal or drain of the transistor 804. a node connected to the other of the input terminals (i.e., the source terminal and the drain terminal of the transistor 808) One of the drain terminals, the other terminal of the capacitor 802, and the gate terminal of the transistor 805 A potential V1 is applied to node A, which is a node connected to a child. For example, the potential is set to high. The transistor 804 is kept in an off state.

[0281] Then, a potential that turns off the transistor 808 is applied to the gate terminal of the transistor 808. Vext_b1 is input to turn off the transistor 808. After turning off the transistor 804, the potential V1 is set to a low potential. The potential V2 is set to the same potential as the potential V1. When the initialization period is over, the node A and the source voltage of the transistor 804 A potential difference is generated between one of the electrode and drain electrodes of the transistor 808. A potential difference occurs between the source electrode and the drain electrode of the transistor. A small amount of charge flows through the transistor 804 and the transistor 808. In other words, an off-current occurs. do.

[0282] Next, an outline of the measurement period of the off-state current will be described. The potential of one of the source terminal or drain terminal of 804 (i.e., V2) and The potential of the other terminal of the source terminal or the drain terminal of the transistor 808 (i.e., V1) is On the other hand, during the measurement period, the potential of the node A is not fixed (flow This causes a charge to flow through the transistor 804, and over time, The amount of charge held at node A fluctuates. In other words, the output potential Vout of the output terminal also fluctuates. .

[0283] The details of the relationship between the potentials during the initialization period in which the above potential difference is applied and the subsequent measurement period are as follows: The timing chart is shown in FIG.

[0284] In the initialization period, first, the potential Vext_b2 is set to the ON state by the transistor 804. This sets the potential of node A to V2, that is, a low potential ( VSS). After that, the potential Vext_b2 is set to Vext_b1 when the transistor 804 is turned off. The transistor 804 is turned off by applying a voltage (low potential) to the transistor 804. The potential Vext_b1 is set to a potential (high potential) that turns on the transistor 808. This causes the potential of node A to become V1, i.e., the high potential (VDD). ext_b1 is set to a potential that turns off the transistor 808. , node A becomes floating, and the initialization period ends.

[0285] In the subsequent measurement period, charges flow into node A, causing potentials V1 and V2 to Or, the potential is set so that charge flows out from node A. Here, the potential V1 and the potential V 2 is the low potential (VSS). However, at the timing when the output potential Vout is measured, In this case, it is necessary to operate the output circuit, so V1 is temporarily set to a high potential (VDD). The period when V1 is at a high potential (VDD) should be short enough so as not to affect the measurement. The period.

[0286] As described above, when a potential difference is applied and the measurement period begins, the voltage at node A increases over time. The amount of charge held changes, and the potential at node A changes accordingly. This means that the potential of the gate terminal of the transistor 805 fluctuates, so over time, the output The potential of the output potential Vout of the terminal also changes.

[0287] A method for calculating the off-state current from the obtained output potential Vout will be described below.

[0288] Before calculating the off-state current, the potential V of node A A and the output voltage Vout. This causes the output potential Vout to change to the potential V at node A. A can be obtained. From the above relationship, the potential of node A, V A is expressed as a function of the output potential Vout as follows: It is possible.

[0289]

number

[0290] Also, the charge Q at node A A is the potential V of node A A , capacitance C connected to node A A , fixed Using a constant, it is expressed as follows: C A is the sum of the capacitance of the capacitive element 802 and other capacitances.

[0291]

number

[0292] Current I at node A A is the charge flowing into (or out of) node A. Since it is a time derivative, the current I at node A A is expressed as follows:

[0293]

number

[0294] In this way, the capacitance C connected to node A A The output potential Vout of the output terminal is Current I A can be obtained.

[0295] By using the method described above, the leakage current flowing between the source and drain of the transistor in the off state can be reduced. The off-state current (off current) can be measured.

[0296] In this example, a highly purified oxide film having a channel length L=10 μm and a channel width W=50 μm was used. A transistor 804, a transistor 805, a transistor 806, and a transistor 807 are formed using a compound semiconductor. In each of the paralleled measurement systems 800, a capacitance element 802 The capacitance values were set to 100fF, 1pF, and 3pF.

[0297] In the measurement according to this embodiment, VDD=5V and VSS=0V. In this case, the potential V1 is set to VSS as a rule, and the voltage is increased by 100 msec every 10 to 300 sec. Vout was measured as VDD for the period c. The time Δt was set to approximately 30,000 seconds.

[0298] FIG. 21 shows the relationship between the elapsed time Time in the current measurement and the output potential Vout. From FIG. 21, it can be seen that the potential changes over time.

[0299] FIG. 22 shows the off-state current at room temperature (25° C.) calculated from the above current measurement. FIG. 22 shows the relationship between the source-drain voltage V and the off-state current I. 22, the off-current is about 40zA / μm when the source-drain voltage is 4V. In addition, under the condition of a source-drain voltage of 3.1 V, the off-current It was found that the current density was 10zA / μm or less. -21 Represents A.

[0300] Furthermore, the off-state current calculated from the above current measurement in a temperature environment of 85°C was The figure shows the source-drain voltage V and the off-state voltage V under a temperature environment of 85°C. This shows the relationship between the source and drain voltage and the current I. It was found that the off-state current was 100 zA / μm or less.

[0301] As described above, in this example, in a transistor using a highly purified oxide semiconductor, It was confirmed that the flow was sufficiently small. [Example]

[0302] The number of times that a semiconductor device according to one embodiment of the disclosed invention can be rewritten was investigated. The survey results will now be explained with reference to FIG.

[0303] The semiconductor device used in the investigation has a circuit configuration shown in FIG. A transistor corresponding to the transistor 162 is formed using an oxide semiconductor. The corresponding capacitance element used had a capacitance value of 0.33 pF.

[0304] The investigation involves setting the initial memory window width and repeating the retention and writing of information a predetermined number of times. This is done by comparing the memory window width after the data is returned. The write operation is performed by applying either 0V or 5V to the wiring corresponding to the third wiring in FIG. 11(A). and the wire corresponding to the fourth wire is given either 0V or 5V. When the potential of the wiring corresponding to the fourth wiring is 0 V, the transistor 162 The corresponding transistor (write transistor) is in the off state, so the floating The potential given to the gate FG is maintained. The potential of the wiring corresponding to the fourth wiring is 5V. In this case, the transistor corresponding to the transistor 162 is in the ON state, so the third The potential of the wiring corresponding to the wiring is applied to the floating gate portion FG.

[0305] The memory window width is one of the indicators that show the characteristics of a memory device. Between the states, the potential Vcg of the wiring corresponding to the fifth wiring and the potential Vcg of the wiring corresponding to the transistor 160 The curve (V The difference between the flow The state where 0V is applied to the gate FG (hereinafter referred to as the low state) and the state where This refers to the state in which 5V is applied to the input gate FG (hereinafter referred to as the High state). The memory window width is determined by sweeping the potential Vcg in the low and high states. Here, in the low state, the potential Vcg is in the range of -2V to 5V. In the High state, the potential Vcg was swept in the range of −7 V or more and 0 V or less. In either case, the potential difference between the drain potential and the source potential is Vds=1V. did.

[0306] Figure 24 shows the initial memory window width and the 1×10 9 Notes after writing The results of the investigation of the re-windowing width are shown in Fig. 24. In Fig. 24, the horizontal axis represents Vcg (V), The vertical axis indicates Id (A). The solid line indicates the characteristic curve for the first write, and the dashed line indicates the characteristic curve for the second write. is 1 x 10 9 The characteristic curves for the th write are shown. The curve on the left shows the characteristic curve in the high state, and the curve on the right shows the characteristic curve in the low state. From Figure 24, the 1×10 9 The memory window width before and after each write is It can be confirmed that there is no change. 1×10 9 Before and after the write operation, the memory window The fact that the width does not change means that the characteristics of the semiconductor device will not change at least during this period. This shows that:

[0307] As described above, the semiconductor device according to one embodiment of the disclosed invention performs storage and writing in a 1×1 0 9 Even after repeated rewriting, the characteristics do not change and the rewriting durability is extremely high. According to one embodiment of the present invention, a highly reliable semiconductor device can be achieved. [Explanation of symbols]

[0308] 100 boards 102 Protective layer 104 Semiconductor Area 106 Element isolation insulating layer 108 Gate insulating layer 110 gate electrode 116 Channel formation region 120 Impurity region 122 Metal layer 124 Metal compound area 126 electrode 128 Insulating Layer 130 Insulating layer 142a Source electrode or drain electrode 142b Source electrode or drain electrode 143a Insulating layer 143b Insulating layer 144 Oxide semiconductor layer 146 Gate insulating layer 148a Gate electrode 148b Electrode 150 insulating layer 152 Insulating layer 154 Electrode 156 Wiring 160 transistors 162 transistors 164 Capacitor 180 areas 182 Contact Area 500 base board 502 Nitrogen-containing layer 510 Single crystal semiconductor substrate 512 Oxide film 514 Embrittlement area 516 Single crystal semiconductor layer 518 Single crystal semiconductor layer 520 Semiconductor layer 522 Insulation layer 522a Gate insulating layer 524 Conductive Layer 524a Gate electrode 526 Channel formation region 528 Impurity region 530 electrode 532 Insulating layer 534 Insulating Layer 542a Source electrode or drain electrode 542b Source or drain electrode 543a Insulating layer 543b Insulating layer 544 Oxide semiconductor layer 546 Gate insulating layer 548a Gate electrode 548b electrode 550 insulating layer 552 Insulation layer 554 Electrode 556 Wiring 560 transistors 562 transistors 564 Capacitor 701 Case 702 Case 703 Display section 704 keyboard 711 Main Unit 712 Stylus 713 Display section 714 Operation Button 715 external interface 720 e-books 721 Case 723 Case 725 Display section 727 Display section 731 Power supply 733 Operation Key 735 Speaker 737 Shaft 740 chassis 741 Case 742 Display Panel 743 Speaker 744 microphone 745 Operation Key 746 Pointing Device 747 Camera Lens 748 External connection terminal 749 Solar Cells 750 external memory slot 761 Main Unit 763 Eyepiece 764 Operation Switch 765 Display section 766 Battery 767 Display section 770 Television Equipment 771 Case 773 Display section 775 Stand 780 Remote Controlled Machine 800 measurement system 802 Capacitor element 804 transistor 805 transistor 806 Transistor 808 Transistor 1100 memory cells 1111 First driving circuit 1112 Second driver circuit 1113 Third driving circuit 1114 4th driving circuit

Claims

1. a first transistor, a second transistor, and a capacitor; a gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitor element are electrically connected to each other; a silicon layer having a channel formation region of the first transistor and an impurity region; a first conductive layer having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a first insulating layer having a region in contact with a side surface of the first conductive layer; a second conductive layer having a region located above the first insulating layer and a region in contact with an upper surface of the first conductive layer, and having a function as one of a source electrode and a drain electrode of the second transistor and a function as one electrode of the capacitor; a third conductive layer having a region in contact with a top surface of the impurity region of the first transistor and functioning as the other of the source electrode and the drain electrode of the second transistor; a fourth conductive layer having a region overlapping with the second conductive layer and functioning as the other electrode of the capacitor; an oxide semiconductor layer having a region located above the first insulating layer and including a channel formation region of the second transistor; a second insulating layer having a region located above the oxide semiconductor layer and functioning as a gate insulating layer of the second transistor; a fifth conductive layer having a region located above the second insulating layer and functioning as a gate electrode of the second transistor; the fourth conductive layer has a first region overlapping the second conductive layer; the fourth conductive layer has a second region overlapping the first conductive layer; a region where the first conductive layer and the second conductive layer are in contact with each other includes a region overlapping with the first region; a region where the first conductive layer and the second conductive layer are in contact with each other includes a region overlapping with the second region; the fourth conductive layer and the fifth conductive layer have the same material; a channel formation region of the first transistor not overlapping with the fifth conductive layer;

2. a first transistor, a second transistor, and a capacitor; a gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitor element are electrically connected to each other; a silicon layer having a channel formation region of the first transistor and an impurity region; a first conductive layer having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a first insulating layer having a region in contact with a side surface of the first conductive layer; a second conductive layer having a region located above the first insulating layer and a region in contact with an upper surface of the first conductive layer, and having a function as one of a source electrode and a drain electrode of the second transistor and a function as one electrode of the capacitor; a third conductive layer having a region in contact with a top surface of the impurity region of the first transistor and functioning as the other of the source electrode and the drain electrode of the second transistor; a fourth conductive layer having a region overlapping with the second conductive layer and functioning as the other electrode of the capacitor; an oxide semiconductor layer having a region located above the first insulating layer and including a channel formation region of the second transistor; a second insulating layer having a region located above the oxide semiconductor layer and functioning as a gate insulating layer of the second transistor; a fifth conductive layer having a region located above the second insulating layer and functioning as a gate electrode of the second transistor; the fourth conductive layer has a first region overlapping the second conductive layer; the fourth conductive layer has a second region overlapping the first conductive layer; a region where the first conductive layer and the second conductive layer are in contact with each other includes a region overlapping with the first region; a region where the first conductive layer and the second conductive layer are in contact with each other includes a region overlapping with the second region; the fourth conductive layer and the fifth conductive layer have the same material; a channel formation region of the first transistor does not overlap with the fifth conductive layer; the fourth conductive layer has a region in contact with an upper surface of the second insulating layer, The fifth conductive layer has a region in contact with an upper surface of the second insulating layer.

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