Semiconductor device, electronic appliance, and design method for semiconductor device

Abstract

To improve the performance of a semiconductor device including a diamond device.SOLUTION: The present disclosure is related to a design technology (design method) for a semiconductor device including a field effect transistor having a diamond layer and a surface protection film that is in contact with a part of the diamond layer. In the present disclosure, the semiconductor device is designed and the material of the surface protection film is selected so that the breakdown voltage of the surface protection film becomes higher than that of the diamond layer.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, an electronic device, and a method for designing a semiconductor device, and relates to a technique that is effective when applied to, for example, a semiconductor device having a diamond layer. [Background technology]

[0002] Japanese Patent No. 5551648 (Patent Document 1) describes a technology relating to a diamond transistor in which the shape of the gate electrode is a so-called "T-shaped gate." [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 5551648 Summary of the Invention [Problem to be solved by the invention]

[0004] Diamond has overwhelming potential as a semiconductor device material compared to other materials. However, the present inventors have newly discovered that in order to realize diamond devices that utilize the high potential of diamond, it is necessary to suppress dielectric breakdown caused by materials other than diamond that make up the diamond device.

[0005] In other words, the above-mentioned dielectric breakdown hinders the production of high-performance diamond devices. In other words, in order to produce high-performance diamond devices, it is necessary to devise new methods for designing diamond devices and selecting materials. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment includes a field effect transistor having a diamond layer, and a surface protection film in contact with a portion of the diamond layer, wherein the surface protection film has a breakdown voltage greater than the breakdown voltage of the diamond layer.

[0007] In one embodiment, a semiconductor device design method is provided, which includes a field-effect transistor having a diamond layer and a surface protection film in contact with a portion of the diamond layer, and includes the steps of designing a structure of the field-effect transistor and selecting a constituent material of the surface protection film so that the breakdown voltage of the surface protection film is greater than the breakdown voltage of the diamond layer. [Effects of the Invention]

[0008] According to one embodiment, the performance of a semiconductor device including a diamond device can be improved. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 2 is a diagram showing the configuration of a first surface conduction type FET. [Figure 2] FIG. 2 is a diagram showing the configuration of a second surface conduction type FET. [Figure 3] FIG. 10 is a diagram illustrating the configuration of a third surface conduction type FET. [Figure 4] 1A and 1B are diagrams illustrating the configuration of a surface conduction FET according to an embodiment. [Figure 5] FIG. 5 is an enlarged cross-sectional view of a portion of the surface conduction FET shown in FIG. [Figure 6] FIG. 5 is an enlarged plan view of a portion of the surface conduction FET shown in FIG. [Figure 7] FIG. 1 is a diagram showing a surface conduction FET in an example. [Figure 8] 1A to 1C are diagrams illustrating a manufacturing process of a surface conduction FET in an example. [Figure 9] 9A to 9C are diagrams showing the manufacturing process of the surface conduction FET following FIG. 8. [Figure 10]10A to 10C are diagrams showing the manufacturing process of the surface conduction FET following FIG. 9. [Figure 11] 11A to 11C are diagrams showing the manufacturing process of the surface conduction FET following FIG. 10. [Figure 12] 12A to 12C are diagrams showing the manufacturing process of the surface conduction FET following FIG. 11. [Figure 13] 13A to 13C are diagrams showing the manufacturing process of the surface conduction FET following FIG. 12. [Figure 14] FIG. 11 is an enlarged cross-sectional view of a part of a surface-conduction FET according to Modification 3. [Figure 15] FIG. 11 is an enlarged plan view of a part of a surface conduction type FET according to Modification 3. DETAILED DESCRIPTION OF THE INVENTION

[0010] In all the drawings for explaining the embodiments, the same components are generally designated by the same reference numerals, and repeated explanations thereof will be omitted. In addition, hatching may be used even in plan views to make the drawings easier to understand.

[0011] <The usefulness of diamond as a semiconductor material> For example, future mobile communications, satellite communications, and ultra-small radars will require high-power, high-frequency field-effect transistors (FETs). Semiconductor materials, such as silicon (Si) and gallium arsenide (GaAs), have limitations in their power density at frequencies above several GHz. For this reason, wide-bandgap semiconductor materials, such as silicon carbide (SiC), gallium nitride (GaN), and diamond, are being considered for use in FETs. Diamond, in particular, has the highest thermal conductivity of any material (four times that of SiC and 16 times that of GaN) and the highest dielectric breakdown field strength of any semiconductor material (three times that of SiC and 10 times that of GaN). Furthermore, the hole mobility and hole saturation velocity in diamond are comparable to those of silicon.

[0012] Diamond has excellent heat dissipation characteristics due to its high thermal conductivity. Therefore, when diamond is used as a semiconductor material, heat generation in semiconductor devices can be suppressed. From this, semiconductor devices using diamond can be expected to operate at high temperatures.

[0013] Also, due to the high breakdown electric field strength of diamond, semiconductor devices are less likely to be damaged even when a high voltage is applied. From this, semiconductor devices using diamond are suitable for semiconductor devices for high-power applications. Furthermore, the high carrier mobility of diamond indicates that diamond has great potential as a semiconductor device for high frequencies.

[0014] From the above, diamond as a semiconductor material is regarded as promising in realizing next-generation semiconductor devices including FETs that can operate at high power and high frequencies.

[0015] <Difficulty in fabricating n-type diamond> As described above, diamond is a wide-bandgap semiconductor material. Therefore, n-type diamond can be fabricated by introducing n-type impurities called donors into diamond. Specifically, it is considered that n-type diamond can be realized by supplying electrons from the donor level of the donor to the conduction band of diamond.

[0016] Here, nitrogen can be cited as a donor. However, in diamond, the donor level of nitrogen does not exist near the conduction band but exists at a "deep level" far from the conduction band. Specifically, the donor level of nitrogen exists at an energy position 1.7 eV lower than the conduction band of diamond. As a result, in diamond, the activation energy for exciting electrons from the donor level of nitrogen to the conduction band of diamond is large.

[0017] For this reason, even if nitrogen, a donor, is introduced into diamond, it is difficult to increase the number of electrons supplied to the conduction band, and as a result, it is difficult to make nitrogen-introduced diamond function as n-type diamond.

[0018] On the other hand, p-type diamond can be created by introducing p-type impurities called acceptors into diamond. Specifically, it is thought that p-type diamond can be realized by exciting electrons from the valence band of diamond to the acceptor level of the acceptor, thereby generating holes in the valence band of diamond.

[0019] Here, boron can be mentioned as an acceptor. The acceptor level of this boron exists near the valence band of diamond. Specifically, the acceptor boron forms an acceptor level at an energy position 0.37 eV higher than the valence band of diamond. In other words, in diamond, the acceptor level of boron does not constitute a "deep level" like the donor level of nitrogen. For this reason, the activation energy for exciting electrons from the valence band of diamond to the acceptor level of boron is not very large. As a result, it is easier to produce p-type diamond from diamond than to produce n-type diamond.

[0020] Therefore, FETs manufactured using diamond generally do not use n-channel FETs, which require n-type diamond, but rather p-channel FETs, which use p-type diamond, which is easier to fabricate than n-type diamond. In other words, FETs manufactured using diamond are realized as FETs that use holes as carriers, rather than FETs that use electrons as carriers. In particular, FETs manufactured using diamond include p-channel FETs called "surface conduction FETs."

[0021] This "surface conduction FET" will be explained below.

[0022] <Surface conduction FET> When diamond is hydrogen-terminated, there is a phenomenon in which holes (two-dimensional hole gas) are induced on the surface of the hydrogen-terminated diamond. An FET that utilizes this phenomenon is called a "surface-conduction FET." In other words, a "surface-conduction FET" is an FET that uses the two-dimensional hole gas induced on the surface of the hydrogen-terminated diamond as its channel. This "surface-conduction FET" performs switching operations by controlling the conduction / non-conduction of the channel by changing the gate voltage applied to the gate electrode. A "surface-conduction FET" enables high-temperature operation with high breakdown voltage. This is because extremely strong "C-H" bonds are formed when diamond is hydrogen-terminated.

[0023] The mechanism by which holes are induced on the surface of hydrogen-terminated diamond has not been fully elucidated. The following two theories are considered to be the most likely explanations.

[0024] One theory is the "transfer doping model," which states that differences in chemical potential caused by adsorbates or changes in the pH of the surface cause electrons in the diamond's valence band to move to levels determined by the chemical potential of the surface, generating holes near the surface where these electrons are lost.

[0025] On the other hand, the other theory is the "negative ion model." This theory is as follows: In the "CH" bond created by hydrogen-terminating diamond, hydrogen becomes positively charged and carbon becomes negatively charged due to the difference in electronegativity. As a result, negative ions in the atmosphere are adsorbed onto the positively charged hydrogen, and these adsorbed negative ions attract holes to the surface of the diamond.

[0026] As such, the mechanism has not been fully elucidated. Nevertheless, the phenomenon of holes being induced on the surface of hydrogen-terminated diamond does occur. This phenomenon has been utilized to create an excellent FET called a "surface-conduction FET" that can withstand high voltages and operate at high temperatures.

[0027] Some of the excellent properties of surface conduction FETs are listed below.

[0028] Excellent properties for power device applications (1) The breakdown field strength is large at 10 MV / cm (2) Large carrier density (10 13 / cm 3 (End) Excellent characteristics for high frequency device applications (1) The dielectric constant is small at 5.7 (2) The channel formation region is near the surface (10 nm or less from the surface). Excellent characteristics for high temperature operation (1) High thermal conductivity of 22 W / cm K (2) The cooling system can be removed or made smaller. <History of research into surface conduction FETs> FIG. 1 is a diagram showing the configuration of a surface conduction type FET 100A.

[0029] In FIG. 1, a surface-conduction FET 100A has a diamond substrate 101 doped with nitrogen. An undoped layer 102 is provided on the diamond substrate 101. A hydrogen-terminated region 103 and an oxygen-terminated region 104 are formed on the upper surface of the undoped layer 102. A channel-forming region 105 having a two-dimensional hole gas is formed below the hydrogen-terminated region 103. As shown in FIG. 1, a source electrode 106 and a drain electrode 107 are disposed on the hydrogen-terminated region 103, spaced apart from each other. A gate electrode 109 is disposed on the hydrogen-terminated region 103 between the source electrode 106 and the drain electrode 107, with a gate insulating film 108 interposed therebetween. The gate electrode 109 is disposed apart from both the source electrode 106 and the drain electrode 107.

[0030] 1, a portion of the hydrogen-terminated region 103 formed on the channel-forming region 105 is exposed. As a result, the exposed hydrogen-terminated region 103 is exposed to positive ions or negative ions (hereinafter, positive ions and negative ions are collectively referred to as ions) in the atmosphere.

[0031] Therefore, the ions may adversely affect the channel formation region 105 formed below the hydrogen-terminated region 103. This may cause fluctuations in the characteristics of the surface-conduction FET 100A.

[0032] Note that substances that may adversely affect the channel formation region 105 may not be limited to ions. Therefore, substances that may adversely affect the channel formation region 105 may include ions in the atmosphere and neutral substances present in the atmosphere. In consideration of this, in this specification, substances that may adversely affect the channel formation region 105 are referred to as ions, etc.

[0033] Therefore, the following surface conduction type FET 100B is being considered.

[0034] FIG. 2 is a diagram showing the configuration of the surface conduction type FET 100B.

[0035] As shown in FIG. 2 , a surface protective film 110 is formed to cover the source electrode 106, the drain electrode 107, and the gate electrode 109. The surface protective film 110 is also called a "passivation film." The surface protective film 110 covers the exposed hydrogen-termination region 103. That is, the hydrogen-termination region 103 is not exposed to ions in the atmosphere. In other words, the surface protective film 110 prevents ions in the atmosphere from contacting the hydrogen-termination region 103. This prevents ions from adversely affecting the channel formation region 105 formed below the hydrogen-termination region 103. Therefore, the surface-conduction FET 100B is less likely to experience characteristic fluctuations due to ions in the atmosphere. Therefore, the surface-conduction FET 100B can improve reliability.

[0036] From the above, the surface protection film 110 is effective in suppressing the characteristic fluctuation caused by ions in the atmosphere by covering the exposed hydrogen-terminated region 103.

[0037] However, it is possible that the hydrogen termination region 103 is not exposed, for example, when the hydrogen termination region 103 is covered with the gate insulating film 108. Even in this case, it is effective to form the surface protective film 110. This is because covering the entire device with the surface protective film 110 can reduce the influence of ions and the like present outside the device on the device characteristics. In this way, regardless of whether the hydrogen termination region 103 is exposed, the surface protective film 110 is useful for improving the reliability of the device.

[0038] In this regard, the present inventors have newly discovered that there is room for improvement in realizing a surface conduction FET that utilizes the high potential of diamond by providing a surface protection film 110. The following describes the new findings discovered by the present inventors.

[0039] <New findings discovered by the inventors> The high breakdown field of diamond used in surface-conduction FETs makes them less susceptible to breakdown even when high voltages are applied. This makes surface-conduction FETs suitable for high-power applications. In surface-conduction FETs used in high-power applications, for example, a high potential difference occurs between the gate electrode and the drain electrode.

[0040] In this case, for example, in FIG. 2, attention is focused on the non-doped layer 102 in which the channel formation region 105 is formed. The non-doped layer is made of diamond. Diamond has a high dielectric breakdown field. Therefore, even if a high potential difference occurs between the gate electrode 109 and the drain electrode 107, dielectric breakdown is unlikely to occur in the non-doped layer 102. This enables the surface conduction FET to operate under high voltage conditions that are only possible with diamond devices. However, the present inventors have newly discovered that, as shown in FIG. 2, when a surface protection film 110 is formed, dielectric breakdown may occur in the surface protection film 110 between the gate electrode 109 and the drain electrode 107 before dielectric breakdown occurs in the non-doped layer 102.

[0041] If breakdown occurs in the surface protection film 110 between the gate electrode 109 and the drain electrode 107 before breakdown occurs in the non-doped layer 102 made of diamond, it means that the surface-conduction FET will no longer function as a transistor before the diamond can exhibit its inherent performance. In other words, breakdown in the surface protection film 110 prevents operation under high-voltage conditions that are only possible with diamond devices. In other words, to ensure that the surface-conduction FET exhibits its inherent performance, it is necessary to devise a design for the surface-conduction FET and a selection of materials for the surface protection film 110.

[0042] Therefore, in this embodiment, a special technique is employed to utilize the high potential of diamond to maximize the inherent performance of the surface conduction FET. The technical concept of this specially designed embodiment is explained below.

[0043] <Basic Concept of the Embodiment> The basic idea in this embodiment relates to a design technique (design method) for a semiconductor device including a field-effect transistor having a diamond layer and a surface protection film in contact with a part of the diamond layer. The basic idea is to design the semiconductor device and select the material constituting the surface protection film such that the breakdown voltage of the surface protection film is greater than the breakdown voltage of the diamond layer. That is, the basic idea is to design the structure of the semiconductor device and select the surface protection film so that breakdown does not occur in the surface protection film between the gate electrode and the drain electrode before the diamond layer breaks down. Thereby, the high-voltage operation of the field-effect transistor can be implemented without being limited by the breakdown of the surface protection film. Therefore, according to the basic idea, the original performance of the field-effect transistor having a diamond layer can be exhibited. As a result, according to the basic idea, the performance of the semiconductor device can be improved.

[0044] Hereinafter, an embodiment that embodies the basic idea will be described. Note that the embodiment is an example that embodies the basic idea, and it is needless to say that the technical idea in this embodiment is not limited to the following-described embodiment.

[0045] <Embodiment> In the embodiment, as an example of a field-effect transistor having a diamond layer, a surface conduction type FET is cited. For example, an embodiment that embodies the basic idea will be described by taking as an example the configuration of a surface conduction type FET operating in a frequency range of GHz or higher.

[0046] Note that the technical idea in this embodiment is not limited to the surface conduction type FET operating in the high-frequency range described below. For example, in technical fields other than the high-frequency field, there is a great demand for device miniaturization. Therefore, the technical idea in this embodiment can be widely applied to surface conduction type FETs used in technical fields other than the high-frequency field.

[0047] <<T-gate structure>> In this specification, a FET that operates in the GHz or higher frequency range is called a "high-frequency FET." High-frequency FETs must satisfy two mutually conflicting requirements to improve their high-frequency characteristics. These requirements relate to the configuration of the gate electrode of a high-frequency FET. Specifically, the two mutually conflicting requirements are as follows:

[0048] (1) Shorten the gate length. This is because reducing the transit time of carriers (holes) controlled by the gate electrode contributes greatly to improving frequency characteristics. To shorten the transit time of carriers, it is important to shorten the gate length.

[0049] (2) Reducing gate resistance. Resistance is inversely proportional to the cross-sectional area. Considering this, increasing the cross-sectional area of the gate electrode is an effective way to reduce gate resistance.

[0050] The above-mentioned requirement (1) is a requirement that provides an incentive to reduce the cross-sectional area of the gate electrode. In contrast, the above-mentioned requirement (2) is a requirement that provides an incentive to increase the cross-sectional area of the gate electrode. Therefore, requirements (1) and (2) are mutually contradictory. In this regard, in order to satisfy the two mutually contradictory requirements, it is effective to configure the gate electrode using a so-called "T-gate structure." The "T-gate structure" will be explained below.

[0051] FIG. 3 is a diagram showing the configuration of the surface conduction type FET 100C.

[0052] As shown in FIG. 3, the surface-conduction FET 100C has a gate electrode 130 configured with a T-gate structure. Specifically, the gate electrode 130 has a first width portion 120A and a second width portion 120B. The width G1 of the first width portion 120A in the X direction is smaller than the width G2 of the second width portion 120B in the X direction. The first width portion 120A is formed on the gate insulating film 108. The second width portion 120B is formed on the first width portion 120A.

[0053] In the T-gate structure, the width G1 of the first width portion 120A close to the channel formation region 105 is small. Therefore, the transit time of carriers (holes) traveling directly below the first width portion 120A of the gate electrode 130 is short. Therefore, the surface-conduction FET 100C improves frequency characteristics. Furthermore, in the T-gate structure, the width G2 of the second width portion 120B is large. Therefore, the gate resistance of the gate electrode 130 can be reduced.

[0054] From the above, the surface-conduction FET 100C having the gate electrode 130 with the T-gate structure can achieve both improved frequency characteristics and reduced gate resistance. In other words, the surface-conduction FET 100C can simultaneously satisfy two contradictory requirements.

[0055] However, as shown in FIG. 3, even in the surface-conduction FET 100C, a portion of the hydrogen-termination region 103 formed on the channel-formation region 105 is exposed. As a result, the exposed hydrogen-termination region 103 is exposed to ions and the like in the atmosphere. Therefore, the ions and the like may adversely affect the channel-formation region 105 formed below the hydrogen-termination region 103. This raises concerns about fluctuations in the characteristics of the surface-conduction FET 100C.

[0056] Therefore, it is conceivable to form a surface protective film on the surface-conduction FET 100C so as to cover the source electrode 106, the drain electrode 107, and the gate electrode 130. As a result, the exposed hydrogen-termination region 103 is covered with the surface protective film. That is, the hydrogen-termination region 103 is not exposed to ions and the like in the atmosphere. In this way, by providing a surface protective film on the surface-conduction FET 100C having a T-gate structure, it is possible to prevent ions and the like in the atmosphere from adversely affecting the channel formation region 105 formed below the hydrogen-termination region 103. Therefore, by providing a surface protective film on the surface-conduction FET 100C, it is possible to reduce the occurrence of characteristic fluctuations caused by ions and the like in the atmosphere.

[0057] In this specification, a diamond device in which a surface-conduction FET 100C having a T-gate structure is provided with a surface protection film is referred to as a surface-conduction FET 100. This surface-conduction FET 100 is a novel diamond device that is of practical importance. The following describes the configuration of the surface-conduction FET 100 having a T-gate structure and a surface protection film.

[0058] <<Configuration of surface conduction FET 100>> FIG. 4 is a diagram showing the configuration of the surface conduction type FET 100. As shown in FIG.

[0059] 4, a surface conduction FET 100 has a nitrogen-doped diamond substrate 101. An undoped layer 102 is provided on the diamond substrate 101. For example, the top surface of the undoped layer 102 is a (001) plane.

[0060] Here, the diamond substrate 101 into which nitrogen is introduced is used, but the present invention is not limited to this. For example, the surface conduction FET 100 may be fabricated on a free-standing film made of the non-doped layer 102.

[0061] The non-doped layer 102 has a (001) plane. <110> The laser beam may be configured to have an off-angle (for example, 3 degrees) in the direction.

[0062] Here, the non-doped layer 102 referred to in this specification is a diamond layer in which the nitrogen impurity concentration is 10, which is the lower limit of detection of a measuring device using SIMS (Secondary Ion Mass Spectrometry). 16 / cm 3 Diamond layer having a thickness of less than 100 nm.

[0063] A hydrogen termination region 103 and an oxygen termination region 104 are formed on the surface of the non-doped layer 102. As a result, a channel formation region 105 having a two-dimensional hole gas is formed in the hydrogen termination region 103 of the non-doped layer 102.

[0064] 4, a source electrode 106 and a drain electrode 107 are disposed apart from each other on the hydrogen-terminated region 103. That is, the source electrode 106 and the drain electrode 107, which are made of gold electrodes or the like, are formed directly on the hydrogen-terminated non-doped layer 102. The source electrode 106 and the drain electrode 107 are each in ohmic contact with the hydrogen-terminated non-doped layer 102.

[0065] A contact layer may be interposed between the hydrogen-terminated non-doped layer 102 and the source electrode 106, and between the hydrogen-terminated non-doped layer 102 and the drain electrode 107. The contact layer may be, for example, a p-type impurity layer having boron introduced therein at a high concentration. + Specifically, a high concentration of boron is introduced into the contact layer so as to form an ohmic contact with the non-doped layer 102. The concentration of boron is, for example, 5×10 19 / cm 3 That's it, 1 x 10 22 / cm 3 The thickness of the contact layer is, for example, about 20 nm to 300 nm.

[0066] A gate electrode 130 is disposed on the hydrogen-terminated region 103 between the source electrode 106 and the drain electrode 107, with a gate insulating film 108 interposed therebetween. The gate electrode 130 is disposed apart from each of the source electrode 106 and the drain electrode 107.

[0067] The gate electrode 130 has a T-gate structure. Specifically, the gate electrode 130 has a first width portion 120A and a second width portion 120B. The width G1 of the first width portion 120A in the X direction is smaller than the width G2 of the second width portion 120B in the X direction. The first width portion 120A is formed on the gate insulating film 108. The second width portion 120B is formed on the first width portion 120A. In this way, by configuring the gate electrode 130 with a T-gate structure, it is possible to achieve both improved frequency characteristics and reduced gate resistance.

[0068] The electrode materials of the source electrode 106, the drain electrode 107, and the gate electrode 130 are, for example, gold (Au), ruthenium (Ru), aluminum (Al), titanium (Ti), molybdenum (Mo), copper (Cu), chromium (Cr), lead (Pb), zinc (Zn), platinum (Pt), or a combination thereof (such as Ti / Mo / Au).

[0069] The thickness of each of the source electrode 106, the drain electrode 107, and the gate electrode 130 is, for example, about 10 nm or more and 500 nm or less.

[0070] The metal films constituting the source electrode 106, the drain electrode 107, and the gate electrode 130 can be formed by physical deposition methods such as sputtering and evaporation, or chemical deposition methods such as CVD and MOCVD.

[0071] As shown in FIG. 4, a surface protective film 110 is formed to cover the source electrode 106, the drain electrode 107, and the gate electrode 130. The surface protective film 110 covers the exposed hydrogen termination region 103. That is, the surface protective film 110 is in contact with the exposed hydrogen termination region 103. This prevents the hydrogen termination region 103 from being exposed to ions in the atmosphere. In other words, the surface protective film 110 prevents ions in the atmosphere from coming into contact with the hydrogen termination region 103. This prevents the ions in the atmosphere from adversely affecting the channel formation region 105 formed below the hydrogen termination region 103.

[0072] The surface conduction FET 100 is configured as described above.

[0073] The surface-conduction FET 100 has a gate electrode 130 having a T-gate structure. Therefore, the surface-conduction FET 100 can achieve both improved frequency characteristics and reduced gate resistance. In particular, the improvement of frequency characteristics is due to the small width G1 in the X direction of the first width portion 120A of the gate electrode 130 having the T-gate structure. On the other hand, the reduction of gate resistance is due to the large width G2 in the X direction of the second width portion 120B of the gate electrode 130 having the T-gate structure.

[0074] The surface-conduction FET 100 also has a surface protection film 110 that covers the exposed hydrogen-termination region 103. This prevents the hydrogen-termination region 103 from being exposed to ions in the atmosphere. As a result, the channel-forming region 105 formed below the hydrogen-termination region 103 can be prevented from being adversely affected by ions in the atmosphere. In other words, the surface-conduction FET 100 can reduce the occurrence of characteristic fluctuations caused by ions in the atmosphere. Therefore, the surface-conduction FET 100 can improve reliability.

[0075] In a surface-conduction FET, a two-dimensional hole gas is induced in the hydrogen-terminated region of the diamond layer even when no gate voltage is applied to the gate electrode. That is, in a surface-conduction FET, a channel made of a two-dimensional hole gas is formed in the hydrogen-terminated region even when no gate voltage is applied to the gate electrode. In other words, in a surface-conduction FET, a channel made of a two-dimensional hole gas is formed in the hydrogen-terminated region even when a gate voltage of 0 V is applied to the gate electrode. For this reason, a surface-conduction FET is usually a "normally-on FET." Therefore, in the embodied embodiment, a "normally-on FET" is assumed. However, the technical concept of this embodiment is not limited to a "normally-on FET." For example, the technical concept of this embodiment can be widely applied to a "normally-off FET."

[0076] <<Operation of the surface conduction FET 100>> Next, the operation of the surface conduction FET 100 will be described.

[0077] For example, when "+3 V" is applied to the gate electrode 130, the surface-conduction FET 100 is in an off state. That is, when "+3 V" is applied to the gate electrode 130, no channel is formed in the first region P1 of the channel-forming region 105, even if a potential difference is applied between the source electrode 106 and the drain electrode 107. This is because when a positive potential of "+3 V" is applied to the gate electrode 130, a repulsive force is applied to the holes in the first region P1 of the channel-forming region 105. As a result, the hole concentration in the first region P1 decreases. This causes the channel consisting of the two-dimensional hole gas to disappear in the first region P1. Therefore, no hole current flows between the source electrode 106 and the drain electrode 107.

[0078] In contrast, when "0 V" is applied to the gate electrode 130, the repulsive force exerted by the gate electrode 130 on the holes in the first region P1 disappears. As a result, the hole concentration in the first region P1 located directly below the gate electrode 130 increases. This causes a channel due to two-dimensional electron gas to be formed not only in the second region P2 but also in the first region P1. That is, a channel is formed throughout the entire channel formation region 105, including the first region P1 and the second region P2. Therefore, while "0 V" is applied to the gate electrode 130, for example, "0 V" is applied to the source electrode 106. Furthermore, "-100 V" is applied to the drain electrode 107. As a result, a hole current flows from the source electrode 106 to the second region P2 of the channel formation region 105 to the first region P1 of the channel formation region 105 to the second region P2 of the channel formation region 105 to the drain electrode 107.

[0079] As described above, by controlling the gate voltage applied to the gate electrode 130, it is possible to realize the switching operation (ON / OFF operation) of the surface-conduction FET 100. For example, the surface-conduction FET 100 operates as a "normally-on FET."

[0080] <<Consideration for improvement>> The present inventors have been studying room for improvement that becomes apparent in the surface-conduction FET 100 having the above-described T-gate structure and the surface protective film 110. As a result, the present inventors have newly found room for improvement that becomes apparent in the surface-conduction FET 100.

[0081] The following describes novel areas for improvement.

[0082] The surface-conduction FET 100, which is a diamond device, is not easily broken down even when a high voltage is applied due to the high breakdown field of diamond. For this reason, the surface-conduction FET 100 is used, for example, in high-power applications. Therefore, in the surface-conduction FET 100, a high potential difference occurs between the gate electrode 130 and the drain electrode 107.

[0083] For example, as described in the operation of the surface-conduction FET 100, when the surface-conduction FET 100 is in the on state, "0 V" is applied to the gate electrode 130 and "-100 V" is applied to the drain electrode 107. Therefore, when the surface-conduction FET 100 is in the on state, the potential difference between the gate electrode 130 and the drain electrode 107 is "100 V." When the surface-conduction FET 100 is in the off state, "+3 V" is applied to the gate electrode 130 and "-100 V" is applied to the drain electrode 107. Therefore, when the surface-conduction FET 100 is in the off state, the potential difference between the gate electrode 130 and the drain electrode 107 is "103 V."

[0084] In this way, in the surface conduction FET 100 in which a large potential difference occurs between the gate electrode 130 and the drain electrode 107, the room for improvement newly discovered by the present inventor becomes apparent.

[0085] FIG. 5 is a diagram illustrating room for improvement.

[0086] 5, when a large voltage of, for example, about 100 V is applied between the gate electrode 130 and the drain electrode 107, there is a high possibility that dielectric breakdown will occur in the surface protection film 110 between the gate electrode 130 and the drain electrode 107. In other words, there is a possibility that dielectric breakdown will occur in the surface protection film 110 between the gate electrode 130 and the drain electrode 107 before dielectric breakdown occurs in the non-doped layer 102 made of diamond.

[0087] This is because the surface conduction FET 100 shown in FIG. 5 employs a T-gate structure. As a result, the shortest distance d (nm) between the gate electrode 130 (second width portion 120B) and the drain electrode 107 in the surface protection film 110 becomes small enough to cause dielectric breakdown. For example, the shortest distance d (nm) is about 100 nm. In other words, when the T-gate structure is employed, a phenomenon becomes apparent in which the surface protection film 110 between the gate electrode 130 and the drain electrode 107 is more likely to suffer dielectric breakdown before the non-doped layer 102 made of diamond suffers dielectric breakdown.

[0088] From the above, the inventors have newly discovered room for improvement in the surface conduction FET 100 in that, when a large voltage is applied between the gate electrode 130 and the drain electrode 107, dielectric breakdown occurs in the surface protection film 110 between the gate electrode 130 and the drain electrode 107 before dielectric breakdown occurs in the non-doped layer 102 made of diamond.

[0089] This means that the surface-conduction FET 100 will cease to function as a transistor before the inherent performance of diamond is exhibited. In other words, the dielectric breakdown occurring in the surface protection film 110 prevents operation under high voltage conditions that are only possible with diamond devices. In other words, in order to exhibit the inherent performance of the surface-conduction FET, it is desirable to find a way to overcome the room for improvement described above. Therefore, in the present embodiment, ingenuity is applied to the structural design of the surface-conduction FET 100 and the selection of materials constituting the surface protection film 110.

[0090] <<Features in Realization Mode>> In one embodiment, a design method for a semiconductor device including a surface conduction FET 100 includes the steps of designing the semiconductor device and selecting a material for the surface protection film so that the breakdown voltage of the surface protection film is greater than the breakdown voltage of the diamond layer. In particular, in the design method in one embodiment, the semiconductor device is designed and a material for the surface protection film is selected so that the breakdown voltage of the surface protection film 110 is greater than the breakdown voltage of the channel formation region of the diamond layer.

[0091] 1. Structural design of the surface conduction FET 100 FIG. 5 is an enlarged cross-sectional view of a portion of the surface conduction FET 100. As shown in FIG.

[0092] FIG. 6 is an enlarged plan view of a portion of the surface conduction FET 100. As shown in FIG.

[0093] 5 and 6, the dielectric breakdown field of the surface protection film 110 is defined as Emax(p) (V / cm). The dielectric breakdown field of the non-doped layer 102, which is a diamond layer, is defined as Emax(d) (V / cm). For example, Emax(d)=10 (MV / cm). The shortest distance between the drain electrode 107 and the gate electrode 130 in the surface protection film 110 is defined as d1 (nm). The shortest distance between the drain electrode 107 and the gate electrode 130 in the non-doped layer 102 in a plan view is defined as L1 (nm).

[0094] In this embodiment, the surface-conduction FET 100 is structurally designed so that the breakdown voltage of the surface protective film 110 is greater than the breakdown voltage of the non-doped layer 102. That is, in this embodiment, the surface-conduction FET 100 is structurally designed so that the relational expression Emax(p)×d1≧Emax(d)×L1 holds.

[0095] As a result, even if a large voltage of, for example, 100 V or more is applied between the gate electrode 130 and the drain electrode 107, it is possible to prevent breakdown in the surface protection film 110 between the gate electrode 130 and the drain electrode 107 before breakdown occurs in the non-doped layer 102 made of diamond. As a result, according to the embodiment, operation under high voltage conditions that are only possible with a diamond device can be achieved. In other words, the original performance of the surface conduction FET 100, which is a diamond device, can be exhibited.

[0096] (1) Design guidelines for "d1" Transforming the above-mentioned relational expression with respect to "d1" yields Emax(d)×L1 / Emax(p)≦d1. Furthermore, the thickness of the drain electrode 107 is defined as t (nm). Considering process constraints to prevent the step from becoming too large, d1+t≦500 nm. Generally, t≧10 nm. This results in d1≦490 nm. On the other hand, in the range of d1≦10 nm, it becomes difficult to control the leakage current that flows between the drain electrode 107 and the gate electrode 130 via the surface protective film 110.

[0097] Therefore, taking the above into consideration, the design guideline for d1 is required to satisfy 10 nm≦Emax(d)×L1 / Emax(p)≦d1≦490 nm.

[0098] (2) "L1" design guidelines When the surface-conduction FET 100 is used as a high-frequency FET that operates in a frequency range of several GHz or higher, L1≦2.4 μm is required to ensure high-frequency characteristics. Furthermore, by modifying the above-mentioned relational expression for L1, L1≦Emax(p)×d1 / Emax(d) is obtained. Therefore, L1≦Emax(p)×d1 / Emax(d)≦2.4 μm. Meanwhile, due to process constraints, L1≧30 nm is generally required.

[0099] Considering the above, the design guideline for L1 is required to satisfy 30 nm≦L1≦Emax(p)×d1 / Emax(d)≦2.4 μm.

[0100] (3) Design guidelines for the thickness of the gate insulating film 108 For example, if the breakdown voltage of the surface protective film 110 is lower than that of the gate insulating film 108, the performance of the surface conduction FET 100 will be limited by the breakdown of the surface protective film 110 before the surface conduction FET 100 can exhibit its intended performance. Therefore, the breakdown voltage of the surface protective film 110 needs to be higher than that of the gate insulating film 108.

[0101] The dielectric breakdown field of the surface protective film 110 is defined as Emax(p) (V / cm). The dielectric breakdown field of the gate insulating film 108 is defined as Emax(i) (V / cm). The shortest distance between the drain electrode 107 and the gate electrode 130 in the surface protective film 110 is defined as d1 (nm). The thickness of the gate insulating film 108 is defined as t(i) (nm).

[0102] In this embodiment, the surface-conduction FET 100 is structurally designed so that the breakdown voltage of the surface protective film 110 is greater than the breakdown voltage of the gate insulating film 108. That is, in this embodiment, the surface-conduction FET 100 is structurally designed so that the relational expression Emax(p)×d1≧Emax(i)×t(i) holds.

[0103] This makes it possible to prevent breakdown of the surface protective film 110 between the gate electrode 130 and the drain electrode 107 before breakdown of the gate insulating film occurs. As a result, according to this embodiment, the inherent performance of the surface conduction FET 100 can be exhibited.

[0104] When the above-mentioned relational expression is modified with respect to "d1," Emax(i)×t(i) / Emax(p)≦d1 is obtained. Also, d1+t(i)≦500 nm. Generally, t(i)≧10 nm. This results in d1≦490 nm. On the other hand, in the range of d1≦10 nm, it becomes difficult to control the leakage current that flows between the drain electrode 107 and the gate electrode 130 via the surface protective film 110.

[0105] Therefore, taking the above into consideration, the design guideline for d1 is required to satisfy 10 nm≦Emax(i)×t(i) / Emax(p)≦d1≦490 nm.

[0106] 2. Selection of materials for the surface protection film 110 5, a surface protection film 110 is interposed between the gate electrode 130 and the drain electrode 107. As a result, a parasitic capacitance called a gate-drain capacitance is formed between the gate electrode 130 and the drain electrode 107.

[0107] In this regard, when the surface-conduction FET 100 is used as a high-frequency FET that operates in a frequency range of several GHz or higher, the impedance between the gate electrode 130 and the drain electrode 107, which is expressed as 1 / jωC (ω=2πf: f is frequency, C: gate-drain capacitance), decreases as the frequency increases. This means that the higher the frequency of the signal, the more likely it is that the gate electrode 130 and the drain electrode 107 will be short-circuited. Furthermore, as the gate-drain capacitance increases, the impedance decreases further. Therefore, in order to prevent the high-frequency signal from short-circuiting the gate electrode 130 and the drain electrode 107, it is desirable that the gate-drain capacitance be small.

[0108] Here, the gate-drain capacitance is proportional to the relative dielectric constant of the surface protective film 110 interposed between the gate electrode 130 and the drain electrode 107. For this reason, in order to make it difficult for a high-frequency signal to short-circuit between the gate electrode 130 and the drain electrode 107, it is desirable that the relative dielectric constant of the surface protective film 110 is small. In other words, a design guideline for selecting a material for the surface protective film 110 is to select a material that has a large dielectric breakdown field and a small relative dielectric constant. For example, it is desirable to select a material for the surface protective film 110 that has a relative dielectric constant of less than 15.

[0109] Specifically, the surface protection film 110 is made of a material containing, for example, any of Al2O3, SiO2, CaF2, HfO2, AlN, BN, Si3N4, SiON, MgF2, YF3, polyimide resin, epoxy resin, and acrylic resin.

[0110] 3. Selection of materials for the gate insulating film 108 In the surface-conduction FET 100, the hydrogen-terminated region 103 formed on the surface of the non-doped layer 102 directly affects the channel. Therefore, the gate insulating film 108 in contact with the hydrogen-terminated region 103 significantly affects the electrical characteristics of the surface-conduction FET 100.

[0111] Therefore, the material used for the surface protection film 110 is not necessarily suitable for the gate insulating film 108. In other words, the material of the gate insulating film 108 is not necessarily the same as the material of the surface protection film 110, and may be different from the material of the surface protection film 110.

[0112] Specifically, the gate insulating film 108 is made of, for example, Al2O3, SiO2, CaF2, HfO2, AlN, BN, Si3N4, SiON, Ta2O5, TiO2, WO3, LaF3, MgF2, YF3, LiF, or a material containing LiF3.

[0113] <Example> A surface-conduction FET was actually fabricated based on the technical concept of the present embodiment described above. The surface-conduction FET that was actually fabricated will be described below.

[0114] Fig. 7 is a diagram showing a surface conduction FET 200 according to an embodiment. Note that Fig. 7 is not drawn to scale, taking into consideration ease of viewing the drawing. For example, Fig. 7 shows "d" < "Lgd", but in reality, "d" may be greater than "Lgd".

[0115] The surface conduction FET 200 includes a diamond substrate 101, an undoped layer 102, a source electrode 106, a source pad 106A, a drain electrode 107, a drain pad 107A, a gate insulating film 108, a surface protection film 110, and a gate electrode 130.

[0116] A hydrogen termination region 103 and an oxygen termination region 104 are formed on the surface of the non-doped layer 102. A channel formation region 105 having a hole accumulation layer is formed in the non-doped layer 102 below the hydrogen termination region 103.

[0117] The top surface of the non-doped layer 102 is the (001) plane, but may be another plane such as the (111) plane. The thickness of the non-doped layer 102 is not particularly limited, but is preferably 10 μm or less from the viewpoint of the number of steps in the manufacturing process.

[0118] The source electrode 106 and the drain electrode 107 are each made of, for example, gold (Au). The gate electrode 130 is made of, for example, copper (Cu). The gate insulating film 108 is made of, for example, calcium fluoride (CaF). The surface protective film 110 is made of, for example, aluminum oxide (AlO).

[0119] In Figure 7, for example, "Lgd" = 100 nm and "d" = 200 nm. The dielectric breakdown field Emax(d) of diamond is 10 (MV / cm). The dielectric breakdown field Emax(p) of aluminum oxide is 7.5 (MV / cm).

[0120] Therefore, Emax(p)×d=150 V and Emax(d)×Lgd=100 V. Therefore, the surface-conduction FET 200 satisfies Emax(p)×d>Emax(d)×Lgd. That is, the surface-conduction FET 200 is designed based on the design guidelines (technical concepts) of this embodiment.

[0121] Furthermore, the gate length ("Lg") and other design parameters are set appropriately. Furthermore, for example, when the material of the gate insulating film 108 is calcium fluoride and the material of the surface protective film 110 is aluminum oxide, as in the example, the thickness t(i) of the gate insulating film 108 can be set to, for example, 50 nm. This is because, in this case, Emax(p)×d≧Emax(i)×t(i) is satisfied. As described above, the design parameters of the surface conduction FET 200 in the example are set based on the design method of this embodiment.

[0122] Then, a simulation was performed based on the set parameters. As a result, it was confirmed that the surface-conduction FET 200 in this example is capable of high-frequency and high-output operation. In other words, it was confirmed that the surface-conduction FET 200 can suppress the occurrence of dielectric breakdown in the surface protection film 110 located between the gate electrode 130 and the drain electrode 107 before the non-doped layer 102 made of diamond experiences dielectric breakdown.

[0123] Therefore, by designing a surface-conduction FET based on the technical concept of this embodiment, it is possible to achieve operation under high voltage conditions that are only possible with a diamond device. In other words, it is confirmed that by adopting the design method of this embodiment, the inherent performance of the surface-conduction FET 200, which is a diamond device, can be exhibited.

[0124] Next, a method for manufacturing the surface conduction type FET 200 will be described.

[0125] (1) Preparation of diamond substrate First, as shown in FIG. 8, a diamond substrate 101 made of single-crystal diamond is prepared. The top surface of the diamond substrate 101 is then polished. For example, the top surface of the diamond substrate 101 is polished so that the surface roughness of the top surface of the diamond substrate 101 is less than 1 nm. This facilitates ensuring the flatness of the top surface of the non-doped layer 102 formed on the diamond substrate 101. As a result, the adhesion between the non-doped layer 102 and an electrode formed on the non-doped layer 102 can be improved. Furthermore, it is desirable to eliminate polishing defects. Therefore, after polishing, it is desirable to remove the polishing defects by ion beam etching (IBE). Furthermore, before forming the non-doped layer 102, it is desirable to remove organic and inorganic substances present on the top surface of the diamond substrate 101 by strong acid cleaning treatment in a clean room. This facilitates ensuring the flatness of the top surface of the non-doped layer 102 formed on the diamond substrate 101. As a result, the adhesion between the non-doped layer 102 and an electrode formed on the non-doped layer 102 can be improved.

[0126] (2) Formation of a non-doped layer Next, as shown in FIG. 9, an undoped layer 102 made of diamond is formed on the upper surface of the diamond substrate 101. The undoped layer 102 can be formed, for example, by using the MPCVD method. The conditions are, for example, CH4 / H=0.5%, no impurity added, a total gas flow rate of 500 sccm, a chamber pressure of 110 torr, a synthesis temperature of 900°C, and an input power of 1 kW. The thickness of the undoped layer 102 is approximately 0.1 μm or more and 1 μm or less. A hydrogen-terminated region 103 is formed on the surface of the undoped layer 102 thus formed. Due to the presence of this hydrogen-terminated region 103, a channel-forming region 105 made of a two-dimensional hole gas (hole accumulation layer) is formed below the hydrogen-terminated region 103.

[0127] The thickness of the non-doped layer 102 is preferably small within a range that allows for sufficient electrical properties to be obtained. This is because a thinner layer is more likely to have a flat upper surface. The surface resistance of the non-doped layer 102 is preferably, for example, 15 kΩ / □ or less. Furthermore, the surface roughness of the non-doped layer 102 is preferably small.

[0128] (3) Formation of metal film and oxygen termination region 10, a metal film 140 is formed on the hydrogen-terminated region 103. The metal film 140 can be formed by, for example, electron beam evaporation or resistance heating evaporation. The material constituting the metal film 140 is, for example, gold (Au).

[0129] Next, photolithography and etching are used to remove a portion of the metal film 140. Then, oxygen plasma treatment is used to selectively form the oxygen termination region 104 in the region where the metal film 140 has been removed. The oxygen termination region 104 functions as an element isolation region. For example, a plasma generator is used to form the oxygen termination region 104. At this time, it is desirable to form the oxygen termination region 104 in an apparatus that can increase the degree of vacuum as much as possible, from the viewpoint of improving adhesion with the surface protection film formed on the oxygen termination region 104.

[0130] (4) Formation of source and drain electrodes 11, the metal film 140 is patterned using photolithography and etching techniques, thereby forming the source electrode 106 and the drain electrode 107 that are spaced apart from each other.

[0131] (5) Patterning of resist film Next, as shown in FIG. 11 , a resist film 150 is applied onto the non-doped layer 102 on which the source electrode 106 and the drain electrode 107 have been formed. Then, the resist film 150 is patterned using photolithography. The resist film 150 is patterned to form a T-gate pattern for forming a T-gate structure. FIG. 11 schematically shows the T-gate pattern formed on the resist film 150. In practice, a plurality of resist films are stacked and each resist film is patterned differently to form the T-gate pattern.

[0132] (6) Formation of gate insulating film and gate electrode Next, as shown in FIG. 12 , a gate insulating film 108 is formed on the non-doped layer 102 exposed by the patterned resist film 150. The gate insulating film 108 is made of, for example, calcium fluoride. Then, a gate electrode 130 is formed on the gate insulating film 108. The gate electrode 130 is made of, for example, copper. The gate electrode 130 is formed using the resist film 150 with the T-gate pattern formed thereon, resulting in a T-gate structure. Both the gate insulating film 108 and the gate electrode 130 can be formed by resistance heating evaporation. In this case, forming the gate insulating film 108 and the gate electrode 130 in succession can prevent contamination during the manufacturing process. This improves adhesion between the gate insulating film 108 and the gate electrode 130.

[0133] (7) Removal of resist film and formation of surface protection film Next, the patterned resist film 150 is removed. Then, as shown in FIG. 13, a surface protective film 110 is formed to cover the source electrode 106, the drain electrode 107, and the gate electrode 130. The surface protective film 110 is made of, for example, aluminum oxide. The surface protective film 110 can be formed by, for example, atomic layer deposition (ALD). As shown in FIG. 13, the surface protective film 110 contacts the hydrogen-terminated region 103. As a result, the exposed portion of the hydrogen-terminated region 103 is covered with the surface protective film 110. As a result, the hydrogen-terminated region 103 is protected by the surface protective film 110.

[0134] (8) Formation of source and drain pads Next, as shown in FIG. 7 , source contact holes and drain contact holes are formed in the surface protection film 110 using photolithography and etching techniques. Thereafter, the source contact holes and drain contact holes are filled and a metal film is formed on the surface protection film 110 using, for example, a vapor deposition method. Subsequently, the metal film is patterned using photolithography and etching techniques. This forms a source pad 106A and a drain pad 107A. The source pad 106A is electrically connected to the source electrode 106. Meanwhile, the drain pad 107A is electrically connected to the drain electrode 107.

[0135] In this manner, the surface conduction FET 200 can be manufactured.

[0136] <Variation 1> The surface-conduction FET in the embodiment is an FET having a gate insulating film. However, the technical idea of the present embodiment is not limited to this, and can be widely applied to a surface-conduction FET not having a gate insulating film. In other words, the technical idea of the present embodiment can also be applied to a surface-conduction FET in which a gate electrode and a non-doped layer are connected by a Schottky junction.

[0137] <Variation 2> In the embodiment, for example, as shown in Fig. 6, a surface-conduction FET having a structure in which the second width portion 120B constituting a part of the gate electrode 130 and the drain electrode 107 overlap in plan view is described. However, the technical idea of the present embodiment is not limited to this, and can be widely applied to a surface-conduction FET having a structure in which the second width portion constituting a part of the gate electrode and the drain electrode do not overlap in plan view.

[0138] <Variation 3> In the embodiment, it is assumed that the surface conduction FET 100 is operated under a voltage condition in which a high voltage is applied between the gate electrode 130 and the drain electrode 107. Specifically, the voltage condition in the embodiment is a condition in which "0 V" is applied to the gate electrode 130, "0 V" to the source electrode 106, and "-100 V" to the drain electrode 107.

[0139] However, the technical idea of this embodiment is not limited to this, and can also be applied, for example, to a case where the surface-conduction FET 100 is operated under a voltage condition in which a high voltage is applied between the gate electrode 130 and the source electrode 106. For example, the technical idea of this embodiment can also be applied to a case where the surface-conduction FET 100 is operated under a voltage condition in which "0 V" is applied to the gate electrode 130, "100 V" is applied to the source electrode 106, and "0 V" is applied to the drain electrode 107.

[0140] FIG. 14 is an enlarged cross-sectional view of a portion of the surface conduction FET 100. As shown in FIG.

[0141] FIG. 15 is an enlarged plan view of a portion of the surface conduction FET 100. As shown in FIG.

[0142] 14 and 15, the breakdown field of the surface protection film 110 is defined as Emax(p) (V / cm). The breakdown field of the non-doped layer 102, which is a diamond layer, is defined as Emax(d) (V / cm). For example, Emax(d)=10 (MV / cm). The shortest distance between the source electrode 106 and the gate electrode 130 in the surface protection film 110 is defined as d2 (nm). The shortest distance between the source electrode 106 and the gate electrode 130 in the non-doped layer 102 in a plan view is defined as L2 (nm).

[0143] In this third modification, the surface-conduction FET 100 is structurally designed so that the breakdown voltage of the surface protective film 110 is greater than the breakdown voltage of the non-doped layer 102. That is, in the third modification, the surface-conduction FET 100 is structurally designed so that the relational expression Emax(p)×d2≧Emax(d)×L2 holds.

[0144] As a result, even if a large voltage of, for example, 100 V or more is applied between the gate electrode 130 and the source electrode 106, it is possible to prevent breakdown in the surface protection film 110 between the gate electrode 130 and the source electrode 106 before breakdown occurs in the non-doped layer 102 made of diamond. As a result, according to Modification 3, operation under high voltage conditions that are only possible with a diamond device can be achieved. In other words, the original performance of the surface conduction FET 100, which is a diamond device, can be exhibited.

[0145] (1) Design guidelines for "d2" Transforming the above-mentioned relational expression with respect to "d2" yields Emax(d)×L2 / Emax(p)≦d2. Furthermore, the thickness of the source electrode 106 is defined as t (nm). Considering process constraints to prevent the step from becoming too large, d2+t≦500 nm. Generally, t≧10 nm. This results in d2≦490 nm. On the other hand, in the range of d2≦10 nm, it becomes difficult to control the leakage current that flows between the source electrode 106 and the gate electrode 130 via the surface protective film 110.

[0146] Therefore, taking the above into consideration, the design guideline for d2 is required to satisfy 10 nm≦Emax(d)×L2 / Emax(p)≦d2≦490 nm.

[0147] (2) "L2" design guidelines When the surface-conduction FET 100 is used as a high-frequency FET that operates in a frequency range of several GHz or higher, L2≦2.4 μm is required to ensure high-frequency characteristics. Furthermore, by modifying the above-mentioned relational expression for L2, L2≦Emax(p)×d2 / Emax(d) is obtained. Therefore, L2≦Emax(p)×d2 / Emax(d)≦2.4 μm. Meanwhile, due to process constraints, L2≧30 nm is generally required.

[0148] Considering the above, the design guideline for L2 is required to satisfy 30 nm≦L2≦Emax(p)×d2 / Emax(d)≦2.4 μm.

[0149] <Application to electronic devices> An example of application of the semiconductor device of this embodiment to an electronic device will be described.

[0150] The semiconductor device according to the present embodiment has high potential as a semiconductor device and is expected to be applied to various electronic devices. An example of an electronic device to which the semiconductor device according to the present embodiment can be applied will be described below.

[0151] In recent years, the advancement of broadband information and communications has led to a demand for higher frequencies and higher output power in the high-frequency transistors that support communication systems. At the same time, from the perspective of energy conservation, there is also a demand for energy efficiency in high-frequency transistors. In this regard, diamond can be cited as a semiconductor material that meets the above requirements.

[0152] For example, the operating frequencies and output power of broadcasting terrestrial stations, communication satellites, and radar exceed the capabilities of current semiconductors, so vacuum tubes called traveling wave tubes are still in use, and there is a demand for improved reliability, efficiency, and miniaturization through the use of semiconductors.

[0153] Therefore, if high-frequency transistors using diamond as a semiconductor material are put into practical use, the high-frequency characteristics and high-output characteristics of communication systems including broadcasting terrestrial stations, communication satellites, radar, etc. can be dramatically improved. Therefore, using the semiconductor device of this embodiment as a high-frequency semiconductor device, which is a component of the above-mentioned communication system, is very useful from the perspective of improving the high-frequency characteristics and high-output characteristics of the communication system. In other words, the semiconductor device of this embodiment has excellent high-frequency characteristics, such as a high cutoff frequency. Therefore, by using an electronic device including the semiconductor device of this embodiment as a component of a communication system, the performance of the communication system can be improved.

[0154] Furthermore, the semiconductor device according to the present embodiment can be used in electronic devices mounted on automobiles, such as automobile sensors, thereby improving the performance of the electronic devices mounted on automobiles. As a result, the performance of the automobiles can be improved.

[0155] The invention made by the inventor has been specifically described above based on the embodiments thereof, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention. [Explanation of symbols]

[0156] 100 Surface conduction FET 100A surface conduction FET 100B surface conduction FET 100C surface conduction FET 101 Diamond substrate 102 Non-doped layer 103 Hydrogen-terminated region 104 Oxygen termination region 105 Channel formation region 106 Source electrode 106A Sauce Pad 107 Drain electrode 107A Drain Pad 108 Gate insulating film 109 Gate electrode 110 Surface protective film 120A First width section 120B 2nd width part 130 gate electrode 140 Metal Film 150 resist film 200 Surface conduction FET

Claims

1. a diamond layer including a hydrogen-terminated region; a channel formation region formed in the diamond layer; a drain electrode electrically connected to the channel formation region; a source electrode electrically connected to the channel formation region; a gate electrode formed on a portion of the hydrogen-terminated region; a surface protection film filled between the gate electrode and the drain electrode and between the gate electrode and the source electrode; A semiconductor device comprising: The surface protection film has a dielectric breakdown voltage greater than the dielectric breakdown voltage of the diamond layer.

2. 2. The semiconductor device according to claim 1, The breakdown voltage of the surface protection film is greater than the breakdown voltage of the channel formation region of the diamond layer.

3. 2. The semiconductor device according to claim 1, The surface protection film is in contact with the hydrogen-terminated region.

4. 2. The semiconductor device according to claim 1, The dielectric breakdown field of the surface protective film is Emax (p) (V / cm), The dielectric breakdown field of the diamond layer is defined as Emax (d) (V / cm), When the shortest distance between the drain electrode and the gate electrode in the surface protection film is d1 (nm) and the shortest distance between the drain electrode and the gate electrode in the diamond layer in a planar view is L1 (nm), Emax(p)×d1≧Emax(d)×L1.

5. 5. The semiconductor device according to claim 4, 10 nm≦Emax(d)×L1 / Emax(p)≦d1≦490 nm.

6. 5. The semiconductor device according to claim 4, 30 nm≦L1≦Emax(p)×d1 / Emax(d)≦2.4 μm.

7. 2. The semiconductor device according to claim 1, The dielectric breakdown field of the surface protective film is Emax (p) (V / cm), The dielectric breakdown field of the diamond layer is defined as Emax (d) (V / cm), When the shortest distance between the source electrode and the gate electrode in the surface protection film is d2 (nm) and the shortest distance between the source electrode and the gate electrode in the diamond layer in a planar view is L2 (nm), Emax(p)×d2≧Emax(d)×L2.

8. 8. The semiconductor device according to claim 7, 10 nm≦Emax(d)×L2 / Emax(p)≦d2≦490 nm.

9. 8. The semiconductor device according to claim 7, 30 nm≦L2≦Emax(p)×d2 / Emax(d)≦2.4 μm.

10. 2. The semiconductor device according to claim 1, The surface protection film has a relative dielectric constant of less than 15.

11. 11. The semiconductor device according to claim 10, The surface protection film is made of Al ２ O ３ , SiO ２ , CaF ２ , HfO ２ , AlN, BN, Si ３ N ４ , SiON, MgF ２ , Y.F. ３ , polyimide resin, epoxy resin or acrylic resin.

12. 2. The semiconductor device according to claim 1, a gate insulating film is interposed between the hydrogen termination region and the gate electrode; The breakdown voltage of the surface protection film is greater than the breakdown voltage of the gate insulating film.

13. 13. The semiconductor device according to claim 12, The gate insulating film is a film of a different type from the surface protection film.

14. 13. The semiconductor device according to claim 12, The dielectric breakdown field of the surface protective film is Emax (p) (V / cm), The dielectric breakdown field of the gate insulating film is defined as Emax(i) (V / cm), When the shortest distance between the drain electrode and the gate electrode in the surface protective film is d1 (nm) and the thickness of the gate insulating film is t(i) (nm), Emax(p)×d1≧Emax(i)×t(i).

15. 15. The semiconductor device according to claim 14, 10 nm≦Emax(i)×t(i) / Emax(p)≦d1≦490 nm.

16. 2. The semiconductor device according to claim 1, The gate electrode has a T-gate structure.

17. An electronic device comprising the semiconductor device according to claim 1.

18. a field effect transistor having a diamond layer; a surface protection film in contact with a portion of the diamond layer; A semiconductor device comprising: The surface protection film has a dielectric breakdown voltage greater than the dielectric breakdown voltage of the diamond layer.

19. A method for designing a semiconductor device including a field effect transistor having a diamond layer and a surface protection film in contact with a part of the diamond layer, comprising: The method includes a step of designing the structure of the field effect transistor and selecting a constituent material of the surface protection film so that the dielectric breakdown voltage of the surface protection film is greater than the dielectric breakdown voltage of the diamond layer.

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