Semiconductor device and manufacturing method for semiconductor device

Abstract

To provide a semiconductor device 1 enabling minute flip-chip connection with high reliability.SOLUTION: In a semiconductor device 1, semiconductor devices 10, 30 include silicon substrates 11, 31, and electrodes 12, 32 formed in the silicon substrates 11, 31. In the semiconductor devices 10, 30, organic insulating films 14, 34 are formed. In the organic insulating films 14, 34, opening parts 64, 74 for exposing the electrodes 12, 32 are formed. Outer peripheries 63, 73 of the organic insulating films 14, 34 exist inside outer peripheries 60, 70 of the semiconductor devices 10, 30. The outer peripheries 63, 73 of the organic insulating films 14, 34 are covered with mold resin.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, particularly to a semiconductor device capable of fine connection, and a method for manufacturing the same. [Background technology]

[0002] Conventionally, in typical flip-chip connections, bumps formed on a chip are connected to opposing electrodes, and then underfill is filled in. As the connection pitch becomes finer, the gap between the chip and the substrate becomes narrower, making filling difficult. For this reason, a technique has been proposed in which the bumps are covered with resin after they are formed and then ground to expose the bumps. Patent Document 1 is a document that discloses a bonding method for flip-chip type semiconductor elements related to this technique. Patent Document 1 discloses a technique in which a buried film resist is formed on one of the substrates before flip-chip connection. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 7-249732 Summary of the Invention [Problem to be solved by the invention]

[0004] The above-mentioned conventional flip chip connection in which underfill is filled has a problem that as the connection pitch becomes finer, there are portions where the underfill is not filled, which deteriorates the connection reliability.

[0005] To address this issue, flip-chip connections have been proposed, in which the bumps are covered with resin after formation and then exposed during connection. However, flip-chip connections have the problem of unstable connections and the inability to ensure connection reliability.

[0006] In semiconductor devices with low connection reliability, cracks easily occur or connections are torn apart when a force such as warping is applied.

[0007] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a semiconductor device that allows highly reliable fine flip-chip connections. [Means for solving the problem]

[0008] The semiconductor device of the present invention is a semiconductor device in which semiconductor devices are flip-chip connected to another wiring substrate, and each of the semiconductor devices comprises a silicon substrate and an electrode formed on the silicon substrate, and each of the semiconductor devices has an organic insulating film formed thereon, and an opening is formed in the organic insulating film to expose the electrode, and the outer periphery of the organic insulating film is located inside the outer periphery of the semiconductor device, and the outer periphery of the organic insulating film is covered with a mold resin. Furthermore, a method for manufacturing a semiconductor device of the present invention includes the steps of: forming an organic insulating film on one main surface of a semiconductor device having an electrode formed thereon; opening the organic insulating film on the electrode; curing the organic insulating film; filling the opened portion with metal; removing the organic insulating film from an outer periphery of the semiconductor device; cutting the semiconductor device at the portion from which the organic insulating film has been removed; aligning the cut semiconductor device with another wiring substrate and simultaneously bonding and connecting them; and sealing the outer periphery with a molding resin. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide a semiconductor device that enables highly reliable fine flip-chip connection. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention; [Figure 2] 1 is a cross-sectional view of a semiconductor device before being flip-chip bonded in a semiconductor device according to an embodiment of the present invention. [Figure 3] FIG. 10 is a diagram showing the behavior of warpage of a package substrate depending on temperature. [Figure 4] 1 is a cross-sectional view of a semiconductor device and a package substrate according to an embodiment of the present invention. [Figure 5] FIG. 1 is a cross-sectional view of a conventional semiconductor device and a package substrate. [Figure 6] FIG. 2 is a diagram showing the physical properties of an underfill material and a molding resin. [Figure 7A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7C] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7D] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7E] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7F] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7G] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7H] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7I] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8] FIG. 4 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention. [Figure 9A] 10A to 10C are cross-sectional views of a carrier substrate and the like for explaining a method for manufacturing a carrier wiring substrate according to a second embodiment of the present invention. [Figure 9B] 10A to 10C are cross-sectional views of a carrier substrate and the like for explaining a method for manufacturing a carrier wiring substrate according to a second embodiment of the present invention. [Figure 9C] 10A to 10C are cross-sectional views of a carrier substrate and the like for explaining a method for manufacturing a carrier wiring substrate according to a second embodiment of the present invention. [Figure 9D]10A to 10C are cross-sectional views of a carrier substrate and the like for explaining a method for manufacturing a carrier wiring substrate according to a second embodiment of the present invention. [Figure 10A] 5A to 5C are cross-sectional views illustrating a method for manufacturing a chip according to a second embodiment of the present invention. [Figure 10B] 5A to 5C are cross-sectional views illustrating a method for manufacturing a chip according to a second embodiment of the present invention. [Figure 10C] 5A to 5C are cross-sectional views illustrating a method for manufacturing a chip according to a second embodiment of the present invention. [Figure 10D] 5A to 5C are cross-sectional views illustrating a method for manufacturing a chip according to a second embodiment of the present invention. [Figure 11] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention. [Figure 12] FIG. 10 is a diagram showing the entire structure of a semiconductor device according to a second embodiment of the present invention. [Figure 13] FIG. 1 is a diagram showing an entire conventional semiconductor device. [Figure 14] FIG. 10 is a diagram showing the entire structure of another example of the semiconductor device according to the second embodiment of the present invention. [Figure 15] FIG. 10 is a diagram showing the entire structure of another example of a conventional semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the accompanying drawings. Fig. 1 is a cross-sectional view of a semiconductor device 1 according to an embodiment of the present invention. Fig. 2 is a cross-sectional view of a first semiconductor device 10 and a second semiconductor device 30 in the semiconductor device 1 before they are flip-chip bonded.

[0012] The semiconductor device 1 is a semiconductor device mounted on another wiring substrate. Examples of the other wiring substrate include a semiconductor device including an active element such as a semiconductor chip, a substrate with only wiring and no active element such as a silicon interposer, and a substrate with a wiring layer formed on a glass carrier. Hereinafter, the semiconductor device 1 will be described using an example in which the other wiring substrate is a semiconductor device (first semiconductor device 10).

[0013] (Semiconductor Device Overview) As shown in Fig. 1, the semiconductor device 1 is formed by flip-chip bonding a first semiconductor device 10 and a second semiconductor device 30. The semiconductor device 1 is formed by connecting the first semiconductor device 10 and the second semiconductor device 30 in the direction of arrow 200 shown in Fig. 2. The direction of arrow 200 is referred to as the connection direction 200. The first semiconductor device 10 and the second semiconductor device 30 may also be referred to as two semiconductor devices or as each semiconductor device.

[0014] (Semiconductor Devices) The semiconductor device will be described using a first semiconductor device 10 as an example. The second semiconductor device 30 has a similar configuration to the first semiconductor device 10. The first semiconductor device 10 mainly includes a first silicon substrate 11 and a first electrode 12. The first electrode 12 is not shown in FIGS. 1 and 2. The first electrode 12 is shown in FIG. 4 and other figures.

[0015] (organic insulating film) A first organic insulating film 14 and a first bump 16 are formed on one main surface 65 of the first silicon substrate 11. The direction from the main surface 65 of the first silicon substrate 11 that is perpendicular to the main surface 65 and moves away from the main surface 65 is called the upward direction. The direction of an arrow 201 shown in FIG. 1 is the upward direction 201. The upward direction 201 is similarly defined for the second silicon substrate 31. An opening 64 is formed in the first organic insulating film 14. The opening 64 is formed above the first electrode 12. The opening 64 exposes the first electrode 12 from the first organic insulating film 14.

[0016] (bump) The first bump 16 is formed inside the opening 64. The first bump 16 is electrically connected to the first electrode 12.

[0017] Referring to FIG. 2, in the first semiconductor device 10 of this embodiment, a surface 20 of the first organic insulating film 14 and a surface 21 of the first bump 16 are flat.

[0018] The structure of the second semiconductor device 30 is similar to that of the first semiconductor device 10. As shown in FIGS. 1 and 2, in the second semiconductor device 30, a second silicon substrate 31 corresponds to the first silicon substrate 11. A second electrode 32 corresponds to the first electrode 12. The second electrode 32 is not shown in FIGS. 1 and 2. The second electrode 32 is shown in FIG. 4 and the like.

[0019] Similar to the first semiconductor device 10, an organic insulating film and bumps are formed on the second semiconductor device 30. The second organic insulating film 34 corresponds to the first organic insulating film 14. The opening 74 of the second organic insulating film 34 corresponds to the opening 64 of the first organic insulating film 14. The second bump 36 corresponds to the first bump 16. The second bump 36 is electrically connected to the second electrode 32.

[0020] Referring to FIG. 2, in the second semiconductor device 30 of this embodiment, similar to the first semiconductor device 10, the surface 40 of the second organic insulating film 34 and the surface 41 of the second bump 36 are flat. (flip chip connection) The first semiconductor device 10 and the second semiconductor device 30 are flip-chip connected in a connection direction 200 with the positions of the first bumps 16 of the first semiconductor device 10 aligned with the positions of the second bumps 36 of the second semiconductor device 30.

[0021] (Openings in the organic insulating film) In the semiconductor device 1 of this embodiment, a gap in the organic insulating film is formed at the periphery of the semiconductor device. The gap in the organic insulating film refers to a portion where no organic insulating film is formed. As shown in FIGS. 1 and 2, in the first semiconductor device 10, a gap 62 in the first organic insulating film 14, where the first organic insulating film 14 is missing, is formed at the periphery 61 of the first semiconductor device 10. Here, the periphery 61 refers to the periphery region on the main surface 65 side of the first silicon substrate 11. Due to the formation of the gap 62, the periphery 63 of the first organic insulating film 14 is located inside the periphery 60 of the first semiconductor device 10. The "inward" direction is indicated by arrow 202 in FIGS. 1 and 2. The direction indicated by arrow 202 is referred to as the "inward direction."

[0022] The second semiconductor device 30 also has a hole in the organic insulating film, similar to the first semiconductor device 10. In the second semiconductor device 30, the periphery 70 of the second semiconductor device 30 corresponds to the periphery 60 of the first semiconductor device 10. The periphery 71 of the second semiconductor device 30 corresponds to the periphery 61 of the first semiconductor device 10. The hole 72 of the second organic insulating film 34 corresponds to the hole 62 of the first organic insulating film 14. The periphery 73 of the second organic insulating film 34 corresponds to the periphery 63 of the first organic insulating film 14.

[0023] The material of the organic insulating film is not particularly limited. An example of the material of the organic insulating film is photosensitive polyimide. The material of the bump is not particularly limited. An example of the material of the bump is solder or copper. The material of the first bump 16 and the material of the second bump 36 can be different. For example, the material of the first bump 16 can be copper, and the material of the second bump 36 can be solder.

[0024] In the above description, the configuration has been described in which the outer periphery 70 of the second semiconductor device 30 is located in the inward direction 202 of the outer periphery 60 of the first semiconductor device 10. The sizes, arrangements, etc. of the first semiconductor device 10 and the second semiconductor device 30 are not limited to the example described above.

[0025] (Mounting on package substrate) A case will be described in which the semiconductor device 1 is mounted on a package substrate 90 for use. Fig. 3 is a diagram showing the behavior of warpage of the package substrate 90 depending on temperature. The horizontal axis X of the graph shown in Fig. 3 represents time (seconds), and the vertical axis Y represents temperature (°C).

[0026] The semiconductor device 1 mounted on the package substrate 90 is called a package 120. As shown in FIG. 3, the semiconductor device 1 is mounted on the package substrate 90 via package bumps 91. A package sealant 92 is disposed in the region between the semiconductor device 1 and the package substrate 90 and on at least a part of the outer periphery 2 of the semiconductor device 1. The outer periphery 2 of the semiconductor device 1 refers to the outermost parts of the components that make up the semiconductor device 1, such as the first semiconductor device 10, the second semiconductor device 30, and the molded resin part 50.

[0027] For example, when heat is applied to package substrate 90 during a reflow process, the warpage behavior of package substrate 90 changes. The diagrams indicated by arrows 110 to 114 in Figure 3 show the state of package 120 from box 100 to box 104 on the graph, respectively. As package substrate 90 continues to cool from box 104 (see arrow 105), and is cooled to room temperature, e.g., 25°C, it returns to the warpage state indicated by arrow 110.

[0028] 3, a force is applied to the semiconductor device 1. This force can cause defects in the semiconductor device 1.

[0029] 4, a force applied to the semiconductor device 1 due to warpage when the semiconductor device 1 is mounted on the package substrate 90 by a process involving heating such as reflow will be described. FIG. 4 is a cross-sectional view of the semiconductor device 1 and the package substrate 90.

[0030] (Configuration of semiconductor device) Before describing the force due to warping, we will explain the configuration of the semiconductor device 1, which is not shown in Figures 1 and 2. As shown in Figure 4, a first electrode 12 is formed on a main surface 65 of the first silicon substrate 11. Similarly, a second electrode 32 is formed on a main surface 75 of the second silicon substrate 31.

[0031] A first oxide film 13 is formed on a main surface 65 of the first silicon substrate 11. Similarly, a second oxide film 33 is formed on a main surface 75 of the second silicon substrate 31. An opening 22 is formed in the first oxide film 13. The opening 22 is formed above the first electrode 12. An opening 64 exposes the first electrode 12 from the first oxide film 13. Similarly, an opening 42 is formed in the second oxide film 33. The opening 42 is formed above the second electrode 32. The opening 42 exposes the second electrode 32 from the second oxide film 33.

[0032] A first metal film 15 is formed on the surface of the first electrode 12 exposed by the opening 22 in the first oxide film 13, the inner surface of the opening 22, and the inner surface of the opening 64 in the first organic insulating film 14. Similarly, a second metal film 35 is formed on the surface of the second electrode 32 exposed by the opening 42 in the second oxide film 33, the inner surface of the opening 42, and the inner surface of the opening 74 in the second organic insulating film 34.

[0033] The first metal film 15 and the second metal film 35 function as, for example, a seed layer for plating. Plating is used when filling each opening with a metal for a bump.

[0034] 1 and 2, the first bump 16 is formed inside the opening 64 of the first organic insulating film 14. Similarly, the second bump 36 is formed inside the opening 74 of the second organic insulating film 34. The first organic insulating film 14 is formed between the first bumps 16 and 16, etc. Similarly, the second organic insulating film 34 is formed between the second bumps 36 and 36.

[0035] (Molded resin part) After flip-chip bonding, the semiconductor device 1 is molded with a mold resin. The portion where the mold resin is disposed is called a mold resin portion 50. In the example shown in FIG. 4, the mold resin portion 50 covers the outer periphery 70 of the second semiconductor device 30, the outer periphery 73 of the second organic insulating film 34, and the outer periphery 63 of the first organic insulating film 14. The mold resin portion 50 also covers the outer periphery 70 of the second semiconductor device 30. The outer periphery 54 of the mold resin portion 50 and the outer periphery 60 of the first semiconductor device 10 are flat.

[0036] (force due to warping) The force due to warping will now be explained. As shown in FIG. 3, the state of warping of the package substrate 90 changes depending on the temperature of the package substrate 90. For example, when the package substrate 90 is cooled from a high temperature of 200°C or higher to room temperature, the package substrate 90 warps in the direction of arrow 203 shown in FIG. 4. As a result, a force that warps the semiconductor device 1 in the direction of arrow 204 is applied to the semiconductor device 1. Arrow 205 in FIG. 4 indicates a corner 205 of the second semiconductor device 30 on the first semiconductor device 10 side. The force that warps the semiconductor device 1 in the direction of arrow 204 is likely to be applied to the corner 205 of the second semiconductor device 30 on the first semiconductor device 10 side.

[0037] In the semiconductor device 1 of this embodiment, a hole 72 is formed in the second organic insulating film 34. The hole 72 is filled with a mold resin. In the mold resin portion 50, the portion of the hole 72 filled with the mold resin is called the second insulating film side filling portion 52 of the mold resin portion 50. Because the second insulating film side filling portion 52 is formed, the corner 205 of the second semiconductor device 30 is covered with the mold resin. As a result, defects are less likely to spread from the corner 205 of the second semiconductor device 30. This makes it possible to achieve highly reliable flip-chip connections. Therefore, in the present invention, it is particularly important that the hole 72 is formed in the second organic insulating film 34.

[0038] Furthermore, in the semiconductor device 1 of this embodiment, a hole 62 is formed in the first organic insulating film 14. The hole 62 is filled with molding resin. In the molding resin portion 50, the portion where the hole 62 is filled with molding resin is called the first insulating film side surface filling portion 51 of the molding resin portion 50. Because the first insulating film side surface filling portion 51 is formed, a sufficient amount of molding resin is disposed at the corner 206 of the first semiconductor device 10 on the side of the second semiconductor device 30. As a result, defects are less likely to spread from the corner 206 of the first semiconductor device 10. This makes it possible to achieve highly reliable flip-chip connections.

[0039] (Molding resin and organic insulating film) The dispersion of force applied to the corner 205 due to warpage of the package substrate 90 will be described in relation to the presence or absence of a hole in the organic insulating film. As shown in FIG. 4 , the semiconductor device 1 of this embodiment has a hole 72 formed in the second organic insulating film 34. A second insulating film side filling portion 52 is formed in the hole 72. The outer periphery 70 of the second semiconductor device 30 is covered with the molded resin portion 50. Therefore, the corner 205 is covered with the molded resin portion 50. On the other hand, if the hole 72 in the second organic insulating film 34 is not formed, the second organic insulating film 34 will be disposed at the corner 205.

[0040] (flexural modulus) The material forming the mold resin part 50 has a higher flexural modulus than the material forming the organic insulating film. Therefore, in the semiconductor device 1 of this embodiment, the force applied to the corner 205 is more easily dispersed than in a case where the missing portion 72 of the second organic insulating film 34 is not formed and the second organic insulating film 34 is disposed at the corner 205.

[0041] (coefficient of thermal expansion) Furthermore, the material forming the mold resin portion 50 has a smaller thermal expansion coefficient than the material forming the organic insulating film. Therefore, in the semiconductor device 1 of this embodiment, thermal stress is less likely to be applied to the corners 205 than in a case where the missing portions 72 of the second organic insulating film 34 are not formed and the second organic insulating film 34 is disposed at the corners 205.

[0042] For the reasons described above, connection defects such as cracks in the bumps are less likely to occur in the semiconductor device 1 of this embodiment, and the semiconductor device 1 of this embodiment can provide highly reliable flip chip connections.

[0043] (Molding compound and underfill) The distribution of force applied to corner 205 due to warpage of package substrate 90 will be described in comparison with a conventional semiconductor device 300 in which underfill 81 is disposed. First, the configuration of conventional semiconductor device 300 will be described with reference to FIG. 5. FIG. 5 is a cross-sectional view of the conventional semiconductor device and package substrate. The conventional semiconductor device 300 will be described, focusing on differences from the semiconductor device 1 of this embodiment shown in FIG. 4.

[0044] (underfill) In the semiconductor device 1 of this embodiment, an organic insulating film is disposed in the area between the first semiconductor device 10 and the second semiconductor device 30, except for the bumps. In contrast, in the conventional semiconductor device 300, an underfill 81 is disposed in the area between the first semiconductor device 10 and the second semiconductor device 30, except for the bumps.

[0045] 5, the first bump 16 and the second bump 36 are connected via solder 80. The underfill 81 is arranged in the region sandwiched between the first semiconductor device 10 and the second semiconductor device 30 so as to fill in the portions where the first bump 16, the second bump 36, and the solder 80 are not present.

[0046] The underfill 81 includes a device facing portion 82, a wetting portion 83, and a wetting spreading portion 84. The device facing portion 82 is a portion of the underfill 81 that is located between the first semiconductor device 10 and the second semiconductor device 30. The wetting portion 83 is a portion of the underfill 81 that covers the outer periphery 70 of the second semiconductor device 30. The wetting portion 83 is also called a fillet. The wetting spreading portion 84 is a portion of the underfill 81 that covers the first semiconductor device 10 that does not face the second semiconductor device 30.

[0047] As described above, the underfill 81 includes the device-facing portion 82, the wetting-up portion 83, and the wetting-spreading portion 84. Therefore, in the conventional semiconductor device 300, the corner portion 205 of the second semiconductor device 30 is covered with the underfill 81.

[0048] The case where force is applied to the corner 205 of the semiconductor device 1 of this embodiment and the case where force is applied to the corner 205 of the conventional semiconductor device 300 shown in FIG. 5 will be compared from the viewpoint of material properties.

[0049] (Material properties) Fig. 6 is a diagram showing the physical properties of the underfill material that forms the underfill 81 and the mold resin that forms the mold resin portion 50. Fig. 6 shows the physical properties of epoxy resin as an example of the underfill material and the mold resin.

[0050] 4, the corners 205 of the semiconductor device 1 of this embodiment are covered with the mold resin part 50. As shown in FIG. 5, the corners 205 of the conventional semiconductor device 300 are covered with the underfill 81.

[0051] (flexural modulus) As shown in FIG. 6, the flexural modulus of the mold resin is higher than that of the underfill material. Therefore, the force applied to the corner 205 of the semiconductor device 1 of this embodiment is easily dispersed in the mold resin portion 50. As a result, poor connection is less likely to occur. In contrast, the flexural modulus of the underfill material is lower than that of the mold resin. Therefore, the force applied to the corner 205 of the conventional semiconductor device 300 is likely to cause the underfill 81 to cleave.

[0052] 5, the propagation of a force applied to a corner 205 in a conventional semiconductor device 300 will be described. When a force due to warping of the package substrate 90 is applied to the corner 205, the force propagates in the direction from arrow 210 to arrow 212. The direction of arrow 210 is a direction from the corner 205 toward the center in the distance direction between the first semiconductor device 10 and the second semiconductor device 30. The direction of arrow 211 is a direction proceeding from the corner 205 along the surface of the second semiconductor device 30. The direction of arrow 212 is a direction proceeding from the corner 205 along the outer periphery 70 of the second semiconductor device 30.

[0053] In the conventional semiconductor device 300, the underfill material has a low modulus of elasticity. Therefore, stress directed in the outward direction 207, which occurs when the semiconductor device 300 is warped in the direction of arrow 203, is difficult to alleviate. As a result, the underfill 81 is likely to crack in the direction indicated by arrows 210 and 212. Furthermore, the stress applied near the end 215 of the first oxide film 13 becomes large, which may cause cracks to form near the outer periphery 60 of the first semiconductor device. As described above, the reliability of the conventional semiconductor device 300 is low.

[0054] (coefficient of thermal expansion) 6, the thermal expansion coefficient of the mold resin is smaller than that of the underfill material. Therefore, in the semiconductor device 1 of this embodiment, in which the corners 205 are covered with the mold resin portion 50, thermal stress is less likely to be applied to the corners 205 than in the conventional semiconductor device 300, in which the corners 205 are covered with the underfill 81. In particular, the thermal expansion coefficients of the mold resin are smaller than those of the underfill material, not only in terms of thermal expansion coefficient α1 (the thermal expansion coefficient in a temperature range below the glass transition temperature) but also in terms of thermal expansion coefficient α2 (the thermal expansion coefficient in a temperature range above the glass transition temperature) in the temperature range in which the resin expands or contracts significantly. Therefore, the corners 205 are less likely to be subjected to thermal stress in the mold resin than in the underfill material.

[0055] Furthermore, the difference in thermal expansion coefficient between the molding resin and the silicon substrate is smaller than the difference in thermal expansion coefficient between the underfill material and the silicon substrate, making it less likely that cracks will occur due to the difference in thermal expansion coefficient between the resin and silicon.

[0056] As described above, the molding resin has a high flexural modulus and a small thermal expansion coefficient, which suppresses the spread of defects in the molding resin part 50. As a result, the semiconductor device 1 of this embodiment is less susceptible to connection defects such as cracks in the bumps. The semiconductor device 1 of this embodiment can provide highly reliable flip-chip connections.

[0057] (flatness) 2, in the first semiconductor device 10 of this embodiment, the surface 20 of the first organic insulating film 14 and the surface 21 of the first bump 16 are flat. Similarly, in the second semiconductor device 30, the surface 40 of the second organic insulating film 34 and the surface 41 of the second bump 36 are flat. This improves the adhesion between the first semiconductor device 10 and the second semiconductor device 30. As a result, the semiconductor device 1 of this embodiment can provide a semiconductor device that enables highly reliable fine flip-chip connection.

[0058] Note that "flat" does not only mean that the surface 20 of the first organic insulating film 14 and the surface 21 of the first bump 16 are flush with each other, or that the surface 40 of the second organic insulating film 34 and the surface 41 of the second bump 36 are flush with each other. For example, even if there is a slight difference in level between the surface of the organic insulating film and the surface of the bump, the surface of the organic insulating film and the surface of the bump can be said to be flat as long as the difference in level is not enough to cause mounting defects in the subsequent mounting step.

[0059] When mounting is performed by flip-chip bonding, the organic insulating film is deformed by the heat and load applied during bonding. Therefore, even if there is a slight step between the surface of the organic insulating film and the surface of the bump, the step is absorbed during flip-chip bonding, allowing connection at the bump surface. Therefore, when the surface of the organic insulating film and the surface of the bump are flat, it means that there is no step that exceeds the step that can be absorbed during flip-chip bonding. In other words, a concave level that can be absorbed by flip-chip bonding can be considered flat.

[0060] An example of a concave level that can be absorbed by flip-chip bonding is a shape in which the surface of the bump is recessed below the surface of the organic insulating film after chemical mechanical polishing (CMP). This shape is also called a dish. The height of the dish can be between 10 nm and 150 nm, depending on the metal type and conditions of the bump. Even when such a dish exists, the surface of the organic insulating film and the surface of the bump can be said to be flat.

[0061] (Method of manufacturing a semiconductor device) A method for manufacturing the semiconductor device 1 of this embodiment will be described with reference to Figures 7A to 7I. Figures 7A to 7I are cross-sectional views of a silicon substrate, etc. Figures 7A to 7I show the manufacturing process of the semiconductor device 1 in order from Figure 7A.

[0062] Hereinafter, a method for manufacturing the semiconductor device 1 will be described using the second semiconductor device 30 as an example. The method for manufacturing the first semiconductor device 10 is the same as the method for manufacturing the second semiconductor device 30. In FIGS. 7A to 7I, the portion that will become the first semiconductor device 10, even if it is incomplete, is indicated by the reference numeral 10. Similarly, the portion that will become the second semiconductor device 30, even if it is incomplete, is indicated by the reference numeral 30. The arrow 201 shown in FIG. 7A etc. indicates the upward direction 201, as in FIG. 1 etc.

[0063] (silicon wafer) 7A, a second electrode 32 and a second oxide film 33 are formed in this order on a main surface 75 of a second silicon substrate 31. Then, an opening 42 for exposing the second electrode 32 is formed in the second oxide film 33.

[0064] (Polyimide coating) 7B, a second organic insulating film 34 is formed on the second oxide film 33 and the exposed second electrode 32. The material of the second organic insulating film 34 can be, for example, photosensitive polyimide.

[0065] (Polyimide opening and sputtering) As shown in FIG. 7C , an opening 74 for exposing the second electrode 32 is formed in the second organic insulating film 34. The opening 74 can be formed using an exposure and development process. Next, a second metal film 35 is formed on the entire surface of the exposed portion on the upward direction 201 side of the second silicon substrate 31. The second metal film 35 can be formed by, for example, sputtering. The second metal film 35 can be used as a seed electrode when forming bumps by plating.

[0066] (Full plating) As shown in FIG. 7D, in the second semiconductor device 30, plating is performed on the entire surface of the second metal film 35. The plating is performed so as to cover the second organic insulating film 34. The plating metal is solder. The formed plating layer is called a second bump metal layer 37.

[0067] In the first semiconductor device 10, which has been fabricated in the same manner as the second semiconductor device 30, plating is performed on the entire surface of the first metal film 15. The plating is performed so as to cover the first organic insulating film 14. The plating metal is copper. The formed plating layer is called a first bump metal layer 17.

[0068] (Chemical mechanical polishing (CMP)) As shown in FIG. 7E, in the first semiconductor device 10, the first bump metal layer 17 is polished by CMP. In the second semiconductor device 30, the second bump metal layer 37 is polished by CMP. This polishing forms the first bump 16 and the second bump 36. Furthermore, by polishing, the surface 20 of the first organic insulating film 14 and the surface 21 of the first bump 16 are flattened in the first semiconductor device 10. In the second semiconductor device 30, the surface 40 of the second organic insulating film and the surface 41 of the second bump 36 are flattened.

[0069] In CMP, the polishing end position can be determined by utilizing the difference in polishing rate between the organic insulating film and the bump metal layer.

[0070] (Laser grooving and dicing) 7F, in the first semiconductor device 10, the first organic insulating film 14 located in the outer periphery 61 of the first semiconductor device 10 is removed by laser grooving. As a result, a missing portion 62 of the first organic insulating film 14 where the first organic insulating film 14 is not present is formed in the outer periphery 61 of the first semiconductor device 10.

[0071] Similarly, in the second semiconductor device 30, the second organic insulating film 34 located in the outer periphery 71 of the second semiconductor device 30 is removed by laser grooving. As a result, the second organic insulating film 34 is removed in the outer periphery 61 of the second semiconductor device 30, and a missing portion 72 of the second organic insulating film 34, which is a portion where the second organic insulating film 34 does not exist, is formed.

[0072] Next, the second semiconductor device 30 is diced to produce chips. Dicing can be performed using, for example, a blade 130. In the above description, the holes in the organic insulating film were formed by laser grooving. The method for forming the holes in the organic insulating film is not limited to laser grooving. The holes in the organic insulating film can also be formed by cutting away the organic insulating film located on the periphery of the semiconductor device during dicing.

[0073] (flip chip connection) As shown in FIG. 7G, the first semiconductor device 10 and the second semiconductor device 30 are flip-chip bonded together.

[0074] (Molding and backside grinding) 7H, the flip-chip bonded first semiconductor device 10 and second semiconductor device 30 are molded with molding resin 50. By molding, molding resin part 50 including first insulating film side filling part 51 and second insulating film side filling part 52 is formed.

[0075] Subsequently, the backside portion 53 of the mold resin portion 50 located on the rear surface 76 side of the second silicon substrate 31 is removed by grinding.

[0076] (Singulation) 7I, singulation is performed by, for example, dicing to cut out the packages, that is, the semiconductor devices 1. In this manner, the semiconductor device 1 can be manufactured.

[0077] (Second embodiment) Regarding the semiconductor device 1 of the present invention, an embodiment different from the embodiment described above will be described. Hereinafter, the embodiment described above will be referred to as the first embodiment, and the embodiment described below will be referred to as the second embodiment. In the following explanation, differences from the first embodiment will be mainly described. Items not specifically described for the second embodiment can be the same as those for the first embodiment.

[0078] FIG. 8 is a cross-sectional view of a semiconductor device 100 according to a second embodiment of the present invention. In the semiconductor device 1 according to the first embodiment, as shown in FIG. 1, one second semiconductor device 30 is flip-chip connected to a first semiconductor device 10 serving as another wiring substrate. In contrast, in the semiconductor device 100 according to the second embodiment, as shown in FIG. 8, multiple second semiconductor devices 30 are flip-chip connected to another wiring substrate. Examples of other wiring substrates include semiconductor devices including active elements such as semiconductor elements, substrates containing only wiring without active elements such as silicon interposers, and substrates in which a wiring layer is formed on a glass carrier. Below, the semiconductor device 100 will be described in order, taking as an example a case in which the wiring substrate is a carrier wiring substrate 110.

[0079] (First chip and second chip) First, the second semiconductor device 30 in the second embodiment will be described. In the second embodiment, a plurality of second semiconductor devices 30 are connected to a carrier wiring substrate 110. In the following description, attention will be focused on two of the plurality of second semiconductor devices 30. The two second semiconductor devices 30 of interest will be referred to as a first chip 30A and a second chip 30B. The first chip 30A and the second chip 30B have the same structure as the second semiconductor device 30 described in the first embodiment. In the following description and drawings, for the components described for the second semiconductor device 30 in the first embodiment, the components of the first chip 30A will be marked with an A. Similarly, the components of the second chip 30B will be marked with a B. Note that the number of second semiconductor devices 30 connected to the carrier wiring substrate 110 is not limited to two.

[0080] (carrier wiring board) The carrier wiring substrate 110 will be described. The carrier wiring substrate 110 includes a carrier substrate 160 and a wiring layer 166 formed on the carrier substrate 160. Note that in the second embodiment, as in the first embodiment, the direction indicated by the arrow 201 is the upward direction.

[0081] (carrier board) The carrier substrate 160 can be formed of, for example, a glass substrate or a silicon substrate, etc. The carrier substrate 160 is removed after the semiconductor device 30 is connected to the carrier wiring substrate 110.

[0082] (wiring layer) Wiring layer 166 includes electrode layer 162 and insulating layer 164. After carrier substrate 160 is removed, first chip 30A and second chip 30B connected to carrier wiring substrate 110 are mounted on an organic substrate or the like via wiring layer 166. At this time, wiring layer 166 functions as a rewiring layer for electrically connecting first chip 30A or second chip 30B to the organic substrate.

[0083] (insulating layer) The insulating layer 164 can be formed of, for example, polyimide or polybenzoxazole. Wiring (not shown) is formed in the insulating layer 164. The wiring formed in the insulating layer 164 is drawn out to the two main surfaces, the upper and lower surfaces, of the insulating layer 164.

[0084] (electrode layer) The electrode layer 162 is a layer on which electrodes are formed on the wiring layer 166 side when the carrier substrate 160 is removed and the wiring layer 166 is mounted on an organic substrate or the like. The wiring layer 166 and the organic substrate or the like are connected, for example, by BGA. Electrodes are formed on the electrode layer 162 in a form corresponding to the solder balls in BGA connection, for example.

[0085] As in the first embodiment, a first organic insulating film 14 and a first bump 16 are formed on the wiring layer 166. The first bump 16 is disposed at a position corresponding to a wiring (electrode) drawn out to the upper main surface of the insulating layer 164.

[0086] (Connection between chip and carrier wiring board) The connection between the first chip 30A and the second chip 30B and the carrier wiring substrate 110 will be described. As shown in FIG. 8 , the second bumps 36A of the first chip 30A and the second bumps 36B of the second chip 30B are connected to the first bumps 16 of the carrier wiring substrate 110. Furthermore, the second organic insulating film 34A of the first chip 30A and the second organic insulating film 34B of the second chip 30B are connected to the first organic insulating film 14 of the carrier wiring substrate 110. In this manner, the first chip 30A and the second chip 30B are flip-chip connected to the carrier wiring substrate 110 in the same manner as the second semiconductor device 30 of the first embodiment.

[0087] (Chip proximity) The arrangement of the first chip 30A and the second chip 30B will be described. The double-headed arrow 221 in FIG. 8 refers to the first arrangement direction 221 of the first chip 30A and the second chip 30B. In the semiconductor device 100 of the second embodiment, the adjacent first chip 30A and the second chip 30B are arranged close to each other in the first arrangement direction 221. Distance D1 in FIG. 8 indicates the distance D1 in the first arrangement direction 221 between the second silicon substrate 31A of the first chip 30A and the second silicon substrate 31B of the second chip 30B. Distance D2 in FIG. 8 indicates the distance D2 in the first arrangement direction 221 between the second organic insulating film 34A of the first chip 30A and the second organic insulating film 34B of the second chip 30B. Distance D1 is shorter than distance D2. In other words, the distance between the silicon substrates of adjacent chips is shorter than the distance between the organic insulating films of adjacent chips. The distance D1 can be, for example, less than 50 μm, or even 10 μm or less.

[0088] This allows for extremely high-density arrangement of chips on the carrier wiring substrate 110 in a semiconductor device in which multiple chips are arranged in parallel. Furthermore, by arranging multiple chips closely together, finer pitches for wiring or electrodes become possible. This allows for the shortest possible distance between connections between adjacent chips, enabling high-speed transmission.

[0089] 8, in the second embodiment, the second organic insulating film 34 (34A, 34B) has a missing portion 72A and a missing portion 72B formed at the outer periphery 71A and the outer periphery 71B of the second semiconductor device. This allows the semiconductor device 100 of the second embodiment to achieve a highly reliable flip-chip connection, similar to the semiconductor device 1 of the first embodiment. The semiconductor device 100 after flip-chip connection may be molded with a molding resin, similar to the first embodiment. The outer peripheries of the second organic insulating films 34A and 34B may be covered with a molding resin.

[0090] (Method for manufacturing the semiconductor device according to the second embodiment) A method for manufacturing the semiconductor device 100 of the second embodiment will be described below. In the following description, explanations of the same parts as in the method for manufacturing the semiconductor device 1 of the first embodiment will be omitted.

[0091] (Manufacturing method of carrier wiring board) 9A to 9D, a method for manufacturing the carrier wiring substrate 110 will be described. Figures 9A to 9D are cross-sectional views of the carrier substrate 160 and the like for explaining the method for manufacturing the carrier wiring substrate 110 of this embodiment.

[0092] 9A, a substrate is prepared in which an electrode layer 162, an insulating layer 164, and a first organic insulating film layer 14 are formed on one main surface of a carrier substrate 160. The electrodes included in the electrode layer 162 may be made of copper, for example. The electrodes may be arranged in a manner that corresponds to, for example, BGA connection.

[0093] The insulating layer 164 can be formed mainly from an insulating material such as polyimide, polybenzoxazole, etc. Furthermore, the insulating layer 164 can be formed with through vias and wiring, etc., as needed.

[0094] The first organic insulating film layer 14 can be formed in the same manner as in the first embodiment.

[0095] Next, as shown in FIG. 9B , openings 64 of the first organic insulating film are formed in the first organic insulating film 14. Electrodes (not shown) arranged on the surface of the insulating layer 164 are exposed through the openings 64 of the first organic insulating film. The openings 64 of the first organic insulating film can be formed using an exposure and development process. The openings 64 of the first organic insulating film are formed at positions corresponding to the electrode arrangement of chips to be connected to the carrier wiring substrate 110 later. In this embodiment, at least two chips are arranged closely to each other on the carrier wiring substrate 110. Therefore, an inter-chip portion 142 of the first organic insulating film that is long in the first arrangement direction 221 may be formed between the position where the first chip 30A is connected and the position where the second chip 30B is connected.

[0096] 9C, plating is then performed on the entire surface of the first organic insulating film 14 and the opening 64 in the first organic insulating film. This forms a first bump metal layer 17 that fills the opening 64 in the first organic insulating film and covers the first organic insulating film 14. Note that, before plating, a seed electrode may be formed on the inner surface of the opening 64 in the first organic insulating film and on the surface of the first organic insulating film 14 by, for example, sputtering.

[0097] 9D, the first bump metal layer 17 is polished by CMP. This polishing removes the first bump metal layer 17 on the first organic insulating film 14, forming the first bumps 16. In this way, the carrier wiring substrate 110 is prepared.

[0098] (Chip manufacturing method) Next, a method for manufacturing a chip will be described with reference to Figures 10A to 10D. Figures 10A to 10D are cross-sectional views of the second silicon substrate 31A and the like for explaining the method for manufacturing the first chip 30A. In the following explanation, the method for manufacturing the chip will be explained using the first chip 30A as an example. The second chip 30B can also be manufactured in the same manner as the first chip 30A.

[0099] 10A, a second organic insulating film 34 is formed on one main surface of a second silicon substrate 31A. At this time, similarly to the first embodiment, a hole 72A is formed in the second organic insulating film at a peripheral portion 71A of the second semiconductor device.

[0100] Next, as shown in FIG. 10B, an opening 74 of the second organic insulating film is formed in the second organic insulating film 34A. An electrode (not shown) arranged on the surface of the second silicon substrate 31A is exposed from the opening 74 of the second organic insulating film. The opening 74 of the organic insulating film can be formed using an exposure and development process. Thereafter, the organic insulating film is hardened.

[0101] 10C, plating is performed on the entire surface of the second organic insulating film 34A and the opening 74 in the second organic insulating film. This forms a second bump metal layer 37 that fills the opening 74 in the second organic insulating film and covers the second organic insulating film 34A. Note that, before plating, a seed electrode may be formed by, for example, sputtering on the inner surface of the opening 74 in the second organic insulating film and on the surface of the second organic insulating film 34A.

[0102] In this way, the chip preparation process for preparing a chip includes a film formation process for forming an organic insulating film on one main surface of the chip on which an electrode is formed, an opening process for opening the organic insulating film on the electrode, a curing process for curing the organic insulating film, a filling process for filling the opened portion with metal, and a peripheral removal process for removing the organic insulating film from the peripheral part of the chip.The peripheral removal process may be performed at any timing, such as between the film formation process and the opening process, between the opening process and the curing process, between the curing process and the filling process, or after the filling process, and regardless of the timing at which it is performed, it is included in the above-mentioned chip preparation process.

[0103] Next, as shown in Fig. 10D, the second bump metal layer 37 is polished by CMP. This polishing removes the second bump metal layer 37 on the second organic insulating film 34A, and forms the second bumps 36. In this way, the first chip 30A is prepared. The second chip 30B can be prepared in a similar manner.

[0104] Next, flip-chip connection will be described with reference to FIG. 11. FIG. 11 is a diagram showing how a first chip 30A and a second chip 30B are flip-chip connected to a carrier wiring substrate 110. As shown in FIG. 11, the first chip 30A and the second chip 30B are connected to the carrier wiring substrate 110 at positions adjacent to each other in a first arrangement direction 221. During connection, as in the first embodiment, the second bumps 36A and 36B are aligned with the first bumps 16. Furthermore, the second organic insulating films 34A and 34B are arranged to be in contact with the first organic insulating film 14. For example, the second bumps 36A and the first bumps 16 of the first chip 30A are aligned, their opposing surfaces are brought into contact, and they are simultaneously bonded and connected by heat and load, and then the second bumps 36B and the first bumps 16 of the second chip 30B are aligned, their opposing surfaces are brought into contact, and they are simultaneously bonded and connected by heat and load, and the first chip 30A and the second chip 30B are mounted with almost no gap between them. In this way, the semiconductor device 100 of the second embodiment is manufactured.

[0105] An example of the overall structure of the semiconductor device 100 of the second embodiment will be described with reference to Figures 12 and 13. Figure 12 is a diagram showing an example of the overall structure of the semiconductor device 100 of the second embodiment. Figure 13 is a diagram showing an example of the overall structure of a conventional semiconductor device 200. Arrows 222 in Figures 12 and 13 indicate a second arrangement direction 222. The second arrangement direction 222 is a direction perpendicular to the first arrangement direction 221.

[0106] 12, in the semiconductor device 100 of this embodiment, adjacent second semiconductor devices 30 are connected to the carrier wiring substrate 110 in a close proximity not only in the first arrangement direction 221 described with reference to Fig. 8 but also in the second arrangement direction 222. Therefore, the second semiconductor devices 30, i.e., chips, can be arranged on the carrier wiring substrate 110 at high density.

[0107] On the other hand, in the conventional semiconductor device 200 shown in FIG. 13 , it is difficult to densely arrange chips 230 on a substrate 210 such as a carrier wiring substrate. In the conventional semiconductor device 200, when multiple chips 230 are connected to the substrate 210 in a matrix, at least one margin for filling with underfill is required for each chip. For example, if the chip 230 is rectangular, this "at least one margin" refers to one side of a rectangle observed when the chip 230 is viewed perpendicular to one main surface of the substrate 210. The dashed-line box 240 in FIG. 13 indicates the margin required for filling with underfill. This margin is called the underfill application area 240. The width of the underfill application area 240 in the second arrangement direction 222 shown in FIG. 13 is typically 50 μm or more. In the conventional semiconductor device 200, the need for the underfill application area 240 makes it difficult to arrange adjacent chips 230 in close proximity, as shown by chips 231 and 232. Therefore, in the conventional semiconductor device 200, it is difficult to arrange chips at high density.

[0108] Another arrangement of chips will now be described. FIG. 14 is a view of the semiconductor device 100 of this embodiment, viewed in a direction perpendicular to one main surface of the carrier wiring substrate 110. FIG. 15 is a view of a conventional semiconductor device 200, viewed in a direction perpendicular to one main surface of the wiring substrate 210. In the previously described FIGS. 12 and 13, the chips flip-chip connected to the semiconductor device were all the same size. In the examples shown in FIGS. 14 and 15, multiple types of chips are connected to the semiconductor device. In both the examples shown in FIGS. 14 and 15, a chip larger than the other chips is arranged in the central portion of the substrate. This chip is called a center chip. Chips smaller than the center chip are arranged around the center chip.

[0109] 15, two chips are arranged on each side of the center chip 235 in the arrangement direction 221. In the conventional semiconductor device 200, it is necessary to provide an underfill region 240 between adjacent chips. Therefore, in the conventional semiconductor device 200, the number of chips arranged on one side of the center chip 235 in the arrangement direction 221 is two.

[0110] 14, three chips are arranged on each side of the center chip 30C in the arrangement direction 221. As described above, the semiconductor device 200 of this embodiment does not require the underfill region 240 and can place adjacent chips close to each other, allowing chips to be arranged at high density on the substrate.

[0111] (alignment mark) The alignment marks will now be described. The semiconductor device 100 of this embodiment allows for high-density chip arrangement. In order to arrange the chips at high density, it is preferable to accurately align the chips. The alignment marks 350 will now be described with reference to FIG. 14. The alignment marks 350 are used to align the second semiconductor device 30 with the carrier wiring substrate 110. The alignment marks 350 include a first alignment mark 352 and a second alignment mark 354. The first alignment mark 352 is an alignment mark formed on the carrier wiring substrate 110. The second alignment mark 354 is an alignment mark formed on the second semiconductor device 30 (first chip 30A, second chip 30B).

[0112] When connecting the second semiconductor device 30 to the carrier wiring substrate 110, the first alignment mark 352 and the second alignment mark 354 are positioned so that they have a predetermined positional relationship. In the example shown in FIG. 14 , the first alignment mark 352 is four points, and the second alignment mark 354 is two perpendicular line segments. As shown in FIG. 14 , during alignment, the two line segments of the second alignment mark 354 are positioned between the four points of the first alignment mark 352. This allows accurate alignment between the second semiconductor device 30 and the carrier wiring substrate 110. Note that the first alignment mark 352 and the second alignment mark 354 shown in FIG. 14 are merely examples and can be modified in various ways. Other examples of alignment marks include circles and points within the circles.

[0113] It is preferable to provide two or more alignment marks 350 on one second semiconductor device 30. It is also preferable to provide the alignment marks 350 at diagonal positions on the second semiconductor device 30. This allows for more accurate alignment.

[0114] The alignment marks 350 are preferably formed in regions where no electrodes or wiring are formed on the second semiconductor device 30 and the carrier wiring substrate 110. This allows alignment to be performed without being obstructed by the metal material forming the electrodes or wiring when checking the position of the alignment marks using, for example, infrared light.

[0115] (Positional relationship with the organic insulating film) The positional relationship between the second organic insulating film 34 and the second alignment mark 354 will be described. In the second semiconductor device 30 of this embodiment, a missing portion 72 in the second organic insulating film is formed in the outer periphery 71 of the second semiconductor device. The missing portion 72 in the second organic insulating film is missing the second organic insulating film 34. A frame 340 in FIG. 14 indicates the outer edge of the second organic insulating film 34. The area outside the frame 340 is where the second organic insulating film 34 is missing, that is, where the second organic insulating film 34 does not exist.

[0116] The second alignment mark 354 is preferably formed in the opening 72 in the second organic insulating film of the second silicon substrate 31. In other words, the second alignment mark 354 is preferably formed on the very outside of the frame 340. By forming the second alignment mark 354 in the opening 72 in the second organic insulating film, the second alignment mark 354 and the first alignment mark 352 can be more clearly recognized without being affected by the second organic insulating film 34. This in turn enables more accurate alignment.

[0117] Although the present invention has been described above as an embodiment, it is not limited to the above-described embodiment, and various changes, modifications, and combinations are possible.

[0118] (1) A semiconductor device in which semiconductor devices are flip-chip connected to another wiring substrate, each of the semiconductor devices comprising a silicon substrate and an electrode formed on the silicon substrate, an organic insulating film formed on each of the semiconductor devices, an opening formed in the organic insulating film to expose the electrode, an outer periphery of the organic insulating film positioned inside the outer periphery of the semiconductor device, and the outer periphery of the organic insulating film covered with a mold resin. (2) In the semiconductor device of (1), the opening is filled with a bump metal, and the surface of the bump metal and the surface of the organic insulating film are flat. (3) In the semiconductor device of (1) to (2), the periphery of at least one of the two semiconductor devices is covered with the molding resin. (4) a step of forming an organic insulating film on one main surface of a semiconductor device having an electrode formed thereon; a step of opening the organic insulating film on the electrode; a step of curing the organic insulating film; a step of filling the opened portion with a metal; a step of removing the organic insulating film from an outer periphery of the semiconductor device; a step of cutting the semiconductor device at the portion where the organic insulating film has been removed; a step of aligning the cut semiconductor device with another wiring substrate and simultaneously bonding and connecting them; and a step of sealing the outer periphery with a molding resin. (5) In the method for manufacturing a semiconductor device (4), a step of planarizing the organic insulating film formed on the one main surface and the portion filled with the metal is included between the step of filling with the metal and the step of removing the organic insulating film. (6) A semiconductor device in which a plurality of semiconductor devices are flip-chip connected to another wiring substrate, The semiconductor device includes a silicon substrate and an electrode formed on the silicon substrate; an organic insulating film is formed on the semiconductor device; an opening for exposing the electrode is formed in the organic insulating film; the outer periphery of the organic insulating film is located inside the outer periphery of the semiconductor device, The semiconductor device, wherein the distance between the silicon substrates of adjacent semiconductor devices is shorter than the distance between the organic insulating films. (7) In the semiconductor device of (6), the distance between the silicon substrates of the adjacent semiconductor devices is less than 50 μm, which is shorter than the distance between the organic insulating films. (8) In the semiconductor device of (6) or (7), an alignment mark for aligning with the other wiring substrate is provided in a portion of one main surface of the semiconductor device on which the electrode is formed, where the electrode is not formed. (9) forming an organic insulating film on one main surface of the semiconductor device on which the electrodes are formed; forming an opening in the organic insulating film on the electrode; curing the organic insulating film; filling the open portion with metal; removing the organic insulating film from the outer periphery of the semiconductor device; cutting the semiconductor device at the portion where the organic insulating film has been removed; and a step of aligning a plurality of the cut semiconductor devices with another wiring substrate so that the distance between silicon substrates included in adjacent semiconductor devices is shorter than the distance between the organic insulating films, and simultaneously bonding and connecting the semiconductor devices to each other. [Explanation of symbols]

[0119] 1. Semiconductor device 2. Outer periphery of semiconductor device 10 First semiconductor device (another wiring substrate) 11 First silicon substrate 12 First electrode 13 First oxide film 14 First organic insulating film 15 First metal film 16 First Bump 17 First bump metal layer 30 Second semiconductor device 30A First Chip 30B Second Chip 31 Second silicon substrate 32 Second electrode 33 Second oxide film 34 Second organic insulating film 35 Second metal film 36 Second Bump 37 Second bump metal layer 42 Opening 50 Molded resin part 51 First insulating film side filling portion of mold resin portion 52 Second insulating film side filling portion of mold resin portion 60 Outer periphery of first semiconductor device 61 Outer periphery of first semiconductor device 62 Hole in first organic insulating film 63 Outer periphery of first organic insulating film 64 Opening in first organic insulating film 70 Outer periphery of second semiconductor device 71 Outer periphery of second semiconductor device 72 Hole in the second organic insulating film 73 Outer periphery of second organic insulating film 74 Opening in second organic insulating film 75 Main surface of second silicon substrate 81 Underfill 82 Device facing part 83 Wetted area 84 Wetting and spreading part 90 Package substrate 100 Semiconductor device 110 Carrier wiring board 142 Inter-chip area 162 Electrode layer 164 Insulating Layer 166 wiring layer 205 Corner of the second semiconductor device on the first semiconductor device side 206 Corner of the first semiconductor device on the side of the second semiconductor device 221 First alignment direction 222 Second alignment direction

Claims

1. A semiconductor device in which a semiconductor device is flip-chip connected to another wiring substrate, The semiconductor device includes a silicon substrate and an electrode formed on the silicon substrate; an organic insulating film is formed on the semiconductor device; an opening for exposing the electrode is formed in the organic insulating film; the outer periphery of the organic insulating film is located inside the outer periphery of the semiconductor device, The semiconductor device is such that the outer periphery of the organic insulating film is covered with a molding resin.

2. The opening is filled with a bump metal, 2. The semiconductor device according to claim 1, wherein a surface of said bump metal and a surface of said organic insulating film are flat.

3. 3. The semiconductor device according to claim 1, wherein the outer periphery of the semiconductor device is covered with the molding resin.

4. forming an organic insulating film on one main surface of the semiconductor device on which the electrodes are formed; forming an opening in the organic insulating film on the electrode; curing the organic insulating film; filling the open portion with metal; removing the organic insulating film from the outer periphery of the semiconductor device; cutting the semiconductor device at the portion where the organic insulating film has been removed; a step of aligning the cut semiconductor device and another wiring substrate, and simultaneously bonding and connecting the same; and sealing the outer periphery with a molding resin.

5. 5. The method for manufacturing a semiconductor device according to claim 4, further comprising, between the step of filling with the metal and the step of removing the organic insulating film, a step of planarizing the organic insulating film formed on the one main surface and the portion filled with the metal.

6. A semiconductor device in which a plurality of semiconductor devices are flip-chip connected to another wiring substrate, The semiconductor device includes a silicon substrate and an electrode formed on the silicon substrate; an organic insulating film is formed on the semiconductor device; an opening for exposing the electrode is formed in the organic insulating film; the outer periphery of the organic insulating film is located inside the outer periphery of the semiconductor device, The semiconductor device, wherein the distance between the silicon substrates of adjacent semiconductor devices is shorter than the distance between the organic insulating films.

7. 7. The semiconductor device according to claim 6, wherein the distance between the silicon substrates of the adjacent semiconductor devices is less than 50 [mu]m and is shorter than the distance between the organic insulating films.

8. 8. The semiconductor device according to claim 6, wherein an alignment mark for alignment with the other wiring substrate is provided in a portion of the main surface of the semiconductor device on which the electrodes are formed, where the electrodes are not formed.

9. forming an organic insulating film on one main surface of the semiconductor device on which the electrodes are formed; forming an opening in the organic insulating film on the electrode; curing the organic insulating film; filling the open portion with metal; removing the organic insulating film from the outer periphery of the semiconductor device; cutting the semiconductor device at the portion where the organic insulating film has been removed; and a step of aligning a plurality of the cut semiconductor devices with another wiring substrate so that the distance between silicon substrates included in adjacent semiconductor devices is shorter than the distance between the organic insulating films, and simultaneously bonding and connecting the semiconductor devices to each other.

Images