Semiconductor element including resonant tunneling layer

Abstract

To provide a semiconductor device which improves operation speed and reduces power consumption, and a method of forming the same.SOLUTION: A semiconductor element includes an upper electrode 29 over a channel pattern CP, and an information storage pattern DSL is disposed between the channel pattern and the upper electrode. The information storage pattern includes: a tunnel layer TL adjacent to the channel pattern; a blocking layer BL adjacent to the upper electrode; a charge trap layer CTL between the tunnel layer and the blocking layer; a first resonant tunneling layer RL1 disposed between the tunnel layer and the charge trap layer, and including a material having a lower energy barrier than the tunnel layer; and a second resonant tunneling layer RL2 disposed between the charge trap layer and the blocking layer, and including a material having a lower energy barrier than the charge trap layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device having a resonant tunneling layer and a method for forming the same. [Background technology]

[0002] Various technologies have been attempted to increase the integration density of nonvolatile memory devices. Nonvolatile memory devices are memories that retain stored data even when the power supply is interrupted, and include programmable read-only memory (PROM) and flash memory. However, there are various technical limitations to increasing the operating speed and minimizing power consumption of nonvolatile memory devices. Summary of the Invention [Problem to be solved by the invention]

[0003] An embodiment of the present disclosure provides a semiconductor device and a method for forming the same that are advantageous in improving the operating speed and reducing power consumption. [Means for solving the problem]

[0004] A semiconductor device according to an embodiment of the present invention may include an electrode on a channel pattern. An information storage pattern may be disposed between the channel pattern and the electrode. The information storage pattern may include a tunnel layer adjacent to the channel pattern, a blocking layer adjacent to the electrode, a charge trap layer between the tunnel layer and the blocking layer, a first resonant tunneling layer disposed between the tunnel layer and the charge trap layer and having a material with a lower energy barrier than the tunnel layer, and a second resonant tunneling layer disposed between the charge trap layer and the blocking layer and having a material with a lower energy barrier than the charge trap layer.

[0005] A semiconductor device according to an embodiment of the present invention may include an electrode on a channel pattern. An information storage pattern may be disposed between the channel pattern and the electrode. The information storage pattern may include a tunnel layer adjacent to the channel pattern, a blocking layer adjacent to the electrode, a charge trap layer between the tunnel layer and the blocking layer, and at least one resonant tunnel layer disposed between the tunnel layer and the blocking layer and made of a material having a lower energy barrier than the tunnel layer and the blocking layer.

[0006] A semiconductor device according to one embodiment of the present invention may include a stacked structure having a plurality of alternating molding layers and a plurality of horizontal electrodes. A source line may be disposed on the stacked structure. A channel structure may be provided extending through the stacked structure into the source line. The channel structure may include a channel pattern in contact with the source line and an information storage pattern between the channel pattern and the stacked structure. The information storage pattern may include a tunnel layer adjacent to the channel pattern, a blocking layer adjacent to the stacked structure, a charge trapping layer between the tunnel layer and the blocking layer, and at least one resonant tunneling layer disposed between the tunnel layer and the blocking layer and made of a material having a lower energy barrier than the tunnel layer and the blocking layer. [Effects of the Invention]

[0007] According to the embodiment of the present invention, a semiconductor device that is advantageous for high speed operation, is capable of high speed switching, and has low power consumption can be realized. [Brief explanation of the drawings]

[0008] [Figure 1]1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention; [Figure 2] 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention; [Figure 3] 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention; [Figure 4] 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention; [Figure 5] 1 is a plan view illustrating a semiconductor device according to an embodiment of the present invention; [Figure 6] 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention; [Figure 7] 1A to 1C are cross-sectional views illustrating a method of forming a semiconductor device according to an embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views illustrating a method of forming a semiconductor device according to an embodiment of the present invention. [Figure 9] 1A to 1C are cross-sectional views illustrating a method of forming a semiconductor device according to an embodiment of the present invention. [Figure 10] 1A to 1C are cross-sectional views illustrating a method of forming a semiconductor device according to an embodiment of the present invention. [Figure 11] 1A to 1C are cross-sectional views illustrating a method of forming a semiconductor device according to an embodiment of the present invention. [Figure 12] 1A to 1C are cross-sectional views illustrating a method of forming a semiconductor device according to an embodiment of the present invention. [Figure 13] 1A to 1C are cross-sectional views illustrating a method of forming a semiconductor device according to an embodiment of the present invention. [Figure 14] 1A to 1C are cross-sectional views illustrating a method of forming a semiconductor device according to an embodiment of the present invention. [Figure 15] 1A to 1C are cross-sectional views illustrating a method of forming a semiconductor device according to an embodiment of the present invention. [Figure 16] 1A to 1C are cross-sectional views illustrating a method of forming a semiconductor device according to an embodiment of the present invention. [Figure 17] 1A to 1C are cross-sectional views illustrating a method of forming a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] 1 to 4 are cross-sectional views illustrating a semiconductor device according to an embodiment of the present invention, and FIG. 5 is a plan view illustrating a semiconductor device according to an embodiment of the present invention. In one embodiment, FIG. 5 may correspond to a portion of FIG. 4 (e.g., a channel structure CH). FIG. 6 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention. In one embodiment, a semiconductor device according to an embodiment of the present invention may include a non-volatile memory device such as a flash memory.

[0010] 1, a semiconductor device according to an embodiment of the present invention may include a first substrate 21, a source region 23, a drain region 25, a channel pattern CP, an information storage pattern DSL, and an upper electrode 29. The information storage pattern DSL may include a tunnel layer (TL), a first resonant tunneling layer (RL1), a charge trap layer (CTL), a second resonant tunneling layer RL2, and a blocking layer (BL).

[0011] A first direction FD, a second direction SD, and a third direction VD can be defined. The second direction SD can intersect the first direction FD. The third direction VD can intersect the first direction FD and the second direction SD. In one embodiment, the first direction FD and the second direction SD can be parallel to the top and bottom surfaces of the first substrate 21. The third direction VD can be perpendicular to the top and bottom surfaces of the first substrate 21. The second direction SD can be perpendicular to the first direction FD. The third direction VD can be perpendicular to the first direction FD and the second direction SD.

[0012] The channel pattern CP may be disposed between the source region 23 and the drain region 25 in the first substrate 21. In one embodiment, the channel pattern CP may include a semiconductor layer having P-type impurities. The channel pattern CP may include a single-crystal silicon layer, a polysilicon layer, or a combination thereof having P-type impurities. Each of the source region 23 and the drain region 25 may include a semiconductor layer having N-type impurities. Each of the source region 23 and the drain region 25 may include a single-crystal silicon layer, a polysilicon layer, or a combination thereof having N-type impurities.

[0013] The information storage pattern DSL may be disposed in the third direction VD on the channel pattern CP. The top electrode 29 may be disposed in the third direction VD on the information storage pattern DSL. The information storage pattern DSL may be overlapped between the top electrode 29 and the channel pattern CP. In one embodiment, the channel pattern CP, the information storage pattern DSL, and the top electrode 29 may form a non-volatile memory cell. The top electrode 29 may be connected to a word line. The top electrode 29 may correspond to a portion of the word line.

[0014] The tunnel layer TL, the first resonant tunnel layer RL1, the charge trapping layer CTL, the second resonant tunneling layer RL2, and the blocking layer BL may be sequentially stacked in the third direction VD. The tunnel layer TL may have a first thickness T1. The first resonant tunneling layer RL1 may have a second thickness T2. The charge trapping layer CTL may have a third thickness T3. The second resonant tunneling layer RL2 may have a fourth thickness T4. The blocking layer BL may have a fifth thickness T5. The equivalent oxide thickness (EOT) of the blocking layer BL may be thicker than the equivalent oxide thickness EOT of the tunnel layer TL. The fifth thickness T5 of the blocking layer BL may be thicker than the first thickness T1 of the tunnel layer TL.

[0015] The tunnel layer TL may be disposed on the channel pattern CP. The tunnel layer TL may be in contact with the channel pattern CP. The tunnel layer TL may be disposed between the channel pattern CP and the charge trapping layer CTL. The first resonant tunnel layer RL1 may be disposed on the tunnel layer TL. The first resonant tunnel layer RL1 may be disposed between the tunnel layer TL and the charge trapping layer CTL. The first resonant tunnel layer RL1 may be in contact with the tunnel layer TL and the charge trapping layer CTL.

[0016] The charge trapping layer CTL may be disposed on the first resonant tunneling layer RL1. The charge trapping layer CTL may be disposed between the first resonant tunneling layer RL1 and the second resonant tunneling layer RL2. The charge trapping layer CTL may be in contact with the first resonant tunneling layer RL1 and the second resonant tunneling layer RL2. The charge trapping layer CTL may be disposed between the tunneling layer TL and the blocking layer BL. The second resonant tunneling layer RL2 may be disposed on the charge trapping layer CTL. The second resonant tunneling layer RL2 may be disposed between the charge trapping layer CTL and the blocking layer BL. The second resonant tunneling layer RL2 may be in contact with the charge trapping layer CTL and the blocking layer BL.

[0017] The blocking layer BL may be disposed on the second resonant tunneling layer RL2. The blocking layer BL may be in contact with the second resonant tunneling layer RL2. The blocking layer BL may be disposed between the second resonant tunneling layer RL2 and the upper electrode 29. The blocking layer BL may be disposed between the charge trapping layer CTL and the upper electrode 29.

[0018] The first resonant tunneling layer RL1 may include a material different from that of the tunneling layer TL. The first resonant tunneling layer RL1 may include a material having a lower energy barrier than the tunneling layer TL. The tunneling layer TL may include silicon oxide, silicon nitride, aluminum oxide (Al2O3), magnesium oxide (MgO), or zirconium oxide (ZrO2). The first resonant tunneling layer RL1 may include tantalum pentoxide (Ta2O5), gallium oxide (Ga2O3), gadolinium oxide (Gd2O3), lanthanum oxide (La2O3), hafnium oxide (HfO2), gallium nitride (GaN), or a combination thereof. In one embodiment, the first resonant tunneling layer RL1 may include a tantalum pentoxide (Ta2O5) layer. The first resonant tunneling layer RL1 may include a material having a lower energy barrier than the charge trapping layer CTL.The first resonant tunneling layer RL1 may include a material having a lower energy barrier than the blocking layer BL.

[0019] The second thickness T2 of the first resonant tunneling layer RL1 may be smaller than the first thickness T1 of the tunneling layer TL. The tunneling layer TL may have a thickness of 1 nanometer (nm) to 7 nanometers (nm). The first resonant tunneling layer RL1 may have a thickness of 0.5 nanometers (nm) to 3 nanometers (nm).

[0020] The charge trapping layer CTL may include a material different from the first resonant tunneling layer RL1, the second resonant tunneling layer RL2, and the blocking layer BL. The charge trapping layer CTL may include a material having a higher energy barrier than the first resonant tunneling layer RL1. In one embodiment, the charge trapping layer CTL may include silicon nitride. The charge trapping layer CTL may include a material having a lower energy barrier than the tunneling layer TL and the blocking layer BL.

[0021] The second resonant tunneling layer RL2 may include a material different from the charge trapping layer CTL and the blocking layer BL. The second resonant tunneling layer RL2 may include a material having a lower energy barrier than the charge trapping layer CTL. The second resonant tunneling layer RL2 may include tantalum pentoxide (TaO), gallium oxide (GaO), gadolinium oxide (GdO), lanthanum oxide (LaO), hafnium oxide (HfO), gallium nitride (GaN), or a combination thereof. In one embodiment, the second resonant tunneling layer RL2 may include a tantalum pentoxide (TaO) layer. The second resonant tunneling layer RL2 may include a material having a lower energy barrier than the blocking layer BL. The second resonant tunneling layer RL2 may include a material having a lower energy barrier than the tunneling layer TL.

[0022] The fourth thickness T4 of the second resonant tunneling layer RL2 may be smaller than the first thickness T1 of the tunneling layer TL. The second resonant tunneling layer RL2 may have a thickness of 0.5 nanometers (nm) to 3 nanometers (nm).

[0023] The blocking layer BL may include a material different from that of the second resonant tunneling layer RL2 and the charge trapping layer CTL. The blocking layer BL may include a material having a higher energy barrier than that of the second resonant tunneling layer RL2 and the charge trapping layer CTL. In one embodiment, the blocking layer BL may include aluminum oxide (Al2O3).

[0024] In one embodiment, a program operation of a semiconductor device according to an embodiment of the present invention may be performed using a resonant tunneling injection (RTI) method. During a program operation of the semiconductor device, electrons passing through the tunnel layer TL from the channel pattern CP may pass through the first resonant tunnel layer RL1 and be injected into the charge trap layer CTL. Some of the electrons injected into the charge trap layer CTL may pass through the charge trap layer CTL, pass through the second resonant tunnel layer RL2, and be reflected by the blocking layer BL. Electrons reflected by the blocking layer BL may pass through the second resonant tunnel layer RL2 and be injected into the charge trap layer CTL. According to an embodiment of the present invention, a semiconductor device that is advantageous for high-speed operation, is capable of high-speed switching, and has low power consumption may be realized.

[0025] The resonant tunneling injection (RTI) method can inject a relatively large number of electrons into the charge trapping layer (CTL) at a relatively low voltage, thereby improving the on / off characteristics of nonvolatile memory elements. The endurance characteristics of nonvolatile memory elements can be improved. A relatively large number of level states can be realized in nonvolatile memory elements.

[0026] 2, the information storage pattern DSL may include a tunnel layer TL, a first resonant tunnel layer RL1, a charge trapping layer CTL, and a blocking layer BL. The charge trapping layer CTL may be disposed between the first resonant tunneling layer RL1 and the blocking layer BL. The charge trapping layer CTL may be in contact with the first resonant tunneling layer RL1 and the blocking layer BL.

[0027] 3, the information storage pattern DSL may include a tunnel layer TL, a charge trapping layer CTL, a second resonant tunneling layer RL2, and a blocking layer BL. The charge trapping layer CTL may be disposed between the tunnel layer TL and the second resonant tunneling layer RL2. The charge trapping layer CTL may be in contact with the tunnel layer TL and the second resonant tunneling layer RL2. The second resonant tunneling layer RL2 may be disposed between the charge trapping layer CTL and the blocking layer BL.

[0028] 4, a semiconductor device according to an embodiment of the present invention may include a stacked structure ST, a channel structure CH, an interlayer insulating layer 52, a bit line 53, and a source line 71. Fig. 4 may correspond to a cross-sectional view seen from a plane forming a first direction FD and a third direction VD.

[0029] The stacked structure ST may include a plurality of molding layers 43 and a plurality of horizontal electrodes 45 alternately stacked in the third direction VD. Each of the top and bottom layers of the stacked structure ST may be one of the molding layers 43. The source line 71 may be disposed on the channel structure CH in the third direction VD. The channel structure CH may include a core layer CO, a channel pattern CP, an information storage pattern DSL, and a drain pad DP. The information storage pattern DSL may include a tunnel layer TL, a first resonant tunneling layer RL1, a charge trapping layer CTL, a second resonant tunneling layer RL2, and a blocking layer BL. The channel structure CH may extend through the stacked structure ST in the third direction VD into the source line 71.

[0030] The core layer CO can extend into the source line 71, penetrating the stacked structure ST in the third direction VD. The channel pattern CP can surround the side and top surface of the core layer CO. The channel pattern CP may extend into the source line 71. The channel pattern CP may be in direct contact with the source line 71.

[0031] The information storage pattern DSL can surround the side of the channel pattern CP. The channel pattern CP can be disposed between the information storage pattern DSL and the core layer CO. The information storage pattern DSL can be disposed between the channel pattern CP and the stacked structure ST. The information storage pattern DSL can include a configuration similar to that described with reference to FIGS. 1 to 3.

[0032] In one embodiment, the tunnel layer TL may be disposed on a side of the channel pattern CP in the first direction FD. The tunnel layer TL may be in contact with the channel pattern CP. The tunnel layer TL may be disposed between the channel pattern CP and the charge trapping layer CTL. The first resonant tunnel layer RL1 may be disposed on a side of the tunnel layer TL in the first direction FD. The first resonant tunnel layer RL1 may be disposed between the tunnel layer TL and the charge trapping layer CTL.

[0033] The charge trapping layer CTL may be disposed on a side surface of the first resonant tunneling layer RL1 in the first direction FD. The charge trapping layer CTL may be disposed between the first resonant tunneling layer RL1 and the second resonant tunneling layer RL2. The charge trapping layer CTL may be disposed between the tunneling layer TL and the blocking layer BL. The second resonant tunneling layer RL2 may be disposed on a side surface of the charge trapping layer CTL in the first direction FD. The second resonant tunneling layer RL2 may be disposed between the charge trapping layer CTL and the blocking layer BL.

[0034] The blocking layer BL may be disposed on a side surface of the second resonant tunneling layer RL2 in the first direction FD. The blocking layer BL may be disposed between the second resonant tunneling layer RL2 and the stack structure ST. The blocking layer BL may be in contact with the stack structure ST. The blocking layer BL may extend between the second resonant tunneling layer RL2 and the horizontal electrodes 45 and between the second resonant tunneling layer RL2 and the molding layers 43. The blocking layer BL may be in contact with the second resonant tunneling layer RL2 and the horizontal electrodes 45. The blocking layer BL may be disposed between the charge trapping layer CTL and the stack structure ST.

[0035] The tunnel layer TL may have a first thickness T1 in the first direction FD. The first resonant tunnel layer RL1 may have a second thickness T2 in the first direction FD. The charge trapping layer CTL may have a third thickness T3 in the first direction FD. The second resonant tunnel layer RL2 may have a fourth thickness T4 in the first direction FD. The blocking layer BL may have a fifth thickness T5 in the first direction FD. An equivalent oxide thickness EOT of the blocking layer BL may be greater than an equivalent oxide thickness EOT of the tunnel layer TL. The fifth thickness T5 of the blocking layer BL may be greater than the first thickness T1 of the tunnel layer TL.

[0036] The drain pad DP may be disposed on the lower surfaces of the channel pattern CP and the core layer CO. The drain pad DP may be in direct contact with the channel pattern CP. An interlayer insulating layer 52 may be disposed on the lower surfaces of the stack structure ST and the channel structure CH. A bit line 53 may be disposed in the interlayer insulating layer 52. The bit line 53 may be connected to the drain pad DP.

[0037] In one embodiment, the source line 71 may correspond to a common source line. The horizontal electrodes 45 may include a plurality of word lines, a plurality of select lines, and at least one gate-induced drain leakage (GIDL) control line. Memory cells MC may be formed at intersections of the channel structures CH and the plurality of word lines. At least one of the horizontal electrodes 45 adjacent to the source line 71 may correspond to a source select line. At least one of the horizontal electrodes 45 adjacent to the drain pad DP may correspond to a drain select line. One of the horizontal electrodes 45 adjacent to the source line 71 and / or one of the horizontal electrodes 45 adjacent to the drain pad DP may correspond to a GIDL control line. A plurality of word lines may be arranged between at least one drain select line of the horizontal electrodes 45 and at least one source select line.

[0038] FIG. 5 may correspond to a plan view of a portion of FIG. 4 (eg, the channel structure CH) as viewed from a plane that defines the first direction FD and the second direction SD.

[0039] Referring to FIG. 5, the channel pattern CP may surround the side of the core layer CO. The information storage pattern DSL may surround the side of the channel pattern CP. The channel pattern CP may be disposed between the core layer CO and the information storage pattern DSL. The information storage pattern DSL may include a configuration similar to that described with reference to FIGS. 1 to 3. In one embodiment, the information storage pattern DSL may include a tunnel layer TL surrounding the outside of the channel pattern CP, a first resonant tunneling layer RL1 surrounding the outside of the tunnel layer TL, a charge trapping layer CTL surrounding the outside of the first resonant tunneling layer RL1, a second resonant tunneling layer RL2 surrounding the outside of the charge trapping layer CTL, and a blocking layer BL surrounding the outside of the second resonant tunneling layer RL2.

[0040] Referring to Figure 6, a semiconductor device according to an embodiment of the present invention may include a second substrate 31, a circuit structure CS, a first insulating bonding layer 38, a plurality of first bonding pads 39, a stacked structure ST, a buried insulating layer 47, a plurality of channel structures CH, a plurality of contact plugs 49, an interlayer insulating layer 52, a plurality of intermediate wirings 53, 54, a second insulating bonding layer 62, a plurality of second bonding pads 63, a source line 71, and an upper insulating layer 98.

[0041] The circuit structure CS may include a page buffer PB, a decoder DE, and a circuit insulating layer 34. The stacked structure ST may include a plurality of molding layers 43 and a plurality of horizontal electrodes 45 alternately stacked in a third direction VD. Each of the plurality of channel structures CH may include a core layer CO, a channel pattern CP, an information storage pattern DSL, and a drain pad DP, similar to that shown in FIG. 4 . In one embodiment, the information storage pattern DSL may include a tunnel layer TL, a first resonant tunneling layer RL1, a charge trapping layer CTL, a second resonant tunneling layer RL2, and a blocking layer BL. The plurality of intermediate wirings 53, 54 may include a plurality of bit lines 53 and a plurality of word connection wirings 54.

[0042] A selected one of the plurality of channel structures CH can be connected to the page buffer PB via a corresponding one of the plurality of bit lines 53, a corresponding one of the plurality of second bonding pads 63, and a corresponding one of the plurality of first bonding pads 39. A selected one of the plurality of horizontal electrodes 45 can be connected to the decoder DE via a corresponding one of the plurality of contact plugs 49, a corresponding one of the plurality of word connection wirings 54, a corresponding one of the plurality of second bonding pads 63, and a corresponding one of the plurality of first bonding pads 39.

[0043] 7 to 12 are cross-sectional views illustrating a method for forming a semiconductor device according to an embodiment of the present invention.

[0044] Referring to FIG. 7, a tunnel layer (TL) having a first thickness T1 may be formed on a first substrate 21.

[0045] The first substrate 21 may include a semiconductor substrate such as a silicon wafer or an SOI (Silicon On Insulator) wafer. The first substrate 21 may include a III-V semiconductor substrate, for example, a compound semiconductor substrate such as GaAs. The first substrate 21 may include single crystal silicon, polysilicon, amorphous silicon, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, or a combination thereof. In one embodiment, the first substrate 21 may include a single crystal silicon wafer having P-type impurities.

[0046] The tunnel layer TL may include silicon oxide, silicon nitride, aluminum oxide (Al2O3), magnesium oxide (MgO), or zirconium oxide (ZrO2). Formation of the tunnel layer TL may include a chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, a cyclic deposition method, a sputtering method, a physical vapor deposition (PVD) method, or a combination thereof. The tunnel layer TL may be formed to cover the first substrate 21 with a uniform thickness. The tunnel layer TL may have a thickness of 1 nanometer (nm) to 7 nanometers (nm).

[0047] 8, a first resonant tunneling layer RL1 having a second thickness T2 may be formed on the tunneling layer TL. The first resonant tunneling layer RL1 may include a material having a lower energy barrier than the tunneling layer TL. The first resonant tunneling layer RL1 may include tantalum pentoxide (Ta2O5), gallium oxide (Ga2O3), gadolinium oxide (Gd2O3), lanthanum oxide (La2O3), hafnium oxide (HfO2), gallium nitride (GaN), or a combination thereof. In one embodiment, the first resonant tunneling layer RL1 may include a tantalum pentoxide (Ta2O5) layer.

[0048] The formation of the first resonant tunneling layer RL1 may include a chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, a cyclic evaporation method, a sputtering method, a physical vapor deposition (PVD) method, or a combination thereof. The second thickness T2 of the first resonant tunneling layer RL1 may be smaller than the first thickness T1 of the tunneling layer TL. The first resonant tunneling layer RL1 may have a thickness of 0.5 nanometers (nm) to 3 nanometers (nm).

[0049] 9 , a charge trapping layer CTL having a third thickness T3 can be formed on the first resonant tunneling layer RL1. The charge trapping layer CTL can include a material having a higher energy barrier than the first resonant tunneling layer RL1. In one embodiment, the charge trapping layer CTL can include a silicon nitride layer. The charge trapping layer CTL can include a material having a lower energy barrier than the tunneling layer TL. Formation of the charge trapping layer CTL can include a chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, a cyclic evaporation method, a sputtering method, a physical vapor deposition (PVD) method, or a combination thereof.

[0050] 10 , a second resonant tunneling layer RL2 having a fourth thickness T4 may be formed on the charge trapping layer CTL. The second resonant tunneling layer RL2 may include a material having a lower energy barrier than the charge trapping layer CTL. The second resonant tunneling layer RL2 may include tantalum pentoxide (TaO), gallium oxide (GaO), gadolinium oxide (GdO), lanthanum oxide (LaO), hafnium oxide (HfO), gallium nitride (GaN), or a combination thereof. In one embodiment, the second resonant tunneling layer RL2 may include a tantalum pentoxide (TaO) layer.

[0051] The formation of the second resonant tunneling layer RL2 may include a chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, a cyclic evaporation method, a sputtering method, a physical vapor deposition (PVD) method, or a combination thereof. The fourth thickness T4 of the second resonant tunneling layer RL2 may be smaller than the first thickness T1 of the tunneling layer TL. The second resonant tunneling layer RL2 may have a thickness of 0.5 nanometers (nm) to 3 nanometers (nm).

[0052] 11 , a blocking layer BL having a fifth thickness T5 may be formed on the second resonant tunneling layer RL2. The blocking layer BL may include a material having a higher energy barrier than the second resonant tunneling layer RL2 and the charge trapping layer CTL. In one embodiment, the blocking layer BL may include an aluminum oxide (Al2O3) layer.

[0053] The formation of the blocking layer BL may include a chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, a cyclic evaporation method, a sputtering method, a physical vapor deposition (PVD) method, or a combination thereof. The equivalent oxide thickness EOT of the blocking layer BL may be greater than the equivalent oxide thickness EOT of the tunnel layer TL. The fifth thickness T5 of the blocking layer BL may be greater than the first thickness T1 of the tunnel layer TL.

[0054] 12, an upper electrode 29 may be formed on the blocking layer BL. The upper electrode 29 may include a conductive material such as a metal, a metal nitride, a metal oxide, a metal silicide, polysilicon, conductive carbon, or a combination thereof. The upper electrode 29 may include W, WN, Ti, TiN, Ta, TaN, Ni, Co, Ru, Sn, Pt, Au, Ag, Cu, Al, or a combination thereof.

[0055] 1 , a patterning process may be used to partially remove the top electrode 29, the blocking layer BL, the second resonant tunneling layer RL2, the charge trapping layer CTL, the first resonant tunneling layer RL1, and the tunneling layer TL, thereby exposing the top surface of the first substrate 21. An ion implantation process may be used to form a source region 23 and a drain region 25 in the first substrate 21. A channel pattern CP may be defined in the first substrate 21 between the source region 23 and the drain region 25. Each of the source region 23 and the drain region 25 may include a semiconductor layer having N-type impurities.

[0056] In one embodiment, a heat treatment step can be further performed to promote crystallization of the tunnel layer TL, the first resonant tunnel layer RL1, and the second resonant tunnel layer RL2. The heat treatment step can be performed in an atmosphere at about 700°C or less (e.g., 600°C to 700°C). The heat treatment step can be performed immediately after the steps of forming the tunnel layer TL, the first resonant tunnel layer RL1, and the second resonant tunnel layer RL2 are completed. The heat treatment step can be performed one or more times between the step of forming the second resonant tunnel layer RL2 and the step of forming the source region 23 and the drain region 25.

[0057] 13 to 17 are cross-sectional views illustrating a method for forming a semiconductor device according to an embodiment of the present invention.

[0058] 13, a circuit structure CS may be formed on a second substrate 31. A first insulating bonding layer 38 and a plurality of first bonding pads 39 may be formed on the circuit structure CS. The second substrate 31 may include a configuration similar to that described with reference to FIG. 7. In one embodiment, the second substrate 31 may include a single crystal silicon wafer having P-type impurities. The circuit structure CS may be formed in and / or on the second substrate 31.

[0059] The circuit structure CS may include various types of active / passive elements, such as transistors. The transistors may include planar transistors, recess channel transistors, vertical transistors, fin field effect transistors (finFETs), gate all around (GAA) transistors, multi-bridge channel transistors, or combinations thereof. In one embodiment, the circuit structure CS may include a page buffer PB, a decoder DE, and a circuit insulating layer 34.

[0060] A circuit insulating layer 34 may be formed on the second substrate 31 to cover the page buffer PB and the decoder DE. A first insulating bonding layer 38 may cover the circuit structure CS. A plurality of first bonding pads 39 may be formed in the first insulating bonding layer 38. Top surfaces of the first insulating bonding layer 38 and the plurality of first bonding pads 39 may form substantially the same plane. Each of the plurality of first bonding pads 39 may be electrically connected to a corresponding at least one of the page buffer PB and the decoder DE.

[0061] Each of the circuit insulating layer 34 and the first insulating bonding layer 38 may include a single layer or multiple layers. Each of the circuit insulating layer 34 and the first insulating bonding layer 38 may include at least two selected from the group consisting of Si, O, N, C, and B. Each of the circuit insulating layer 34 and the first insulating bonding layer 38 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), a low-silica dielectric, a high-silica dielectric, or a combination thereof. In one embodiment, the first insulating bonding layer 38 may include silicon carbonitride (SiCN).

[0062] The plurality of first bonding pads 39 may include a single layer or multiple layers. The plurality of first bonding pads 39 may include a metal, a metal nitride, a metal oxide, a metal silicide, polysilicon, conductive carbon, or a combination thereof. The plurality of first bonding pads 39 may include Cu, Al, Ni, Co, Ru, W, WN, Ti, TiN, Ta, TaN, Sn, Pt, Au, Ag, or a combination thereof. In one embodiment, the plurality of first bonding pads 39 may include a Cu layer formed using an electroplating method.

[0063] 14, a stacked structure ST may be formed on a temporary substrate 41. The stacked structure ST may include a plurality of molding layers 43 and a plurality of horizontal electrodes 45 that are alternately stacked. The plurality of molding layers 43 and the plurality of horizontal electrodes 45 may have a stepped structure. A buried insulating layer 47 may be formed on the plurality of molding layers 43 and the plurality of horizontal electrodes 45 having the stepped structure.

[0064] A plurality of channel structures CH may be formed extending through the stacked structure ST into the temporary substrate 41. Each of the plurality of channel structures CH may include a core layer CO, a channel pattern CP, an information storage pattern DSL, and a drain pad DP, similar to that shown in Fig. 4. The information storage pattern DSL may include a tunnel layer TL, a first resonant tunneling layer RL1, a charge trapping layer CTL, a second resonant tunneling layer RL2, and a blocking layer BL.

[0065] In one embodiment, the core layer CO may include silicon oxide, silicon nitride, silicon oxynitride, polysilicon, or a combination thereof. The channel pattern CP may include a semiconductor material such as polysilicon. The drain pad DP may include a semiconductor material such as polysilicon. The information storage pattern DSL may include a structure similar to that described with reference to FIGS. 1 to 12.

[0066] A plurality of contact plugs 49 connected to the plurality of horizontal electrodes 45 may be formed through the buried insulating layer 47. An interlayer insulating layer 52 may be formed on the stacked structure ST, the plurality of channel structures CH, the buried insulating layer 47, and the plurality of contact plugs 49. A plurality of intermediate wirings 53, 54 may be formed in the interlayer insulating layer 52. The plurality of intermediate wirings 53, 54 may include a plurality of bit lines 53 and a plurality of word connecting wirings 54.

[0067] Each of the plurality of bit lines 53 may be electrically connected to at least one corresponding one of the plurality of channel structures CH. Each of the plurality of word connection wirings 54 may be electrically connected to at least one corresponding one of the plurality of contact plugs 49. For convenience of explanation, the plurality of intermediate wirings 53, 54 are shown as being formed in the same layer, but they may be formed in different layers.

[0068] A second insulating bonding layer 62 may be formed on the interlayer insulating layer 52. A plurality of second bonding pads 63 may be formed in the second insulating bonding layer 62. The top surfaces of the second insulating bonding layer 62 and the plurality of second bonding pads 63 may form substantially the same plane. Each of the plurality of second bonding pads 63 may be electrically connected to a corresponding one of the plurality of intermediate wirings 53, 54.

[0069] The temporary substrate 41 may include a material similar to that of the second substrate 31. Each of the multiple molding layers 43, the buried insulating layer 47, the interlayer insulating layer 52, and the second insulating bonding layer 62 may include a single layer or multiple layers. Each of the multiple molding layers 43, the buried insulating layer 47, the interlayer insulating layer 52, and the second insulating bonding layer 62 may include at least two selected from the group consisting of Si, O, N, C, and B. Each of the multiple molding layers 43, the buried insulating layer 47, the interlayer insulating layer 52, and the second insulating bonding layer 62 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), a low-silica dielectric, a high-silica dielectric, or a combination thereof. The second insulating bonding layer 62 may include a material similar to that of the first insulating bonding layer 38. In one embodiment, the second insulating bonding layer 62 may include silicon carbonitride (SiCN).

[0070] Each of the horizontal electrodes 45, the contact plugs 49, the intermediate interconnects 53 and 54, and the second bonding pads 63 may include a single layer or multiple layers. Each of the horizontal electrodes 45, the contact plugs 49, the intermediate interconnects 53 and 54, and the second bonding pads 63 may include a metal, a metal nitride, a metal oxide, a metal silicide, polysilicon, conductive carbon, or a combination thereof. Each of the horizontal electrodes 45, the contact plugs 49, the intermediate interconnects 53 and 54, and the second bonding pads 63 may include Cu, Al, Ni, Co, Ru, W, WN, Ti, TiN, Ta, TaN, Sn, Pt, Au, Ag, or a combination thereof. The second bonding pads 63 may include a material similar to that of the first bonding pads 39. In one embodiment, the second bonding pads 63 include a Cu layer formed using an electroplating method.

[0071] 15, a temporary substrate 41 having a stacked structure ST can be bonded onto a second substrate 31 having a circuit structure CS. The first insulating bonding layer 38 and the second insulating bonding layer 62 can be bonded facing each other, and the plurality of first bonding pads 39 and the plurality of second bonding pads 63 can be bonded facing each other.

[0072] 16, the temporary substrate 41 can be removed to expose the stacked structure ST and the plurality of channel structures CH. The information storage pattern DSL can be partially removed to partially expose the channel pattern CP included in each of the plurality of channel structures CH.

[0073] 17, a source line 71 covering a plurality of channel structures CH can be formed on the stack structure ST. The channel pattern CP may extend into the source line 71. The channel pattern CP can directly contact the source line 71. The source line 71 can include a semiconductor material such as polysilicon.

[0074] 6 , an upper insulating layer 98 may be formed on the stack structure ST and the source line 71. The upper insulating layer 98 may include a single layer or multiple layers. The upper insulating layer 98 may include at least two selected from the group consisting of Si, O, N, C, and B. The upper insulating layer 98 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), a low-silicon dielectric, a high-silicon dielectric, or a combination thereof.

[0075] The above description merely exemplifies the technical concept of the present disclosure, and various modifications and variations may be made by a person skilled in the art without departing from the essential characteristics of the present invention. Furthermore, the embodiments disclosed in the present invention are for illustrative purposes only and do not limit the technical concept of the present invention. The scope of the present invention should be interpreted by the following claims, and all technical concepts within the scope of the claims should be interpreted as being within the scope of the present invention.

Claims

1. channel patterns, an electrode on the channel pattern; and an information storage pattern between the channel pattern and the electrode; The information storage pattern is a tunnel layer adjacent to the channel pattern; a blocking layer adjacent to the electrode; a charge trap layer between the tunnel layer and the blocking layer; a first resonant tunneling layer disposed between the tunneling layer and the charge trapping layer, the first resonant tunneling layer having a material with a lower energy barrier than the tunneling layer; and A semiconductor device including a second resonant tunneling layer disposed between the charge trapping layer and the blocking layer, the second resonant tunneling layer having a material with a lower energy barrier than the charge trapping layer.

2. The semiconductor device of claim 1 , wherein the second resonant tunneling layer comprises a material having a lower energy barrier than the blocking layer.

3. 10. The semiconductor device of claim 1, wherein the second resonant tunneling layer comprises tantalum pentoxide (Ta2O5), gallium oxide (Ga2O3), gadolinium oxide (Gd2O3), lanthanum oxide (La2O3), hafnium oxide (HfO2), gallium nitride (GaN), or a combination thereof.

4. The semiconductor device of claim 1 , wherein the first resonant tunneling layer comprises a material having a lower energy barrier than the charge trapping layer.

5. 10. The semiconductor device of claim 1, wherein the first resonant tunneling layer comprises tantalum pentoxide (Ta2O5), gallium oxide (Ga2O3), gadolinium oxide (Gd2O3), lanthanum oxide (La2O3), hafnium oxide (HfO2), gallium nitride (GaN), or a combination thereof.

6. the tunnel layer comprises silicon oxide, silicon nitride, aluminum oxide, magnesium oxide, or zirconium oxide; the charge trapping layer comprises silicon nitride; The semiconductor device of claim 1 , wherein the blocking layer comprises aluminum oxide.

7. The semiconductor device of claim 1 , wherein the first resonant tunneling layer has a thickness less than that of the tunneling layer.

8. the tunnel layer has a thickness of 1 nanometer (nm) to 7 nanometers (nm); 8. The semiconductor device of claim 7, wherein the first resonant tunneling layer has a thickness of 0.5 nanometers (nm) to 3 nanometers (nm).

9. The semiconductor device of claim 1 , wherein the second resonant tunneling layer has a thickness less than that of the tunneling layer.

10. the tunnel layer has a thickness of 1 nanometer (nm) to 7 nanometers (nm); 10. The semiconductor device of claim 9, wherein the second resonant tunneling layer has a thickness of 0.5 nanometers (nm) to 3 nanometers (nm).

11. channel patterns, an electrode on the channel pattern; and an information storage pattern between the channel pattern and the electrode; The information storage pattern is a tunnel layer adjacent to the channel pattern; a blocking layer adjacent to the electrode; a charge trap layer between the tunnel layer and the blocking layer; and A semiconductor device including at least one resonant tunneling layer disposed between the tunneling layer and the blocking layer, the resonant tunneling layer having a material with a lower energy barrier than the tunneling layer and the blocking layer.

12. The semiconductor device of claim 11 , wherein the at least one resonant tunneling layer comprises a material with a lower energy barrier than the charge trapping layer.

13. the tunnel layer comprises silicon oxide, silicon nitride, aluminum oxide, magnesium oxide, or zirconium oxide; 12. The semiconductor device of claim 11, wherein the at least one resonant tunneling layer comprises tantalum pentoxide (Ta2O5), gallium oxide (Ga2O3), gadolinium oxide (Gd2O3), lanthanum oxide (La2O3), hafnium oxide (HfO2), gallium nitride (GaN), or a combination thereof.

14. The semiconductor device of claim 11 , wherein the at least one resonant tunneling layer has a thickness less than the tunneling layer.

15. the tunnel layer has a thickness of 1 nanometer (nm) to 7 nanometers (nm); 15. The semiconductor device of claim 14, wherein the at least one resonant tunneling layer has a thickness of 0.5 nanometers (nm) to 3 nanometers (nm).

16. a laminated structure having a plurality of alternating molding layers and a plurality of horizontal electrodes; a source line on the stacked structure; and a channel structure extending through the stack structure and into the source line; The channel structure comprises: a channel pattern contacting the source line; and an information storage pattern between the channel pattern and the stacked structure; The information storage pattern is a tunnel layer adjacent to the channel pattern; a blocking layer adjacent to the laminate structure; a charge trap layer between the tunnel layer and the blocking layer; and A semiconductor device including at least one resonant tunneling layer disposed between the tunneling layer and the blocking layer, the resonant tunneling layer having a material with a lower energy barrier than the tunneling layer and the blocking layer.

17. 17. The semiconductor device of claim 16, wherein the at least one resonant tunneling layer includes a first resonant tunneling layer between the tunneling layer and the charge trapping layer, the first resonant tunneling layer having a thickness less than that of the tunneling layer.

18. The semiconductor device of claim 17 , wherein the first resonant tunneling layer comprises a material having a lower energy barrier than the charge trapping layer.

19. the at least one resonant tunneling layer includes a second resonant tunneling layer disposed between the charge trapping layer and the blocking layer, the second resonant tunneling layer having a material with a lower energy barrier than the charge trapping layer; The semiconductor device of claim 16 , wherein the second resonant tunneling layer has a thickness less than the tunneling layer.

20. the tunnel layer comprises silicon oxide, silicon nitride, aluminum oxide, magnesium oxide, or zirconium oxide; 17. The semiconductor device of claim 16, wherein the at least one resonant tunneling layer comprises tantalum pentoxide (Ta2O5), gallium oxide (Ga2O3), gadolinium oxide (Gd2O3), lanthanum oxide (La2O3), hafnium oxide (HfO2), gallium nitride (GaN), or a combination thereof.

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