Operational amplifier circuit

Abstract

To suppress the power supply voltage dependency of an idle current in an output stage.SOLUTION: A source-grounded class AB output stage 130 includes a P-type output transistor MP1 and an N-type output transistor MN1. An idle current control circuit 140A controls idle currents Iidle_P and Iidle_N of a source-grounded class AB output stage 130 A. A P-type bias transistor MP3 and an N-type bias transistor MN3 are connected in parallel between a gate of the P-type output transistor MP1 and a gate of the N-type output transistor MN1. A first reference current source 142 and a second reference current source 144 generate a first reference current Iref_P and a second reference current Iref_N, respectively, which have a negative correlation with a power source voltage VDD.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to operational amplifier circuits. [Background technology]

[0002] An operational amplifier (op-amp) is a particularly important component of electronic circuits. Op-amp circuit types are classified into Class A, Class AB, Class B, etc. depending on the configuration of the output stage.

[0003] Op-amps that require rail-to-rail operation use a common-source class AB output stage. A cross-coupled feed-forward class AB output stage has a common-source output stage, and its idle current is controlled by a circuit topology called a floating current mirror circuit. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2021-132357

[0005] [overview] The present disclosure has been made in light of this situation, and one exemplary purpose of an embodiment thereof is to provide an operational amplifier circuit in which the dependency of the idle current of the output stage on the power supply voltage is suppressed.

[0006] An operational amplifier circuit according to an embodiment of the present disclosure includes a common-source class AB output stage including a P-type output transistor and an N-type output transistor, and an idle current control circuit that controls an idle current of the class AB output stage. The idle current control circuit includes a P-type bias transistor and an N-type bias transistor connected in parallel between the gate of the P-type output transistor and the gate of the N-type output transistor, a first reference current source that generates a first reference current that has a negative correlation with a power supply voltage, a second reference current source that generates a second reference current that has a negative correlation with the power supply voltage, a P-type replica transistor that corresponds to the P-type output transistor, has its source connected to a power supply line, its gate and drain connected, and is provided on the path of the first reference current, and an N-type replica transistor that corresponds to the N-type output transistor, has its source connected to a ground line, its gate and drain connected, and is provided on the path of the second reference current, wherein the P-type replica transistor and the P-type output transistor form a floating current mirror circuit, and the N-type replica transistor and the N-type output transistor form a floating current mirror circuit.

[0007] Any combination of the above components, or mutual substitution of components or expressions between methods, devices, systems, etc. are also valid aspects of the present invention. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a circuit diagram of an operational amplifier circuit according to an embodiment. [Figure 2] FIG. 2 is a diagram illustrating the operation of the floating current mirror circuit in the comparative technique. [Figure 3] FIG. 3 is a diagram illustrating the power supply voltage dependency of the idle current of an operational amplifier circuit according to the comparative technique. [Figure 4] FIG. 4 is a diagram illustrating the power supply voltage dependency of the idle current of the operational amplifier circuit according to the embodiment. [Figure 5] FIG. 5 is a circuit diagram of an operational amplifier circuit according to the first embodiment. [Figure 6]FIG. 6 is a circuit diagram showing a specific example of the configuration of the first reference current source and the second reference current source. [Figure 7] FIG. 7 is a circuit diagram of an operational amplifier circuit according to a second embodiment. [Figure 8] FIG. 8 is a circuit diagram of an operational amplifier circuit according to a third embodiment.

[0009] [Detailed explanation] (Outline of the embodiment) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. This summary is not an exhaustive overview of all possible embodiments, and is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0010] An operational amplifier circuit according to one embodiment includes a common-source class AB output stage including a P-type output transistor and an N-type output transistor, and an idle current control circuit for controlling an idle current of the class AB output stage. The idle current control circuit includes a P-type bias transistor and an N-type bias transistor connected in parallel between the gate of the P-type output transistor and the gate of the N-type output transistor, a first reference current source for generating a first reference current having a negative correlation with a power supply voltage, a second reference current source for generating a second reference current having a negative correlation with the power supply voltage, a P-type replica transistor corresponding to the P-type output transistor, having its source connected to a power supply line and its gate-drain wired, and provided on the path of the first reference current, and an N-type replica transistor corresponding to the N-type output transistor, having its source connected to a ground line, its gate-drain wired, and provided on the path of the second reference current. The P-type replica transistor and the P-type output transistor form a floating current mirror circuit, and the N-type replica transistor and the N-type output transistor form a floating current mirror circuit.

[0011] This configuration can prevent the bias current of the N-type output transistor from increasing when the power supply voltage increases, and similarly, can prevent the bias current of the P-type output transistor from increasing when the power supply voltage increases.

[0012] In one embodiment, the first reference current source may include a first constant current source that sinks a first constant current and a first variable current source that sources a first variable current that has a positive correlation with the power supply voltage, and the second reference current source may include a second constant current source that sources a second constant current and a second variable current source that sinks a second variable current that has a positive correlation with the power supply voltage.

[0013] In one embodiment, the first variable current source may include a first P-type transistor having a source connected to a power supply line and a gate and a drain connected together, a first resistor connected between the drain of the first P-type transistor and a ground line, and a second P-type transistor having a source connected to the power supply line and a gate connected to the gate of the first P-type transistor.

[0014] In one embodiment, the second variable current source may include a first N-type transistor having a source connected to a ground line and a gate and a drain connected together, a second resistor connected between the drain of the first N-type transistor and a power supply line, and a second N-type transistor having a source connected to the ground line and a gate connected to the gate of the first N-type transistor.

[0015] (Embodiment) The present disclosure will be described below with reference to the drawings based on preferred embodiments. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are examples rather than limitations on the invention or disclosure, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention or disclosure.

[0016] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or impair the functions or effects achieved by their combination.

[0017] Similarly, "a state in which component C is provided between component A and component B" includes not only a case in which component A and component C, or component B and component C, are directly connected, but also a case in which they are indirectly connected via other components that do not substantially affect the electrical connection state between them or impair the functions or effects achieved by their combination.

[0018] 1 is a circuit diagram of an operational amplifier circuit 100A according to an embodiment. The operational amplifier circuit 100A includes a differential input stage 110, a gain stage 120, a class AB output stage 130, and an idle current control circuit 140.

[0019] The class AB output stage 130 is a common-source output stage including a P-type output transistor (P-channel MOSFET: Metal Oxide Semiconductor Field Effect Transistor) MP1 and an N-type output transistor (N-channel MOSFET) MN1.

[0020] The differential input stage 110 outputs a signal corresponding to the error between the differential input signals +IN and −IN. The gain stage 120 amplifies the output of the differential input stage 110 and supplies it to the class AB output stage 130. Note that the gain stage 120 may be omitted, in which case the output signal of the differential input stage 110 is supplied directly to the class AB output stage 130.

[0021] The idle current control circuit 140 controls and adjusts the idle currents Iidle_P and Iidle_N flowing through the P-type output transistor MP1 and the N-type output transistor MN1 of the class AB output stage .

[0022] The idle current control circuit 140 includes a P-type replica transistor MP2, an N-type replica transistor MN2, P-type bias transistors MP3 and MP4, N-type bias transistors MN3 and MN4, a first reference current source 142, a second reference current source 144, and current sources CS1 and CS2.

[0023] The first reference current source 142 sinks the reference current Iref_P. The P-type replica transistor MP2 is a replica of the P-type output transistor MP1, and its gate and drain are connected together, and its source is connected to a power supply line. The P-type replica transistor MP2 is disposed on the path of the reference current Iref_P.

[0024] The second reference current source 144 sources a reference current Iref_N. The N-type replica transistor MN2 is a replica of the N-type output transistor NP1, and has its gate and drain connected together and its source connected to a ground line. The N-type replica transistor MN2 is disposed on the path of the reference current Iref_N.

[0025] The P-type bias transistor MP3 and the N-type bias transistor MN3 are connected in parallel between the gate of the P-type output transistor MP1 and the gate of the N-type output transistor MN1.

[0026] The current source CS1 is connected between the power supply line and the gate of the P-type output transistor MP1, and the current source CS2 is connected between the gate of the N-type output transistor MN1 and the ground line.

[0027] The P-type bias transistor MP4 has its gate and drain connected, and is provided between the P-type replica transistor MP2 and the first reference current source 142. The N-type bias transistor MN4 has its gate and drain connected, and is provided between the N-type replica transistor MN2 and the second reference current source 144.

[0028] When the gate-source voltages of transistors MP3 and MP4 are equal, the gate-source voltages of the P-type output transistor MP1 and the P-type replica transistor MP2 are equal, and the transistor pair MP1 and MP2 form a current mirror circuit (called a floating current mirror circuit). Therefore, an idle current Iidle_P proportional to the reference current Iref_P flows through the P-type output transistor MP1.

[0029] Similarly, when the gate-source voltages of transistors MN3 and MN4 are equal, the gate-source voltages of N-type output transistor MN1 and N-type replica transistor MN2 are also equal, and the transistor pair MN1 and MN2 form a floating current mirror circuit. As a result, an idle current Iidle_N proportional to the reference current Iref_N flows through N-type output transistor MN1.

[0030] In this embodiment, the reference current Iref_P generated by the first reference current source 142 is DD Similarly, the reference current Iref_N generated by the second reference current source 144 has a negative correlation (negative power supply voltage dependency) with the power supply voltage V DD It has a negative correlation with (negative power supply voltage dependency).

[0031] The above is the configuration of the operational amplifier circuit 100A.

[0032] The advantages of the operational amplifier circuit 100A become clear when compared with the comparative technique, in which the first reference current source 142 and the second reference current source 144 generate constant reference currents Iref_P and Iref_N that are independent of the power supply voltage.

[0033] 2 is a diagram illustrating the operation of the floating current mirror circuit, showing the IV characteristics of transistors MP1 and MP2.

[0034] Regarding the P-type replica transistor MP2, the drain-source voltage Vds2 is equal to the gate-source voltage Vgs2, and when a certain amount of reference current Iref_P flows, the power supply voltage V DD On the other hand, the drain-source voltage Vds1 of the P-type output transistor MP1 is a constant voltage regardless of the power supply voltage V DD The higher the value, the larger the value.

[0035] 3 is a diagram illustrating the power supply voltage dependence of the idle current of an operational amplifier circuit according to a comparative technique. The upper part shows the current ratio (mirror ratio) α of the floating current mirror circuit, the middle part shows the reference current Iref_P, and the lower part shows the idle current Iidle_P of the P-type output transistor MP1.

[0036] Power supply voltage V DDWhen the drain-source voltage Vds2 of the P-type output transistor MP1 increases relative to the drain-source voltage Vds1 of the P-type replica transistor MP2, and the current ratio of the floating current mirror circuit increases. In the comparative technology, the reference current Iref_P, which is the input current of the floating current mirror circuit, is constant. Therefore, the idle current Iidle_P, which is the output current of the floating current mirror circuit, is the product of the current ratio α and the input current, and is expressed as follows: DD increases as increases.

[0037] The same problem occurs with a floating current mirror circuit consisting of an N-type output transistor MN1 and an N-type replica transistor MN2. These are the problems with the comparative technology.

[0038] Next, the operation of the operational amplifier circuit 100A according to the embodiment will be described.

[0039] 4 is a diagram illustrating the power supply voltage dependence of the idle current of the operational amplifier circuit according to the embodiment. The upper part shows the current ratio (mirror ratio) α of the floating current mirror circuit, the middle part shows the reference current Iref_P, and the lower part shows the idle current Iidle_P.

[0040] The current ratio (mirror ratio) α of the floating current mirror circuit in the upper stage is the same as that of the comparative technology. In the comparative technology, the reference current Iref_P is DD In the embodiment, the reference current Iref_P is constant regardless of the power supply voltage V DD It has a negative dependency on

[0041] Therefore, the power supply voltage dependency of the current ratio α and the power supply voltage dependency of the reference current Iref_P cancel each other out, and the power supply voltage dependency of the idle current Iidle_P, which is their product, can be reduced. In other words, the power supply voltage dependency of the reference current Iref_P is DD It is designed to be constant regardless of

[0042] Similarly, the power supply voltage dependency of the idle current Iidle_N can be reduced for the floating current mirror circuit made up of the N-type output transistor MN1 and the N-type replica transistor MN2.

[0043] The present disclosure covers various devices and methods that can be understood as the block diagram or circuit diagram of Figure 1 or derived from the above description, and is not limited to a specific configuration. Below, more specific configuration examples and examples will be described not to narrow the scope of the present disclosure, but to aid in understanding and clarify the essence and operation of the present disclosure and the present invention.

[0044] Example 1 5 is a circuit diagram of an operational amplifier circuit 100B according to the first embodiment. In the first embodiment, the gain stage 120 is omitted.

[0045] The differential input stage 110B includes a differential pair 112, a tail current source 114, and a current mirror load 116. The output signal of the differential input stage 110B is supplied to the gate of an N-type output transistor MN1.

[0046] In the idle current control circuit 140B, the first reference current source 142 includes a first constant current source 142a and a first variable current source 142b whose outputs are connected in common. The first constant current source 142a is connected to a power supply voltage V DD The first variable current source 142b sinks a constant current Ic1 that is independent of the power supply voltage V DD The first reference current source 142 sources a variable current Iv1 having a positive correlation (positive power supply voltage dependency) with respect to the reference current Iref_P. The reference current Iref_P generated by the first reference current source 142 is expressed by the following equation. Iref_P(V DD )=Ic1-Iv1(V DD )

[0047] The second reference current source 144 includes a second constant current source 144a and a second variable current source 144b, the outputs of which are connected in common. The second constant current source 144a is connected to a power supply voltage V DDThe second variable current source 144b sources a constant current Ic2 that is independent of the power supply voltage V DD The second reference current source 144 sinks a variable current Iv2 that has a positive correlation (positive power supply voltage dependency) with respect to the reference current Iref_N. The reference current Iref_N generated by the second reference current source 144 is expressed by the following equation. Iref_N(V DD )=Ic2-Iv2(V DD )

[0048] FIG. 6 is a circuit diagram showing a specific example of the configuration of the first reference current source 142 and the second reference current source 144. As shown in FIG.

[0049] The first constant current source 142a includes an N-type transistor MN11. A bias voltage N_bias_ref is applied to the gate of the N-type transistor MN11 so that a constant current Ic1 flows.

[0050] The first variable current source 142b includes P-type transistors MP12 and MP13 and a first resistor R11. The P-type transistors MP12 and MP13 form a current mirror circuit, and the first resistor R11 is connected between the drain of the input-side transistor MP12 and the ground line. The first variable current Iv1 is expressed by the following equation: Iv1=(V DD -Vgs) / R11×β1 Vgs is the gate-source voltage of the P-type transistor MP12, and β1 is the current ratio determined by the ratio of the sizes (W / L) of the transistors MP12 and MP13. That is, the first variable current Iv1 is DD It changes at a constant slope relative to

[0051] The second constant current source 144a includes a P-type transistor MP11. A bias voltage P_bias_ref is applied to the gate of the P-type transistor MP11 so that a constant current Ic2 flows.

[0052] The second variable current source 144b includes N-type transistors MN12 and MN13 and a second resistor R12. The N-type transistors MN12 and MN13 form a current mirror circuit, and the second resistor R12 is connected between the drain of the input-side transistor MN12 and the power supply line. The second variable current Iv2 is expressed by the following equation: Iv2=(V DD -Vgs) / R12×β2 Vgs is the gate-source voltage of N-type transistor MN12, and β2 is the current ratio determined by the ratio of the sizes (W / L) of transistors MN12 and MN13.

[0053] The configuration of the first reference current source 142 and the second reference current source 144 is not limited to that shown in FIG. 6, and they can be configured using known technology or circuits that can be used in the future.

[0054] Example 2 7 is a circuit diagram of an operational amplifier circuit 100C according to a second embodiment. The operational amplifier circuit 100C is a rail-to-rail amplifier. A differential input stage 110C includes a differential pair 112P, 112N and tail current sources 114P, 114N.

[0055] The idle current control circuit 140C is integrally formed with the gain stage 120C. The gain stage 120C is a folded cascode circuit and includes transistors MN5 to MN8 and MP5 to MP8. The cross-coupled bias transistor pairs MP3_1, MN3_1 and MP3_2, MN3_2, which are part of the idle current control circuit 140C, are incorporated into the gain stage 120C. In the figure, P_bias_R, N_bias_R, P_bias_ref, and N_bias_ref indicate bias voltages.

[0056] Example 3 8 is a circuit diagram of an operational amplifier circuit 100D according to Example 3. The operational amplifier circuit 100D is a rail-to-rail amplifier, similar to the operational amplifier circuit 100C in FIG.

[0057] The idle current control circuit 140D in Fig. 8 is provided with an operational amplifier OA1 instead of the transistor MP14 in the idle current control circuit 140C in Fig. 7, and an operational amplifier OA2 instead of the transistor MN14. The operational amplifier OA1 generates a bias voltage P_bias_C so that the gate voltage of the P-type output transistor MP1 is equal to the gate voltage of the P-type replica transistor MP2. As a result, the P-type output transistor MP1 and the P-type replica transistor MP2 operate as a current mirror circuit, and an idle current Iidle_P proportional to the reference current Iref_P flows through the P-type output transistor MP1.

[0058] The operational amplifier OA2 generates a bias voltage N_bias_C so that the gate voltage of the N-type output transistor MN1 is equal to the gate voltage of the N-type replica transistor MN2. As a result, the N-type output transistor MN1 and the N-type replica transistor MN2 operate as a current mirror circuit, and an idle current Iidle_N proportional to the reference current Iref_N flows through the N-type output transistor MN1.

[0059] The embodiments are merely examples, and it will be understood by those skilled in the art that there are various variations in the combination of each component and each treatment process, and that such variations are also included in the present disclosure and can constitute the scope of the present invention.

[0060] (Addendum) The present specification discloses the following techniques.

[0061] (Item 1) a source-grounded class AB output stage including a P-type output transistor and an N-type output transistor; an idle current control circuit for controlling an idle current of the class AB output stage; Equipped with The idle current control circuit includes: a P-type bias transistor and an N-type bias transistor connected in parallel between the gate of the P-type output transistor and the gate of the N-type output transistor; a first reference current source that generates a first reference current that has a negative correlation with a power supply voltage; a second reference current source that generates a second reference current that has a negative correlation with the power supply voltage; a P-type replica transistor corresponding to the P-type output transistor, the source of which is connected to a power supply line, the gate of which is connected to a drain of which is connected, and the P-type replica transistor is provided on a path of the first reference current; an N-type replica transistor corresponding to the N-type output transistor, the source of which is connected to a ground line, the gate of which is connected to a drain of which is connected, and the N-type replica transistor is provided on a path of the second reference current; wherein the P-type replica transistor and the P-type output transistor form a floating current mirror circuit, and the N-type replica transistor and the N-type output transistor form a floating current mirror circuit.

[0062] (Item 2) The first reference current source is a first constant current source that sinks a first constant current; a first variable current source that sources a first variable current that has a positive correlation with the power supply voltage; Including, The second reference current source is a second constant current source that sources a second constant current; a second variable current source that sinks a variable current that has a positive correlation with the power supply voltage; Item 2. The operational amplifier circuit of item 1, comprising:

[0063] (Item 3) The first variable current source a first P-type transistor having a source connected to the power supply line and a gate and a drain connected together; a first resistor connected between the drain of the first P-type transistor and the ground line; a second P-type transistor having a source connected to the power supply line and a gate connected to the gate of the first P-type transistor; 3. The operational amplifier circuit of claim 2, comprising:

[0064] (Item 4) The second variable current source a first N-type transistor having a source connected to the ground line and a gate and a drain connected together; a second resistor connected between the drain of the first N-type transistor and the power supply line; a second N-type transistor having a source connected to the ground line and a gate connected to the gate of the first N-type transistor; 4. The operational amplifier circuit of claim 2 or 3, comprising: [Explanation of symbols]

[0065] 100 Op-amp Circuits 110 Differential Input Stage 112 differential pair 114 Tail Current Source 116 Current mirror load 120 gain stage 130 AB class output stage MP1 P-type output transistor MN1 N-type output transistor MP2 P-type replica transistor MN2 N-type replica transistor MP3 P-type bias transistor MN3 N-type bias transistor 140 Idle current control circuit 142 1st reference current source 142a 1st constant current source 142b First variable current source 144 2nd reference current source 144a 2nd constant current source 144b Second variable current source

Claims

1. a source-grounded class AB output stage including a P-type output transistor and an N-type output transistor; an idle current control circuit for controlling an idle current of the class AB output stage; Equipped with The idle current control circuit includes: a P-type bias transistor and an N-type bias transistor connected in parallel between the gate of the P-type output transistor and the gate of the N-type output transistor; a first reference current source that generates a first reference current that has a negative correlation with a power supply voltage; a second reference current source that generates a second reference current that has a negative correlation with the power supply voltage; a P-type replica transistor corresponding to the P-type output transistor, having a source connected to a power supply line, a gate and a drain connected together, and provided on a path of the first reference current; an N-type replica transistor corresponding to the N-type output transistor, having a source connected to a ground line, a gate and a drain connected together, and provided on a path of the second reference current; wherein the P-type replica transistor and the P-type output transistor form a floating current mirror circuit, and the N-type replica transistor and the N-type output transistor form a floating current mirror circuit.

2. The first reference current source is a first constant current source that sinks a first constant current; a first variable current source for sourcing a first variable current having a positive correlation with the power supply voltage; Including, The second reference current source is a second constant current source that sources a second constant current; a second variable current source for sinking a variable current having a positive correlation with the power supply voltage; 2. The operational amplifier circuit of claim 1, comprising:

3. The first variable current source a first P-type transistor having a source connected to the power supply line and a gate and a drain connected together; a first resistor connected between the drain of the first P-type transistor and the ground line; a second P-type transistor having a source connected to the power supply line and a gate connected to the gate of the first P-type transistor; 3. The operational amplifier circuit of claim 2, comprising:

4. The second variable current source a first N-type transistor having a source connected to the ground line and a gate and a drain connected together; a second resistor connected between the drain of the first N-type transistor and the power supply line; a second N-type transistor having a source connected to the ground line and a gate connected to the gate of the first N-type transistor; 4. The operational amplifier circuit of claim 2, comprising:

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