Electrostatic discharge protection structure, semiconductor power device, and manufacturing method thereof

Abstract

To provide a trench-type semiconductor power device having an electrostatic discharge protection structure, and a method for manufacturing the same.SOLUTION: An electrostatic discharge protection structure 150 in a semiconductor device includes a first trench structure TR2 including a first polysilicon structure 144, and a first oxide layer 143 surrounding the first polysilicon structure. A second trench structure TR3 includes a second polysilicon structure 146, and a second oxide layer 145 surrounding the second polysilicon structure. A first diode string 151 is disposed between the first trench structure and the second trench structure and adjoins the first polysilicon structure and the second polysilicon structure. A first spacing oxide layer SX1 is disposed on the first diode string. A second diode string 156 is disposed on the first spacing oxide layer and connected in parallel with the first diode string.SELECTED DRAWING: Figure 3A

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This patent application claims priority to Chinese Patent Application No. 202410126085.1, entitled "ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE, SEMICONDUCTOR POWER DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR POWER DEVICE," filed on January 30, 2024, which is incorporated herein by reference as if reprinted in its entirety.

[0002]

[0002] The present disclosure relates generally to the field of semiconductor devices, and more particularly to techniques and mechanisms for electrostatic discharge protection structures, semiconductor power devices, and methods for manufacturing semiconductor power devices. Particular embodiments provide trench-type semiconductor power devices with electrostatic discharge protection structures and methods for manufacturing the same. [Background technology]

[0003]

[0003] Semiconductor power devices are widely used in the field of electronics. Trench power devices, in which a gate oxide layer is grown on the sidewalls of a gate trench and filled with polysilicon to form the gate, are one of the most common power switching devices. Trench power devices can improve the utilization efficiency of device area, and therefore can achieve a larger device unit channel width per unit area, thereby achieving a larger current carrying capacity.

[0004]

[0004] Semiconductor power devices are susceptible to voltage spikes caused by electrostatic discharge (ESD) events. The momentary large current and high voltage caused by an ESD event can cause dielectric breakdown of the gate oxide layer of trench power devices, leading to damage and even burnout or high leakage. Therefore, semiconductor power devices must have ESD protection capabilities. Summary of the Invention

[0005] Technical advantages are generally achieved by embodiments of the present disclosure which describe electrostatic discharge protection structures, semiconductor power devices, and methods of manufacturing semiconductor power devices.

[0006]

[0006] An embodiment of the present disclosure relates to an electrostatic discharge protection structure. The electrostatic discharge protection structure includes a first trench structure, a second trench structure, a first diode string, a first spacer oxide layer, and a second diode string. The first trench structure includes a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure. The second trench structure includes a second polysilicon structure and a second oxide layer surrounding the second polysilicon structure. The first diode string is adjacent to the first polysilicon structure and the second polysilicon structure and is disposed between the first trench structure and the second trench structure. The first spacer oxide layer is disposed on the first diode string. The second diode string is disposed on the first spacer oxide layer and is disposed in parallel with the first diode string.

[0007]

[0007] An embodiment of the present disclosure relates to a semiconductor power device. The semiconductor power device includes a substrate, a lightly doped layer, a first trench structure, a source-doped region, an interlayer dielectric layer, a source electrode, a gate electrode, and an electrostatic discharge protection structure. The lightly doped layer is disposed on the substrate. The first trench structure is disposed in the lightly doped layer and extends toward the substrate. The first trench structure includes a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure. The source-doped region is disposed in the lightly doped layer and is spaced from the substrate. The interlayer dielectric layer is disposed on the lightly doped layer. The source electrode is connected to the source-doped region. The gate electrode is connected to the first polysilicon structure. The electrostatic discharge protection structure is disposed in the interlayer dielectric layer and includes a first diode string, a second diode string, and a first spacer oxide layer. The second diode string is disposed on the first diode string. The first spacer oxide layer is disposed between the first and second diode strings, the first and second diode strings being arranged in parallel between the source and gate electrodes.

[0008]

[0008] An embodiment of the present disclosure relates to a method for manufacturing a semiconductor power device. The method includes: forming a lightly doped layer on a substrate; forming a first opening, a second opening, and a third opening in the lightly doped layer extending toward the substrate; forming a first diode string on the second opening and the third opening; forming a first spacer oxide layer on the first diode string to surround the first diode string; forming a second diode string on the first spacer oxide layer; forming a first trench structure in the first opening, the first trench structure including a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure; forming a source-doped region in the lightly doped layer disposed between the first trench structure and the second opening; forming a source electrode connected to the source-doped region and a gate electrode connected to the first polysilicon structure. The first diode string and the second diode string are arranged in parallel between the source electrode and the gate electrode.

[0009] According to one aspect of the present disclosure, there is provided an electrostatic discharge protection structure for use in a semiconductor device, the electrostatic discharge protection structure including: a first trench structure including a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure; a second trench structure including a second polysilicon structure and a second oxide layer surrounding the second polysilicon structure; a first diode string disposed between the first trench structure and the second trench structure and adjacent to the first polysilicon structure and the second polysilicon structure; a first spacer oxide layer disposed on the first diode string; and a second diode string disposed on the first spacer oxide layer, wherein the second diode string and the first diode string are connected in parallel.

[0010] According to another aspect of the present disclosure, there is provided a semiconductor power device including: a lightly doped layer disposed on a substrate; a first trench structure disposed in the lightly doped layer and extending toward the substrate, the first trench structure including a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure; an interlayer dielectric layer disposed on the lightly doped layer; a source electrode connected to a source-doped region disposed in the lightly doped layer; a gate electrode connected to the first polysilicon structure; and an electrostatic discharge protection structure disposed in the interlayer dielectric layer. The electrostatic discharge protection structure includes a first diode string; a second diode string disposed above the first diode string and connected in parallel with the first diode string between the source electrode and the gate electrode; and a first spacer oxide layer disposed between the first diode string and the second diode string.

[0011]

[0011] According to another aspect of the present disclosure, there is provided a method for manufacturing a semiconductor power device, the method including: forming a lightly doped layer on a substrate; forming a first opening, a second opening, and a third opening on the lightly doped layer extending toward the substrate; forming a first diode string above the second opening and the third opening; forming a first spacer oxide layer on the first diode string surrounding the first diode string; forming a second diode string on the first spacer oxide layer; forming a first trench structure in the first opening, the first trench structure having a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure; forming a source doped region in the lightly doped layer, the source doped region being disposed between the first trench structure and the second opening; forming a source electrode connected to the source doped region; and forming a gate electrode connected to the first polysilicon structure, wherein the first diode string and the second diode string are connected in parallel between the source electrode and the gate electrode.

[0012] The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the present disclosure will be described hereinafter, which form the subject of the claims of the present disclosure. Those skilled in the art should appreciate that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. Those skilled in the art should also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure as set forth in the appended claims.

[0013]

[0013] Aspects of certain embodiments of the present disclosure can be best understood when considering the following detailed description in conjunction with the accompanying drawings. It should be noted that the various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of illustration.

[0014] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a circuit diagram of an exemplary semiconductor power device according to an embodiment of the present disclosure. [Figure 2] FIG. 1 is a schematic diagram of an exemplary semiconductor power device according to an embodiment of the present disclosure. [Figure 3A] 1 is a schematic diagram of an exemplary electrostatic discharge protection structure according to an embodiment of the present disclosure. [Figure 3B] FIG. 1 is a circuit diagram of an electrostatic discharge protection structure according to an embodiment of the present disclosure. [Figure 4] 1 is a flowchart of a method for manufacturing a semiconductor power device according to an embodiment of the present disclosure. [Figure 5] 1 is a schematic diagram illustrating an exemplary semiconductor power device during fabrication in accordance with an embodiment of the present disclosure. [Figure 6] 1 is a schematic diagram illustrating an exemplary semiconductor power device during fabrication in accordance with an embodiment of the present disclosure. [Figure 7] 1 is a schematic diagram illustrating an exemplary semiconductor power device during fabrication in accordance with an embodiment of the present disclosure. [Figure 8] 1 is a schematic diagram illustrating an exemplary semiconductor power device during fabrication in accordance with an embodiment of the present disclosure. [Figure 9] 1 is a schematic diagram illustrating an exemplary semiconductor power device during fabrication in accordance with an embodiment of the present disclosure. [Figure 10] 1 is a schematic diagram illustrating an exemplary semiconductor power device during fabrication in accordance with an embodiment of the present disclosure. [Figure 11] 1 is a schematic diagram illustrating an exemplary semiconductor power device during fabrication in accordance with an embodiment of the present disclosure. [Figure 12] 1 is a schematic diagram illustrating an exemplary semiconductor power device during fabrication in accordance with an embodiment of the present disclosure. [Figure 13] 1 is a schematic diagram illustrating an exemplary semiconductor power device during fabrication in accordance with an embodiment of the present disclosure. [Figure 14] 1 is a schematic diagram illustrating an exemplary semiconductor power device during fabrication in accordance with an embodiment of the present disclosure. [Figure 15] 1 is a schematic diagram illustrating an exemplary semiconductor power device during fabrication in accordance with an embodiment of the present disclosure. [Figure 16] 1 is a schematic diagram illustrating an exemplary semiconductor power device during fabrication in accordance with an embodiment of the present disclosure. [Figure 17] 1 is a schematic diagram illustrating an exemplary semiconductor power device during fabrication in accordance with an embodiment of the present disclosure. [Figure 18] 1 is a schematic diagram illustrating an exemplary semiconductor power device during fabrication in accordance with an embodiment of the present disclosure. [Figure 19] 1 is a schematic diagram illustrating an exemplary semiconductor power device during fabrication in accordance with an embodiment of the present disclosure. [Figure 20] 1 is a schematic diagram illustrating an exemplary semiconductor power device during fabrication in accordance with an embodiment of the present disclosure. [Figure 21] 1 is a schematic diagram illustrating an exemplary semiconductor power device during fabrication in accordance with an embodiment of the present disclosure. [Figure 22] 1 is a schematic diagram illustrating an exemplary semiconductor power device during fabrication in accordance with an embodiment of the present disclosure. [Figure 23] 1 is a schematic diagram illustrating an exemplary semiconductor power device during fabrication in accordance with an embodiment of the present disclosure. [Figure 24] 1 is a schematic diagram illustrating an exemplary semiconductor power device during fabrication in accordance with an embodiment of the present disclosure. [Figure 25] 1 is a schematic diagram illustrating an exemplary semiconductor power device during fabrication in accordance with an embodiment of the present disclosure. [Figure 26] 1 is a schematic diagram illustrating an exemplary semiconductor power device during fabrication in accordance with an embodiment of the present disclosure. [Figure 27] 1 is a schematic diagram illustrating an exemplary semiconductor power device during fabrication in accordance with an embodiment of the present disclosure. [Figure 28] 1 is a schematic diagram illustrating an exemplary semiconductor power device during fabrication in accordance with an embodiment of the present disclosure. [Figure 29]1 is a schematic diagram illustrating an exemplary semiconductor power device during fabrication in accordance with an embodiment of the present disclosure. [Figure 30] 1 is a schematic diagram illustrating an exemplary semiconductor power device during fabrication in accordance with an embodiment of the present disclosure. [Figure 31] 1 is a schematic diagram illustrating an exemplary semiconductor power device during fabrication in accordance with an embodiment of the present disclosure. [Figure 32] 1 is a schematic diagram illustrating an exemplary semiconductor power device during fabrication in accordance with an embodiment of the present disclosure. [Figure 33] 1 is a schematic diagram illustrating an exemplary semiconductor power device during fabrication in accordance with an embodiment of the present disclosure. [Figure 34] 1 is a schematic diagram illustrating an exemplary semiconductor power device during fabrication in accordance with an embodiment of the present disclosure. [Figure 35] FIG. 2 is a schematic diagram of another exemplary semiconductor power device according to an embodiment of the present disclosure. [Figure 36] 1 is a schematic diagram of yet another exemplary semiconductor power device and an enlarged view of a portion thereof according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0016]

[0023] The same or similar components are designated with the same reference numerals in the drawings and the detailed description.Several embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0017]

[0024] Corresponding numbers and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly show relevant aspects of the embodiments and are not necessarily drawn to scale.

[0018]

[0025] The making and using of embodiments of the present disclosure are described in detail below. However, it should be understood that the concepts disclosed herein can be embodied in a wide variety of specific contexts, and that the specific embodiments described herein are merely illustrative and do not serve to limit the scope of the claims. Furthermore, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure, as defined by the appended claims.

[0019]

[0026] Furthermore, one or more features from one or more of the embodiments described below may be combined to produce alternative embodiments not expressly described, and features suitable for such combinations are understood to be within the scope of this disclosure. Accordingly, it is intended that the appended claims cover any such modifications or embodiments.

[0020]

[0027] The present disclosure is described with respect to embodiments in specific contexts, namely, electrostatic discharge protection structures, semiconductor power devices, and methods for manufacturing semiconductor power devices. However, the present disclosure may be applied to a variety of semiconductor devices. Various embodiments are described in detail below with reference to the accompanying drawings.

[0021]

[0028] The following disclosure provides numerous different embodiments or examples for implementing the different features provided. Specific examples of components and configurations are described below. Of course, these are merely examples and are not intended to be limiting. In this disclosure, a reference to a first feature being formed above or on a second feature can include embodiments in which the first and second features are formed so that they are in direct contact, as well as embodiments in which additional features may be formed between the first and second features such that they do not need to be in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations described.

[0022]

[0029] The following is a detailed description of embodiments of the present disclosure. However, it should be understood that the present disclosure provides many applicable concepts that can be embodied in a variety of specific environments. The specific embodiments described are merely examples and do not limit the scope of the present disclosure.

[0023]

[0030] The present disclosure provides an electrostatic discharge protection structure. The electrostatic discharge protection structure uses a stacked design, so that multiple diode strings for discharging a momentary large current can be arranged in parallel with each other according to the stacked structure, which does not occupy additional circuit area (footprint) and also increases the amount of electrostatic discharge conduction current. Compared with general electrostatic discharge protection structures, the electrostatic discharge protection structure of the present disclosure can have more diode strings for discharging a momentary large current on the same circuit area, thereby providing greater electrostatic discharge protection capability.

[0024]

[0031] The present disclosure further provides a semiconductor power device and a method for manufacturing the same, which includes the electrostatic discharge protection structure described above and can accommodate more diode strings in the same circuit area to dissipate momentary large currents compared to a typical semiconductor power device, thereby providing greater electrostatic discharge protection capability.

[0025]

[0032] 1 is a circuit diagram of a semiconductor power device 1 according to some embodiments of the present disclosure. The semiconductor power device 1 has a gate electrode G, a drain electrode D, and a source electrode S (sometimes referred to as a gate terminal G, a drain terminal D, and a source terminal S, respectively), and includes a power transistor, a gate resistor RG, and an electrostatic discharge protection structure 150. In some embodiments, the power transistor may be a vertical power transistor 10. The power transistor 10 may be various types of semiconductor power devices or may be fabricated by different technologies. The source and drain of the power transistor 10 are connected to the source electrode S and the drain electrode D, respectively. The gate of the power transistor 10 is connected to the gate electrode G via the gate resistor RG. The electrostatic discharge protection structure 150 is connected between the gate electrode G and the source electrode S.

[0026]

[0033] 1, the power transistor 10 is an N-type transistor, however, the present disclosure is not limited thereto, and in other embodiments, the power transistor 10 may be a P-type transistor.

[0027]

[0034] In some embodiments, the electrostatic discharge protection structure 150 includes multiple diode strings connected in parallel between a gate electrode G and a source electrode S. Each diode string includes multiple back-to-back diodes connected in series. In some embodiments, each diode string has the same configuration.

[0028]

[0035] 1, electrostatic discharge protection structure 150 may include diode string 151 and diode string 156, and each of diode string 151 and diode string 156 may include two back-to-back diodes. While the present disclosure uses the number of diode strings and the number of back-to-back diodes as shown in FIG. 1 for illustrative purposes only, it should be understood that the present disclosure is not limited thereto and that various numbers of diode strings and various numbers of back-to-back diodes may be included in electrostatic discharge protection structure 150 and are within the scope of the present disclosure.

[0029]

[0036] The number of back-to-back diodes in a single diode string determines the withstand voltage of the electrostatic discharge protection structure 150, and the number of diode strings connected in parallel determines the amount of conduction current of the electrostatic discharge protection structure 150. The electrostatic discharge protection structure 150 can be viewed as a current path, and the number of back-to-back diodes in a single diode string can determine the conduction voltage threshold, and the number of diode strings connected in parallel can determine the width of the current path.

[0030]

[0037] In some embodiments, the number of back-to-back diodes may be determined by the withstand voltage of the semiconductor power device 1, such as the breakdown voltage of the gate oxide layer of the power transistor 10. More specifically, when an electrostatic discharge event occurs, the gate resistor RG can prevent a momentary large current generated by the electrostatic discharge event from the gate electrode G from directly attacking the gate (e.g., gate oxide) of the power transistor 10, and can direct the momentary large current away from the power transistor 10 to the source electrode S via the electrostatic discharge protection structure 150. In some embodiments, the source electrode S may be connected to a ground terminal, so that a momentary large current caused by the electrostatic discharge event can flow to the ground terminal through the electrostatic discharge protection structure 150. In other words, when an electrostatic discharge event occurs, the gate resistor RG and the electrostatic discharge protection structure 150 can provide electrostatic discharge protection for the power transistor 10. However, for the electrostatic discharge protection structure 150 to function, a condition must be met: the withstand voltage of the electrostatic discharge protection structure 150 must be lower than the breakdown voltage of the gate oxide layer of the power transistor 10. If the voltage caused by the momentary large current first reaches the withstand voltage of the electrostatic discharge protection structure 150, the electrostatic discharge protection structure 150 can be turned on and no current will flow to the gate of the power transistor 10. Therefore, the number of back-to-back diodes in each diode string is limited by the breakdown voltage of the gate oxide layer of the power transistor 10.

[0031]

[0038] 2 is a schematic diagram of a semiconductor power device 1 according to some embodiments of the present disclosure. The semiconductor power device 1 includes a substrate 100, a lightly doped layer 110, and an interlayer dielectric layer 130. The lightly doped layer 110 is disposed on the substrate 100, and the interlayer dielectric layer 130 is disposed on the lightly doped layer 110.

[0032]

[0039] In some embodiments, the substrate 100 may be disposed adjacent to the top surface of a silicon wafer or other substrate of semiconductor material. In some embodiments, the substrate 100 is a portion of a silicon wafer. The material of the substrate 100 may include single crystal silicon material, epitaxial silicon material, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), gallium arsenide phosphide (GaAsP), or other semiconductor material. In some embodiments, the doping concentration of the substrate 100 may be higher than the doping concentration of the lightly doped region 110.

[0033]

[0040] In some embodiments, the lightly doped layer 110 may include, for example, a single-crystal silicon material, an epitaxial silicon material, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), gallium arsenide phosphide (GaAsP), or other semiconductor material, which may be N-type or P-type. In some embodiments, the lightly doped layer 110 is an N-type (first conductivity type) epitaxial material. For ease of explanation, the N-type is used as an example for the lightly doped layer 110 and the power transistor 10, but the present disclosure is not limited thereto. Whether the lightly doped layer 110 is N-type (first conductivity type) or P-type (second conductivity type) may be adjusted depending on the conductivity type of the power transistor 10.

[0034]

[0041] The semiconductor power device 1 further includes a plurality of trench structures TR1, TR2, TR3, and an electrostatic discharge protection structure 150. The plurality of trench structures TR1, TR2, and TR3 are disposed in the lightly doped layer 110 and extend toward the substrate 100 without contacting the substrate 100. Each trench structure may have sidewalls and a bottom surface. In some embodiments, each trench structure may have vertical sidewalls and an arc-shaped bottom surface. The electrostatic discharge protection structure 150 is disposed in the interlayer dielectric layer 130.

[0035]

[0042] Each trench structure TR1 includes a polysilicon structure 142 and an oxide layer 141 surrounding the polysilicon structure 142. Trench structure TR2 includes a polysilicon structure 144 and an oxide layer 143 surrounding the polysilicon structure 144. Trench structure TR3 includes a polysilicon structure 146 and an oxide layer 145 surrounding the polysilicon structure 146. In some embodiments, the multiple trench structures TR1 may be part of a gate structure of the power transistor 10, and the oxide layer 141 in trench structure TR1 is the gate oxide layer of the power transistor 10. In some embodiments, trench structure TR2 and trench structure TR3 may be part of an electrostatic discharge protection structure 150. Although FIG. 2 shows two trench structures TR1 in the semiconductor power device 1, there may be three or more trench structures TR1.

[0036]

[0043] The semiconductor power device 1 may further include a plurality of body doped regions 121, a plurality of source doped regions 122, a plurality of heavily doped regions 123, a drain doped region 124, a heavily doped region 125, a plurality of conductive plugs CP1, and a conductive plug CP2. The body doped region 121, the source doped region 122, the heavily doped region 123, the drain doped region 124, and the heavily doped region 125 are disposed in the lightly doped layer 110. One of the body doped regions 121 may be located between two adjacent trench structures TR1 and adjacent to the oxide layer 141 of the two adjacent trench structures TR1. Another body doped region 121 may be located between the trench structure TR2 and a trench structure TR1 adjacent to the trench structure TR2 and adjacent to the oxide layer 141 of the trench structure TR1 and the oxide layer 143 of the trench structure TR2. One of the source-doped regions 122 may be located between two adjacent trench structures TR1 and on the corresponding body-doped region 121. Another source-doped region 122 may be located between the trench structure TR2 and the trench structure TR1 adjacent to the trench structure TR2 and on the corresponding body-doped region 121. In some embodiments, the thickness of the source-doped region 122 may be smaller than the thickness of the body-doped region 121. The source-doped region 122 may be adjacent to the body-doped region 121, the oxide layer 141, and / or the oxide layer 143. The drain-doped region 124 may be separated from the trench structure TR1, the trench structure TR2, and the trench structure TR3.

[0037]

[0044] The multiple heavily doped regions 123 may be disposed within the multiple body doped regions 121, respectively. In some embodiments, the heavily doped regions 123 may not be adjacent to the source doped regions 122. The heavily doped region 125 may be disposed within the lightly doped layer 110 below the drain doped region 124 and may not be adjacent to the drain doped region 124. The multiple conductive plugs CP1 may extend through the interlayer dielectric layer 130, further extend through each of the multiple source doped regions 122, and extend to the heavily doped region 123 within the multiple body doped regions 121. The conductive plug CP2 may extend through the interlayer dielectric layer 130 and the drain doped region 124 to reach the heavily doped region 125. The configuration of each conductive plug may vary depending on process or electrical requirements. The material of the conductive plugs may include gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), or other metals or alloys. In some embodiments, the conductive plugs CP1 and CP2 may have approximately the same length. In some embodiments, the conductive plugs CP1 and CP2 may have a configuration that is wide at the top and narrow at the bottom.

[0038]

[0045] The semiconductor power device 1 may further include metal wires 161, 162, and 163 disposed on the interlayer dielectric layer 130. The metal wire 161 may be electrically connected to the source doped region 122 via a conductive plug CP1 and may be connected to the source electrode S via an interconnect structure (not shown). The metal wire 162 may be electrically connected to the polysilicon structure 142 in the trench structure TR1 and may be connected to the gate electrode G via the interconnect structure. The metal wire 163 may be electrically connected to the drain doped region 124 via a conductive plug CP2 and may be connected to the drain electrode D via the interconnect structure. The electrostatic discharge protection structure 150 may be connected between the metal wire 161 and the metal wire 162. In other words, the electrostatic discharge protection structure 150 is connected between the source electrode S and the gate electrode G.

[0039]

[0046] In some embodiments, the width of metal wire 161 may be greater than the width of metal wire 162 and metal wire 163. The material of metal wire 161, metal wire 162, and metal wire 163 may include copper (Cu), gold (Au), silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), tungsten (W), tin (Sn), or other metals or alloys. In some embodiments, metal wire 161, metal wire 162, and metal wire 163 may be the metal layer closest to lightly doped layer 110 (e.g., the M1 layer).

[0040]

[0047] For ease of explanation and to keep the diagram simple, please refer to Figures 3A and 3B for symbols and details of the electrostatic discharge protection structure 150. Figure 3A is a schematic diagram of the electrostatic discharge protection structure 150 of Figure 2. Figure 3B is a circuit diagram of the electrostatic discharge protection structure 150 of Figure 2.

[0041]

[0048] The electrostatic discharge protection structure 150 may include a trench structure TR2, a trench structure TR3, a diode string 151, a diode string 156, a spacer oxide layer SX1, a spacer oxide layer SX2, a conductive plug CP3, and a conductive plug CP4. The trench structure TR2 and the trench structure TR3 are disposed in the lightly doped layer 110. The diode string 151 is connected between the trench structure TR2 and the trench structure TR3 and is disposed on the lightly doped layer 110. The diode string 156 is disposed on the diode string 151 and is electrically insulated from each other by the spacer oxide layer SX1. The spacer oxide layer SX2 is disposed on the diode string 156 and surrounds the diode string 156.

[0042]

[0049] The conductive plug CP3 and the conductive plug CP4 are electrically connected to the source electrode S and the gate electrode G via metal wires 161 and 162, respectively. The diode strings 151 and 156 are connected in parallel between the conductive plug CP3 and the conductive plug CP4. In other words, the diode strings 151 and 156 are connected in parallel between the source electrode S and the gate electrode G.

[0043]

[0050] Trench structure TR2 includes a polysilicon structure 144 and an oxide layer 143 surrounding polysilicon structure 144. Trench structure TR3 includes a polysilicon structure 146 and an oxide layer 145 surrounding polysilicon structure 146. As shown in FIGS. 2 and 3A, oxide layer 143 and oxide layer 145 extend along lightly doped layer 110 and are adjacent to each other. In some embodiments, oxide layer 143 and oxide layer 145 may be a single continuous structure.

[0044]

[0051] The diode string 151 includes a plurality of doped regions 151 a and a plurality of doped regions 151 b arranged alternately. The doped regions 151 a and the doped regions 151 b are of different conductivity types. The following description is based on the doped regions 151 a being N-type and the doped regions 151 b being P-type, and uses the number of doped regions as shown in FIGS. 2 and 3A as an example, but this is not intended to limit the present disclosure.

[0045]

[0052] In some embodiments, the diode string 151 includes three N-type doped regions 151a and two P-type doped regions 151b. The doped region 151a includes doped region 151a1, doped region 151a2, and doped region 151a3, and the doped region 151b includes doped region 151b1 and doped region 151b2. The doped regions 151a1, 151b1, 151a2, 151b2, and 151a3 may be arranged in order, and the doped regions 151a1 and 151a3 may function as a first end and a second end, respectively, of the diode string 151. The first end of the diode string 151 may be connected to the source electrode S and may be adjacent to the polysilicon structure 144 of the trench structure TR2. In some embodiments, doped region 151a1 and polysilicon structure 144 may be a single continuous structure. A second end of diode string 151 may be connected to gate electrode G and adjacent to polysilicon structure 146 in trench structure TR3. In some embodiments, doped region 151a3 and polysilicon structure 146 may be a single continuous structure.

[0046]

[0053] In the diode string 151, two adjacent doped regions have different conductivity types, thus forming a PN junction at the interface between the adjacent doped regions. As shown in FIG. 3B , the diode string 151 includes four interfaces between adjacent doped regions: the interface between adjacent doped regions 151a1 and 151b1, the interface between adjacent doped regions 151b1 and 151a2, the interface between adjacent doped regions 151a2 and 151b2, and the interface between adjacent doped regions 151b2 and 151a3. Thus, four PN junctions are formed. Because the different conductivity types are alternated, these four PN junctions form two back-to-back diodes connected in series.

[0047]

[0054] In some embodiments, diode string 151 and diode string 156 have the same number and type of doped regions. In some embodiments, diode string 151 and diode string 156 have the same structure.

[0048]

[0055] In some embodiments, the diode string 156 includes three N-type doped regions 156a and two P-type doped regions 156b. The doped region 156a includes doped region 156a1, doped region 156a2, and doped region 156a3, and the doped region 156b includes doped region 156b1 and doped region 156b2. The doped regions 156a1, 156b1, 156a2, 156b2, and 156a3 may be arranged in order, and the doped regions 156a1 and 156a3 may function as the first and second ends of the diode string 156, respectively. The first end of the diode string 156 is connected to the source electrode S, and the second end of the diode string 156 is connected to the gate electrode G. The diode string 156 includes four interfaces of adjacent doped regions, thereby forming four PN junctions, which form two back-to-back diodes connected in series.

[0049]

[0056] A spacer oxide layer SX1 is disposed on and surrounds the diode string 151. As shown in FIG. 2, the spacer oxide layer SX1 may further extend onto the surface of the lightly doped layer 110, covering the source doped region 122, the drain doped region 124, and the trench structure TR1. The conductive plugs CP1 and CP2 further extend through the spacer oxide layer SX1. A spacer oxide layer SX2 is disposed on and surrounds the diode string 156. The spacer oxide layer SX2 may be adjacent to the spacer oxide layer SX1 along a side of the diode string 156. The diode string 151 and the diode string 156 may be separated from the interlayer dielectric layer 130 by the spacer oxide layer SX1 and the spacer oxide layer SX2.

[0050]

[0057] The electrostatic discharge protection structure 150 may further include a heavily doped region 147 and a heavily doped region 148. The heavily doped region 147 may be disposed within the doped region 151a1, and the heavily doped region 148 may be disposed within the doped region 151a3. A conductive plug CP3 extends through the spacer oxide layer SX2, the doped region 156a1, and the spacer oxide layer SX1 to the heavily doped region 147 within the doped region 151a1 and connects the source electrode S to the doped region 151a1 and the doped region 156a1. A conductive plug CP4 extends through the spacer oxide layer SX2, the doped region 156a3, and the spacer oxide layer SX1 to the heavily doped region 148 within the doped region 151a3 and connects the gate electrode G to the doped region 151a3 and the doped region 156a3.

[0051]

[0058] An end of the conductive plug CP3 contacts the heavily doped region 147. The width of the heavily doped region 147 may be greater than the width of the end of the conductive plug CP3, and therefore the heavily doped region 147 may surround the end of the conductive plug CP3. An end of the conductive plug CP4 contacts the heavily doped region 148. The width of the heavily doped region 148 may be greater than the width of the end of the conductive plug CP4, and therefore the heavily doped region 148 may surround the end of the conductive plug CP4.

[0052]

[0059] For certain electrostatic discharge protection structures in the prior art, the current that can turn on the electrostatic discharge protection structure at a predetermined fixed withstand voltage is limited by the available circuit area. Furthermore, multiple diodes in an electrostatic discharge protection structure are typically arranged on the same plane. In comparison, the embodiments of the present disclosure better utilize three-dimensional space to provide multiple diodes in the electrostatic discharge protection structure 150. The diodes are arranged in stacks or layers within the available circuit area, and spacer oxide layers SX1 are used to separate diode rows in different layers. Therefore, for the same circuit area, the electrostatic discharge protection structure 150 provided in the embodiments of the present disclosure has a higher density of diodes. Furthermore, by using a parallel arrangement to increase the width of the equivalent current channel and reduce the resistance, the current that can turn on the electrostatic discharge protection structure 150 increases.

[0053]

[0060] FIG. 4 is a flowchart of a manufacturing method 4 of a semiconductor power device according to some embodiments of the present disclosure. The manufacturing method 4 includes steps S41, S42, S43, S44, S45, S46, and S47. FIGS. 5-34 are schematic diagrams of a manufacturing process of a semiconductor power device according to some embodiments of the present disclosure. For ease of understanding, the manufacturing method 4 will be described with reference to FIGS. 5-34. The manufacturing method 4 may illustrate operations used to manufacture the semiconductor power device 1 as described with respect to FIG. 1, and FIGS. 5-34 illustrate the semiconductor power device 1 at various stages of the manufacturing process. The manufacturing method 4 may also be applied to manufacturing other semiconductor devices having an electrostatic discharge protection structure 150, such as the semiconductor devices of FIGS. 35 and 36, without departing from the spirit and principles of the present disclosure.

[0054]

[0061] 5 , in step S41, a lightly doped layer 110 is formed on the substrate 100. Next, an oxidation hard mask 201 can be formed on the lightly doped layer 110 using, for example, a thermal oxidation process, and a patterned photoresist layer 202 can be formed on the oxidation hard mask 201. The oxidation hard mask 201 can be etched according to the patterned photoresist layer 202 to transfer the pattern on the photoresist layer 202 to the oxidation hard mask 201. In some embodiments, after the pattern on the photoresist layer 202 is transferred to the oxidation hard mask 201, the photoresist layer 202 is removed.

[0055]

[0062] 6, in step S42, a plurality of openings O1, O2, and O3 extending toward the substrate 100 are formed in the lightly doped layer 110. The positions of the plurality of openings O1, O2, and O3 correspond to the pattern of the oxidation hard mask 201.

[0056]

[0063] Referring to FIG. 7, after the plurality of openings O1, O2, and O3 are formed, the oxidation hard mask 201 is removed.

[0057]

[0064] In some embodiments, after the oxide hard mask 201 is removed, an oxidation process may be used to form a sacrificial oxide layer on the exposed surface of the lightly doped layer 110, and the sacrificial oxide layer is then removed. The oxidation process may be performed by adding oxygen and heating to form an oxide, such as silicon dioxide, on the surface of the lightly doped layer 110. In some embodiments, the formation and removal of the sacrificial oxide layer optimizes the surface of the lightly doped layer 110.

[0058]

[0065] 8-10, in step S43, diode string 151 is formed on openings O2 and O3. As shown in FIG. 8, a gate oxide layer 203 is formed on the surface of lightly doped layer 110. Gate oxide layer 203 is also formed on the surfaces of openings O1, O2, and O3. In some embodiments, the thickness of gate oxide layer 203 may be substantially uniform.

[0059]

[0066] 9, polysilicon may be formed on the gate oxide layer 203, filling the openings O1, O2, and O3. In some embodiments, after the polysilicon is formed, a planarization process may be further performed to give the polysilicon a smooth surface. Then, an ion implantation process may be performed on the polysilicon to form polysilicon 204 of a second conductivity type (P type). In some embodiments, a thermal annealing process may be performed on the polysilicon 204 to eliminate damage to the polysilicon 204 caused by the ion implantation process.

[0060]

[0067] 10 , a photoresist layer 205 may be formed on the polysilicon 204, where the photoresist layer 205 defines the positions of the doped regions 151a1, 151a2, and 151a3 in the diode string 151. Openings in the photoresist layer 205 expose portions of the surface of the polysilicon 204. Then, using the photoresist layer 205 as a shield, an ion implantation process may be performed on the exposed portions of the polysilicon 204, such that the exposed portions of the polysilicon 204 form the doped regions 151a1, 151a2, and 151a3. In addition, the doping concentration of the polysilicon 204 in the openings O2 and O3 changes due to the performed ion implantation process, thereby causing the polysilicon 204 in the openings O2 to become the polysilicon structure 144 and the polysilicon 204 in the openings O3 to become the polysilicon structure 146. After the ion implantation process is performed, the photoresist layer 205 is removed. 10. The conductivity types of doped regions 151a1, 151a2, 151a3, polysilicon structure 144, and polysilicon structure 146 formed after the ion implantation process are different from the conductivity type of polysilicon 204. In other words, the conductivity types of doped region 151a1, doped region 151a2, doped region 151a3, polysilicon structure 144, and polysilicon structure 146 are different from the conductivity type of doped region 151b1 and doped region 151b2.

[0061]

[0068] 11 , a hard mask layer 206 may be formed on the polysilicon 204, the doped region 151 a, and the doped region 151 b, and a photoresist layer 207 may be formed on the hard mask layer 206. The photoresist layer 207 may be used to define the location of the electrostatic discharge protection structure 150. More specifically, the photoresist layer 207 covers the location of the electrostatic discharge protection structure 150.

[0062]

[0069] 12, an etching process can be performed on the hard mask layer 206 based on the photoresist layer 207 to remove portions of the hard mask layer 206 that are not covered by the photoresist layer 207. The photoresist layer 207 is then removed.

[0063]

[0070] 13 , based on the hard mask layer 206, an etching process can be performed on the polysilicon 204 to remove the polysilicon 204 that is not covered by the hard mask layer 206. In some embodiments, the polysilicon 204 that fills the opening O1 may not be removed. After the etching process is completed, the top surface of the remaining polysilicon 204 may be substantially flush with the top surface of the lightly doped layer 110.

[0064]

[0071] 14, hard mask layer 206 covering diode string 151 and gate oxide layer 203 covering lightly doped layer 110 are removed. The original gate oxide layer 203 is now in multiple discontinuous portions. The gate oxide layer 203 in opening O1 becomes oxide layer 141, and the gate oxide layer 203 in openings O2 and O3 become oxide layer 143 and oxide layer 145, respectively.

[0065]

[0072] 15 , an oxide layer 207 may be formed on the lightly doped layer 110. The oxide layer 207 may further cover the diode string 151, the oxide layer 141, the polysilicon 204, a portion of the oxide layer 143, and a portion of the oxide layer 145. In some embodiments, the oxide layer 207 may be formed by a thermal oxidation process.

[0066]

[0073] 16 , a photoresist layer 208 can be formed on the oxide layer 207. The photoresist layer 208 can be used to define the position of the body doped region 121. Next, an ion implantation process can be performed on the lightly doped layer 110 based on the photoresist layer 208, such that a portion of the lightly doped layer 110 becomes the body doped region 121.

[0067]

[0074] Referring to FIG. 17, after the body doped region 121 is formed, the photoresist layer 208 and the oxide layer 207 are removed.

[0068]

[0075] 18 , in step S44, a spacer oxide layer SX1 is formed on and surrounds the diode string 151. The spacer oxide layer SX1 is also formed on the lightly doped layer 110, the polysilicon 204, the oxide layer 141, the oxide layer 143, and the oxide layer 145. After the spacer oxide layer SX1 is formed, the diode string 151 is surrounded by the spacer oxide layer SX1, the oxide layer 143, and the oxide layer 145. In some embodiments, the thickness of the spacer oxide layer SX1 may be greater than the thickness of the oxide layer 207. In some embodiments, the spacer oxide layer SX1 may be formed by a thin film process such as a chemical vapor deposition (CVD) process. In some embodiments, the insulation between the diode string 151 and adjacent components can be determined by the thickness of the spacer oxide layer SX1, and the spacer oxide layer SX1 formed by CVD can have a precisely controlled deposition thickness.

[0069]

[0076] 19 to 24, in step S45, diode string 156 is formed on spacer oxide layer SX1. As shown in FIG. 19, polysilicon 209 of a second conductivity type (P type) is formed on spacer oxide layer SX1. In some embodiments, polysilicon 209 may be conformally formed on spacer oxide layer SX1. As shown in FIG. 20, a hard mask layer 210 may be formed on polysilicon 209, and a photoresist layer 211 may be formed on hard mask layer 210. Photoresist layer 211 is used to define the position of diode string 156. As shown in FIG. 21, an etching process is performed on hard mask layer 210 based on photoresist layer 211, such that the hard mask layer 210 located below photoresist layer 211 is maintained and other portions of hard mask layer 210 are removed. After the etching process is completed, photoresist layer 211 is removed. 22, another etching process can be performed on the polysilicon 209 along with the remaining hard mask layer 210, such that the polysilicon 209 not covered by the hard mask layer 210 is removed and the polysilicon 209 below the hard mask layer 210 is retained. After the etching process on the polysilicon 209 is completed, the hard mask layer 210 is removed.

[0070]

[0077] 23, a spacer oxide layer SX2 is formed on and surrounds the polysilicon 209. The spacer oxide layer SX2 extends along the sidewalls of the polysilicon 209 and is adjacent to the spacer oxide layer SX1.

[0071]

[0078] As shown in FIG. 24, a photoresist layer 211 can be formed on the spacer oxide layer SX2. The photoresist layer 211 is used to define the positions of the doped region 156a, the source doped region 122, and the drain doped region 124. Next, in step S46, an ion implantation process is performed on the polysilicon 209, the lightly doped region 110, and the body doped region 121 based on the photoresist layer 211 to form the trench structure TR1 and the source doped region 122. The region on the polysilicon 209 where the photoresist layer 211 does not exist forms N-type (first conductivity type) doped regions 156a1, 156a2, and 156a3. The upper part of the body doped region 121 forms the source doped region 122. The polysilicon 204 becomes the polysilicon structure 142. A portion of the lightly doped region 110 forms the drain doped region 124. Because portions of polysilicon 209 are formed into doped regions 156a1, 156a2, and 156a3, the portions of polysilicon 209 between doped regions 156a1 and 156a3 are doped regions 156b1 and 156b2. Thus, doped regions 156a and 156b of diode string 156 are formed in the step of FIG. 24, and doped regions 156a and 156b have different conductivity types.

[0072]

[0079] 25, after the ion implantation process is completed, the photoresist layer 211 is removed. In some embodiments, after the photoresist layer 211 is removed, a thermal annealing process may be performed on the polysilicon structure 142, the source doped region 122, the doped region 156a, and the drain doped region 124.

[0073]

[0080] Referring to FIG. 26, an interlevel dielectric layer 130 is formed over the spacer oxide layers SX1 and SX2.

[0074]

[0081] 27, a photoresist layer 212 may be formed on the interlayer dielectric layer 130. The photoresist layer 212 is used to define the positions of conductive plugs CP1, CP2, CP3, and CP4.

[0075]

[0082] 28 , an etching process can be performed on the interlayer dielectric layer 130, the spacer oxide layer SX1, and the spacer oxide layer SX2 based on the photoresist layer 212 to form openings OC1, OC2, OC3, and OC4. Specifically, openings OC1, OC2, OC3, and OC4 correspond to the conductive plugs CP1, CP2, CP3, and CP4, respectively. A portion of the source doped region 122 is exposed by opening OC1, a portion of the drain doped region 124 is exposed by opening OC2, a portion of the doped region 156a1 is exposed by opening OC3, and a portion of the doped region 156a3 is exposed by opening OC4.

[0076]

[0083] Referring to FIG. 29, after the etching process is completed, the photoresist layer 212 is removed.

[0077]

[0084] 30 , an etching process can be performed on source-doped region 122, drain-doped region 124, doped region 156a1, and doped region 156a3 through openings OC1, OC2, OC3, and OC4. After the etching process, opening OC1 extends toward substrate 100 to the top surface of body-doped region 121, opening OC2 extends toward substrate 100 to the bottom surface of drain-doped region 124, and openings OC3 and OC4 extend toward substrate 100 to the top surface of spacer oxide layer SX1. In some embodiments, interlayer dielectric layer 130 can be partially etched at the same time to reduce the thickness of interlayer dielectric layer 130.

[0078]

[0085] Referring to FIG. 31, an etching process can be performed on the spacer oxide layer SX1 through openings OC3 and OC4 such that openings OC3 and OC4 extend toward the substrate 100 and penetrate through the spacer oxide layer SX1 to the top surfaces of the doped regions 151a1 and 151a3.

[0079]

[0086] 32 , an etching process can be performed on body doped region 121, lightly doped layer 110, doped region 151a1, and doped region 151a3 via openings OC1, OC2, OC3, and OC4, respectively. After the etching process, opening OC1 extends into body doped region 121 toward substrate 100, opening OC2 extends into lightly doped layer 110 toward substrate 100, opening OC3 extends into doped region 151a1 toward substrate 100, and opening OC4 extends into doped region 151a3 toward substrate 100.

[0080]

[0087] 33, an ion implantation process can be performed on body doped region 121, lightly doped layer 110, doped region 151a1, and doped region 151a3 through openings OC1, OC2, OC3, and OC4, respectively, to form heavily doped region 123, heavily doped region 125, heavily doped region 147, and heavily doped region 148. Heavily doped region 123, heavily doped region 125, heavily doped region 147, and heavily doped region 148 are doped regions of P-type (second conductivity type) and are used as ohmic contacts between conductive plugs and the doped regions.

[0081]

[0088] 34 and 2, in step S47, a source electrode S can be formed to couple to the source-doped region 122, and a gate electrode G can be formed to couple to the polysilicon structure 142. As shown in FIG. 34, a conductive material can be formed in the openings OC1, OC2, OC3, and OC4 and on the interlayer dielectric layer 130, after which an etch-back process can be performed so that the top surface of the interlayer dielectric layer 130 is flush with the top surface of the conductive material. After the openings OC1, OC2, OC3, and OC4 are filled with the conductive material, conductive plugs CP1, CP2, CP3, and CP4 are formed. In some embodiments, the filled conductive material can be a metal. In some embodiments, the filled conductive material can be tungsten (W).

[0082]

[0089] Referring again to FIG. 2 , metal wires 161, 162, and 163 may be formed on the interlayer dielectric layer 130, with the metal wires 161, 162, and 163 spaced apart from one another. The metal wire 161 is used to connect to the source electrode S, the metal wire 162 is used to connect to the gate electrode G, and the metal wire 163 is used to connect to the drain electrode D. The metal wire 161 is adjacent to the conductive plug CP1 and the conductive plug CP3, and thus the conductive plugs CP1 and CP3 may be electrically connected to the source electrode S via the metal wire 161. The metal wire 162 is adjacent to the conductive plug CP4, and thus the conductive plug CP4 may be electrically connected to the gate electrode G via the metal wire 162. The metal wire 163 is adjacent to the conductive plug CP2, and thus the conductive plug CP2 may be electrically connected to the drain electrode D via the metal wire 163.

[0083]

[0090] It should be understood that the semiconductor power device 1 of the present disclosure is not limited to the above structure. For example, the gate of the semiconductor power device 1 may be implemented with a different structure, which is also within the scope of the present disclosure.

[0084]

[0091] 35 and 36, Fig. 35 is a schematic diagram of another exemplary semiconductor power device 2 according to an embodiment of the present disclosure, and Fig. 36 is a schematic diagram and a partially enlarged view of yet another exemplary semiconductor power device 3 according to an embodiment of the present disclosure. For ease of understanding, the symbols in Figs. 35 and 36 follow the symbols in Figs. 1, 2, 3A, and 3B, but this does not mean that components using the same symbols must be identical.

[0085]

[0092] The semiconductor power device 2 is substantially similar to the semiconductor power device 1, except for the trench structure. Specifically, the trench structure TR1 of the semiconductor power device 2 is arranged in the form of a split gate. The trench structure TR1 of the semiconductor power device 2 has two separated polysilicon structures, i.e., polysilicon structure 142a and polysilicon structure 142b, with the polysilicon structure 142a being arranged above the polysilicon structure 142b. In addition, the oxide layer 141 of the trench structure TR1 may extend further between the polysilicon structure 142a and the polysilicon structure 142b. In some embodiments, the polysilicon structure 142a may be part of a gate structure, and the polysilicon structure 142b may be part of a source structure.

[0086]

[0093] The semiconductor power device 3 is substantially similar to the semiconductor power device 1, except that the power transistor of the semiconductor power device 3 includes a dual trench structure. The semiconductor power device 3 further includes a trench structure TR5, a conductive plug CP5, a heavily doped region 126, and a heavily doped region 127. The trench structure TR5 is disposed between the two trench structures TR1 and between the trench structure TR2 and the trench structure TR1 adjacent to the trench structure TR2. As an example, FIG. 36 shows two trench structures TR5. One trench structure TR5 is disposed between the two trench structures TR1, and the other is disposed between the trench structure TR2 and the trench structure TR1 adjacent to the trench structure TR2. The trench structure TR5 is disposed in the lightly doped layer 110, extends through the source-doped region 122 toward the substrate 100, and protrudes from the body-doped region 121. The depth of the trench structure TR5 may be smaller than the depth of the trench structure TR1.

[0087]

[0094] Taking trench structure TR5 as an illustrative example, trench structure TR5 may include a polysilicon structure 172 and an oxide layer 171 surrounding the polysilicon structure 172. Two conductive plugs CP5 are disposed on both sides of trench structure TR5. The conductive plugs CP5 are connected to metal wires 161 and extend through the interlayer dielectric layer 130, the spacer oxide layer SX1, and the source-doped region 122 to reach the heavily doped region 126 in the body-doped region 121.

[0088]

[0095] Heavily doped region 127 is disposed within polysilicon structure 142 and adjacent to spacer oxide layer SX1. Conductive plug CP1 is disposed on trench structure TR1 and extends into heavily doped region 127. In some embodiments, oxide layer 171 and polysilicon structure 172 may be part of a gate structure, and oxide layer 141 and polysilicon structure 142 may be part of a source structure.

[0089]

[0096] According to one aspect of the present disclosure, there is provided an electrostatic discharge protection structure including: a first trench structure comprising a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure; a second trench structure comprising a second polysilicon structure and a second oxide layer surrounding the second polysilicon structure; a first diode string adjacent to the first polysilicon structure and the second polysilicon structure and disposed between the first trench structure and the second trench structure; a first spacer oxide layer disposed on the first diode string; and a second diode string disposed on the first spacer oxide layer and connected in parallel to the first diode string.

[0090]

[0097] Optionally, in any of the aforementioned aspects, the first diode string comprises a plurality of first doped regions of a first conductivity type and a plurality of second doped regions of a second conductivity type, the plurality of first doped regions and the plurality of second doped regions being arranged in an alternating manner, and a PN junction being formed at an interface between each first doped region and an adjacent second doped region.

[0091]

[0098] Optionally, in any of the aforementioned aspects, first ends of the plurality of first doped regions are adjacent to the first polysilicon structure and second ends of the plurality of first doped regions are adjacent to the second polysilicon structure.

[0092]

[0099] Optionally, in any of the preceding aspects, the first polysilicon structure and the second polysilicon structure have a first conductivity type.

[0093]

[0100] Optionally, in any of the preceding embodiments, the first conductivity type is N-type and the second conductivity type is P-type.

[0094]

[0101] Optionally, in any of the aforementioned aspects, the second diode string comprises a plurality of third doped regions of the first conductivity type and a plurality of fourth doped regions of the second conductivity type, the plurality of third doped regions and the plurality of fourth doped regions being alternately arranged, and a PN junction being formed at an interface between each third doped region and an adjacent fourth doped region.

[0095]

[0102] Optionally, in any of the aforementioned aspects, the electrostatic discharge protection structure may further include: a first conductive plug extending through first ends of the plurality of third doped regions and the first spacer oxide layer to the first ends of the plurality of first doped regions, connecting the first electrode to the first ends of the plurality of third doped regions and the first ends of the plurality of first doped regions; a second conductive plug extending through second ends of the plurality of third doped regions and the first spacer oxide layer to the second ends of the plurality of first doped regions, connecting the second electrode to the second ends of the plurality of third doped regions and the second ends of the plurality of first doped regions; a first heavily doped region disposed within the first ends of the plurality of first doped regions and surrounding an end of the first conductive plug; and a second heavily doped region disposed within the second ends of the plurality of first doped regions and surrounding an end of the second conductive plug.

[0096]

[0103] Optionally, in any of the aforementioned aspects, the electrostatic discharge protection structure may further include a second spacer oxide layer disposed on and surrounding the second diode string.

[0097]

[0104] Optionally, in any of the preceding embodiments, the first oxide layer and the second oxide layer are adjacent to one another, and the first diode string is disposed between the first spacer oxide layer and the adjacent first and second oxide layers.

[0098]

[0105] Optionally, in any of the preceding aspects, the first diode string and the second diode string each comprise a plurality of back-to-back diodes connected in series.

[0099]

[0106] According to another aspect of the present disclosure, there is provided a semiconductor power device including: a substrate; a lightly doped layer disposed on the substrate; a first trench structure disposed in the lightly doped layer and extending toward the substrate, the first trench structure including a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure; a source doped region disposed in the lightly doped layer away from the substrate; an interlayer dielectric layer disposed on the lightly doped layer; a source electrode connected to the source doped region; a gate electrode connected to the first polysilicon structure; and an electrostatic discharge protection structure disposed in the interlayer dielectric layer, the electrostatic discharge protection structure including: a first diode string; a second diode string disposed on the first diode string; and a first spacer oxide layer disposed between the first diode string and the second diode string, the first diode string and the second diode string being connected in parallel between the source electrode and the gate electrode.

[0100]

[0107] Optionally, in any of the aforementioned aspects, the electrostatic discharge protection structure further comprises a second spacer oxide layer disposed on the second diode string and on a side of the second diode string and adjacent to the first spacer oxide layer.

[0101]

[0108] Optionally, in any of the aforementioned aspects, each of the first and second diode strings comprises a plurality of first doped regions of a first conductivity type and a plurality of second doped regions of a second conductivity type, the plurality of second doped regions and the plurality of first doped regions being alternately arranged, and a PN junction being formed at an interface between each first doped region and an adjacent second doped region.

[0102]

[0109] Optionally, in any of the aforementioned aspects, the semiconductor power device may further include: a first conductive plug extending through the second diode string and the first spacer oxide layer to the first diode string, the first conductive plug connecting a source electrode to a first end of the plurality of first doped regions of the first diode string and a first end of the plurality of first doped regions of the second diode string; a second conductive plug extending through the second diode string and the first spacer oxide layer to the first diode string, the second conductive plug connecting a gate electrode to a second end of the plurality of first doped regions of the first diode string and a second end of the plurality of first doped regions of the second diode string; a first heavily doped region disposed within the first end of the plurality of first doped regions of the first diode string and surrounding an end of the first conductive plug; and a second heavily doped region disposed within the second end of the plurality of first doped regions of the first diode string and surrounding an end of the second conductive plug.

[0103]

[0110] Optionally, in any of the preceding embodiments, the first conductivity type is N-type and the second conductivity type is P-type.

[0104]

[0111] Optionally, in any of the aforementioned aspects, the semiconductor power device may further include a body doped region disposed in the lightly doped layer and adjacent to the first oxide layer, and a drain doped region disposed in the lightly doped layer, and the source doped region disposed in the body doped region.

[0105]

[0112] Optionally, in any of the preceding embodiments, the first spacer oxide layer extends to the sidewalls and lightly doped layer of the first diode string, covering the source doped region, the drain doped region, and the first trench structure.

[0106]

[0113] Optionally, in any of the aforementioned aspects, the semiconductor power device may further include a third heavily doped region disposed in the body doped region, and a third conductive plug connected to the source electrode and extending through the interlayer dielectric layer and the source doped region to the body doped region, wherein the third heavily doped region surrounds one end of the third conductive plug.

[0107]

[0114] Optionally, in any of the aforementioned aspects, the semiconductor power device may further include a drain electrode disposed on the interlayer dielectric layer; a fourth heavily doped region disposed in the body doped region; and a fourth conductive plug connected to the drain electrode and extending through the interlayer dielectric layer and the drain doped region to the lightly doped layer, wherein the fourth heavily doped region surrounds one end of the fourth conductive plug.

[0108]

[0115] Optionally, in any of the aforementioned aspects, the breakdown voltage of the first diode string is substantially equal to the breakdown voltage of the second diode string.

[0109]

[0116] Optionally, in any of the preceding embodiments, the breakdown voltage of the first diode string is lower than the breakdown voltage of the first oxide layer.

[0110]

[0117] According to another aspect of the present disclosure, there is provided a method for manufacturing a semiconductor power device, the method including: forming a lightly doped layer on a substrate; forming a first opening, a second opening, and a third opening in the lightly doped layer extending toward the substrate; forming a first diode string on the second opening and the third opening; forming a first spacer oxide layer on the first diode string surrounding the first diode string; forming a second diode string on the first spacer oxide layer; forming a first trench structure in the first opening, the first trench structure including a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure; forming a source-doped region in the lightly doped layer, the source-doped region being disposed between the first trench structure and the second opening; and forming a source electrode connected to the source-doped region and a gate electrode connected to the first polysilicon structure, wherein the first diode string and the second diode string are connected in parallel and disposed between the source electrode and the gate electrode.

[0111]

[0118] Optionally, in any of the aforementioned aspects, the manufacturing method may further include forming a second spacer oxide layer disposed on the second diode string, surrounding the second diode string, and adjacent to the first spacer oxide layer; and forming an interlayer dielectric layer on the lightly doped layer, wherein the source electrode and the gate electrode are formed on the interlayer dielectric layer.

[0112]

[0119] Optionally, in any of the aforementioned aspects, the manufacturing method may further include forming a first conductive plug, a second conductive plug, and a third conductive plug, wherein the first conductive plug reaches the source-doped region through the interlayer dielectric layer and the first spacer oxide layer, and the second conductive plug and the third conductive plug reach the first diode string through the second spacer oxide layer, the second diode string, and the first spacer oxide layer.

[0113]

[0120] Optionally, in any of the aforementioned embodiments, a first conductive plug connects the source electrode to the source-doped region, a second conductive plug connects the source electrode to the first and second diode strings, and a third conductive plug connects the gate electrode to the first and second diode strings.

[0114]

[0121] Optionally, in any of the aforementioned aspects, the manufacturing method may further include forming a drain-doped region in the lightly doped layer; forming a fourth conductive plug through the interlayer dielectric layer and the first spacer oxide layer to the drain-doped region; and forming a drain electrode, the fourth conductive plug connecting the drain electrode to the drain-doped region.

[0115]

[0122] Optionally, in any of the aforementioned aspects, the step of forming the first diode string over the second opening and the third opening includes forming a first semiconductor material in the second opening and the third opening; patterning the first semiconductor material; and performing ion implantation into the patterned first semiconductor material to form a plurality of first doped regions having a first conductivity type and a plurality of second doped regions having a second conductivity type, the plurality of first doped regions and the plurality of second doped regions being alternately arranged, and forming a PN junction at an interface between each first doped region and an adjacent second doped region.

[0116]

[0123] Optionally, in any of the aforementioned aspects, the step of forming the second diode string on the first spacer oxide layer includes forming a second semiconductor material on the first spacer oxide layer, patterning the second semiconductor material, and performing ion implantation into the patterned second semiconductor material to form a plurality of third doped regions having the first conductivity type and a plurality of fourth doped regions having the second conductivity type, the plurality of third doped regions and the plurality of fourth doped regions being alternately arranged, and a PN junction being formed at an interface between each third doped region and an adjacent fourth doped region.

[0117]

[0124] In this disclosure, for convenience of explanation, spatially relative terms such as "lower," "below," "lower side," "upper," "upper side," "left side," "right side," etc. may be used to describe the relationship of a component or feature to one or more other components or features as shown in the accompanying drawings. In addition to the orientation shown in the accompanying drawings, spatially relative terms are intended to encompass various orientations of the device in use or operation. The device may be oriented in other manners (rotated 90 degrees or at other orientations), and the spatially relative terms used herein may be similarly interpreted in a corresponding manner. When a component is referred to as "connected" or "coupled" to another component, it should be understood that it may be directly connected or coupled to the other component, or there may be intervening components.

[0118]

[0125] As used herein, the terms "approximately," "essentially," "substantially," and "about" are used to describe and account for small variations. When used in connection with an event or instance, these terms can refer to embodiments in which the event or instance exists exactly as well as embodiments in which the event or instance approximately exists. When used herein with respect to a given value or range, the term "about" generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges herein may be referred to as being from one endpoint to the other endpoint or as being between two endpoints. All ranges disclosed herein include endpoints unless otherwise indicated. The term "substantially coplanar" may mean that the difference in position of two surfaces relative to the same plane is within a few micrometers (μm), for example, within 10 μm, within 5 μm, within 1 μm, or within 0.5 μm. When values or properties are referred to as being "substantially" the same, the term may refer to values within ±10%, ±5%, ±1%, or ±0.5% of the mean of the value.

[0119]

[0126] The foregoing has outlined features and detailed aspects of several embodiments of the present disclosure. The embodiments described in this disclosure may readily be used as a basis for designing or modifying other processes and structures to carry out the same or similar purposes and / or achieve the same or similar advantages as the embodiments presented herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations may be made thereto without departing from the spirit and scope of the present disclosure.

[0120]

[0127] Although the description has been set forth in detail, it should be understood that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the present disclosure, as defined by the appended claims. Moreover, the scope of the present disclosure is not intended to be limited to the particular embodiments described herein, since those skilled in the art will readily appreciate from this disclosure that they can utilize, in accordance with the present disclosure, any now-existing or later-developed process, machine, manufacture, composition of matter, means, method, or step that performs substantially the same function or can achieve substantially the same result as the corresponding embodiment described herein. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. [Explanation of symbols]

[0121] 1. Semiconductor power devices 2. Semiconductor power devices 3. Semiconductor power devices 4 Manufacturing method 10 Vertical power transistor 100 boards 110 Lightly doped layer, lightly doped region 121 Body Dope Region 122 Source doped region 123 Highly doped region 124 drain doped region 125 Highly doped region 126 Highly doped region 127 Highly doped region 130 Interlayer dielectric layer 141 Oxide layer 142 Polysilicon Structure 142a Polysilicon structure 142b Polysilicon structure 143 Oxide layer 144 Polysilicon Structure 145 oxide layer 146 Polysilicon Structure 147 Highly doped region 148 Highly doped region 150 Electrostatic discharge protection structure 151 First diode string 151a N-type doped region 151a1 doped region 151a2 doped region 151a3 doped region 151b P-type doped region 151b1 doped region 151b2 doped region 156 Second diode string 156a doped region 156a1 doped region 156a2 doped region 156a3 doped region 156b P-type doped region 156b1 doped region 156b2 doped region 161 Metal Wire 162 Metal Wire 163 Metal Wire 171 Oxide layer 172 Polysilicon Structure 201 Oxide hard mask, oxide hard mask 202 Patterned photoresist layer 203 Gate oxide layer 204 Polysilicon 205 Photoresist layer 206 Hard mask layer 207 Photoresist layer, oxide layer 208 Photoresist layer 209 Polysilicon 210 Hard mask layer 211 Photoresist layer 212 Photoresist layer CP1 Conductive Plug CP2 Conductive Plug CP3 Conductive Plug CP4 Conductive Plug CP5 Conductive Plug D drain electrode G gate electrode O1 opening O2 opening O3 opening OC1 opening OC2 opening OC3 opening OC4 opening RG Gate resistor S Source electrode, source terminal SX1 spacer oxide layer SX2 spacer oxide layer TR1 Trench Structure TR2 trench structure TR3 trench structure TR5 trench construction

Claims

1. a first trench structure comprising a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure; a second trench structure comprising a second polysilicon structure and a second oxide layer surrounding the second polysilicon structure; a first diode string disposed between the first trench structure and the second trench structure and adjacent to the first polysilicon structure and the second polysilicon structure; a first spacer oxide layer disposed on the first diode string; a second diode string disposed on the first spacer oxide layer; and Equipped with The electrostatic discharge protection structure, wherein the second diode string and the first diode string are connected in parallel.

2. The first diode string comprises: a plurality of first doped regions of a first conductivity type; a plurality of second doped regions of a second conductivity type; Equipped with 2. The electrostatic discharge protection structure of claim 1, wherein the plurality of first doped regions and the plurality of second doped regions are alternately arranged, and a PN junction is formed at an interface between each first doped region and a second doped region adjacent to each first doped region.

3. The second diode string comprises: a plurality of third doped regions of the first conductivity type; a plurality of fourth doped regions of the second conductivity type; Equipped with 3. The electrostatic discharge protection structure of claim 2, wherein the plurality of third doped regions and the plurality of fourth doped regions are arranged in an alternating manner, and a PN junction is formed at an interface between each third doped region and a fourth doped region adjacent to each third doped region.

4. a first conductive plug extending through a first end of the second diode string and the first spacer oxide layer to a first end of the first diode string, connecting a first electrode to the first end of the second diode string and the first end of the first diode string; a second conductive plug extending through the second end of the second diode string and the first spacer oxide layer to the second end of the first diode string, connecting a second electrode to the second end of the second diode string and the second end of the first diode string; a first heavily doped region disposed within the first end of the first diode string and surrounding an end of the first conductive plug; a second heavily doped region disposed within the second end of the first diode string and surrounding an end of the second conductive plug; 10. The electrostatic discharge protection structure of claim 1, further comprising:

5. 2. The electrostatic discharge protection structure of claim 1, wherein a first end of said first diode string is adjacent to said first polysilicon structure and a second end of said first diode string is adjacent to said second polysilicon structure.

6. a second spacer oxide layer disposed on the second diode row and surrounding the second diode row; 10. The electrostatic discharge protection structure of claim 1, further comprising:

7. 2. The electrostatic discharge protection structure of claim 1, wherein the first oxide layer is adjacent to the second oxide layer, and the first diode string is disposed between the first spacer oxide layer and the first and second oxide layers.

8. 2. The electrostatic discharge protection structure of claim 1, wherein the first and second diode strings each comprise a plurality of back-to-back diodes connected in series.

9. a lightly doped layer disposed on a substrate; a first trench structure disposed within the lightly doped layer and extending toward the substrate, the first trench structure comprising a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure; an interlevel dielectric layer disposed on the lightly doped layer; a source electrode connected to a source doped region disposed within the lightly doped layer; a gate electrode connected to the first polysilicon structure; an electrostatic discharge protection structure disposed within the interlevel dielectric layer; It is equipped with The electrostatic discharge protection structure comprises: a first diode string; a second diode row disposed above the first diode row and connected in parallel with the first diode row between the source electrode and the gate electrode; a first spacer oxide layer disposed between the first and second diode rows; A semiconductor power device comprising:

10. The electrostatic discharge protection structure comprises: a second spacer oxide layer disposed on the second diode row and on a sidewall of the second diode row and adjacent to the first spacer oxide layer; 10. The semiconductor power device of claim 9, further comprising:

11. Each of the first diode string and the second diode string comprises: a plurality of first doped regions of a first conductivity type; a plurality of second doped regions of a second conductivity type; Equipped with 10. The semiconductor power device of claim 9, wherein the plurality of second doped regions and the plurality of first doped regions are arranged in an alternating manner, and a PN junction is formed at an interface between each first doped region and a second doped region adjacent to each first doped region.

12. a first conductive plug extending through the second diode string and the first spacer oxide layer to the first diode string, connecting the source electrode to a first end of the first diode string and a first end of the second diode string; a second conductive plug extending through the second diode string and the first spacer oxide layer to the first diode string, connecting the gate electrode to a second end of the first diode string and a second end of the second diode string; a first heavily doped region disposed within the first end of the first diode string and surrounding an end of the first conductive plug; a second heavily doped region disposed within the second end of the first diode string and surrounding an end of the second conductive plug; 10. The semiconductor power device of claim 9, further comprising:

13. a body doped region disposed within the lightly doped layer and adjacent to the first oxide layer, the body doped region being disposed within the source doped region; a third heavily doped region disposed within the body doped region; a third conductive plug connected to the source electrode and extending through the interlayer dielectric layer and the source doped region to the body doped region; Furthermore, The semiconductor power device of claim 9 , wherein the third heavily doped region surrounds one end of the third conductive plug.

14. a drain doped region disposed within the lightly doped layer; a fourth heavily doped region disposed within the lightly doped region below the drain doped region; a fourth conductive plug connected to a drain electrode of the semiconductor power device and extending through the interlayer dielectric layer and the drain doped region into the lightly doped layer; Furthermore, The semiconductor power device of claim 9 , wherein the fourth heavily doped region surrounds one end of the fourth conductive plug.

15. 10. The semiconductor power device of claim 9, wherein a breakdown voltage of the first diode string is substantially equal to a breakdown voltage of the second diode string, or the breakdown voltage of the first diode string is lower than a breakdown voltage of the first oxide layer.

16. 1. A method of manufacturing a semiconductor power device, comprising: forming a lightly doped layer on a substrate; forming a first opening, a second opening, and a third opening in the lightly doped layer extending toward the substrate; forming a first diode string above the second opening and the third opening; forming a first spacer oxide layer on the first diode string surrounding the first diode string; forming a second diode string on the first spacer oxide layer; forming a first trench structure in the first opening, the first trench structure comprising a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure; forming a source doped region in the lightly doped layer disposed between the first trench structure and the second opening; forming a source electrode connected to the source doped region; forming a gate electrode connected to the first polysilicon structure; It contains The first and second diode strings are connected in parallel between the source electrode and the gate electrode.

17. forming a second spacer oxide layer on the second diode string surrounding the second diode string and adjacent to the first spacer oxide layer; forming an interlevel dielectric layer over the lightly doped layer; further comprising 17. The method of claim 16, wherein the source electrode and the gate electrode are formed on the interlevel dielectric layer.

18. forming a first conductive plug, a second conductive plug, and a third conductive plug; further comprising 18. The method of claim 17, wherein the first conductive plug extends through the interlevel dielectric layer and the first spacer oxide layer to the source doped region, and the second conductive plug and the third conductive plug extend through the second spacer oxide layer, the second diode string, and the first spacer oxide layer to the first diode string.

19. 20. The method of claim 18, wherein the first conductive plug connects the source electrode to the source-doped region, the second conductive plug connects the source electrode to the first and second diode strings, and the third conductive plug connects the gate electrode to the first and second diode strings.

20. forming a drain doped region in the lightly doped layer; forming a fourth conductive plug extending through the interlevel dielectric layer and the first spacer oxide layer to the drain doped region; forming a drain electrode; further comprising 17. The method of claim 16, wherein the fourth conductive plug connects the drain electrode to the drain doped region.

Images