Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device capable of suppressing warpage and cracks even without an Si through electrode substrate.SOLUTION: A semiconductor device includes: a sealing material layer; a plurality of semiconductor chips two-dimensionally arranged in the sealing material layer; a rewiring layer electrically connected to the plurality of semiconductor chips; a support substrate arranged on one side or the other side in a thickness direction of the sealing material layer; and an adhesive layer arranged between the sealing material layer and the support substrate.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] As electronic devices become smaller, lighter, and more powerful, there is a demand for higher integration of semiconductor chips. To achieve this, methods are being considered that involve integrating semiconductor chips in two dimensions at high density to improve the degree of integration within a surface.

[0003] In package design for integrated circuits (ICs), a Si interposer is often placed between a semiconductor chip and a package substrate (see, for example, Patent Document 1). The Si interposer includes a redistribution layer and a through-silicon via (TSV) substrate. The Si interposer connects semiconductor chips to each other or connects a semiconductor chip to a package substrate.

[0004] FIG. 1 is a schematic diagram showing a conventional semiconductor device equipped with a Si interposer. As shown in FIG. 1, the semiconductor device 1 includes a Si through-hole electrode substrate 2, a rewiring layer 3 (collectively referred to as a Si interposer), multiple semiconductor chips 4, and an encapsulant layer 5 that encapsulates the multiple semiconductor chips 4.

[0005] However, to manufacture a Si interposer, it is necessary to form a Si through-hole electrode, which tends to complicate the manufacturing process and increase costs. For these reasons, it is desirable to eliminate the need for a Si through-hole electrode substrate. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-069480 Summary of the Invention [Problem to be solved by the invention]

[0007] However, semiconductor devices that do not have a Si through electrode substrate have a problem in that they have low mechanical strength and are prone to warping and cracking.

[0008] For example, the semiconductor device described above is obtained through a process of encapsulating multiple semiconductor chips with an encapsulant. Therefore, the resulting semiconductor device is prone to residual stress due to factors such as curing shrinkage of the encapsulant. Semiconductor devices without a through-silicon substrate have low mechanical strength and therefore cannot withstand such residual stress, resulting in warping and cracking.

[0009] The present invention has been made in view of the above-mentioned problems, and aims to provide a semiconductor device and a manufacturing method thereof that can suppress warping and cracking even without a Si through electrode substrate. [Means for solving the problem]

[0010] The above problem can be solved by the following configuration.

[0011] [1] A semiconductor device having an encapsulant layer, a plurality of semiconductor chips arranged two-dimensionally within the encapsulant layer, a redistribution layer electrically connected to the plurality of semiconductor chips, a support substrate arranged on one or the other side of the thickness direction of the encapsulant layer, and an adhesive layer arranged between the encapsulant layer and the support substrate.

[0012] [2] A method for manufacturing a semiconductor device, comprising the steps of: arranging a plurality of semiconductor chips on a support substrate via an adhesive layer; encapsulating the plurality of semiconductor chips arranged on the support substrate with an encapsulant to form an encapsulant layer; and forming a redistribution layer electrically connected to the plurality of semiconductor chips on the opposite side of the encapsulant layer from the support substrate. [3] A method for manufacturing a semiconductor device, comprising: a step of forming a redistribution layer on a support substrate via an adhesive layer; a step of arranging a plurality of semiconductor chips on the redistribution layer; a step of encapsulating the plurality of semiconductor chips arranged on the support substrate with an encapsulant to form an encapsulant layer; and a step of forming a through electrode that penetrates the encapsulant layer in a thickness direction and is electrically connected to the redistribution layer. [4] A method for manufacturing a semiconductor device, comprising: a step of forming a rewiring layer on a temporary fixing substrate via a temporary fixing material; a step of arranging a plurality of semiconductor chips on the rewiring layer; a step of encapsulating the plurality of semiconductor chips arranged on the support substrate with an encapsulant to form an encapsulant layer; a step of stacking a support substrate on the opposite side of the encapsulant layer from the temporary fixing substrate via an adhesive layer; and a step of removing the temporary fixing material and the temporary fixing substrate from the laminate obtained by stacking the support substrates. [Effects of the Invention]

[0013] According to the present invention, it is possible to provide a semiconductor device and a manufacturing method thereof that can suppress warping and cracking even without a Si through electrode substrate. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a schematic diagram showing a conventional semiconductor device having a Si interposer. [Figure 2] FIG. 2 is a schematic partial cross-sectional view showing the configuration of the semiconductor device according to the first embodiment. [Figure 3] 3A to 3D are schematic partial cross-sectional views showing a method for manufacturing the semiconductor device of FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view showing a semiconductor device according to the first modification. [Figure 5] 5A to 5D are schematic partial cross-sectional views showing a method for manufacturing the semiconductor device of FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view showing a semiconductor device according to the second modification. [Figure 7]7A to 7E are schematic partial cross-sectional views showing a method for manufacturing the semiconductor device of FIG. [Figure 8] FIG. 8 is a schematic partial cross-sectional view showing the configuration of a semiconductor device according to the second embodiment. [Figure 9] 9A to 9D are schematic partial cross-sectional views showing a method for manufacturing the semiconductor device of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0015] A semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described below.

[0016] [First embodiment] FIG. 2 is a schematic partial cross-sectional view showing the configuration of the semiconductor device 10 according to the first embodiment. As shown in FIG. 2, the semiconductor device 10 according to this embodiment includes a sealing material layer 11, a plurality of semiconductor chips 12, a rewiring layer 13, a support substrate 14, and an adhesive layer 15.

[0017] (Encapsulant layer 11) The encapsulant layer 11 encapsulates the plurality of semiconductor chips 12. The encapsulant layer 11 includes a cured product of an encapsulant.

[0018] The sealing material is not particularly limited, and any known sealing material used for sealing semiconductor chips can be used. The sealing material may be, for example, a curable resin composition containing an epoxy resin and a curing agent.

[0019] The epoxy resin is not particularly limited as long as it is one that is commonly used as an encapsulant. Examples of the epoxy resin include novolac epoxy resins such as phenol novolac epoxy resins, orthocresol novolac epoxy resins, and epoxy resins having a triphenylmethane skeleton; bisphenol epoxy resins which are diglycidyl ethers of bisphenol A, bisphenol F, bisphenol S, alkyl-substituted or unsubstituted biphenols, etc.; glycidyl ester epoxy resins; and glycidylamine epoxy resins.

[0020] There are no particular restrictions on the curing agent, as long as it is one that is commonly used as a curing agent for epoxy resins. Examples of curing agents include novolac-type phenolic resins, phenol-aralkyl resins, aralkyl-type phenolic resins, dicyclopentadiene-type phenolic novolac resins, and terpene-modified phenolic resins.

[0021] The sealing material may further contain an inorganic filler, a silane coupling agent, or the like, as required. Examples of inorganic fillers include particles of silica (fused silica, crystalline silica), alumina, zircon, calcium silicate, calcium carbonate, potassium titanate, silicon carbide, silicon nitride, aluminum nitride, boron nitride, beryllia, zirconia, zircon, and titania, as well as glass fibers.

[0022] The silane coupling agent is not particularly limited, and examples thereof include various silane compounds such as silane compounds having at least one amino group selected from primary, secondary, and tertiary amino groups, epoxy silane, mercapto silane, alkyl silane, ureido silane, and vinyl silane.

[0023] The thickness of the encapsulant layer 11 is not particularly limited as long as it is thick enough to encapsulate the semiconductor chip 12. For example, the thickness of the encapsulant layer 11 is preferably thicker than the thickness of the semiconductor chip 12.

[0024] (Semiconductor chip 12) A plurality of semiconductor chips 12 are arranged two-dimensionally within the encapsulant layer 11 (see FIG. 2).

[0025] The semiconductor chip 12 is a small piece of semiconductor material such as silicon (Si), SiC, GaN, etc., on which an integrated circuit, etc. is formed. A specific example of the semiconductor chip 12 is a silicon die.

[0026] (Redistribution layer 13) The rewiring layer 13 is disposed on one side in the thickness direction of the semiconductor chips 12 (or one side in the thickness direction of the encapsulant layer 11), preferably on the surface (circuit formation surface) side of the semiconductor chips 12. In Fig. 2, the surfaces of the semiconductor chips 12 are exposed to the outside of the encapsulant layer 11, and the rewiring layer 13 is disposed on the exposed surface.

[0027] The redistribution layer 13 includes conductor portions (rewiring, vias, pads, etc.) made of Cu or the like, and an insulating portion covering the conductor portions. The conductor portions are electrically connected to the multiple semiconductor chips 12, thereby electrically connecting the redistribution layer 13 to each of the multiple semiconductor chips 12. Portions of the conductor portions exposed from the insulating portion can be used as terminals or the like. The material of the insulating portion can be, for example, a resin material such as polyimide resin, polybenzoxazole resin, epoxy resin, or polyolefin resin. For specific examples of the redistribution layer 13, see the description of element 310 chip-level BEOL in U.S. Patent Application Publication No. 2022 / 0013504.

[0028] (Support substrate 14) The support substrate 14 is disposed on one or the other side in the thickness direction of the encapsulant layer 11 (or on one or the other side in the thickness direction of the plurality of semiconductor chips 12). In FIG. 2, the support substrate 14 is disposed on the other side in the thickness direction of the encapsulant layer 11 (or on the other side in the thickness direction of the plurality of semiconductor chips 12). The support substrate 14 supports and reinforces the encapsulant layer 11.

[0029] The support substrate 14 is not particularly limited as long as it can support and reinforce the sealing material layer 11. Examples of the support substrate 14 include a Si substrate, a glass substrate such as borosilicate glass (Pyrex (registered trademark)) or quartz glass (SiO2), a metal substrate such as Al, Ti, Fe, Cu, or Ag, and a ceramic substrate.

[0030] The thickness of the support substrate 14 is not particularly limited as long as it is sufficient to support and reinforce the encapsulant layer 11, and may be thinner than the thickness of the encapsulant layer 11. The thickness of the support substrate 14 is preferably, for example, 0.1 mm or more and 2 mm or less, and more preferably 0.3 mm or more and 1 mm or less.

[0031] (adhesive layer 15) The adhesive layer 15 is disposed between the encapsulant layer 11 and the support substrate 14 to bond them together. In Fig. 2, the adhesive layer 15 is disposed on the other side (rear surface side) of the plurality of semiconductor chips 12 in the thickness direction.

[0032] It is preferable that the adhesive layer 15 is bonded to the support substrate 14 or the sealing material layer 11 via a chemical bond, specifically, that a functional group (e.g., an amino group, an epoxy group, a vinyl group, a silanol group (Si-OH group), etc.) on the surface of the adhesive layer 15 reacts with a functional group on the surface of the support substrate 14 or the sealing material layer 11 to form a chemical bond. In particular, it is preferable that the adhesive layer 15 is bonded to the support substrate 14 or the sealing material layer 11 via a Si-OM bond (M is a metal atom such as Al or a semiconductor atom such as Si).

[0033] The adhesive layer 15 preferably contains a material having the above-described functional group or a material capable of generating the above-described functional group by surface treatment. From this perspective, the adhesive layer 15 preferably contains at least one selected from the group consisting of an imide bond, an amide bond, a siloxane bond, an epoxy group, and a benzocyclobutene structure as a partial structure, and preferably contains a resin containing the above partial structure.

[0034] Examples of resins containing at least one selected from the group consisting of an imide bond, an amide bond, a siloxane bond, an epoxy group, and a benzocyclobutene structure include polyimide, polyamide, polyamideimide, maleimide resin, parylene, polyarylene ether, polybenzoxazole, a benzocyclobutene resin, an epoxy resin, a resin containing a siloxane bond, etc. Among these, a resin containing a siloxane bond is preferred from the viewpoint of easily generating a silanol group on the surface and achieving better adhesion between the support substrate 14 and the sealing material layer 11.

[0035] Examples of resins containing a siloxane bond include divinylsiloxane benzocyclobutene polymer, siloxane imide polymer, siloxane amide polymer, siloxane amide imide polymer, epoxy-modified siloxane polymer, etc. Among them, from the viewpoint of more stably bonding the support substrate 14 and the sealing material layer 11 and also having better heat resistance, a resin containing a siloxane bond and at least one of an amide bond and an imide bond is preferred, and a siloxane imide polymer is more preferred.

[0036] The resin containing a siloxane bond and at least one of an amide bond and an imide bond may contain a structure represented by any one of formulas (1) to (3).

[0037] [ka]

[0038] In a resin containing a siloxane bond and at least one of an amide bond and an imide bond, the group bonded to Si may be substituted with a divalent group such as an alkylene group or a phenylene group. For example, the structure containing a siloxane bond may have a structure having (-O-)x(R1)ySi-R2-Si(R1)y(-O-)x (R1 is a monovalent group such as a methyl group, R2 is a divalent group such as an alkylene group or a phenylene group, x and y are each an integer of 0 or more, and x + y is 3).

[0039] The adhesive layer 15 containing such a resin containing a siloxane bond and at least one of an amide bond and an imide bond can be obtained by heating and reacting (curing) an adhesive composition containing a compound containing three or more silanol groups, an amide group, and a carboxy group in one molecule. For example, a resin having a structure represented by formula (1) can be obtained by heating and reacting a compound represented by formula (4). Similarly, a resin having a structure represented by formula (2) can be obtained by heating and reacting a compound represented by formula (5). [ka]

[0040] In addition, an adhesive layer containing a resin containing a siloxane bond and at least one of an amide bond and an imide bond can also be obtained by heating and reacting (curing) an adhesive composition containing a compound (A) having an Si-O bond and an amino group and a crosslinking agent (B) having three or more -C(=O)OX groups (X is a hydrogen atom or an alkyl group having 1 to 6 carbon atoms), at least one of which is a carboxy group.

[0041] Examples of the compound (A) include siloxane diamine, a silane coupling agent having an amino group, or a polymer (siloxane polymer) formed from these silane coupling agents via a siloxane bond (Si—O—Si). The crosslinking agent (B) includes a trivalent or tetravalent carboxylic acid compound or carboxylic acid ester compound. Examples of the carboxylic acid compound include alicyclic carboxylic acids such as 1,3,5-cyclohexanetricarboxylic acid; aromatic carboxylic acids such as pyromellitic acid, 1,4,5,8-naphthalenetetracarboxylic acid, biphenyl-3,3',4,4'-tetracarboxylic acid, benzophenone-3,3',4,4'-tetracarboxylic acid, and 4,4'-oxydiphthalic acid; and fluorinated aromatic carboxylic acids such as 1,4-ditrifluoromethylpyromellitic acid. Examples of the carboxylic acid ester compound include compounds in which some of the carboxy groups of the above carboxylic acid compounds have been substituted with ester groups.

[0042] The adhesive composition may further contain a polar solvent. Examples of polar solvents include protic inorganic compounds such as water and heavy water; alcohols such as methanol, ethanol, 1-propanol, 2-propanol, 1-butanol, ethylene glycol, and propylene glycol; ethers such as tetrahydrofuran and dimethoxyethane; aldehydes and ketones such as acetone, ethyl methyl ketone, and cyclohexane; acid derivatives such as ethyl acetate, butyl acetate, N,N-dimethylformamide, N-methylacetamide, N,N-dimethylacetamide, and N-methyl-2-pyrrolidone; and sulfur compounds such as dimethyl sulfoxide.

[0043] The thickness of adhesive layer 15 is not particularly limited, but is preferably 10 μm or less, more preferably 8 μm or less, even more preferably 5 μm or less, and particularly preferably 3 μm or less. When adhesive layer 15 is 10 μm or less in thickness, stress caused by mismatch in the coefficient of linear thermal expansion between adhesive layer 15 and support substrate 14, semiconductor chip 12, or encapsulant can be further reduced, and warping during heating or cooling can be further reduced. The lower limit of the thickness of adhesive layer 15 should be such that it can sufficiently bond support substrate 14 and encapsulant layer 11, and can be, for example, 0.1 μm or more, preferably 0.3 μm or more, and more preferably 0.5 μm or more.

[0044] (Manufacturing method) The semiconductor device 10 according to this embodiment can be manufactured by any method, for example, a method of forming a sealing body including a sealing material layer 11 sealing a plurality of semiconductor chips 12 and a rewiring layer 13 on a support substrate 14 (see FIG. 3 described later), or a method of forming the sealing body on a temporary fixing substrate 17 and then bonding the temporary fixing substrate 17 to the support substrate 14 (see FIG. 7 described later).

[0045] 3A to 3D are schematic partial cross-sectional views showing a method for manufacturing the semiconductor device 10 according to this embodiment.

[0046] The semiconductor device 10 can be manufactured by a manufacturing method including, for example, 1) a step of arranging a plurality of semiconductor chips 12 on a support substrate 14 via an adhesive layer 15 (see Figure 3A), 2) a step of encapsulating the plurality of semiconductor chips 12 arranged on the support substrate 14 with an encapsulant to form an encapsulant layer 11 (see Figure 3B), and 3) a step of forming a redistribution layer 13 electrically connected to the plurality of semiconductor chips 12 on the opposite side of the encapsulant layer 11 from the support substrate 14 (see Figures 3C and 3D).

[0047] Regarding step 1) A plurality of semiconductor chips 12 are arranged on a support substrate 14 via an adhesive layer 15 (see FIG. 3A). The adhesive layer 15 may be arranged on the support substrate 14 or on the semiconductor chips 12.

[0048] The adhesive layer 15 can be formed by applying the adhesive composition described above onto the support substrate 14 or the semiconductor chip 12, and then heating it to harden it.

[0049] The method for applying the adhesive composition is not particularly limited, and may be, for example, a method such as spin coating, slit coating, spray coating, screen printing, squeegeeing, or inkjet printing.

[0050] The heating temperature of the adhesive composition may be set so that the solvent in the adhesive composition can be removed and the cure rate of the resulting adhesive layer 15 falls within the range described below. For example, when the adhesive composition contains the compounds described above, the temperature is preferably equal to or higher than the cure temperature, and can be, for example, 100°C or higher and 450°C or lower, and preferably 150°C or higher and 300°C or lower.

[0051] By heating the adhesive composition in this way, the solvent contained in the adhesive composition is removed, and the components in the adhesive composition react to obtain a cured product, and an adhesive layer 15 containing the cured product is formed.

[0052] Next, the support substrate 14 and the plurality of semiconductor chips 12 are bonded together via an adhesive layer 15 .

[0053] In this case, the surface of the adhesive layer 15 preferably has a functional group capable of forming a chemical bond. Examples of such functional groups include amino groups, epoxy groups, vinyl groups, and silanol groups (Si-OH groups). Among these, silanol groups are preferred from the viewpoints of adhesiveness and heat resistance. These functional groups may be formed by surface treatment or may be formed by the material constituting the adhesive layer.

[0054] Whether or not the adhesive layer 15 has silanol groups on its surface can be confirmed by surface analysis using time-of-flight secondary ion mass spectrometry (TOF-SIMS). Specifically, using a TOF-SIMS PHI nanoTOFII (ULVAC-PHI, Inc.), whether or not the adhesive layer 15 has silanol groups on its surface can be confirmed based on the presence or absence of a peak at a mass-to-charge ratio (m / Z) of 45.

[0055] The bonding may be performed at room temperature or under heating. From the viewpoint of more firmly bonding the support substrate 14 and the semiconductor chips 12, the bonding is preferably performed under heating.

[0056] The bonding temperature is not particularly limited, but is preferably, for example, 150°C or lower. If the bonding temperature is 150°C or lower, heat damage to the circuits formed on the semiconductor chip 12 can be further reduced. From the same viewpoint, the bonding temperature may be from room temperature (for example, 25°C) to 100°C or from room temperature to 70°C.

[0057] The bonding is preferably performed when the cure rate of the adhesive layer 15 is 70% or higher. That is, the bonding is preferably performed when the cure rate of the adhesive layer 15 is 70% or higher and at a temperature of 150° C. or lower.

[0058] If the cure rate of adhesive layer 15 is 70% or more, it is possible to further reduce misalignment when bonding support substrate 14 and semiconductor chip 12. From the same viewpoint, the cure rate of adhesive layer 15 is more preferably 80% or more, and even more preferably 90% or more. Furthermore, the upper limit of the cure rate of adhesive layer 15 is not particularly limited, but may be 99% or less from the viewpoint of more easily obtaining adhesion or further reducing residual stress after forming encapsulant layer 11.

[0059] The cure rate of the adhesive layer 15 can be confirmed by measuring the peak intensity of specific bonds and structures (the sum of the peak intensities when there are multiple peaks such as imide, amide, etc.) of the adhesive layer 15 by FT-IR (Fourier transform infrared spectroscopy) and determining the rate of increase or decrease in the peak intensity. Note that when there are band-like peaks that are difficult to separate, such as siloxane bonds, the maximum peak intensity can be used.

[0060] Furthermore, when specific bonds and structures are formed by the curing reaction, the rate of increase in peak intensity may be calculated using the following formula, and the calculated value may be used as the curing rate of the adhesive layer. Increase rate of peak strength (%)=[(peak strength of the specific bond and structure of the adhesive layer 15 before heating) / (peak strength of the specific bond and structure of the adhesive layer 15 after heating at 300° C. for 1 hour)]×100 The background signal can be removed by a conventional method. If necessary, the FT-IR measurement can be performed by the transmission method or the reflection method.

[0061] In the above-mentioned rate of increase in peak intensity, when there are a plurality of bonds and structures that cause an increase in peak intensity, the peak intensity may be interpreted as the total intensity of the plurality of peak intensities.

[0062] Regarding step 2) Next, the plurality of semiconductor chips 12 arranged on the support substrate 14 are sealed with a sealing material to form a sealing material layer 11 (see FIG. 3B).

[0063] Specifically, the above-described encapsulant is applied so as to bury the plurality of semiconductor chips 12 fixed on the support substrate 14, and then cured. For example, when the encapsulant is the above-described curable resin composition, the encapsulant can be cured by heating. This allows the formation of an encapsulant layer 11 in which the semiconductor chips 12 are buried in the cured product of the encapsulant.

[0064] Regarding step 3) Next, a rewiring layer 13 electrically connected to the plurality of semiconductor chips 12 is formed on the opposite side of the sealing material layer 11 from the support substrate 14 .

[0065] In this embodiment, a portion of the encapsulant layer 11 covering the surface of the semiconductor chip 12 is removed to expose the surfaces of the multiple semiconductor chips 12 (see Figure 3C), and then a rewiring layer 13 is formed on the exposed multiple semiconductor chips 12 (or on the surface of the encapsulant layer 11 where the multiple semiconductor chips 12 are exposed) (see Figure 3D).

[0066] The removal of a portion of the sealing material layer 11 can be performed by, for example, dry etching, etc. The formation of the rewiring layer 13 can be performed by, for example, a semi-additive process method, etc.

[0067] Through the above steps, a semiconductor device 10 having an encapsulant layer 11, a plurality of semiconductor chips 12, a rewiring layer 13, a support substrate 14, and an adhesive layer 15 is obtained.

[0068] (action) As described above, in the step of encapsulating the semiconductor chips with an encapsulant (step 2) above), residual stress may occur in the encapsulant, which includes the encapsulant layer 11 encapsulating the multiple semiconductor chips 12 and the rewiring layer 13, due to the curing and shrinkage of the encapsulant, etc. Such residual stress may cause warping or cracking of the semiconductor device.

[0069] In contrast, in the above embodiment, the sealing body including the sealing material layer 11 sealing the multiple semiconductor chips 12 and the rewiring layer 13 is supported and reinforced by the support substrate 14 via the adhesive layer 15. Therefore, even in the semiconductor device 10 that does not have a Si through electrode substrate, the mechanical strength can be maintained, and warping and cracking can be suppressed.

[0070] In particular, when the adhesive layer 15 has silanol groups on its surface, it is likely to form hydrogen bonds with functional groups such as hydroxyl groups and silanol groups on the surface of the support substrate 14 and the surfaces of the semiconductor chips 12, and when heated, it is likely to undergo a condensation reaction with these functional groups to form siloxane bonds. This allows the thickness of the adhesive layer 15 to be made thinner, thereby further reducing stress during heating or cooling caused by mismatches in the coefficient of linear thermal expansion between the adhesive layer 15 and the support substrate 14, semiconductor chips 12, or encapsulant. This further reduces warping of the semiconductor device 10.

[0071] (Variation) In the above embodiment, the semiconductor device 10 is configured as shown in FIG. 1, but is not limited to this, and may be configured as shown in FIG. 4 or FIG.

[0072] 4 is a schematic cross-sectional view showing the semiconductor device 10 according to Modification 1. FIGS. 5A to 5D are schematic partial cross-sectional views showing a manufacturing method of the semiconductor device 10 of FIG.

[0073] 4, a portion of the encapsulant layer 11 may be interposed between the redistribution layer 13 and the plurality of semiconductor chips 12. In this case, the semiconductor device 10 may further include through electrodes 16 that penetrate a portion of the encapsulant layer 11 and electrically connect the redistribution layer 13 and the plurality of semiconductor chips 12. This allows the redistribution layer 13 and the plurality of semiconductor chips 12 to be electrically connected even if the thickness of the encapsulant layer 11 is greater than the thickness of the plurality of semiconductor chips 12.

[0074] Such a semiconductor device 10 can be obtained in the same manner as in the above embodiment, except that the following steps are performed in the step 3) above (see FIGS. 5A to 5D). For example, in the above step 3), through electrodes 16 are further formed that penetrate a portion of the encapsulant layer 11 covering the surfaces of the plurality of semiconductor chips 12 and electrically connect the plurality of semiconductor chips 12 to the rewiring layer 13 (see FIG. 5C). Specifically, after forming holes that penetrate a portion of the encapsulant layer 11 covering the surfaces of the plurality of semiconductor chips 12, the holes are filled with a conductor such as Cu to form the through electrodes 16. Then, the rewiring layer 13 is formed on the encapsulant layer 11 on which the through electrodes 16 have been formed (see FIG. 5D).

[0075] In FIG. 5, the through electrodes 16 are formed after sealing with a sealing material (see FIGS. 5B and 5C), but the through electrodes 16 may be formed in advance in the semiconductor chip 12 before sealing with a sealing material.

[0076] 6 is a schematic cross-sectional view showing a semiconductor device 10 according to Modification 2. FIGS. 7A to 7D are schematic partial cross-sectional views showing a manufacturing method of the semiconductor device 10 of FIG.

[0077] As shown in FIG. 6, in the semiconductor device 10, a part of the sealing material layer 11 may be interposed between the adhesive layer 15 and the plurality of semiconductor chips 12.

[0078] Such a semiconductor device 10 can be obtained, for example, through the steps of: 1) forming a rewiring layer 13 on a temporary fixing substrate 17 via a temporary fixing material 18 (see Figure 7A); 2) arranging a plurality of semiconductor chips 12 on the rewiring layer 13 (see Figure 7B); 3) sealing the plurality of semiconductor chips 12 arranged on the temporary fixing substrate 17 with a sealing material to form a sealing material layer 11 (see Figure 7C); 4) stacking a support substrate 14 on the opposite side of the sealing material layer 11 from the temporary fixing substrate 17 via an adhesive layer 15 (see Figure 7D); and 5) removing the temporary fixing material 18 and the temporary fixing substrate 17 from the obtained laminate (see Figure 7E).

[0079] Regarding step 1) The rewiring layer 13 is formed on the temporary fixing substrate 17 via the temporary fixing material 18 (see FIG. 7A).

[0080] The temporary fixing substrate 17 is not particularly limited as long as it can stably support the semiconductor chip 12. The temporary fixing substrate 17 can be the same as the support substrate 14. When the temporary fixing substrate 17 is removed by a laser lift-off method, it is preferably a substrate that can transmit laser light, and more preferably a transparent glass substrate or a resin substrate.

[0081] A known temporary fixing material or the same material as the adhesive composition described above may be used as the temporary fixing material 18. The temporary fixing material 18 is applied onto the temporary fixing substrate 17 by a known method, and then the rewiring layer 13 is formed.

[0082] Regarding step 2) Next, a plurality of semiconductor chips 12 are arranged on the rewiring layer 13 (see FIG. 7B). Specifically, the surfaces of the plurality of semiconductor chips 12 are arranged to face the rewiring layer 13, and the semiconductor chips 12 are electrically connected to conductor portions (not shown) of the rewiring layer 13. This electrically connects the rewiring layer 13 and the semiconductor chips 12.

[0083] Regarding step 3) Next, the plurality of semiconductor chips 12 arranged on the temporary fixing substrate 17 are encapsulated to form an encapsulant layer 11 (see FIG. 7C). The encapsulant layer 11 can be formed in the same manner as in the above step 2).

[0084] Regarding step 4) Next, a support substrate 14 is laminated on the opposite side of the sealing material layer 11 from the temporary fixing substrate 17 via an adhesive layer 15 (see FIG. 7D).

[0085] The sealing material layer 11 and the support substrate 14 are bonded together via an adhesive layer 15. The bonding method can be the same as in step 1) in the first embodiment.

[0086] Regarding process 5) Next, the temporary fixing substrate 17 is removed together with the temporary fixing material 18 from the sealing material layer 11 (see FIG. 7E).

[0087] The method for removing the temporary fixing substrate 17 is not particularly limited, and may be a mechanical grinding method or a laser lift-off method. Similarly, the method for removing the temporary fixing material 18 may be a mechanical grinding method or a method for dissolving and removing it with a solvent.

[0088] [Second embodiment] FIG. 8 is a schematic partial cross-sectional view showing the configuration of a semiconductor device 10 according to the second embodiment.

[0089] The semiconductor device 10 according to this embodiment is configured in the same manner as the semiconductor device 10 according to the first embodiment, except that the rewiring layer 13 and the adhesive layer 15 are both arranged on one side in the thickness direction of the semiconductor chip 12, and the semiconductor device 10 further includes a through electrode 19 that penetrates the sealing material layer 11 in the thickness direction. Therefore, members having the same configuration and function as those in the first embodiment are given the same reference numerals, and their description will be omitted.

[0090] 8, the rewiring layer 13 is disposed between the plurality of semiconductor chips 12 and the adhesive layer 15. The rewiring layer 13 is electrically connected to each of the plurality of semiconductor chips 12.

[0091] The through electrodes 19 penetrate the sealing material layer 11 in the thickness direction and are electrically connected to the rewiring layer 13. This allows a terminal (not shown) to be formed on the back surface side of the semiconductor chip 12.

[0092] 9A to 9D are schematic partial cross-sectional views showing a method for manufacturing the semiconductor device 10 of FIG.

[0093] The semiconductor device 10 of this embodiment can be manufactured by a manufacturing method including, for example, 1) a step of forming a redistribution layer 13 on a support substrate 14 via an adhesive layer 15 (see Figure 9A), 2) a step of arranging multiple semiconductor chips 12 on the redistribution layer 13 (see Figure 9B), 3) a step of sealing the multiple semiconductor chips 12 arranged on the support substrate 14 with a sealing material to form a sealing material layer 11 (see Figure 9C), and 4) a step of forming a through electrode 19 that penetrates the sealing material layer 11 in the thickness direction and is electrically connected to the redistribution layer 13 (see Figure 9D).

[0094] In step 1), an adhesive layer 15 is formed on a support substrate 14. The method for forming the adhesive layer 15 can be the same as in step 1) of the first embodiment. Next, a rewiring layer 13 is formed on the adhesive layer 15. Specifically, after a plurality of semiconductor chips 12 are arranged on the rewiring layer 13, conductor portions (not shown) of the rewiring layer 13 and the semiconductor chips 12 are electrically connected.

[0095] Steps 2) and 3) can be performed in the same manner as steps 2) and 3) in Modification 2 of the first embodiment.

[0096] In step 4), for example, holes are formed through the sealing material layer 11 in the thickness direction, and then the holes are filled with a conductive material to form the through electrodes 19 (see FIG. 9D). Alternatively, the through electrodes 19 electrically connected to the rewiring layer 13 may be formed in advance before sealing with the sealing material.

[0097] (action) The semiconductor device 10 according to the above embodiment is reinforced by the support substrate 14, and therefore can achieve the same effects as above. In particular, in the semiconductor device 10 according to the first embodiment, the back side of the semiconductor chip 12 is reinforced while electricity can be extracted from the front side, whereas in the semiconductor device 10 according to the present embodiment, the front side of the semiconductor chip 12 is reinforced while electricity can be extracted from the back side.

[0098] In the above embodiment, the method shown in FIG. 9 has been described as a method for manufacturing the semiconductor device 10, but the present invention is not limited to this, and a method in which a sealing body is formed on a temporary fixing substrate and then bonded to a support substrate 14 may also be used. Specifically, instead of steps 4) and 5) in the manufacturing method of the semiconductor device 10 of the above-mentioned variant example 2, step 4) of removing the temporary fixing substrate 17 and the temporary fixing material 18 may be performed, and then step 5) of bonding the rewiring layer 13 of the resulting sealing body to the support substrate 14 via the adhesive layer 15 may be performed. [Industrial Applicability]

[0099] According to the present invention, it is possible to provide a semiconductor device and a manufacturing method thereof that can suppress warping and cracking even without a Si through electrode substrate. [Explanation of symbols]

[0100] 10 Semiconductor device 11 Encapsulant layer 12 Semiconductor chips 13 Redistribution layer 14 Support substrate 15 Adhesive layer 16, 19 Through electrode 17 Temporary fixing board 18 Temporary fixing material

Claims

1. an encapsulant layer; a plurality of semiconductor chips arranged two-dimensionally within the encapsulant layer; a rewiring layer electrically connected to the plurality of semiconductor chips; a support substrate disposed on one side or the other side of the sealing material layer in a thickness direction; an adhesive layer disposed between the encapsulant layer and the support substrate; having Semiconductor device.

2. the rewiring layer is disposed on one side of the plurality of semiconductor chips in a thickness direction; the adhesive layer is disposed on the other side of the plurality of semiconductor chips in the thickness direction. The semiconductor device according to claim 1 .

3. a part of the encapsulant layer is interposed between the rewiring layer and the plurality of semiconductor chips; The semiconductor device further includes a through electrode that penetrates a portion of the sealing material layer and electrically connects the rewiring layer and the plurality of semiconductor chips. The semiconductor device according to claim 2 .

4. a part of the encapsulant layer is interposed between the adhesive layer and the plurality of semiconductor chips; The semiconductor device according to claim 2 .

5. the redistribution layer is disposed between the plurality of semiconductor chips and the adhesive layer; The sealing material layer further includes a through electrode that penetrates the sealing material layer in a thickness direction and is electrically connected to the rewiring layer. The semiconductor device according to claim 1 .

6. The thickness of the adhesive layer is 10 μm or less. The semiconductor device according to claim 1 .

7. The adhesive layer and the support substrate or the sealing material layer are bonded via a Si-O-M bond (M is a metal atom or a semiconductor atom). The semiconductor device according to claim 1 .

8. the adhesive layer contains a resin containing a siloxane bond and at least one of an amide bond and an imide bond; The semiconductor device according to claim 7 .

9. a step of arranging a plurality of semiconductor chips on a support substrate via an adhesive layer; a step of encapsulating the semiconductor chips arranged on the support substrate with an encapsulant to form an encapsulant layer; forming a rewiring layer electrically connected to the plurality of semiconductor chips on the opposite side of the encapsulant layer from the support substrate; Including, A method for manufacturing a semiconductor device.

10. In the step of forming the rewiring layer, removing a portion of the encapsulant layer to expose surfaces of the semiconductor chips, and forming the rewiring layer on the exposed semiconductor chips; The method for manufacturing a semiconductor device according to claim 9 .

11. In the step of forming the rewiring layer, Further, through electrodes are formed to penetrate a part of the sealing material layer covering the surfaces of the plurality of semiconductor chips and to electrically connect the plurality of semiconductor chips to the rewiring layer. The method for manufacturing a semiconductor device according to claim 9 .

12. forming a rewiring layer on a support substrate via an adhesive layer; disposing a plurality of semiconductor chips on the rewiring layer; encapsulating the semiconductor chips arranged on the support substrate with an encapsulant to form an encapsulant layer; forming a through electrode that penetrates the sealing material layer in a thickness direction and is electrically connected to the rewiring layer; Including, A method for manufacturing a semiconductor device.

13. forming a rewiring layer on a temporary fixing substrate via a temporary fixing material; disposing a plurality of semiconductor chips on the rewiring layer; a step of encapsulating the semiconductor chips arranged on the temporary fixing substrate with an encapsulant to form an encapsulant layer; laminating a support substrate on the opposite side of the sealing material layer from the temporary fixing substrate via an adhesive layer; a step of removing the temporary fixing material and the temporary fixing substrate from a laminate obtained by laminating the support substrates; Including, A method for manufacturing a semiconductor device.

14. The adhesive layer has a silanol group on the surface. The method for manufacturing a semiconductor device according to any one of claims 9 to 13.

15. the adhesive layer contains a resin containing a siloxane bond and at least one of an amide bond and an imide bond; The method for manufacturing a semiconductor device according to any one of claims 9 to 13.

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