Semiconductor device manufacturing method and semiconductor substrate

Abstract

To provide a technique for forming a p-type region on a nitride semiconductor.SOLUTION: A semiconductor device manufacturing method includes: an ion implantation process of ion-implanting beryllium into a compound semiconductor substrate containing aluminum; and an annealing process of annealing the compound semiconductor substrate after the ion implantation process to replace aluminum atoms with beryllium atoms.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a method for manufacturing a semiconductor device and a semiconductor substrate. [Background technology]

[0002] Because aluminum-containing compound semiconductors (e.g., aluminum nitride) have a wide band gap, there is a demand for expanded applications as materials for power devices. Patent Document 1 discloses a technique for doping aluminum-containing compound semiconductors with p-type impurities (beryllium) using molecular beam epitaxy (MBE). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2023-527310 Summary of the Invention [Problem to be solved by the invention]

[0004] Impurity doping by molecular beam epitaxy is difficult to apply to the field of semiconductor manufacturing from the viewpoint of production costs and the like. [Means for solving the problem]

[0005] One embodiment of the method for manufacturing a semiconductor device disclosed in this specification includes an ion implantation step of ion-implanting beryllium into a surface of a compound semiconductor substrate containing aluminum, and an annealing step of annealing the compound semiconductor substrate after the ion implantation step so that aluminum atoms are replaced with beryllium atoms.

[0006] According to the above-described configuration, the aluminum-containing compound semiconductor can be made p-type by implanting beryllium ions, which makes it possible to reduce the manufacturing cost of the semiconductor device compared to molecular beam epitaxy and the like.

[0007] After the ion implantation process, the beryllium concentration distribution in a direction perpendicular to the surface of the compound semiconductor substrate may have a first peak having a first height at a position deeper than the surface, and may have a tail shape in which the concentration decreases from the first peak toward both the deeper and shallower sides. After the annealing process, the beryllium concentration distribution may have, in addition to the first peak, a second peak having a second height near the surface. The second peak may have a tail shape in which the concentration decreases from the second peak toward one side in the deeper side. The first height after the annealing process may be lower than the first height before the annealing process. The second height may be higher than the first height after the annealing process. Details of the effects will be described in the examples.

[0008] The second peak may be present in a region from the surface to the depth of the second peak.

[0009] By the annealing step, a conductive region having electrical conductivity may be selectively formed in a region having a depth from the surface to the second peak.

[0010] The annealing step may be carried out in an oxygen-free atmosphere.

[0011] The annealing step may be carried out at a temperature of 750° C. or higher for 3 minutes or longer.

[0012] One embodiment of the semiconductor substrate disclosed in this specification is a semiconductor substrate of a compound semiconductor containing aluminum. The beryllium concentration distribution in a direction perpendicular to the surface of the semiconductor substrate has a first peak with a first height at a position deeper than the surface, and a second peak with a second height near the surface. The first peak has a tail shape in which the concentration decreases from the first peak toward both the deeper and shallower sides. The second peak has a tail shape in which the concentration decreases from the second peak toward one side in the deeper side. The second height is higher than the first height. [Brief explanation of the drawings]

[0013] [Figure 1]It is a diagram showing the Be concentration distribution after the ion implantation process. [Figure 2] It is a diagram showing the Be concentration distribution after the annealing process. [Figure 3] It is a graph showing the concentration distribution profile of Be. [Figure 4] It is a graph showing the concentration distribution profile of Be. [Figure 5] It is a diagram showing the AlN substrate 1 before separation by the mesa groove MT. [Figure 6] It is a diagram showing the AlN substrate 1 after separation by the mesa groove MT. [Figure 7] It is a diagram showing the atomic site arrangement that Be can occupy in the AlN lattice. [Figure 8] It is an analysis image of the surface 1s before the annealing process. [Figure 9] It is an analysis image of the surface 1s after the annealing process. [Figure 10] It is a schematic cross-sectional view of the light-emitting diode 20. [Figure 11] It is a schematic cross-sectional view of the field-effect transistor 30. [Figure 12] It is a schematic view of the modified FET 130.

Embodiments for Carrying Out the Invention

Examples

[0014] <Method for Forming p-Type AlN> In this example, a case where aluminum nitride (AlN) is used as a compound semiconductor containing aluminum and beryllium (Be) is used as an acceptor impurity of group II elements will be described. Using the cross-sectional views of FIGS. 1 and 2, the process of forming a p-type region in the AlN substrate 1 will be described. FIGS. 1 and 2 are partial enlarged views near the surface of the AlN substrate 1. The AlN substrate 1 is an AlN single crystal that is not doped with impurities.

[0015] In the first step, an ion implantation process is performed. In the ion implantation process, Be is ion-implanted from the surface 1s of the AlN substrate 1 (see Fig. 1). In this embodiment, the ion implantation energy is set to 200 keV, and the Be dose amount is 2.9×10 15 cm -2 . In Fig. 1, the vertically upward direction with respect to the surface 1s is defined as the z direction. And the region where Be is implanted is shown in gray. The darker the gray, the higher the Be concentration. Also, the profile BP0 of the Be concentration distribution after the ion implantation process is shown in a graph. The profile BP0 in Fig. 1 is a graph schematically showing the profiles BP0 in Figs. 3 and 4 described later.

[0016] In the second step, an annealing process is performed. In the annealing process, the AlN substrate after the ion implantation process is heat-treated. The annealing temperature and time may be determined according to the conductivity described later. In the annealing conditions of this embodiment, the atmosphere is a pure nitrogen atmosphere. The temperature is set to 800 °C or 1300 °C. The annealing time is set to 5 minutes, 20 minutes, or 60 minutes.

[0017] Fig. 2 shows the profile BP3 of the Be concentration distribution after the annealing process. The profile BP3 in Fig. 2 is a graph schematically showing the profiles BP3 in Figs. 3 and 4 described later. Thereby, as will be described later, Al atoms are replaced by Be atoms, and the conductivity of the surface 1s is obtained.

[0018] <Be concentration distribution profile> The Be concentration distribution profiles after the ion implantation process and the annealing process will now be described. Figures 3 and 4 show the Be concentration distribution profiles in the direction perpendicular to the surface 1s (i.e., the depth direction). Figures 3 and 4 are diagrams obtained using secondary ion mass spectrometry (SIMS). The vertical axis represents the Be concentration. The horizontal axis represents the depth from the surface 1s of the AlN substrate 1. Figure 3 shows a profile up to a depth of 1500 nm using high energy. Figure 4 shows a profile near the surface up to a depth of 20 nm using low energy. In other words, Figure 4 is an enlarged view of the near-surface region SR in Figure 3.

[0019] Profile BP0 is the concentration distribution after the ion implantation process but before the annealing process. Profile BP1 is the concentration distribution when the annealing process is performed at 800°C for 5 minutes. Profile BP2 is the concentration distribution when the annealing process is performed at 1300°C for 5 minutes. Profile BP3 is the concentration distribution when the annealing process is performed at 1300°C for 20 minutes. Profile BP4 is the concentration distribution when the annealing process is performed at 1300°C for 60 minutes.

[0020] The Be concentration distribution before the annealing process will be described. As shown in FIG. 3, the profile BP0 of the Be concentration distribution before the annealing process has a first peak P1 at a position deeper than the surface 1s (at a depth of approximately 500-600 nanometers). The concentration also exponentially decreases from the first peak P1 in both the deeper and shallower directions. That is, the profile BP0 has a tailing shape that is approximately symmetrical on both sides with respect to the first peak P1. The first peak P1 before the annealing process has a first height H1a. Furthermore, as shown in FIG. 4, in the profile BP0 before the annealing process, almost no Be is detected near the surface 1s (in a region within 10 nm from the surface 1s).

[0021] Next, the Be concentration distribution after the annealing process will be described. As shown in Figure 3, the profiles BP2 and BP3 after the annealing process each have a first peak P1. As shown in Figure 4, the profiles BP2 and BP3 each have a second peak P2 near the surface 1s. The second peak is present in the surface region SA at a depth of 5 nm from the surface 1s. The second peak P2 has a one-sided skirt shape in which the concentration decreases toward one side in the deeper direction (-z direction) from the second peak P2.

[0022] That is, the Be implanted into the AlN substrate 1 by the ion implantation process can be spontaneously diffused to the surface by the annealing process. It can be seen that the high concentration of Be accumulates in the surface region SA, resulting in the new formation of a second peak P2 in the Be concentration distribution.

[0023] The relationship between peak heights will be explained using the schematic diagrams of Figures 1 and 2. In the profile BP0 (Figure 1) before the annealing process, the first peak P1 has a first height H1a. On the other hand, in the profile BP3 (Figure 2) after the annealing process, the first peak P1 has a first height H1b, and the second peak P2 has a second height H2. The first height H1b after the annealing process is lower than the first height H1a before the annealing process. The second height H2 is higher than the first height H1b.

[0024] <Control of surface conductivity> The p-type conductivity of the surface 1s of the AlN substrate 1 was measured before and after the annealing process. The measurements were carried out using a multimeter. In the sample before the annealing process (in the as-ion-implanted state), Be was not detected on the surface 1s. In addition, the conductivity of the surface 1s could not be measured.

[0025] In the sample subjected to the annealing process of profile BP1 (800 °C, 5 min), the Be concentration at the surface 1s was 4 × 10 19 [cm -3] (Figure 4, region R1). It became possible to measure the surface conductivity using a multimeter. In addition, for the sample that underwent the annealing process of profile BP2 (1300 °C, 5 min), the Be concentration in the surface 1s was 3 × 10 21 [cm -3 ] (Figure 4, region R2). The conductivity, as measured by a multimeter, improved by more than 100 times.

[0026] In the sample that underwent the annealing process (1300 °C, 20 min) of profile BP3, the Be concentration at the surface 1s was 1 × 10 22 [cm -3 ] (Figure 4, region R3). In this sample, the surface temperature was 10 20 [cm -3 A high hole concentration of the order of ] was observed at room temperature, and the resistivity was 1.46 × 10 2 As a result, the lowest values reported so far for p-type AlN were achieved in terms of acceptor concentration, hole concentration, and electrical conductivity (the reciprocal of electrical resistivity).

[0027] We also conducted experiments to identify the depth of the conductive region with p-type conductivity. As shown in Figures 5 and 6, metal electrodes 3 were placed on the surface 1s of the annealed AlN substrate 1, spaced apart from each other. In Figure 6, the two electrodes 3 were separated by a mesa groove MT with a depth D1 of approximately 10 nm. The mesa groove MT was formed by ICP-RIE. A voltage was applied between the two electrodes 3 using a power supply (not shown). As a result, current was detected in the sample shown in Figure 5. On the other hand, no current was detected in the sample shown in Figure 6, which had the mesa groove MT. This confirmed that p-type conductivity is obtained in the region extending from the surface 1s to a depth of 10 nm. More specifically, it was confirmed that p-type conductivity is obtained in the region extending from the surface 1s to a second peak P2. This indicates that p-type conductivity can be achieved by a layer with a high concentration of Be selectively formed at a depth of 10 nm from the surface 1s.

[0028] From the above, it can be seen that p-type conductivity is obtained by Be that diffuses from the inside of the AlN substrate 1 to the surface 1s and accumulates in the vicinity of the surface 1s. And it can be seen that the higher the Be concentration on the surface 1s, the lower the resistivity can be made. That is, it can be seen that by controlling the diffusion and accumulation of Be atoms in the vicinity of the surface 1s according to the temperature and time of the annealing process, the conductivity on the surface 1s can be variably controlled. Also, the surface conductivity can be measured under the annealing conditions (800 °C, 5 minutes) of the profile BP1. From this, it can be seen that in order to exhibit p-type conductivity on the surface 1s, conditions of 750 °C or higher and 3 minutes or longer can be used.

[0029] <Model of the manifestation of p-type conductivity> The technology of this specification explains the reason for obtaining p-type conductivity. The high-energy Be ion implantation in the ion implantation process damages the lattice of the AlN single crystal and generates point defects such as Al vacancies. Two thermal activation processes are performed by the subsequent annealing process. The first process is a lattice recovery process in which Al atoms thermally move to re-occupy the Al vacancies. The second process is a substitution process in which Be atoms thermally move to occupy the Al vacancies and substitutional Be Al is generated.

[0030] Be atoms have the characteristic that they have a smaller atomic radius than Al atoms and can diffuse at ultra-high speed between the lattices of the AlN crystal. And due to the crystal damage caused by ion implantation, Be atoms can be spontaneously diffused toward the surface 1s. Therefore, at a high temperature of 800 °C or higher, Be reaches the surface 1s of the AlN substrate 1 in a short time of several hundred seconds by high-speed diffusion and accumulates on the surface 1s. And in the vicinity of the surface 1s, before Al atoms thermally move to re-occupy the Al vacancies, Be that has diffused to the surface 1s occupies the Al vacancies and substitutional Be Al is formed. Since substitutional Be Al can be present at a high concentration in the vicinity of the surface 1s, it becomes possible to exhibit p-type conductivity on the surface 1s.

[0031] That is, thermal diffusion allows Be and Al atoms to move competitively within a limited time frame. Then, due to the slight mismatch in atomic radii between Be and Al, Be atoms preferentially substitute for Al vacancies, resulting in the formation of substitutional Be atoms. Al This substitution Be Al The generation of can be further promoted by the presence of Al vacancies generated by high-energy Be ion implantation.

[0032] <Annealing temperature range> An experiment was conducted to confirm the optimum annealing temperature range for the annealing process. Specifically, several AlN substrates 1 implanted with Be ions were prepared. Each AlN substrate 1 was annealed at 1000°C, 1100°C, 1200°C, and 1300°C. X-ray diffraction rocking curves were obtained for the (0002) and (10-15) planes of the annealed samples. As a result, it was found that an annealing temperature of 1200°C or higher can sufficiently repair the crystal damage caused by Be ion implantation. From the above, it is preferable that the temperature for the annealing process be 1200°C or higher.

[0033] <Replace Be Al How to check > Figure 7 shows the atomic site configurations that Be can take in a hexagonal AlN lattice. The atomic site configurations are determined by the substitution of Al (Be Al ), substitution of N (Be N ), tetrahedral interstitial sites (Be i (Tet)) and the four nearest-neighbor N atoms in the octahedral interstitial site (Be i (Oct)) are the six nearest N atoms. In this atomic site configuration, Be N and Be i leads to lattice expansion. Be N The reason why N causes lattice expansion is because the atomic radius of N is significantly larger than that of Be. Therefore, it is Be that causes lattice contraction. Al This is because the atomic radius of Be is smaller than that of Al. Note that the presence of Al vacancies and N vacancies can also cause lattice contraction.

[0034] An AlN substrate 1 was fabricated by performing the ion implantation and annealing processes described herein. The surface 1s of the fabricated AlN substrate 1 was analyzed at atomic resolution. Figure 8 shows an image after the ion implantation process but before the annealing process. Figure 9 shows an image after the annealing process. Figures 8(A) and 9(A) are drift-corrected high-angle annular dark-field scanning transmission electron microscope (HAADF-STEM) images. The insets show diffraction patterns for geometric phase analysis (GPA). Figures 8(B) and 9(B) are aligned GPA mapping images. Line scans of the strain distribution were calculated within the regions delimited by the dotted boxes.

[0035] Before and after the annealing process, we performed GPA analysis to understand the distribution of in-plane and out-of-plane strain near the AlN surface 1s. Because the in-plane lattice is constrained by the underlying AlN film, no in-plane strain is generated. As a result, lattice expansion and contraction manifest as adjustments to the out-of-plane lattice, resulting in uniaxial strain along the c-axis becoming tensile or compressive, respectively.

[0036] According to the GPA results in Figure 8(B), before the annealing process, significant out-of-plane tensile strain was measured, suggesting lattice expansion in the c-axis direction. This may be generated by Al and N interstitials due to the ion implantation process. In contrast, according to the GPA results in Figure 9(B), no significant tensile strain was observed after the annealing process. This suggests that the crystalline damage and point defects (e.g., Al and N interstitials) induced by the ion implantation process are repaired by the annealing process.

[0037] Furthermore, as shown in Figure 9(B), it was measured that the region of 3 to 4 nm deep near the surface 1s of the AlN after the annealing process had a uniaxial compressive strain of -0.4% in the c-axis direction. This compressive strain was due to the substitutional Be AlThis is thought to be due to the underlying Al vacancies and N vacancies. However, since no compressive strain was observed before the annealing process, it is unlikely that Al vacancies or N vacancies are the cause. Furthermore, the thickness of the compressive layer is almost identical to the thickness of the Be accumulation layer (see surface region SA in Figure 4) shown by the SIMS results, suggesting that the compressive strain is closely related to the accumulation of Be. In other words, compressive strain was observed at the depth where Be accumulated due to the annealing process. This fact suggests that the Be accumulation after the annealing process is due to the compressive strain. Al The formation of

[0038] From the above, by measuring (1) whether strain occurs in the region where Be is accumulated, and (2) whether the generated strain is compressive, it is possible to determine the substitutional Be near the surface 1s. Al This makes it possible to identify whether or not an AlN substrate having p-type conductivity is formed by the technology of the present specification. [Example]

[0039] The near-surface region containing the second Be peak produced by the techniques described herein can be used as a p-type ohmic contact layer, which is important for p-n junction diodes and bipolar transistors, including deep ultraviolet emitters such as light-emitting diodes and laser diodes.

[0040] 10 shows a schematic cross-sectional view of a light-emitting diode 20 fabricated using the technology of this specification. The light-emitting diode 20 has a structure in which a substrate 21, an AlN buffer layer 22, an n-type AlN layer 24, a light-emitting layer 25, a p-type AlN layer 26, a p-type ohmic contact layer 27, and a p-type electrode layer 28 are stacked in this order. An n-type electrode 29 is disposed on the n-type AlN layer 24.

[0041] Various materials can be used for the substrate 21. For example, the substrate 21 may be AlN, sapphire, SiC, Si, or the like. The light-emitting layer 25 is an undoped AlN layer. The n-type AlN layer 24 may be made of another material, such as n-type AlGaN. The p-type AlN layer 26 may be made of another material, such as p-type AlGaN.

[0042] The p-type ohmic contact layer 27 is a layer formed by the technology described in this specification. The surface 27s of the p-type ohmic contact layer 27 has high p-type conductivity, which allows for low-resistance ohmic contact with the p-type electrode layer 28. Therefore, by applying a forward voltage to the light-emitting diode 20, far-ultraviolet light can be emitted with high efficiency. [Example]

[0043] 11 shows a schematic cross-sectional view of a field-effect transistor (FET) 30 using an AlN substrate 1 fabricated by the technology of this specification. The FET 30 is a normally-on p-channel transistor. The FET 30 mainly includes the AlN substrate 1, a gate insulating film 31, a gate electrode 32, a source electrode 33, and a drain electrode 34.

[0044] An active region separated by a mesa groove MT is formed on the surface 1s. A source electrode 33 and a drain electrode 34 are disposed on the surface 1s of the active region. A gate electrode 32 is disposed on the surface 1s between the source electrode 33 and the drain electrode 34 with a gate insulating film 31 interposed therebetween.

[0045] When no gate voltage is applied to the gate electrode 32, a current flows depending on the potential difference applied between the source electrode 33 and the drain electrode 34. In this state, by applying a positive gate voltage to the gate electrode 32, a depletion layer can be generated in the p-type AlN region in the surface layer of the surface 1s, thereby blocking the current.

[0046] The manufacturing process of the FET 30 will be described below. (1) The AlN substrate 1 having a p-type AlN layer formed on the surface 1s is formed by the ion implantation process and annealing process described above. (2) A mesa groove MT is formed by dry etching. (3) A source electrode 33, a drain electrode 34 (metal contacts), a gate insulating film 31 (e.g., a silicon nitride film), and a gate electrode 32 (metal contact) are formed.

[0047] (Modification of Example 3) FIG. 12 shows a modified FET 130. The modified FET 130 is an example in which the mesa groove MT is omitted by using a ring-shaped gate electrode. FIG. 12(A) is a top view. FIG. 12(B) is a cross-sectional view along line BB. A source electrode 133 and a drain electrode 134 are disposed on the surface 1s of an AlN substrate 1 fabricated using the technology of this specification. The source electrode 133 is disposed so as to surround the periphery of the drain electrode 134. A ring-shaped groove TR is formed between the source electrode 133 and the drain electrode 134. A ring-shaped gate electrode 132 is disposed within the groove TR with a gate insulating film 131 interposed therebetween.

[0048] Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of these objectives alone is technically useful.

[0049] (Variation) The aluminum-containing compound semiconductor to which the technology of this specification can be applied is not limited to aluminum nitride (AlN). For example, aluminum oxide (Al2O3), aluminum fluoride (AlF3), etc. may also be used. Also, a mixture of AlN, Al2O3, AlF3, etc. may be used. In this case, it is preferable that the ratio of AlN, Al2O3, AlF3, etc. contained in the mixture is 60% or more. An example of a mixture is Al 0.75 Ga 0.25 N, A.L. 0.6 Ga 0.2 In 0.2 N, (Al 0.6 Ga 0.4 )2O3), etc.

[0050] Aspects of the present technology are listed below. [Aspect 1] an ion implantation step of ion-implanting beryllium into a surface of a compound semiconductor substrate containing aluminum; an annealing step of annealing the compound semiconductor substrate after the ion implantation step so that aluminum atoms are replaced with beryllium atoms; A method for manufacturing a semiconductor device, comprising: [Aspect 2] after the ion implantation step, a beryllium concentration distribution in a direction perpendicular to the surface of the compound semiconductor substrate has a first peak having a first height at a position deeper than the surface, and has a tailing shape in which the concentration decreases toward both a deeper direction and a shallower direction from the first peak, after the annealing step, the beryllium concentration distribution has, in addition to the first peak, a second peak having a second height near the surface; the second peak has a tailing shape in which the concentration decreases toward one side in a deeper direction from the second peak, the first height after the annealing step is lower than the first height before the annealing step; 2. The method for manufacturing a semiconductor device according to aspect 1, wherein the second height is greater than the first height after the annealing step. [Aspect 3] 3. The method for manufacturing a semiconductor device according to aspect 2, wherein the second peak is present in a region at a depth of up to 5 nm from the surface. [Aspect 4] 4. The method for manufacturing a semiconductor device according to aspect 2 or 3, wherein the annealing step selectively forms a conductive region having conductivity in a region having a depth from the surface to the second peak. [Aspect 5] 5. The method for manufacturing a semiconductor device according to any one of aspects 1 to 4, wherein the annealing step is performed in an oxygen-free atmosphere. [Aspect 6] 6. The method for manufacturing a semiconductor device according to any one of aspects 1 to 5, wherein the annealing step is carried out under conditions of 750° C. or higher and 3 minutes or longer. [Aspect 7] A semiconductor substrate made of a compound semiconductor containing aluminum, a beryllium concentration distribution in a direction perpendicular to a surface of the semiconductor substrate has a first peak having a first height at a position deeper than the surface and a second peak having a second height near the surface; the first peak has a tailing shape in which the concentration decreases toward both the deep and shallow sides of the first peak, the second peak has a tailing shape in which the concentration decreases toward one side in a deeper direction from the second peak, The second height is greater than the first height. Semiconductor substrate. [Aspect 8] 8. The semiconductor substrate of claim 7, wherein the second peak is present in a region up to 5 nm deep from the surface. [Aspect 9] 9. The semiconductor substrate according to claim 7, wherein a conductive region having conductivity is selectively formed in a region having a depth from the surface to the second peak. [Explanation of symbols]

[0051] 1: AlN substrate 1s: surface BP0-BP4: profile P1: first peak P2: second peak

Claims

1. an ion implantation step of ion-implanting beryllium into a surface of a compound semiconductor substrate containing aluminum; an annealing step of annealing the compound semiconductor substrate after the ion implantation step so that aluminum atoms are replaced with beryllium atoms; A method for manufacturing a semiconductor device, comprising:

2. after the ion implantation step, a beryllium concentration distribution in a direction perpendicular to the surface of the compound semiconductor substrate has a first peak having a first height at a position deeper than the surface, and has a tail shape in which the concentration decreases toward both a deeper direction and a shallower direction from the first peak, after the annealing step, the beryllium concentration distribution has, in addition to the first peak, a second peak having a second height near the surface, the second peak has a tail shape in which the concentration decreases toward one side in a deeper direction from the second peak, the first height after the annealing step is lower than the first height before the annealing step; The method for manufacturing a semiconductor device according to claim 1 , wherein the second height is higher than the first height after the annealing step.

3. 3. The method for manufacturing a semiconductor device according to claim 2, wherein the second peak is present in a region at a depth of up to 5 nm from the surface.

4. 4. The method for manufacturing a semiconductor device according to claim 3, wherein a conductive region having conductivity is selectively formed in the region having a depth from the surface to the second peak by the annealing step.

5. 2. The method for manufacturing a semiconductor device according to claim 1, wherein said annealing step is performed in an atmosphere containing no oxygen.

6. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the annealing step is performed under conditions of 750[deg.] C. or higher and 3 minutes or longer.

7. A semiconductor substrate made of a compound semiconductor containing aluminum, a beryllium concentration distribution in a direction perpendicular to a surface of the semiconductor substrate has a first peak having a first height at a position deeper than the surface and a second peak having a second height near the surface; the first peak has a tailing shape in which the concentration decreases toward both the deep and shallow sides of the first peak, the second peak has a tail shape in which the concentration decreases toward one side in a deeper direction from the second peak, The second height is greater than the first height. Semiconductor substrate.

8. The semiconductor substrate according to claim 7 , wherein the second peak is present in a region having a depth of up to 5 nm from the surface.

9. 9. The semiconductor substrate according to claim 8, wherein a conductive region having conductivity is selectively formed in a region having a depth from the surface to the second peak.

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