Sensor data compression in plasma tool

Abstract

To provide a system and a method for compressing data regarding sensor data compression in a plasma tool.SOLUTION: A method according to an embodiment includes receiving a plurality of measurement signals from one or more sensors coupled to a radio frequency (RF) transmission line of a plasma tool. The RF transmission line extends from an output of an RF generator to an electrode of a plasma chamber. The method includes converting the plurality of measurement signals from an analog format to a digital format to obtain sampled data and processing the data to reduce the amount of data. The amount of data is compressed, and compressed data is output. The method includes transmitting the compressed data to a controller for controlling the plasma tool.SELECTED DRAWING: Figure 3F-1

Description

[Technical Field]

[0001] The embodiments described in this disclosure relate to sensor data compression in plasma tools. [Background technology]

[0002] The background discussion provided herein is intended to provide a general background to the present disclosure. The work of the presently named inventors, as well as aspects of the specification that may not otherwise qualify as prior art at the time of filing, are not admitted, expressly or impliedly, as prior art to the present disclosure to the extent that they are described in this Background section.

[0003] In a plasma tool, one or more radio frequency (RF) generators are coupled to an impedance matching network. The impedance matching network is coupled to a plasma chamber. An RF signal is supplied from the RF generator to the impedance matching network. The impedance matching network receives the RF signal and outputs the RF signal to the plasma chamber. Additionally, multiple process gases are supplied to a gap in the plasma chamber. Wafers are processed in the plasma chamber as the RF signal is supplied from the impedance matching network to the plasma chamber and the process gases are supplied.

[0004] During wafer processing, a large amount of data is collected.

[0005] It is against this background that the embodiments described in this disclosure arise. Summary of the Invention

[0006] Embodiments of the present disclosure provide sensor data compression in plasma tools. It should be appreciated that the embodiments can be implemented in numerous ways, such as, for example, a process on a computer readable medium, an apparatus, a system, a piece of hardware, or a method. Various embodiments are described below.

[0007] In one embodiment, a method for compressing data is described. The method includes receiving a plurality of measurement signals from one or more sensors coupled to a radio frequency (RF) transmission path of a plasma tool. The RF transmission path extends from the output of an RF generator to an electrode of a plasma chamber. The method includes converting the plurality of measurement signals from analog to digital format to obtain sample data and processing the sample data to reduce the amount of sample data. The amount of sample data is compressed while maintaining important information for optimizing wafer processing. The method includes transmitting the compressed data to a controller for controlling the plasma tool. Examples of important information include a master maximum peak-to-peak value, a slave maximum peak-to-peak value, a master average frequency value, and an average phase value, as described below.

[0008] In one embodiment, a compression-integrated system for compressing data is described. The compression-integrated system includes an analog-to-digital converter that receives a plurality of measurement signals from one or more sensors coupled to an RF transmission line of a plasma tool. The analog-to-digital converter converts the plurality of measurement signals from analog format to digital format to provide sampled data. The compression-integrated system includes a data compression unit coupled to the analog-to-digital converter. The data compression unit processes the data to reduce the amount of data. The amount of data is compressed, and compressed data is output. The compression-integrated system includes a transmitter coupled to the data compression unit. The transmitter transmits the compressed data to a controller for controlling the plasma tool.

[0009] In one embodiment, a system for compressing data is described. The system includes an RF generator coupled to an RF path. The RF generator provides a first RF signal to the RF path. The system includes an RF sensor coupled to the RF path. The RF sensor senses the first RF signal and a second RF signal and outputs a plurality of measurement signals. The system includes a data integration system coupled to the RF sensor. The data integration system receives the plurality of measurement signals. The data integration system converts the plurality of measurement signals from an analog format to a digital format to obtain sample data, and processes the data to synchronously reduce the amount of data. For example, the data is compressed and the compressed data is output synchronously with a clock signal. The data integration system transmits the compressed data to a controller for controlling the system.

[0010] Some advantages of the systems and methods described herein for compressing sensor data in a plasma tool include reducing the amount of data used to control the plasma tool. An RF generator provides an RF signal having many voltage cycles. The RF signal is also reflected back toward the RF generator, resulting in a reflected RF signal having many voltage cycles. A large amount of data represented by the provided and reflected RF signals is measured. This large amount of data can be unmanageable when determining which portions of the data to use to control the plasma tool. The systems and methods described herein provide a controlled method for reducing the large amount of data to a manageable amount that is representative of the large amount of data. As an example, the compressed amount of data includes a master maximum peak-to-peak value, a slave maximum peak-to-peak value, a master average frequency value, and an average phase value, and the compressed amount of data is generated from the large amount of data.

[0011] Another advantage of the systems and methods for sensor data compression in plasma tools described herein includes parallel processing of sensor data. Large amounts of data are stored in multiple registers and processed in parallel to calculate the master maximum peak-to-peak value and the slave maximum peak-to-peak value. This parallel processing increases the speed at which large amounts of data can be processed.

[0012] Yet another advantage of the systems and methods described herein for sensor data compression in plasma tools is that large amounts of data do not need to be stored in a memory device after being processed to determine the compressed amount of data. This reduces the burden of data storage and improves data integrity by increasing the effective number of bits (ENOB per digital measurement). For example, the critical information discussed above is generated and provided to a controller for processing.

[0013] Other aspects will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0014] The embodiments are understood by reference to the following description taken in conjunction with the accompanying drawings.

[0015] [Figure 1A] FIG. 1A is a diagram of one embodiment of a system illustrating a data compression unit (DCU) for compressing data received from a radio frequency (RF) sensor.

[0016] [Figure 1B] FIG. 1B is a diagram of one embodiment of a system to illustrate that data compression is used to compress data received from multiple RF sensors.

[0017] [Figure 1C-1]FIG. 1C-1 is a diagram of one embodiment of a system to illustrate that a data compression unit is used to compress data received from an RF sensor coupled to a match that is coupled to a transformer coupled plasma (TCP) coil.

[0018] [Figure 1C-2] FIG. 1C-2 is a diagram of one embodiment of a system to illustrate the use of an RF sensor in a match.

[0019] [Figure 1D] FIG. 1D is a diagram of one embodiment of a system to illustrate that a data compression unit is used to compress data received from multiple RF sensors coupled to different matches coupled to multiple TCP coils.

[0020] [Figure 1E-1] FIG. 1E-1 is a diagram of one embodiment of a system to illustrate that a data compression unit is used to compress data received from multiple RF sensors coupled to the output of a match.

[0021] [Figure 1E-2] FIG. 1E-2 is a diagram of one embodiment of a system to illustrate the use of an RF sensor in a plasma chamber.

[0022] [Figure 1F] FIG. 1F is a diagram of an embodiment of an RF sensor to illustrate that an analog-to-digital converter (ADC), a DCU, and a data transmitter are integrated within the RF sensor.

[0023] [Figure 1G] FIG. 1G is a diagram of one embodiment of a system to illustrate transmitting compressed data from a data integration system (DIS) to a process controller for processing instead of transmitting the compressed data to an analysis controller.

[0024] [Figure 1H] FIG. 1H is a diagram of an embodiment, referenced 171, illustrating the use of an RF sensor with a matchless plasma source (MPS).

[0025] [Figure 2] FIG. 2 is a diagram of one embodiment of a DCU.

[0026] [Figure 3A] FIG. 3A is a diagram illustrating an embodiment of a method performed by a master maximum peak-to-peak (PTP) determiner to determine a master maximum (max) peak-to-peak (PTP) value, MMaxPTP.

[0027] [Figure 3B] FIG. 3B is a diagram illustrating one embodiment of a method performed by a slave maximum PTP determiner to determine a slave maximum peak-to-peak value SMaxPTP.

[0028] [Figure 3C] FIG. 3C is a diagram illustrating one embodiment of a method performed by the master average frequency determiner to determine the master average frequency MAVF.

[0029] [Figure 3D] FIG. 3D is a diagram illustrating one embodiment of a method performed by the mean phase determiner to determine the mean phase φ.

[0030] [Figure 3E] FIG. 3E is a diagram of one embodiment of a master average frequency determiner that is synchronized among all ADC channels.

[0031] [Figure 3F-1] FIG. 3F-1 is one embodiment of a graph illustrating a master sample data group having a maximum amplitude and a minimum amplitude and its corresponding slave sample data group.

[0032] [Figure 3F-2] FIG. 3F-2 is an embodiment of a graph illustrating that the slave sample data groups do not correspond to the master sample data groups.

[0033] [Figure 4A] FIG. 4A is a diagram of one embodiment of a system to illustrate control of an RF generator and / or an impedance matching network based on compressed data.

[0034] [Figure 4B] FIG. 4B is a diagram of one embodiment of a system to illustrate control of the gap between the lower electrode and the TCP coil based on compression data.

[0035] [Figure 4C] FIG. 4C is a diagram of one embodiment of a system to illustrate compressibility data-based control of pressure and / or gas flow within a plasma chamber.

[0036] [Figure 4D] FIG. 4D is a diagram of one embodiment of a system to illustrate compressed data-based control of temperature in a plasma chamber.

[0037] [Figure 5] FIG. 5 is a diagram of one embodiment of a system to illustrate the details of a matchless plasma source. DETAILED DESCRIPTION OF THE INVENTION

[0038] In the following embodiments, systems and methods for sensor data compression in plasma tools are described. It will be apparent that the embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail in order to not unnecessarily obscure the embodiments.

[0039] FIG. 1A is a diagram of one embodiment of a system 100 to illustrate a data compression unit (DCU) 132. Plasma systems such as the system 100 may be referred to herein as plasma tools. The system 100 includes a radio frequency (RF) generator (RFG) 109, a match 111, a plasma chamber 113, an RF sensor 106, a compression integrated system (DIS) 128, an analysis controller 114, and a process controller 116. The plasma chamber 113 includes an electrode 115, such as a transformer-coupled plasma (TCP) coil or a lower electrode of a substrate support. An example of a substrate support is a chuck. The DIS 128 includes an analog-to-digital converter (ADC) 130, a DCU 132, and a data transmitter (Xmit) 134. The analysis controller 114 includes a processor 101, a memory device 103, and a data transceiver (Xcvr) 125. The process controller 116 includes a processor 105, a memory device 107, and a data transceiver 127. The system 100 further includes an RF cable 124 and an RF transmission line 126.

[0040] Examples of RF generators as used herein include an RF generator having an operating frequency of 100 kilohertz (kHz), or an RF generator having an operating frequency of 400 kHz, or an RF generator having an operating frequency of 1 to 2 megahertz (MHz), or an RF generator having an operating frequency of 13.56 MHz, or an RF generator having an operating frequency of 27 MHz, or an RF generator having an operating frequency of 60 MHz.

[0041] As used herein, examples of a match include an impedance matching network or an impedance matching circuit. For example, a match includes a network of electrical circuit components, such as one or more capacitors, one or more inductors, one or more resistors, or a combination thereof, connected to each other. Illustratively, a match includes multiple shunt capacitors, multiple series capacitors, and inductors. As another example, in a match, any two of the electrical components are connected to each other in series or parallel.

[0042] Examples of plasma chambers used herein include capacitively coupled plasma (CCP) chambers or inductively coupled plasma (ICP) chambers. Examples of electrodes used herein include the lower electrode of a chuck, or the upper electrode, or the RF coil, or the TCP coil.

[0043] Examples of RF sensors used herein include complex voltage-current (VI) probes, directional couplers, complex current sensors, complex voltage sensors, and impedance sensors. A complex VI probe measures complex voltage-current, including the magnitude of the voltage, the magnitude of the current, and the phase between the voltage and the current. A complex current sensor measures complex current, including the magnitude and phase of the current. A complex voltage sensor measures complex voltage, including the magnitude and phase of the voltage. A directional coupler is an example of a power sensor that measures source power and reflected power. In this specification, reflected power may be referred to as reverse power, and source power may be referred to as forward power. Source power is the power of the RF signal 118 generated by the RF generator 109 and supplied to the match 111. Reflected power is the power of the RF signal 120 reflected from the plasma chamber 113 back to the RF generator 109 via the RF transmission line 126, the match 111, and the RF cable 124. An example of a voltage sensor is a phase magnet. A phase magnet measures the magnitude and phase of the voltage.

[0044] Examples of RF transmission lines used herein include an RF cylinder and one or more RF straps that couple an RF rod to the RF cylinder. The RF cylinder is a part of the RF transmission line. An RF transmission line with an RF cylinder is used when the RF transmission line couples a match to a lower electrode. In this example, the RF rod of the RF transmission line is surrounded by an insulating material, which is then surrounded by an RF sheath of the RF transmission line. Other examples of RF transmission lines include an RF rod and an RF strap. In this example, the RF rod of the RF transmission line is surrounded by an insulating material, which is then surrounded by an RF sheath of the RF transmission line. RF transmission lines do not include RF cylinders. RF transmission lines other than an RF cylinder are used when coupling a match to an upper electrode, a TCP coil, or an RF coil. Some RF straps couple the RF rod to the match, and other RF straps couple the RF rod to a TCP coil or an RF coil. Yet another example of an RF transmission line is an RF rod and an RF sheath. In this example, the RF rod of the RF transmission line is surrounded by an insulating material, which is then surrounded by an RF sheath.

[0045] Examples of the DIS 128 include an application-specific integrated circuit (ASIC) or a programmable logic device (PLD), which may be a field-programmable gate array (FPGA). For example, the ADC 130, the DCU 132, and the data transmitter 134 are each programmable logic blocks. As another example, the DCU 132 is made up of multiple logic gates interconnected via programmable switches. As yet another example, the ADC 130, the DCU 132, and the data transmitter 134 are each a processor or microcontroller. Examples of the data transmitter 134 include a universal asynchronous receiver-transmitter (UART), a parallel data transmitter, an Ethernet device, and a universal serial bus (USB) communication device. A UART transmits data serially (e.g., one bit at a time). A parallel data transmitter transmits data in parallel (e.g., multiple bits simultaneously). A USB communication device applies the USB protocol to data before transmitting the data. An Ethernet device applies the Ethernet protocol to data before transmitting the data. An Ethernet protocol is applied to generate data packets from the data.

[0046] Examples of data transceivers used herein include UARTs, parallel data transceivers, Ethernet transceivers, and USB communication devices. UARTs transmit or receive data in a serial manner. Parallel data transceivers transmit or receive data in a parallel manner. USB communication devices apply the USB protocol to data to generate data packets and then transmit the data, or receive data packets and apply the USB protocol to the data packets to extract the data from the data packets. Ethernet transceivers apply the Ethernet protocol to data to generate data packets and then transmit the data, and apply the Ethernet protocol to received data packets to extract the data from the data packets.

[0047] Examples of processors include central processing units (CPUs), controllers, microcontrollers, microprocessors, ASICs, and PLDs. Examples of memory devices used herein include read-only memory (ROM) and random access memory (RAM). Illustratively, memory devices used herein are flash memory or redundant arrays of independent disks.

[0048] RF generator 109 has an output 117 that is coupled to an input 119 of match 111 via RF cable 124, and an output 121 of match 111 is coupled to electrode 115 via RF transmission line 126. RF transmission line 126 couples output 121 of match 111 to input 143 of electrode 115. RF path 108 includes RF cable 124, match 111, and RF transmission line 126. RF path 108 extends from output 117 of RF generator 109 to input 143 of electrode 115.

[0049] The RF sensor 106 is coupled at any point on the RF path 108. For example, the RF sensor 106 is coupled to the output 117 of the RF generator 109, or the input 119 of the match 111, or a point 123 on the RF cable 124, or the output 121 of the match, or a point on the RF transmission line 126, or to an electrical circuit component of the match 111. Illustratively, the RF cable 124 runs from an input port of a directional coupler, through a channel in the directional coupler, to an output port of the directional coupler. As another example, the RF cable 124 runs from an input port of a VI probe, through a channel in the VI probe, to an output port of the VI probe.

[0050] The RF sensor 106 has two measurement ports 129 and 131 coupled to an ADC 130. The ADC 130 is coupled to a DCU 132, which is coupled to a data transmitter 134. The data transmitter 134 is coupled to a data transceiver 125 via a transfer cable 129. Examples of transfer cables used herein include a serial transfer cable, a parallel transfer cable, or a USB cable. The data transceiver 125 is coupled to a processor 101, which is coupled to a memory device 103. The data transceiver 125 is coupled to a data transceiver 127, which is coupled to the processor 105, via a transfer cable 131. The data transceiver 125 is also coupled to an RF generator via a transfer cable 133. The processor 105 is coupled to the memory device 107.

[0051] The RF generator 109 generates an RF signal 118 and provides the RF signal from output 117 to input 119 of match 111 via RF cable 124. Match 111 receives the RF signal 118 and matches the impedance of a load coupled to output 121 with the impedance of a source coupled to input 119 to provide a modified RF signal 122 at the output. Examples of loads include an RF transmission line 126 and a plasma chamber 113, and examples of sources include the RF generator 109 and RF cable 124. When the modified RF signal 122 is provided to the electrode 115 and one or more process gases are provided to the plasma chamber 113, a plasma is struck or maintained in the plasma chamber 113 to process a substrate in the plasma chamber 113. Examples of the one or more process gases include hydrocarbon gases (e.g., C X H Y ), hydrogen fluoride gas (e.g., C X F Y ), oxygen-containing gases (e.g., O), nitrogen-containing gases (e.g., N, NH), and inert gases (e.g., He, Ar). The substrate can be a semiconductor wafer or a substrate stack.

[0052] The RF sensor 106 receives the RF signals 118 and 120, measures one or more parameters, such as forward reflected power, impedance, voltage, complex voltage-current, or complex current, and outputs a measurement signal 102 and another measurement signal 104. Complex parameters include magnitude and phase. For example, a complex voltage includes the voltage magnitude and the voltage phase, and a complex current includes the current magnitude and the current phase. Another example of a complex voltage-current is the voltage magnitude, the current magnitude, and the phase difference between the complex voltage and the complex current.

[0053] Measurement signal 102 is an example of a master measurement signal, and measurement signal 104 is an example of a slave measurement signal. Each measurement signal described herein is an electrical signal. RF signal 118 is an example of a master RF signal, and RF signal 120 is an example of a slave RF signal. An example of measurement signal 102 is an analog signal indicative of the RF power of RF signal 118, and an example of measurement signal 104 is an analog signal indicative of the RF power of RF signal 120. For example, measurement signal 102 indicates the delivered power, and measurement signal 104 indicates the reflected power. Measurement signal 102 is sent from port 129 of the RF sensor to ADC 130, and measurement signal 104 is sent from port 131 of RF sensor 106 to ADC 130.

[0054] The ADC 130 receives the measurement signals 102 and 104 and converts each of the measurement signals 102 and 104 from analog to digital format. For example, the ADC 130 samples a parameter, such as delivered power, from the measurement signal 102 and outputs sample data 110-1 to the DCU 132, and samples a parameter, such as reflected power, from the measurement signal 104 and outputs sample data 110-2 to the DCU 132. For example, the ADC 130 samples the parameter at a rate ranging from 5.5 nanoseconds (ns) to 6.8 ns. As another example, the ADC 130 samples the parameter at a rate ranging from 600 picoseconds (ps) to 900 ps. For further example, the ADC 130 samples the parameter at a rate of 6.4 nanoseconds (ns) or 800 picoseconds (ps). An example of the sample data 110-1 or the sample data 110-2 is 128 samples. For example, each sample of sample data 110-1 or sample data 110-2 is a measurement of a parameter and can be represented by a number of bits, such as 2 bits, 4 bits, or 1 byte. Other examples of sample data 110-1 or sample data 110-2 include 128 samples, 256 samples, 512 samples, 1024 samples, 2048 samples, or an even larger number of samples. As another example, ADC 130 samples the parameters from measurement signals 102 and 104 in synchronization with a clock signal, described further below. For example, the parameters are sampled from measurement signals 102 and 104 during the same clock cycle or the same number of clock cycles of the clock signal. For further example, the parameters are sampled from measurement signals 102 and 104 during clock cycles 1 through 8 or clock cycles 1 through N (where N is an integer greater than 0) of the clock signal.

[0055] DCU 132 processes sample data 110-1 and 110-2 to output compressed data 135, which is provided to data transmitter 134. Compressed data 135 may be referred to herein as reduced data. The number of samples in compressed data 135 is substantially fewer than the number of samples in sample data 110-1 or sample data 110-2. For example, the number of samples in compressed data 135 is 64 times fewer than the number of samples in sample data 110-1 and 110-2. For example, if the number of samples in sample data 110-1 and 110-2 is 256, the number of samples in compressed data 135 is 4.

[0056] The data transmitter 125 outputs a data unit 112 containing compressed data 135 by applying a transfer protocol such as a serial transfer protocol, a parallel transfer protocol, or a USB protocol, and transmits the data unit 112 to the data transmitter 125 via a transfer cable 129. The serial transfer protocol is applied to transfer the compressed data 135 in a serial manner. For example, each byte of the compressed data 135 is converted or divided into bits, and the bits are transferred serially one at a time. The parallel transfer protocol is applied to transfer the compressed data 135 in a parallel manner. For example, each byte of the compressed data 135 is converted or divided into bits, and the bits are transferred multiple times at a time. The USB protocol is applied to generate data packets from the compressed data 135 and transfer the data packets.

[0057] The data transceiver 125 receives the data units 112 and applies a transfer protocol to the data units 112 to extract compressed data 135 from the data units 112. For example, the compressed data 135 may be extracted by converting the bits received in a serial or parallel manner into bytes. As another example, data packets may be converted into bytes of compressed data 135. The data transceiver 125 provides the compressed data 135 to the processor 101, which can store (e.g., write) the compressed data 135 to the memory device 103.

[0058] The processor 101 retrieves compressed data 135 from the memory device 103 and transmits the compressed data 135 to the data transceiver 135. For example, upon receiving a request from the processor 105 via the data transceiver 127, the transmission cable 131, and the data transceiver 125, the processor 101 reads the compressed data 135 from the memory device 103. The data transceiver 135 applies a transmission protocol to the compressed data 135 to generate data units 137 and transmits the data units 137 to the data transceiver 127 via the transmission cable 131. The data transceiver 127 applies a transmission protocol to the data units 137 to extract the compressed data 135 from the data units 137 and provides the compressed data 135 to the processor 105. The processor 105 stores the compressed data 135 in the memory device 107.

[0059] In one embodiment, the DIS 128 does not need to store the sample data 110-1 and 110-2 after generating the compressed data 135. For example, the DIS 128 deletes the sample data 110-1 and 110-2 from a buffer, such as a ring buffer, used to store the sample data 110-1 and 110-2 after using the sample data 110-1 and 110-2 to generate the compressed data 135. As another example, each of the measurement signals 102 and 104 may be continuously converted from analog to digital format to output the sample data 110-1 and 110-2, which may be continuously processed by the DCU 132 to generate the compressed data 135.

[0060] In one embodiment, the sample data 110-1 and 110-2 that generated the compressed data 135 are not stored in a memory device after the compressed data 135 is generated. Thus, the sample data 110-1 and 110-2 are decimated or otherwise unavailable for subsequent use. For example, the DCU 132 does not include a buffer or memory device for storing the sample data 110-1 and 110-2 after the compressed data 135 is generated. As another example, the sample data 110-1 and 110-2 are decimated if they are not stored in a memory device after processing the sample data 110-1 and 110-2 to generate the compressed data 135.

[0061] In one embodiment, sample data 110-1 is output from ADC 130 to DCU 132 via one channel, and sample data 110-2 is output from ADC 130 to DCU 132 via another channel. Examples of the channel include a conductor, a via, a metal link, or a metal path. Sample data 110-1 and 110-2 are output from ADC 130 to DCU 132 synchronously. For example, sample data 110-1 and 110-2 are output from ADC 130 to DCU 132 synchronously with a clock signal, which will be described later. For example, sample data 110-1 and 110-2 are output from ADC 130 to DCU 132 during the same clock cycle of the clock signal or during a predetermined clock cycle, such as N clock cycles of the clock signal.

[0062] In one embodiment, the process controller 116 is coupled to the analysis controller 114 via a computer network, such as a wide area network (WAN) or a local area network (LAN), or a combination thereof. An example of a WAN is the Internet, and an example of a LAN is an intranet. For example, all communication between the process controller 116 and the analysis controller 114 occurs through a network communication device of the analysis controller 114 and a network communication device of the process controller 116. An example of a network communication device is a network interface controller, such as a network interface card (NIC). The processor 101 is coupled to the network communication device of the analysis controller 114, and the processor 105 is coupled to the network communication device of the process controller 116. As an example, all communication between the network communication devices described herein occurs using a communication protocol, such as the Internet Protocol (IP) or Transmission Control Protocol (TCP) over IP.

[0063] In one embodiment, each RF generator described herein and the DIS 128 are coupled to the processor 101 of the analysis controller 114 via multiple network communication devices and a computer network. For example, the network communication device of the analysis controller 114 is coupled to the network communication device of the RF generator described herein via a computer network. The network communication device of the analysis controller 114 is also coupled to the network communication device of the DIS 128 via a computer network. The processor 101 of the analysis controller 114 is coupled to the network communication device of the analysis controller 114, and a controller, such as a digital signal processor and a memory device, within the RF generator is coupled to the network communication device of the RF generator. The digital signal processor is coupled to the memory device of the RF generator. As used herein, each RF generator includes a controller coupled to an RF power source, such as an electronic oscillator of the RF generator. The RF power source generates an RF signal. The DCU 130 of the DIS 128 is coupled to the network communication device of the DIS 128.

[0064] In one embodiment, the RF sensor 106 is integrated within the RF generator 109. For example, the RF sensor 106 is a component of the RF generator 109. As another example, the RF sensor 106 is located within a housing or enclosure of the RF generator 109.

[0065] In one embodiment, the RF sensor 106 is integrated within the match 111. For example, the RF sensor 106 is a component of the match 111. As another example, the RF sensor 106 is located within a housing or enclosure of the match 111.

[0066] In one embodiment, a moving average processor, such as a moving average filter, is coupled between ADC 130 and DCU 132. The moving average processor calculates a moving average from sample data output from ADC 130. The sample data is output from ADC 130 based on a measurement signal, such as measurement signal 118 or 120. For example, the moving average processor calculates a moving average from a predetermined time block. The moving average processor calculates a moving average to provide moving average data, which is sampled by ADC 130 to output sample data, such as sample data 110-1 or 110-2.

[0067] 1B is a diagram of an embodiment of system 139 to illustrate the use of multiple RF sensors 106A and 106B instead of RF sensor 106. Plasma systems such as system 139 may be referred to herein as plasma tools. System 139 is the same as system 100 of FIG. 1A except that system 139 includes RF sensors 106A and 106B instead of RF sensor 106. Examples of RF sensors 106A and 106B are described above. RF sensor 106A is coupled to point 123 between output 117 and input 119.

[0068] RF sensor 106B is coupled at point 141 on RF transmission line 126. For example, the RF rod of RF transmission line 126 passes from the input port of RF sensor 106B through a channel in RF sensor 106B to the output port of RF sensor 106B. Point 141 is located between output 121 and electrode 115.

[0069] RF sensor 106A measures a parameter, such as a complex voltage, at point 123 and outputs measurement signal 102 to ADC 130. Additionally, RF sensor 106B measures a parameter, such as a complex voltage, at point 141 and outputs measurement signal 104 to ADC 130.

[0070] In one embodiment, RF sensor 106B is coupled to output 121 or any other point on RF transmission line 126. For example, RF sensor 106B is coupled to a cylinder or RF strap of RF transmission line 126.

[0071] In one embodiment, the RF sensor 106A is integrated within the RF generator 109 or within the match 111. For example, the RF sensor 106A is a component of the RF generator 109 or the match 111. As another example, the RF sensor 106A is located within the housing or enclosure of the RF generator 109 or the housing or enclosure of the match 111.

[0072] In one embodiment, the RF sensor 106B is integrated within the match 111. For example, the RF sensor 106B is a component of the match 111. As another example, the RF sensor 106B is located within the housing or enclosure of the match 111.

[0073] FIG. 1C-1 is a diagram of one embodiment of a system 150 for illustrating generation of measurement signals 102A, 102B, 102C, and 102D for provision to an ADC 130. Each of measurement signals 102A-102D is an example of a master measurement signal. A plasma system such as system 150 may be referred to herein as a plasma tool. System 150 includes RF generator 109A, RF generator 109B, RF generator 109C, RF generator 109D, RF sensor 106A, RF sensor 106B, RF sensor 106C, RF sensor 106D, match 111A, another match 111B, DIS 128, and a plasma chamber 152.

[0074] The plasma chamber 152 is a TCP plasma chamber having a TCP coil 156 and a dielectric window 160. The TCP coil 156 is disposed above the dielectric window 160. The plasma chamber 152 further includes a lower electrode 154 on which a substrate S is placed for processing.

[0075] An output 117 of RF generator 109A is coupled to an input 119A of match 111A via an RF cable 124A, and an output 151 of RF generator 109B is coupled to another input 119B of match 111A via another RF cable 124B. An output 121A of match 111A is coupled to an input 159 of TCP coil 156 via an RF transmission line 158. One example of an RF transmission line 158 is an RF rod surrounded by an insulator which is surrounded by an RF sheath.

[0076] Similarly, an output 153 of RF generator 109C is coupled to an input 119C of match 111B via RF cable 124C, and an output 155 of RF generator 109C is coupled to another input 119D of match 111B via another RF cable 124D. An output 121B of match 111B is coupled to an input 143 of lower electrode 154 via RF transmission line 126. RF sensors 106A-106D are coupled to ADC 130.

[0077] RF sensor 106A is coupled at point 123A on RF cable 124A. For example, RF cable 124A runs from the input port of a directional coupler through a channel within the directional coupler to the output port of the directional coupler. Similarly, RF sensor 106B is coupled at point 123B on RF cable 124B, RF sensor 106C is coupled at point 123C on RF cable 124C, and RF sensor 106D is coupled at point 123D on RF cable 124D. For example, RF cable 124B runs from the input port of RF sensor 106B through a channel within RF sensor 106B to the output port of RF sensor 106B, RF cable 124C runs from the input port of RF sensor 106C through a channel within RF sensor 106C to the output port of RF sensor 106C, and RF cable 124D runs from the input port of RF sensor 106D through a channel within RF sensor 106D to the output port of RF sensor 106D.

[0078] An RF path includes RF generator 109A, RF cable 124A, match 111A, and RF transmission line 158 and extends from output 117 of RF generator 109A to input 159 of TCP coil 156. Another RF path includes RF generator 109B, RF cable 124B, match 111A, and RF transmission line 158 and extends from output 151 of RF generator 109B to input 159 of TCP coil 156. Yet another RF path includes RF generator 109C, RF cable 124C, match 111B, and RF transmission line 126 and extends from output 153 of RF generator 109C to input 143 of lower electrode 154. Another RF path includes RF generator 109D, RF cable 124D, match 111B, and RF transmission line 126 and extends from output 155 of RF generator 109D to input 143 of lower electrode 154.

[0079] RF generator 109A generates RF signal 118A and provides it to input 119A of match 111A via RF cable 124A. RF generator 109B generates RF signal 118B and provides it to input 119B of match 111A via RF cable 124B. Match 111A receives RF signals 118A and 118B and matches the impedance of a load coupled to output 121A with the impedance of a source coupled to inputs 119A and 119B to provide modified RF signal 122A at output 121A. Examples of sources coupled to inputs 119A and 119B include RF cables 124A and 124B and RF generators 109A and 109B. Examples of loads coupled to output 121A include RF transmission line 158 and plasma chamber 152. The modified RF signal 122B is supplied to the TCP coil 156 via an RF transmission line 158 .

[0080] Similarly, RF generator 109C generates RF signal 118C and provides it to input 119C of match 111B via RF cable 124C. RF generator 109D generates RF signal 118D and provides it to input 119D of match 111B via RF cable 124D. Match 111B receives RF signals 118C and 118D and matches the impedance of a load coupled to output 121B with the impedance of a source coupled to inputs 119C and 119D to provide modified RF signal 122B at output 121B. Examples of sources coupled to inputs 119C and 119D include RF cables 124C and 124D and RF generators 109C and 109D. Examples of loads coupled to output 121B include RF transmission line 126 and plasma chamber 152. The modified RF signal 122 B is provided to the lower electrode 154 via RF transmission line 126 .

[0081] When the modified RF signals 122A and 122B are supplied to the plasma chamber 152, in addition to one or more process gases, a plasma is generated or maintained in the plasma chamber 152 to process the substrate S. Furthermore, when the modified RF signals 122A and 122B are supplied to the plasma chamber 152, the RF signal 120A is reflected from the plasma chamber 152 through the RF transmission line 158 and the match 111A and the RF cable 124A towards the RF generator 109a. Similarly, RF signal 120B is reflected from plasma chamber 152 via RF transmission line 158, match 111A, and RF cable 124B toward RF generator 109B, RF signal 120C is reflected from plasma chamber 152 via RF transmission line 126, match 111B, and RF cable 124C toward RF generator 109C, and RF signal 120D is reflected from plasma chamber 152 via RF transmission line 126, match 111D, and RF cable 124D toward RF generator 109D. Each of RF signals 118A, 118B, 118C, and 118D is an example of a master RF signal, and each of RF signals 120A to 120D is an example of a slave RF signal.

[0082] During processing of substrate S, each of RF sensors 106A-106D senses a parameter and outputs a plurality of measurement signals. For example, RF sensor 106A senses a parameter at point 123A, outputs measurement signal 102A, and provides measurement signal 102A to ADC 130, while RF sensor 106B senses a parameter at point 123B, outputs measurement signal 102B, and provides measurement signal 102B to ADC 130. For example, RF sensor 106A senses the supplied power of RF signal 118A, and RF sensor 106B senses the supplied power of RF signal 118B. As another example, RF sensor 106A senses the reflected power of RF signal 120A, and RF sensor 106B senses the reflected power of RF signal 120B. As yet another example, RF sensor 106A senses the supplied power of RF signal 118A, and RF sensor 106B senses the reflected power of RF signal 120B. As another example, RF sensor 106A senses the reflected power of RF signal 120A, and RF sensor 106B senses the supplied power of RF signal 118B.

[0083] Similarly, RF sensor 106C senses a parameter at point 123C and outputs measurement signal 102C, providing this measurement signal 102C to ADC 130, and RF sensor 106D senses a parameter at point 123D and outputs measurement signal 102D, providing this measurement signal 102D to ADC 130. Illustratively, RF sensor 106C senses the supplied power of RF signal 118C, and RF sensor 106D senses the supplied power of RF signal 118D.

[0084] RF sensors 106A-106D measure parameters such as reflected power to generate additional measurement signals 104A, 104B, 104C, and 104D in addition to measurement signals 102A-102D. For example, RF sensor 106A senses the reflected power of RF signal 120A, outputs measurement signal 104A based on the reflected power, and provides measurement signal 104A to ADC 130. RF sensor 106B senses the reflected power of RF signal 120B, outputs measurement signal 104B based on the reflected power, and provides measurement signal 104B to ADC 130. As another example, RF sensor 106C senses the reflected power of RF signal 120C, outputs measurement signal 104C based on the reflected power, and provides this measurement signal 104C to ADC 130, and RF sensor 106D senses the reflected power of RF signal 120D, outputs measurement signal 104D based on the reflected power, and provides this measurement signal 104D to ADC 130. Each of measurement signals 104a to 104d is an example of a slave measurement signal.

[0085] The ADC 130 converts each of the measurement signals 102A, 104A, 102B, and 104B from analog to digital format and samples the measurement signals. For example, the ADC 130 samples the measurement signal 102A to output sample data 110A-1, and samples the measurement signal 104A to output sample data 110A-2. An example of the sample data 110A-1 or 110A-2 is 128 samples, 256 samples, or 512 samples. For example, each sample of the sample data 110A-1 or 110A-2 is a measurement value of a parameter and can be represented by a number of bits, such as 2 bits, 4 bits, or 1 byte. Similarly, the ADC 130 samples the measurement signal 102B to output sample data 110B-1, and samples the measurement signal 104B to output sample data 110B-2.

[0086] The ADC 130 also converts each of the measurement signals 102C, 104C, 102D, and 104D from analog to digital format and samples the measurement signals. For example, the ADC 130 samples the measurement signal 102C to output sample data 110C-1, samples the measurement signal 104C to output sample data 110C-2, samples the measurement signal 102D to output sample data 110D-1, and samples the measurement signal 104D to output sample data 110D-2. An example of the sample data 110C-1 or 110C-2 is 128 samples, 256 samples, or 512 samples. For example, each sample of the sample data 110C-1 or 110C-2 is a measurement value of a parameter and can be represented by a number of bits, such as 2 bits, 4 bits, or 1 byte.

[0087] DCU 132 processes sample data 110A-1 and 110A-2 to provide at its output compressed data 135A, processes sample data 110B-1 and 110B-2 to provide at its output compressed data 135B, processes sample data 110C-1 and 110C-2 to provide at its output compressed data 135C, and processes sample data 110D-1 and 110D-2 to provide at its output compressed data 135D. For example, DCU 132 processes sample data 110A-1 and 110A-2 to compress them from 256 samples to 4 or 8 samples, and processes sample data 110B-1 and 110B-2 to compress them from 256 samples to 4 or 8 samples.

[0088] DCU 132 transmits compressed data 135A, 135B, 135C, and 135D to data transmitter 134. Data transmitter 134 sends compressed data 135A, 135B, 135C, and 135D to processor 101 (FIG. 1A) for processing.

[0089] In one embodiment, multiple TCP coils, such as two or three TCP coils, are positioned above the dielectric window 160. In some embodiments, in addition to the TCP coil 156 positioned above the dielectric window 160, one or more TCP coils are positioned to the side of the plasma chamber 152.

[0090] In one embodiment, RF sensor 106A or RF sensor 106B is coupled at a point on RF transmission line 158. For example, an RF rod of RF transmission line 158 is coupled to an input port of RF sensor 106B, passes from the input port through RF sensor 106B, and is coupled to an output port of RF sensor 106B. An RF rod of RF transmission line 158 is coupled from the output port of RF sensor 106B to TCP coil 156.

[0091] In one embodiment, two or more RF generators are coupled to a match (not shown) used in place of match 111B. This match has three inputs instead of two inputs 119C and 119D. For example, three RF generators are coupled to a match having three inputs. The three RF generators include RF generators 109C and 109D and a third RF generator. The three inputs include two inputs similar to inputs 124C and 124D and a third input. In this embodiment, the RF sensor is coupled to a point on an RF cable coupled between the third RF generator and the three-input match. The RF cable is coupled to the third RF generator and the third input of the match. RF generators 109C and 109D are coupled to two inputs of the match.

[0092] In one embodiment, sample data 110A-1 and sample data 110A-2, from which compressed data 135A was generated, are not stored in a memory device after compressed data 135A was generated. For example, DCU 132 does not include a buffer or memory device for storing sample data 110A-1 and 110A-2 after compressed data 135A is generated. As another example, if sample data 110A-1 and 110A-2 are not stored in a memory device after processing sample data 110A-1 and 110A-2 to generate compressed data 135A, sample data 110A-1 and 110A-2 are compressed.

[0093] In one embodiment, the sample data 110B-1 and sample data 110B-2 used to generate compressed data 135B are not stored in a memory device after generating compressed data 135B. For example, DCU 132 does not include a buffer or memory device for storing sample data 110B-1 and 110B-2 after generating compressed data 135B. As another example, if sample data 110B-1 and 110B-2 are not stored in a memory device after processing sample data 110B-1 and 110B-2 to generate compressed data 135B, then sample data 110B-1 and 110B-2 are compressed.

[0094] In one embodiment, the sample data 110C-1 and sample data 110C-2 that generated the compressed data 135C are not stored in a memory device after generating the compressed data 135C. For example, the DCU 132 does not include a buffer or memory device for storing the sample data 110C-1 and 110C-2 after generating the compressed data 135C. As another example, the sample data 110C-1 and 110C-2 are compressed if they are not stored in a memory device after processing the sample data 110C-1 and 110C-2 to generate the compressed data 135C.

[0095] In one embodiment, the sample data 110D-1 and sample data 110D-2 used to generate compressed data 135D are not stored in a memory device after generating compressed data 135D. For example, DCU 132 does not include a buffer or memory device for storing sample data 110D-1 and 110D-2 after generating compressed data 135D. As another example, if sample data 110D-1 and 110D-2 are not stored in a memory device after processing sample data 110D-1 and 110D-2 to generate compressed data 135D, then sample data 110D-1 and 110D-2 are compressed.

[0096] In one embodiment, the RF sensor 106A is integrated within the RF generator 109A or the match 111A. For example, the RF sensor 106A is a component of the RF generator 109A or the match 111A. As another example, the RF sensor 106A is located within the housing or enclosure of the RF generator 109A or the housing or enclosure of the match 111A.

[0097] In one embodiment, the RF sensor 106B is integrated within the RF generator 109B or the match 111B. For example, the RF sensor 106B is a component of the RF generator 109B or the match 111B. As another example, the RF sensor 106B is located within the housing or enclosure of the RF generator 109B or the housing or enclosure of the match 111B.

[0098] In one embodiment, RF sensor 106C is integrated within RF generator 109C or within match 111B. For example, RF sensor 106C is a component of RF generator 109C or match 111B. As another example, RF sensor 106C is disposed within a housing or enclosure of RF generator 109C or a housing or enclosure of match 111B. In one embodiment, RF sensor 106D is integrated within RF generator 109D or within match 111B. For example, RF sensor 106D is a component of RF generator 109D or match 111B. As another example, RF sensor 106D is disposed within a housing or enclosure of RF generator 109D or a housing or enclosure of match 111B.

[0099] 1C-2 is a diagram of one embodiment of system 145 to illustrate the use of RF sensor 147 in match 111A. System 145 has the same components as system 150 (FIG. 1C-1), except that system 145 further includes RF sensor 147.

[0100] RF sensor 147 is located within the housing of match 111A. For example, match 111A includes a first branch circuit coupled between input 119A and output 121A and a second branch circuit coupled between input 119B and output 121A. The first branch circuit is coupled to the second branch circuit at a connection point between output 121A and inputs 119A and 119B. RF sensor 147 is coupled to the connection point, output 121A, or a point between the connection point and output 121A.

[0101] The RF sensor 147 is coupled to the ADC 130. During processing of the substrate S, the RF sensor 147 senses a parameter and generates a measurement signal 102D-1 and another measurement signal 104D-1. The ADC 130 converts each of the measurement signals 102D-1 and 104D-1 from analog to digital format and samples the measurement signals. For example, the ADC 130 samples the measurement signal 102D-1 to output sample data 149A and samples the measurement signal 104D-1 to output sample data 149B.

[0102] DCU 132 processes sample data 149A and 149B and provides at its output compressed data 157. For example, DCU 132 processes sample data 149A and 149B to compress them from 256 samples to 8 samples or 4 samples.

[0103] DCU 132 sends compressed data 157 to data transmitter 134. Data transmitter 134 sends compressed data 157 to processor 101 (FIG. 1A) for processing.

[0104] In one embodiment, instead of processing compressed data 157, processor 101 sends compressed data 157 to processor 105 for processing.

[0105] In one embodiment, instead of being located within the match 111A, the RF sensor 147 is coupled to a point on the RF transmission line 158. For example, the RF sensor 147 is coupled to an RF rod of the RF transmission line 158.

[0106] It should be noted that in one embodiment of the present disclosure, all RF sensors described herein are omnidirectional sensors that sense parameters in both forward and reverse directions, or both forward and reflected directions. By way of example, RF sensor 106A transmits both forward and reflected power. It senses forward power and outputs measurement signal 102A, and senses reflected power and outputs measurement signal 102B. In some embodiments, a directional RF sensor can be used in place of any of the omnidirectional RF sensors described herein. For example, a directional RF sensor is coupled to an RF transmission line or placed within a match. For example, RF sensor 147 can be replaced with a directional RF sensor that senses a parameter in a single direction. Further by way of example, a directional RF sensor senses either forward power or reflected power, but not both, and outputs a single measurement signal. As another example, a directional sensor senses the magnitude of a parameter and the phase of the parameter. As another example, a directional sensor measures the phase of an RF signal generated by a source. In this example, the RF signal is supplied from the source to a load, such as a plasma chamber. In this example, the source is an RF generator. As yet another example, a directional sensor measures the phase of an RF signal reflected from a load. In this example, the signal reflects from a load, such as a plasma chamber. The signal reflects back toward a source, such as an RF generator.

[0107] 1D is a diagram of an embodiment of system 162 to illustrate the use of DIS 128 with RF sensors 106A and 106B coupled to different matches 111 and 164. Plasma systems such as system 162 may be referred to herein as plasma tools. System 162 includes RF generators 109A-109D, RF sensors 106A-106D, matches 111, 164, 111B, a plasma chamber 168, and DIS 128. System 162 is similar to system 150 of FIG. 1C-1 except that system 162 includes match 164 coupled to TCP coil 156B of plasma chamber 168 via RF transmission line 166.

[0108] The plasma chamber 168 has a TCP coil 156A, a TCP coil 156B, and a dielectric window 160. The TCP coil 156B is an outer coil, and the TCP coil 156A is an inner TCP coil. The TCP coil 156B has a larger diameter than the TCP coil 156A. For example, each turn of the TCP coil 156B has a larger diameter than each turn of the TCP coil 156A. The TCP coils 156A and 156B are disposed above the dielectric window 160.

[0109] RF generator 109A is coupled to input 119 of match 111 via RF cable 124A, and output 121 of match 111 is coupled to input 159 of TCP coil 156A via RF transmission line 158. RF generator 109B is also coupled to input 170 of match 172 via RF cable 124B, and output 172 of match 172 is coupled to input 161 of TCP coil 156B via RF transmission line 166. RF sensor 106A is coupled at point 123A on RF cable 124A, and RF sensor 106B is coupled at point 123B on RF cable 124B.

[0110] An RF path includes RF generator 109A, RF cable 124A, match 111, and RF transmission line 158 and extends from output 117 of RF generator 109A to input 159 of TCP coil 156A. Another RF path includes RF generator 109B, RF cable 124B, match 164, and RF transmission line 166 and extends from output 151 of RF generator 109B to input 161 of TCP coil 156B. Yet another RF path includes RF generator 109C, RF cable 124C, match 111B, and RF transmission line 126 and extends from output 153 of RF generator 109C to input 143 of lower electrode 154. Another RF path includes RF generator 109D, RF cable 124D, match 111B, and RF transmission line 126 and extends from output 155 of RF generator 109D to input 143 of lower electrode 154.

[0111] RF generator 109A generates RF signal 118A and provides this RF signal 118A to input 119 of match 111 via RF cable 124A. Match 111 receives RF signal 118A and matches the impedance of a load coupled to output 121 with the impedance of a source coupled to input 119 to output modified RF signal 174. Examples of loads coupled to output 121 include RF transmission line 158 and plasma chamber 168. Examples of sources coupled to input 119 include RF cable 124A and RF generator 109A. When RF signal 118A is provided, a reflected RF signal 120A is reflected from plasma chamber 168 through RF transmission line 158, match 111, and RF cable 124A toward RF generator 109A.

[0112] Similarly, RF generator 109B generates RF signal 118B and provides RF signal 118B to input 170 of match 164 via RF cable 124B. Match 164 receives RF signal 118B and matches the impedance of a load coupled to output 172 with the impedance of a source coupled to input 170 to output modified RF signal 176. Examples of loads coupled to output 172 include RF transmission line 166 and plasma chamber 168. Examples of sources coupled to input 170 include RF cable 124B and RF generator 109B. When RF signal 118B is provided, reflected RF signal 120B is reflected from plasma chamber 168 back to RF generator 109B via RF transmission line 166, match 164, and RF cable 124B.

[0113] When the modified RF signals 174, 176, and 122B are supplied to the plasma chamber 168 and one or more process gases are supplied to the plasma chamber 168, a plasma is struck or maintained in the plasma chamber 168 to process a substrate S placed on the lower electrode 154 of the plasma chamber 168. Furthermore, when the modified RF signals 174, 176, and 122B are supplied to the plasma chamber 168, an RF signal 120A is reflected from the plasma chamber 168 to an RF generator 109A via an RF transmission line 158 and a match 111. Furthermore, when the modified RF signals 174, 176, and 122B are supplied to the plasma chamber 168, an RF signal 120B is reflected from the plasma chamber 168 to an RF generator 109B via an RF transmission line 166 and a match 164. Each of the RF signals 118A to 118D is an example of a master RF signal, and each of the RF signals 120A to 120D is an example of a slave RF signal.

[0114] Each of the RF sensors 106A-106D senses a parameter and outputs a plurality of measurement signals. For example, RF sensor 106A senses a parameter at point 123A, outputs measurement signal 102A, and provides measurement signal 102A to ADC 130, while RF sensor 106B senses a parameter at point 123B, outputs measurement signal 102B, and provides measurement signal 102B to ADC 130. For example, RF sensor 106A senses the supplied power of RF signal 118A, and RF sensor 106B senses the supplied power of RF signal 118B. As another example, RF sensor 106A senses the supplied power of RF signal 118A, and RF sensor 106B senses the reflected power of RF signal 120B. As yet another example, RF sensor 106A senses the reflected power of RF signal 120A, and RF sensor 106B senses the supplied power of RF signal 118B. As another example, RF sensor 106A senses the reflected power of RF signal 120A, and RF sensor 106B senses the reflected power of RF signal 120B.

[0115] In addition to measurement signals 102A-102D, RF sensors 106A-106D generate measurement signals 104A, 104B, 104C, and 104D by measuring parameters such as reflected power. For example, RF sensor 106A senses the reflected power of RF signal 120A, outputs measurement signal 104A based on the reflected power, and provides this measurement signal 104A to ADC 130. RF sensor 106B senses the reflected power of RF signal 120B, outputs measurement signal 104B based on the reflected power, and provides this measurement signal 104B to ADC 130.

[0116] In one embodiment, the TCP coil 156 B is positioned to the side of the plasma chamber 168 rather than above the dielectric window 160 .

[0117] In one embodiment, the RF sensor 106A is coupled at a point on the RF transmission line 158 rather than being coupled to the RF cable 124A.

[0118] In one embodiment, RF sensor 106B is coupled at a point on RF transmission line 166 rather than being coupled to RF cable 124B.

[0119] In one embodiment, the RF sensor 106A is integrated within the RF generator 109A or within the match 111. For example, the RF sensor 106A is a component of the RF generator 109A or the match 111. As another example, the RF sensor 106A is located within the housing or enclosure of the RF generator 109A or the housing or enclosure of the match 111.

[0120] In one embodiment, the RF sensor 106B is integrated within the RF generator 109B or within the match 164. For example, the RF sensor 106B is a component of the RF generator 109B or the match 164. As another example, the RF sensor 106B is located within the housing or enclosure of the RF generator 109B or the housing or enclosure of the match 164.

[0121] FIG. 1E-1 is a diagram of one embodiment of system 180 to illustrate the use of RF sensors 106E, 106F, and 106G. Plasma systems such as system 180 may be referred to herein as plasma tools. System 180 is similar to system 162 (FIG. 1D) except that it includes RF sensors 106E, 106F, and 106G in addition to RF sensors 106A-106D. RF sensor 106E is coupled at point 141A on RF transmission line 158, RF sensor 106F is coupled at point 141B on RF transmission line 166, and RF sensor 106G is coupled at point 141C on RF transmission line 126. For example, the RF rod of RF transmission line 158 is coupled to the input port of RF sensor 106E and passes from the input port through RF sensor 106E to the output port of RF sensor 106E. As another example, the RF rod of RF transmission line 166 is coupled to an input port of RF sensor 106F and passes from the input port through RF sensor 106F to an output port of RF sensor 106F. As yet another example, the RF rod of RF transmission line 126 is coupled to an input port of RF sensor 106G and passes from the input port through RF sensor 106G to an output port of RF sensor 106G.

[0122] When modified RF signals 174, 176, and 122B are supplied to plasma chamber 168, RF signals 182, 184, and 186 are reflected from plasma chamber 168. For example, RF signal 182 is reflected from plasma chamber 168 toward match 111 via RF transmission line 158. As another example, RF signal 184 is reflected from plasma chamber 168 toward match 164 via RF transmission line 166, and RF signal 186 is reflected from plasma chamber 168 toward match 111B via RF transmission line 126. Each of modified RF signals 174, 176, and 122B is an example of a master RF signal, and each of RF signals 182, 184, and 186 is an example of a slave RF signal.

[0123] During processing of the substrate S, each of the RF sensors 106E-106G senses a parameter and outputs a plurality of measurement signals. For example, RF sensor 106E senses a parameter at point 141A, outputs measurement signal 102E, and provides this measurement signal 102E to the ADC 130. RF sensor 106F senses a parameter at point 141B, outputs measurement signal 102F, and provides this measurement signal 102F to the ADC 130. RF sensor 106G senses a parameter at point 141C, outputs measurement signal 102G, and provides this measurement signal 102G to the ADC 130. For example, RF sensor 106E senses the supplied power of modified RF signal 174 and outputs measurement signal 102E, RF sensor 106F senses the supplied power of modified RF signal 176 and outputs measurement signal 102F, and RF sensor 106G senses the supplied power of modified RF signal 122B and outputs measurement signal 102G.

[0124] The RF sensors 106E-106G generate additional measurement signals 104E, 104F, and 104G in addition to the measurement signals 102E-102G by measuring parameters such as reflected power. For example, the RF sensor 106E senses the reflected power of the RF signal 182, outputs a measurement signal 104E based on the reflected power, and provides the measurement signal 104E to the ADC 130. The RF sensor 106F senses the reflected power of the RF signal 184, outputs a measurement signal 104F based on the reflected power, and provides the measurement signal 104F to the ADC 130. As another example, the RF sensor 106G senses the reflected power of the RF signal 186, outputs a measurement signal 104G based on the reflected power, and provides the measurement signal 104G to the ADC 130.

[0125] The ADC 130 converts each of the measurement signals 102E, 104E, 102F, 104F, 102G, and 104G from analog to digital format and samples the measurement signals. The ADC 130 samples the measurement signal 102E to output sample data 110E-1, and samples the measurement signal 104E to output sample data 110E-2. An example of the sample data 110E-1 or 110E-2 is 128 samples, 256 samples, or 512 samples. For example, each sample of the sample data 110E-1 or 110E-2 is a measurement value of a parameter and can be represented by a number of bits, such as 2 bits, 4 bits, or 1 byte. Similarly, measurement signal 102F is sampled to output sample data 110F-1, measurement signal 104F is sampled to output sample data 110F-2, measurement signal 102G is sampled to output sample data 110G-1, and measurement signal 104G is sampled to output sample data 110G-2. As another example, ADC 130 samples parameters from measurement signals 102A, 102B, 102C, 102D, 102E, 102F, 102G, 104A, 104B, 104C, 104D, 104E, 104F, and 104G in synchronization with a clock signal. For example, parameters may be sampled from measurement signals 102A, 102B, 102C, 102D, 102E, 102F, 102G, 104A, 104B, 104C, 104D, 104E, 104F, and 104G during the same or a same number of clock cycles of the clock signal. Further, for example, parameters may be sampled from measurement signals 102A, 102B, 102C, 102D, 102E, 102F, 102G, 104A, 104B, 104C, 104D, 104E, 104F, and 104G during 1 to 8 or 1 to N cycles of the clock signal.

[0126] DCU 132 processes sample data 110E-1 and 110E-2 to provide at its output compressed data 135E, processes sample data 110F-1 and 110F-2 to provide at its output compressed data 135F, and processes sample data 110G-1 and 110G-2 to provide at its output compressed data 135G. For example, DCU 132 processes sample data 110E-1 and 110E-2 to compress them from 256 samples to 4 or 8 samples, and processes sample data 110F-1 and 110F-2 to compress them from 256 samples to 4 or 8 samples.

[0127] DCU 132 transmits compressed data 135A-135G to data transmitter 134. Data transmitter 134 transmits compressed data 135A-135G to processor 101 (FIG. 1A) for processing.

[0128] In one embodiment, each of sample data 110A-1, 110A-2, 110B-1, 110B-2, 110C-1, 110C-2, 110D-1, 110D-2, 110E-1, 110E-2, 110F-1, 110F-2, 110G-1, and 110G-2 is output from ADC 130 via a different channel to DCU 132. For example, sample data 110A-1 is output from ADC 130 via a first channel to DCU 132, and sample data 110A-2 is output from ADC 130 via a second channel to DCU 132. The sample data 110A-1, 110A-2, 110B-1, 110B-2, 110C-1, 110C-2, 110D-1, 110D-2, 110E-1, 110E-2, 110F-1, 110F-2, 110G-1, and 110G-2 are output in synchronization from the ADC 130 to the DCU 132. For example, the sample data 110A-1, 110A-2, 110B-1, 110B-2, 110C-1, 110C-2, 110D-1, 110D-2, 110E-1, 110E-2, 110F-1, 110F-2, 110G-1, and 110G-2 are output from the ADC 130 to the DCU 132 in synchronization with the clock signal. For example, sample data 110A-1, 110A-2, 110B-1, 110B-2, 110C-1, 110C-2, 110D-1, 110D-2, 110E-1, 110E-2, 110F-1, 110F-2, 110G-1, and 110G-2 are output from ADC 130 to DCU 132 during the same clock cycle of the clock signal, or during a predetermined clock cycle, or during N clock cycles of the clock signal.

[0129] In one embodiment, the RF sensor 106E is integrated within the match 111. For example, the RF sensor 106E is a component of the match 111. As another example, the RF sensor 106E is located within the housing or enclosure of the match 111.

[0130] In one embodiment, the RF sensor 106F is integrated within the match 164. For example, the RF sensor 106F is a component of the match 164. As another example, the RF sensor 106F is located within the housing or enclosure of the match 164.

[0131] In one embodiment, the RF sensor 106G is integrated within the match 111B. For example, the RF sensor 106G is a component of the match 111B. As another example, the RF sensor 106G is located within the housing or enclosure of the match 111B.

[0132] 1E-2 is a diagram of one embodiment of a system 163 to illustrate the use of an RF sensor 106G in a plasma chamber 168. The RF sensor 106G is disposed within a housing or enclosure of the plasma chamber 168 and is coupled to an RF transmission line 126.

[0133] In one embodiment, instead of being coupled to the RF transmission line 126, the RF sensor 106G is coupled to the bottom surface of the substrate support in which the electrodes 154 are embedded. The substrate S is placed and processed on the top surface of the substrate support 169. The top surface of the substrate support 169 faces the gap between the substrate support 169 and the upper electrodes, such as RF coils 156A and 156B. The bottom surface faces in the opposite direction from the top surface.

[0134] In one embodiment, the RF sensor 106G is coupled at any point between the output 121B and the input 143 of the bottom electrode 154.

[0135] In one embodiment, in addition to providing RF sensor 106G in plasma chamber 168, an additional RF sensor is coupled to point 141C. The additional RF sensor is coupled to ADC 130.

[0136] FIG. 1F is a diagram of an embodiment of an RF sensor 190 to illustrate that the ADC 130, the DCU 132, and the data transmitter 134 are integrated within the RF sensor 190. An example of the RF sensor 190 is a PLD or an ASIC. The RF sensor 190 includes a sensing unit 192, an ADC 130, a DCU 132, and a data transmitter 134. For example, the sensing unit 192, the ADC 130, the DCU 132, and the data transmitter 134 are each logic blocks of an FPGA. An example of the sensing unit 190 is a circuit that measures a parameter and generates a measurement signal. The sensing unit 192 is coupled to the ADC 130, which is coupled to the DCU 132. The DCU 132 is coupled to the data transmitter 134.

[0137] The sensing unit 192 measures parameters and outputs a plurality of measurement signals 194, 196. Examples of the measurement signals 194 and 196 include measurement signals 102 and 104 (FIGS. 1A and 1B), or measurement signals 102A and 104A (FIG. 1C-1), or measurement signals 102B and 104B (FIG. 1C-1), or measurement signals 102C and 104C (FIG. 1C-1), or measurement signals 102D-1 and 104D-1 (FIG. 1C-2), or measurement signals 102E and 104E (FIG. 1E-1), or measurement signals 102F and 104F (FIG. 1F), or measurement signals 102G and 104G (FIG. 1G).

[0138] It should be noted that RF sensor 106 and DIS 128 (FIG. 1A) are replaced by RF sensor 190. Furthermore, RF sensor 190 is used in place of DIS 128 and any of RF sensors 106A, 106G, and 147 (FIGS. 1C-1, 1C-2, and 1E-1).

[0139] 1G is a diagram of one embodiment of a system 198 to illustrate that compressed data 135 is sent from DIS 128 to process controller 116 for processing instead of being sent to analysis controller 114 (FIG. 1A). System 198 includes DIS 128 and process controller 116. DIS 128 is coupled to data transceiver 127 via transfer cable 191.

[0140] The data unit 112 having the compressed data 135 is transmitted from the data transmitter 134 via a transfer cable 191 to the data transceiver 127. The data transceiver 127 applies a transfer protocol to the data unit 112 to extract the compressed data 135 and transmits the compressed data 135 to the processor 105. The processor 105 processes the compressed data 135 in the same manner that the processor 101 of the analysis controller 114 processes the compressed data 135. For example, the processor 105 uses the compressed data 135 to control one or more components of a plasma tool, such as systems 100, 139, 150, 162, and 180. The compressed data 135 is stored by the processor 105 in a memory device 107.

[0141] In one embodiment, each of the RF generators described herein and the DIS 128 are coupled to the processor 105 of the process controller 116 via multiple network communication devices and a computer network. For example, the network communication device of the process controller 116 is coupled to the network communication device of the RF generator described herein via a computer network. The network communication device of the process controller 116 is also coupled to the network communication device of the DIS 128 via a computer network. The processor 105 of the process controller 116 is coupled to the network communication device of the process controller 116, and a controller, such as a digital signal processor and memory device within the RF generator, is coupled to the network communication device of the RF generator.

[0142] 1H is a diagram of one embodiment of a system 171 to illustrate the use of RF sensor 106 with a matchless plasma source (MPS) 173. MPS 173 may be referred to herein as a non-50 Ω source. System 171 is the same as system 100 of FIG. 1A, except for the use of MPS 173 in system 171. There is no match between MPS 172 and plasma chamber 113. For example, there is no inductor and capacitor network between MPS 172 and plasma chamber 113 to provide a balance between the load impedance at the output of the network and the source impedance at the input of the network.

[0143] MPS 172 is coupled to electrode 115 via connection 175. An example of connection 175 is a conductor such as an RF transmission line. MPS 172 generates an RF signal 177 and transmits this RF signal 177 to electrode 155 via RF transmission line 177. RF sensor 106 senses a parameter of RF signal 177 and outputs measurement signals 102 and 104. RF path 179 includes RF transmission line 175. RF path 179 extends from an output 181 of MPS 173 to an input 143 of electrode 115.

[0144] In one embodiment, the RF sensor 106 is coupled at any point on the RF path 179. For example, the RF sensor 106 is coupled to the RF transmission line 177 at any point on the RF rod of the RF transmission line 177.

[0145] 2 is a diagram of one embodiment of DCU 132. DCU 132 includes a plurality of registers 202A, 202B, 202C, 202D, 202E, 202F, 202G, and 202H. DCU 132 further includes a master sample group generator 204 and a slave sample group generator 206. DCU 132 includes a master maximum (max) peak-to-peak (PTP) determiner 208 and a slave maximum PTP determiner 210. DCU 132 also includes a master average (Av.) frequency (Freq.) determiner 212 and an average phase determiner 216.

[0146] An example of each of the registers 202-202H is a flip-flop group. Another example of each of the registers 202A-202H is a shift register. Each of the master sample group generator tool 204, the slave sample group generator 206, the master maximum PTP determiner 208, the slave maximum PTP determiner 210, and the average phase determiner 216 can be a logic block including a logic gate group and interconnections between the logic gates.

[0147] The output of register 202A is coupled to the input of register 202B. Similarly, the output of register 202B is coupled to the input of register 202C, which is coupled to the input of register for 202D. Also, the output of register 202E is coupled to the input of register 202F, which is coupled to the input of register 202G, which is coupled to the input of register 202H.

[0148] Each register 202A and 202E is coupled to the ADC 130 (FIG. 1A). The registers 202A-202D are coupled to a master sample group generator 204, which is coupled to a master maximum PTP determiner 208 via N connections 223 (where N is an integer greater than 0). By way of example, the connections are conductors, such as wires or conductive vias, that transfer electrical signals. The master maximum PTP determiner 208 is coupled to a master average frequency determiner 212 via 2N connections 224. The master maximum PTP determiner 208 is coupled to an average phase determiner 216 via 2N connections 226.

[0149] Registers 202E-202H are also coupled to a slave sample group generator 206, which is coupled to a slave maximum PTP determiner 210 via N connections 228. The slave maximum PTP determiner 210 is coupled to an average phase determiner 216 via 2N connections 230. The average phase determiner 216 is coupled to the data transmitter 134 (FIG. 1A). Each of the master maximum PTP determiner 208, the slave maximum PTP determiner 210, and the master average frequency determiner 212 are also coupled to the data transmitter 134.

[0150] Master sample data 218 is provided to register 202A from ADC 130. One example of master sample data 218 is sample data 110-1 (FIG. 1A). Other examples of master sample data 218 include sample data 110A-1, or sample data 110B-1, or sample data 110C-1, or sample data 110D-1, or sample data 149A (FIGS. 1C-1, 1C-2, and 1D), or sample data 110E-1, or sample data 110F-1, or sample data 110G-1 (FIG. 1E-1).

[0151] Similarly, slave sample data 220 is provided to register 202E from ADC 130. An example of slave sample data 220 is sample data 110-2 (FIG. 1A). Other examples of slave sample data 220 include sample data 110A-2, or sample data 110B-2, or sample data 110C-2, or sample data 110D-2, or sample data 149B (FIGS. 1C-1, 1C-2, and 1D), or sample data 110E-2, or sample data 110F-2, or sample data 110G-2 (FIG. 1E-1).

[0152] Additionally, DCU 132 receives a clock signal, such as a transistor-transistor logic (TTL) signal 222, from processor 101 of analysis controller 114 (FIG. 1A). Processor 101 includes a clock source or clock generator that generates a clock signal that periodically transitions between a high logic level (e.g., 1) and a low logic level (e.g., 0). TTL signal 222 is also provided from processor 101 to RF generator 109 (FIG. 1A), RF generator 109A, RF generator 109B, RF generator 109C, and RF generator 109D (FIGS. 1C-1, 1D, and 1E-1). DCU 132 and RF generators 109 and 109A-109D operate in synchronization with TTL signal 222.

[0153] By providing TTL signal 222 to RF generators 109, 109A-109D and DCU 132, master sample data 218 and slave sample data 220 output from ADC 130 are synchronized to TTL signal 222. For example, master sample data 218 and slave sample data 220 may be generated by ADC 130 based on multiple measurement signals as described herein, where the measurement signals are generated by sensing multiple RF signals during the same clock cycle, or the same number of clock cycles, or N clock cycles of TTL signal 222.

[0154] The TTL signal 222 is supplied to each component of the DIS 128, and the components of the DIS 128 operate in synchronization with the TTL signal 222. For example, the TTL signal is supplied from the processor 101 to the ADC 130, registers 202A-202D, master sample group generator 204, slave sample group generator 206, master maximum PTP determiner 208, slave maximum PTP determiner 210, master average frequency determiner 212, and average phase determiner 216.

[0155] Master sample data 218 shifts from the output of register 202A to the input of register 202B, then from the output of register 202B to the input of register 202C, and then from the output of register 202C to the input of register 202D. Similarly, slave sample data 220 shifts from the output of register 202E to the input of register 202F, then from the output of register 202F to the input of register 202G, and then from the output of register 202G to the input of register 202H.

[0156] After shifting from register 202A through registers 202B and 202C to register 202D, the master sample data 218 is provided from registers 202A-202D to master sample group generator 204. For example, a first portion of master sample data 218 stored in register 202A is sent to master sample group generator 204 from the output of register 202A, a second portion of master sample data 218 stored in register 202B is sent to master sample group generator 204 from the output of register 202B, a third portion of master sample data 218 stored in register 202C is sent to master sample group generator 204 from the output of register 202C, and a fourth portion of master sample data 218 stored in register 202D is sent to master sample group generator 204 from the output of register 202D. Furthermore, after the first to fourth portions are transferred to the master sample group generator 204, the fifth, sixth, seventh, and eighth portions of the master sample data 218 are similarly stored in the registers 202A to 202D and transferred from the registers 202A to 202D to the master sample group generator 204.

[0157] By way of example, each portion of the master sample data 218 represents a cycle of a master RF signal, such as an applied RF signal or voltage signal, as described herein. Illustratively, a first portion of the master sample data 218 represents a first cycle of the RF signal 118 (FIG. 1A), a second portion of the master sample data 218 represents a second cycle of the RF signal 118, and so on until an eighth portion of the master sample data 218 represents an eighth cycle of the RF signal 118. The second cycle of the RF signal 118 is contiguous with the first cycle of the RF signal 118, and so on until the eighth cycle of the RF signal 118 is contiguous with the seventh cycle of the RF signal 118.

[0158] Each operating cycle of an RF signal, such as an supplied RF signal having parameters represented by master sample data 218, begins with a zero crossing, such as a positive zero crossing or a negative zero crossing, and ends with the same type of zero crossing, such as consecutive positive zero crossings or consecutive negative zero crossings. For example, if a first cycle of RF signal 118 begins with a first positive zero crossing, the first cycle ends with a second positive zero crossing. The second positive zero crossing is consecutive to the first positive zero crossing. For example, there is no positive zero crossing between the first and second positive zero crossings of RF signal 118.

[0159] Similarly, slave sample data 220, after shifting from register 202E via registers 202F and 202G to register 202H, is provided from registers 202E-202H to slave sample group generator 206. For example, a first portion of slave sample data 220 stored in register 202E is sent to slave sample group generator 204 from the output of register 202E, a second portion of slave sample data 220 stored in register 202F is sent to slave sample group generator 206 from the output of register 202F, a third portion of slave sample data 220 stored in register 202G is sent to slave sample group generator 206 from the output of register 202G, and a fourth portion of slave sample data 220 stored in register 202H is sent to slave sample group generator 206 from the output of register 202H. Furthermore, after the first to fourth portions are transferred to the slave sample group generator 206, the fifth, sixth, seventh, and eighth portions of the slave sample data 220 are similarly stored in the registers 202E to 202H and transferred from the registers 202E to 202H to the slave sample group generator 206.

[0160] By way of example, each portion of slave sample data 220 represents one cycle of a slave RF signal, such as a reflected RF signal or a voltage signal, as described herein. Illustratively, a first portion of slave sample data 220 represents a first cycle of RF signal 120 (FIG. 1A), a second portion of slave sample data 220 represents a second cycle of RF signal 120, and so on until an eighth portion of slave sample data 220 represents an eighth cycle of RF signal 120. The second cycle of RF signal 120 is contiguous with the first cycle of RF signal 120, and so on until the eighth cycle of RF signal 120 is contiguous with the seventh cycle of RF signal 120.

[0161] Each operating cycle of a slave RF signal, such as a reflected RF signal having parameters represented by slave sample data 220, begins with a zero crossing, such as a positive zero crossing or a negative zero crossing, and ends with consecutive zero crossings of the same type, such as consecutive positive zero crossings or consecutive negative zero crossings. For example, if a first cycle of RF signal 120 begins with a first positive zero crossing, the first cycle ends with a second positive zero crossing. The second positive zero crossing is consecutive to the first positive zero crossing. For example, there is no positive zero crossing between the first and second positive zero crossings of RF signal 120.

[0162] The master sample group generator 204 groups the master sample data 218 into N groups (sometimes referred to herein as sets), where N is an integer greater than 0. For example, the master sample group generator 204 determines to generate a predetermined number of groups, e.g., N (e.g., 8 groups or 16 groups), from the master sample data 218 and divides the master sample data 218 into the predetermined number of groups. Illustratively, the master sample group generator 204 includes a predetermined number of buffers, and each of the predetermined number of groups is stored in a corresponding one of the predetermined number of buffers. Further illustratively, a first group of the master sample data 218 is stored in a first buffer of the master sample group generator 204, and a second group of the master sample data 218 is stored in a second buffer of the master sample group generator 204. As an example, each of the N groups of the master sample data 218 corresponds to one cycle of the master RF signal. For example, a first group of master sample data 218 is generated by sampling parameter measurements for a first cycle of the master RF signal, and a second group of master sample data 218 is generated by sampling parameter measurements for a second cycle of the master RF signal.

[0163] The master sample group generator 204 transmits the N groups to the master maximum PTP determiner 208 via N connections 223. The master maximum PTP determiner 208 determines or calculates a master maximum PTP value (MMaxPTP) from the N groups received from the master sample group generator 204 in a manner described below. Furthermore, the master maximum PTP determiner 208 determines or calculates the times at which the maximum and minimum values are sampled for each of the N groups of master sample data 218. The master maximum PTP determiner 208 transmits the times at which the maximum and minimum values are sampled for each of the N groups of master sample data 218 to the master average frequency determiner 212 via connection 224. The master average frequency determiner 212 determines or calculates a master average frequency MAVF from the times at which the maximum and minimum values are sampled for each of the N groups of master sample data 218 in a manner described below. The master average frequency MAVF is an example of a statistical frequency value. Additionally, the master sample group generator 204 sends the times at which the maximum and minimum values were sampled for each of the N groups of master sample data 218 to the average phase determiner 216 .

[0164] Similarly, the slave sample group generator 206 groups the slave sample data 220 into N groups. For example, the slave sample group generator 206 determines to generate a predetermined number of groups, e.g., N (e.g., 8 groups or 16 groups), from the slave sample data 220 and divides the slave sample data 220 into the predetermined number of groups. Illustratively, the slave sample group generator 206 includes a predetermined number of buffers, and stores each of the predetermined number of groups in a corresponding one of the predetermined number of buffers. Further illustratively, a first group of the slave sample data 220 is stored in a first buffer of the slave sample group generator 206, and a second group of the slave sample data 220 is stored in a second buffer of the slave sample group generator 206. As an example, each of the N groups of the slave sample data 220 corresponds to one cycle of the slave RF signal. Illustratively, a first group of slave sample data 220 is generated by sampling parameter measurements for a first cycle of the slave RF signal, and a second group of slave sample data 220 is generated by sampling parameter measurements for a second cycle of the slave RF signal.

[0165] The slave sample group generator 206 transmits N groups of slave sample data 220 to the slave maximum PTP determiner 210 via N connections 228. The slave maximum PTP determiner 210 determines or calculates a slave maximum PTP (SMaxPTP) from the N groups received from the slave sample group generator 206 in a manner described below. For example, parallel processing of the master sample data 218 and the slave sample data 220 is possible. Illustratively, the slave maximum PTP determiner 210 determines the slave maximum PTP value SMaxPTP simultaneously with the determination of the master maximum PTP value MMaxPTP by the master maximum PTP determiner 208. As another example, the slave maximum PTP determiner 210 determines the slave maximum PTP value SMaxPTP within a preset time from the determination of the master maximum PTP value MMaxPTP by the master maximum PTP determiner 208. As another example, N groups of slave sample data 220 are processed by slave maximum PTP determiner 210 within the time that N groups of master sample data 218 are processed by master maximum PTP determiner 208 .

[0166] Furthermore, the slave maximum PTP determiner 210 determines or calculates the times at which the maximum and minimum values are sampled for each of the N groups of slave sample data 220. The slave maximum PTP determiner 210 transmits the times at which the maximum and minimum values were sampled for each of the N groups of slave sample data 220 to the average phase determiner 216 via connection 230. The average phase determiner 216 determines or calculates an average phase φ from the times at which the maximum and minimum values were sampled for each of the N groups of master sample data 218 and the times at which the maximum and minimum values were sampled for each of the N groups of slave sample data 220. The average phase φ is calculated using a method described below and is an example of a statistical phase value. The values MMaxPTP, SMaxPTP, MAVF, and φ are examples of compressed data 135 (FIG. 1A). Similarly, the values MMaxPTP, SMaxPTP, MAVF, and φ are examples of any of compressed data 135A to 135G.

[0167] By using TTL signal 222 to synchronize the operation of master maximum PTP determiner 208, slave maximum PTP determiner 210, master average frequency determiner 212, and average phase determiner 216 with the operation of ADC 130, which samples measurement signals received from multiple RF sensors described herein, any compressed data 135A-135G is synchronized with all RF sensors to maintain time alignment of the compressed data to the accuracy of ADC 130.

[0168] The average phase φ is generated synchronously with the output of the values MMaxPTP, SMaxPTP, and MAVF. For example, the average phase φ, the values MMaxPTP, SMaxPTP, and MAVF are output synchronously with the TTL signal 222. For example, the average phase φ, the values MMaxPTP, SMaxPTP, and MAVF are output in the same clock cycle. As another example, the average phase φ, the values MMaxPTP, SMaxPTP, and MAVF are output for multiple consecutive clock cycles of the TTL signal 222, where the number of consecutive clock cycles is within a predetermined range. As yet another example, the average phase φ, the values MMaxPTP, SMaxPTP, and MAVF are output for N clock cycles.

[0169] In one embodiment, DCU 132 includes any other number of registers. For example, DCU 132 includes a first set of eight registers instead of four registers 202A-202D and a second set of eight registers instead of four registers 202E-202H. In this embodiment, master sample group generator 204 and slave sample group generator 206 are not required. The first set of eight registers is coupled to master maximum PTP determiner 208, and the second set of status registers is coupled to slave maximum PTP determiner 210. As another example, one register is used instead of four registers 202A-202D, and one register is used instead of four registers 202E-202F.

[0170] In one embodiment, instead of the processor 101 providing the TTL signal 222, the processor 105 of the process controller 116 (FIG. 1A) provides the TTL signal 222.

[0171] In one embodiment, the DCU 132 is specific to the fixed operating range of an RF generator, such as RF generator 109, or RF generator 109A, or RF generator 109B, or RF generator 109C, or RF generator 109D. For example, if the fixed operating range is changed, another DCU is used in place of the DCU 132. Similarly, the DCU 132 is specific to the fixed sampling rate of the ADU 130 and the frequency response of an RF sensor (such as RF sensor 106, or RF sensor 106A, or RF sensor 106B, or RF sensor 106C, or RF sensor 106D, or RF sensor 106E, or RF sensor 106F, or RF sensor 106G). Similarly, the DCU 132 is specific to the fixed coefficients of multiple filters, including a first filter and a second filter. The first filter is connected between the ADC 130 and register 202A, and the second filter is connected between the ADC 130 and register 202E. The first filter is coupled to filter noise from a first digital signal having master sample data 218, and the second filter is coupled to filter noise from a second digital signal having slave sample data 220.

[0172] 3A is a diagram illustrating an embodiment of a method performed by the master max PTP determiner 208 (FIG. 2). The master max PTP determiner 208 receives N groups of master sample data 218 from the master sample group generator 204 (FIG. 2) and identifies a maximum value (e.g., maximum magnitude) and a minimum value (e.g., minimum magnitude) for each of the N groups. The maximum value is the maximum value of all values in the group of master sample data 218, and the minimum value is the minimum value of all values in the group of master sample data 218. For example, the master max PTP determiner 208 identifies a maximum value Mmx1 and a minimum value Mmn1 from group 1 of master sample data 218. As another example, the master maximum PTP determiner 208 identifies a maximum value Mmx2 and a minimum value Mmn2 from group 2 of the master sample data 218, the master maximum PTP determiner 208 identifies a maximum value Mmx3 and a minimum value Mmn3 from group 3 of the master sample data 218, the master maximum PTP determiner 208 identifies a maximum value Mmx(N-2) and a minimum value Mmn(N-2) from group (N-2) of the master sample data 218, the master maximum PTP determiner 208 identifies a maximum value Mmx(N-1) and a minimum value Mmn(N-1) from group (N-1) of the master sample data 218, and the master maximum PTP determiner 208 identifies a maximum value MmxN and a minimum value MmnN from group N of the master sample data 218.

[0173] The master maximum PTP determiner 208 determines the difference between the maximum and minimum values of each of the N groups of master sample data 218. For example, the master maximum PTP determiner 208 calculates a first difference between values Mmx1 and Mmn1, a second difference between values Mmx2 and Mmn2, a third difference between values Mmx3 and Mmn3, and so on until it calculates the (N-2)th difference between values Mmx(N-2) and values Mmn(N-2), the (N-1)th difference between values Mmx(N-1) and values Mmn(N-1), and the Nth difference between values MmxN and values MmnN. The master maximum PTP determiner 208 determines a master maximum peak-to-peak value MMaxPTP, e.g., the largest magnitude of the first through Nth differences calculated from the master sample data 218. For example, the master maximum peak-to-peak value MMaxPTP is determined as the maximum value among the first through Nth differences determined from N groups of master sample data 218. The maximum value MMaxPTP is the master maximum PTP.

[0174] The master maximum PTP determiner 208 transmits the maximum value MMaxPTP to the data transmitter 134 (FIG. 2). The data transmitter 134 transmits the maximum value MMaxPTP to a processor, such as the processor 101 of the analysis controller 114 or the processor 105 of the process controller 116 (FIG. 2).

[0175] Furthermore, the master max PTP determiner 208 identifies the times at which the maximum and minimum values are sampled or achieved for each of the N groups of master sample data 218. For example, the master max PTP determiner 208 determines the time tMmx1 at which the maximum value Mmx1 is sampled by the ADC 130 and the time tMmn1 at which the minimum value Mmn1 is sampled by the ADC 130. The times tMmx1 and tMmn1 are calculated by the master max PTP determiner 208 based on the TTL signal 222. For example, the time tMmx1 is the time at which the maximum value Mmx1 is determined by the master max PTP determiner 208. As another example, the master maximum PTP determiner 208 calculates the difference between the time at which the maximum value Mmx1 is determined by the master maximum PTP determiner 208 and the time it takes to receive the master sample data 218 from the ADC 130 via the registers 202A-202D and the master sample group generator 204, and subtracts this difference from the time at which the maximum value Mmx1 is determined to determine the time at which the maximum value Mmx1 is sampled by the ADC 130. As yet another example, the master maximum PTP determiner 208 requests the ADC 130 the time at which the maximum value Mmx1 is sampled via a connection between the master maximum PTP determiner 208 and the ADC 130. The ADC 130 measures the sampling time of the maximum value Mmx1 while sampling the maximum value Mmx1, and provides the time to the master maximum PTP determiner 208 via a connection between the master maximum PTP determiner 208 and the ADC 130. This time is measured by a timer in ADC 130 based on the TTL signal 222 received by ADC 130. This timer is coupled to a sampling section of ADC 130, which samples the data received by ADC 130 from the master measurement described herein.

[0176] Similarly, the master max PTP determiner 208 determines the time tMmx2 when the maximum value MMx2 is sampled by the ADC 130 and the time tMmn2 when the minimum value Mmn2 is sampled by the ADC 130, and determines the time tMmx3 when the maximum value MMx3 is sampled by the ADC 130 and the time tMmn3 when the minimum value Mmn3 is sampled by the ADC 130. The master max PTP determiner 208 determines the time tMmx(N-2) when the maximum value MMx(N-2) is sampled by the ADC 130 and the time tMmn(N-2) when the minimum value Mmn(N-2) is sampled by the ADC 130, determines the time tMmx(N-1) when the maximum value MMx(N-1) is sampled by the ADC 130 and the time tMmn(N-1) when the minimum value Mmn(N-1) is sampled by the ADC 130, and determines the time tMxN when the maximum value MMxN is sampled by the ADC 130 and the time tMmnN when the minimum value MmnN is sampled by the ADC 130.

[0177] In one embodiment, times tMmn1 through tMmnN are not related to minimum values of the master RF signal described herein, such as RF signal 118 (FIG. 1A) having parameters sampled by ADC 130, but rather times tMmn1 through tMmnN are times of positive zero crossings of a cycle of the master RF signal. For example, time tMmn1 is the time at which the master RF signal transitions from a negative value to a positive value during the first cycle of the master RF signal, and time tMmn2 is the time at which the master RF signal transitions from a negative value to a positive value during the second cycle of the master RF signal. The second cycle of the master RF signal follows the first cycle of the master RF signal. Each cycle of the master RF signal has one positive zero crossing and one negative zero crossing. As another example, if a direct current (DC) offset is applied to the master RF signal, time tMmn1 is the time at which the master RF signal transitions from a first value to a second value during a first cycle of the master RF signal, and time tMmn2 is the time at which the master RF signal transitions from a third value to a fourth value during a second cycle of the master RF signal, where the second value is greater than the first value and the fourth value is greater than the third value.

[0178] Similarly, in this embodiment, times tMmx1 through tMmxN are not associated with the maximum values of the master RF signal, but rather are the times of negative zero crossings in each cycle of the master RF signal. For example, time tMmx1 is the time at which the master RF signal transitions from a positive value to a negative value during the first cycle of the master RF signal, and time tMmx2 is the time at which the master RF signal transitions from a positive value to a negative value during the second cycle of the master RF signal. Note that the negative zero crossing of a cycle of the master RF signal is consecutive to the positive zero crossing of that cycle. For example, there are no other zero crossings between the negative and positive zero crossings of a cycle of the master RF signal. As another example, if a DC offset is applied to the master RF signal, time tMmx1 is the time at which the master RF signal transitions from a first value to a second value during a first cycle of the master RF signal, and time tMmx2 is the time at which the master RF signal transitions from a third value to a fourth value during a second cycle of the master RF signal, where the second value is less than the first value and the fourth value is less than the third value.

[0179] In one embodiment, times tMmn1 through tMmnN are not associated with the minimum value of the master RF signal, but rather are the times of the negative zero crossings of each cycle of the master RF signal. For example, time tMmn1 is the time at which the master RF signal transitions from a positive value to a negative value during the first cycle of the master RF signal, and time tMmn2 is the time at which the master RF signal transitions from a positive value to a negative value during the second cycle of the master RF signal. As another example, if a DC offset is applied to the master RF signal, time tMmx1 is the time at which the master RF signal transitions from a first value to a second value during the first cycle of the master RF signal, and time tMmx2 is the time at which the master RF signal transitions from a third value to a fourth value during the second cycle of the master RF signal. The second value is lower than the first value, and the fourth value is lower than the third value.

[0180] Similarly, in this embodiment, times tMmx1 through tMmxN are not associated with the maximum value of the master RF signal, but rather are the times of positive zero crossings in each cycle of the master RF signal. For example, time tMmx1 is the time at which the master RF signal transitions from a negative value to a positive value during the first cycle of the master RF signal, and time tMmx2 is the time at which the master RF signal transitions from a negative value to a positive value during the second cycle of the master RF signal. As another example, if a DC offset is applied to the master RF signal, time tMmx1 is the time at which the master RF signal transitions from a first value to a second value during the first cycle of the master RF signal, and time tMmx2 is the time at which the master RF signal transitions from a third value to a fourth value during the second cycle of the master RF signal. The second value is greater than the first value, and the fourth value is greater than the third value. Note that the positive zero crossings of a cycle of the master RF signal are consecutive to the negative zero crossings of that cycle. For example, there are no other zero crossings between the positive and negative zero crossings of a cycle of the master RF signal.

[0181] 3B is a diagram illustrating one embodiment of a method performed by slave maximum PTP determiner 210 (FIG. 2). Slave maximum PTP determiner 210 receives N groups of data of slave sample data 220 (FIG. 2) from slave sample group generator 206 and identifies a maximum value (e.g., maximum magnitude) and a minimum value (e.g., minimum magnitude) for each of the N groups. The maximum value is the maximum value of all values of a group of slave sample data 220, and the minimum value is the minimum value of all values of a group of slave sample data 220. For example, slave maximum PTP determiner 210 identifies a maximum value Smx1 and a minimum value Smn1 from group 1 of slave sample data 220. As another example, slave maximum PTP determiner 208 identifies a maximum value Smx2 and a minimum value Smn2 from group 2 of slave sample data 220. Slave maximum PTP determiner 208 identifies a maximum value Smx3 and a minimum value Smn3 from group 3 of slave sample data 220. The slave maximum PTP determiner 208 identifies the maximum value Smx(N-2) and the minimum value Smn(N-2) from group (N-2) of the slave sample data 220. The slave maximum PTP determiner 210 identifies the maximum value Smx(N-1) and the minimum value Smn(N-1) from group (N-1) of the slave sample data 220. The slave maximum PTP determiner 210 identifies the maximum value SmxN and the minimum value SmnN from group N of the slave sample data 220.

[0182] Note that group 1 of slave sample data 220 corresponds to the same period that group 1 of master sample data 218 (FIG. 2) is output from ADC 130 (FIG. 1A). For example, group 1 of slave sample data 220 is output by sampling a portion of the master measurement signal during the same period that the portion of the slave measurement signal is sampled. The slave measurement signal is sampled to output the slave sample data. Similarly, each of the remaining groups 2-N of slave sample data 220 is associated with a corresponding one of groups 2-N of master sample data 218.

[0183] The slave maximum PTP determiner 210 determines the difference between the maximum and minimum values of each group of slave sample data 220. For example, the slave maximum PTP determiner 210 calculates the first difference between values Smx1 and Smn1, the second difference between values Smx2 and Smn2, the third difference between values Smx3 and Smn3, and so on up to the (N-2)th difference between values Smx(N-2) and Smn(N-2), the (N-1)th difference between values Smx(N-1) and Smn(N-1), and the Nth difference between values SmxN and SmnN. The slave maximum PTP determiner 210 determines the maximum value SMaxPTP (e.g., the largest magnitude) of the first to Nth differences calculated from the slave sample data 220. The maximum value SMaxPTP is the slave maximum PTP. For example, the maximum value SMaxPTP is the maximum value of all the differences between the first to Nth groups of the slave sample data 220.

[0184] The slave maximum PTP determiner 210 transmits the maximum value SMaxPTP to the data transmitter 134 (FIG. 2). The data transmitter 134 transmits the maximum value SMaxPTP to a processor, such as the processor 101 of the analysis controller 114 or the processor 105 of the process controller 116 (FIG. 2).

[0185] Furthermore, the slave maximum PTP determiner 210 identifies the times at which the maximum and minimum values are sampled or achieved for each of the N groups of slave sample data 220. For example, the slave maximum PTP determiner 210 determines the time tSmx1 at which the maximum value SMx1 is sampled by the ADC 130 and the time tSmn1 at which the minimum value Smn1 is sampled by the ADC 130. The times tSmx1 and tSmn1 are calculated by the slave maximum PTP determiner 210 based on the TTL signal 222. For example, the time tSmx1 is the time at which the maximum value Smx1 is determined by the slave maximum PTP determiner 210. As another example, the slave maximum PTP determiner 210 determines the difference between the time at which the maximum value Smx1 is determined by the slave maximum PTP determiner 210 and the time it takes to receive the slave sample data 220 from the ADC 130 via registers 202E-202H and the slave sample group generator 206, and subtracts this difference from the time at which the maximum value Smx1 is determined to determine the time at which the maximum value Smx1 is sampled by the ADC 130. As yet another example, the slave maximum PTP determiner 210 requests the time at which the maximum value Smx1 is sampled from the ADC 130 via a connection between the slave maximum PTP determiner 210 and the ADC 130. The ADC 130 measures the time at which the maximum value Smx1 is sampled while sampling the maximum value Smx1, and provides the time to the slave maximum PTP determiner 210 via a connection between the slave maximum PTP determiner 210 and the ADC 130. This time is measured by a timer in the ADC 130 based on the TTL signal 222 received by the ADC 130. The timer is coupled to a sampler in the ADC 130, which samples data from the slave measurement signal received by the ADC 130.

[0186] Similarly, the slave maximum PTP determiner 210 determines the time tSmx2 when the maximum value SMx2 is sampled by the ADC 130 and the time tSmn2 when the minimum value Smn2 is sampled by the ADC 130, and determines the time tSmx3 when the maximum value SMx3 is sampled by the ADC 130 and the time tSmn3 when the minimum value Smn3 is sampled by the ADC 130. The master maximum PTP determiner 208 determines the time tSmx(N-2) when the maximum value Mmx(N-2) is sampled by the ADC 130 and the time tMmn(N-2) when the minimum value Smn(N-2) is sampled by the ADC 130, determines the time tSmx(N-1) when the maximum value SMx(N-1) is sampled by the ADC 130 and the time tSmn(N-1) when the minimum value Smn(N-1) is sampled by the ADC 130, and determines the time tSmxN when the maximum value SMxN is sampled by the ADC 130 and the time tSmnN when the minimum value SmnN is sampled by the ADC 130.

[0187] In one embodiment, times tSmn1 through tSmnN are not related to minimum values of a slave RF signal described herein, such as RF signal 120 (FIG. 1A) having parameters sampled by ADC 130, but rather times tSmn1 through tSmnN are the times of respective positive zero crossings of each cycle of the slave RF signal. For example, time tSmn1 is the time at which the slave RF signal transitions from a negative value to a positive value during the first cycle of the slave RF signal, and time tSmn2 is the time at which the slave RF signal transitions from a negative value to a positive value during the second cycle of the slave RF signal. As another example, if a DC offset is applied to the slave RF signal, time tSmx1 is the time at which the slave RF signal transitions from a first value to a second value during the first cycle of the slave RF signal, and time tSmx2 is the time at which the slave RF signal transitions from a third value to a fourth value during the second cycle of the slave RF signal. The second value is greater than the first value, and the fourth value is greater than the third value. The second cycle of the slave RF signal is consecutive to the first cycle of the slave RF signal, and each cycle of the slave RF signal has one positive zero crossing and one negative zero crossing.

[0188] Similarly, in this embodiment, times tSmx1 through tSmxN are not associated with the maximum value of the slave RF signal, but rather are the times of the negative zero crossings of each cycle of the slave RF signal. For example, time tSmx1 is the time at which the slave RF signal transitions from a positive value to a negative value during the first cycle of the slave RF signal, and time tSmx2 is the time at which the slave RF signal transitions from a positive value to a negative value during the second cycle of the slave RF signal. As another example, if a DC offset is applied to the slave RF signal, time tSmx1 is the time at which the slave RF signal transitions from a first value to a second value during the first cycle of the slave RF signal, and time tSmx2 is the time at which the slave RF signal transitions from a third value to a fourth value during the second cycle of the slave RF signal. The second value is lower than the first value, and the fourth value is lower than the third value. Note that the negative zero crossings of a given cycle of the slave RF signal are consecutive to the positive zero crossings of that cycle. For example, there are no other zero crossings between the negative and positive zero crossings of a cycle of the slave RF signal.

[0189] In one embodiment, times tSmn1 through tSmnN are not associated with minimum values of the slave RF signal, but rather are associated with respective negative zero crossings in each cycle of the slave RF signal. For example, time tSmn1 is the time at which the slave RF signal transitions from a positive value to a negative value during the first cycle of the slave RF signal, and time tSmn2 is the time at which the slave RF signal transitions from a positive value to a negative value during the second cycle of the slave RF signal. As another example, if a DC offset is applied to the slave RF signal, time tSmn1 is the time at which the slave RF signal transitions from a first value to a second value during the first cycle of the slave RF signal, and time tSmn2 is the time at which the slave RF signal transitions from a third value to a fourth value during the second cycle of the slave RF signal. The second value is less than the first value, and the fourth value is less than the third value.

[0190] Similarly, in this embodiment, times tSmx1 through tSmxN are not associated with maximum values of the slave RF signal, but rather are the times of respective positive zero crossings in each cycle of the slave RF signal. For example, time tSmx1 is the time at which the slave RF signal transitions from a negative value to a positive value during the first cycle of the slave RF signal, and time tSmx2 is the time at which the slave RF signal transitions from a negative value to a positive value during the second cycle of the slave RF signal. Note that the positive zero crossing of a cycle of the slave RF signal is consecutive to the negative zero crossing of that cycle. For example, there are no other zero crossings between the positive and negative zero crossings of a cycle of the slave RF signal. As another example, if a DC offset is applied to the slave RF signal, time tSmx1 is the time at which the slave RF signal transitions from a first value to a second value during a first cycle of the slave RF signal, and time tSmx2 is the time at which the slave RF signal transitions from a third value to a fourth value during a second cycle of the slave RF signal, where the second value is greater than the first value and the fourth value is greater than the third value.

[0191] 3C is a diagram illustrating one embodiment of a method performed by master average frequency determiner 212 (FIG. 2) to determine the master average frequency MAVF. Master average frequency determiner 212 receives times associated with master sample data 218 (FIG. 2) from master maximum PTP determiner 208 (FIG. 2). For example, master average frequency determiner 212 receives times tMmx1 through tMmxN and times tMmn1 through tMmnN from master maximum PTP determiner 208 via connection 224 (FIG. 2).

[0192] The master average frequency determiner 212 determines, e.g., by calculating or computing, the master average frequency MAVF from times tMmx1 through tMmxN and times tMmn1 through tMmnN. For example, the master average frequency determiner 212 calculates the absolute value of the difference between times tMmx1 and tMmn1 and multiplies the difference by two to determine the period PM1 associated with the first group of master sample data 218 (FIG. 2). As an example, the period PM1 is the occurrence time of the first cycle of a master RF signal described herein, such as RF signal 118 (FIG. 1A), for which values Mmx1 and Mmn1 are calculated. Similarly, the master average frequency determiner 212 calculates the absolute value of the difference between times tMmx2 and tMmn2 and multiplies the difference by two to determine the period PM2, and calculates the absolute value of the difference between times tMmx3 and tMmn3 and multiplies the difference by two to determine the period PM3. For example, period PM2 is the occurrence time of the second cycle of the master RF signal for which Mmx2 and Mmn2 are calculated. Master average frequency determiner 212 also calculates the absolute value of the difference between times tMmx(N-2) and tMmn(N-2) and multiplies that difference by 2 to determine period PM(N-2), calculates the absolute value of the difference between times tMmx(N-1) and tMmn(N-1) and multiplies that difference by 2 to determine period PM(N-1), and calculates the absolute value of the difference between times tMmxN and tMmnN and multiplies that difference by 2 to determine period PMN. For example, period PMN is the occurrence time of the Nth cycle of the master RF signal for which values MmxN and MmnN are calculated.

[0193] The master average frequency determiner 212 calculates the average of the periods PM1 to PMN and determines the master averaging period MAVP. For example, the master average frequency determiner 212 sums the periods PM1 to PMN and divides the sum by the number of periods N (N is the number of groups of master sample data 118) to determine the average of the periods. The average of the periods PM1 to PMN is the master averaging period MAVP. The master average frequency determiner 212 inverts the master averaging period MAVP to generate the master average frequency MAVF. For example, the frequency determiner 212 calculates the master average frequency MAVF as the ratio of 1 to the master averaging period MAVP.

[0194] The master average frequency determiner 212 transmits the master average frequency MAVF to the data transmitter 134 (FIG. 2), which transmits the master average frequency MAVF to a processor such as the processor 101 of the analysis controller 114 or the processor 105 of the process controller 116 (FIG. 2).

[0195] 3D is a diagram illustrating one embodiment of a method performed by the average phase determiner 216 (FIG. 2) to determine the average phase φ. The average phase determiner 216 receives times associated with the master sample data 218 (FIG. 2) from the master maximum PTP determiner 208 (FIG. 2). For example, the average phase determiner 216 receives times tMmx1 through tMmxN and times tMmn1 through tMmnN from the master maximum PTP determiner 208 via connection 226 (FIG. 2). In addition, the average phase determiner 216 receives times associated with the slave sample data 220 (FIG. 2) from the slave maximum PTP determiner 210 (FIG. 2). For example, the average phase determiner 216 receives times tSmx1 through tSmxN and times tSmn1 through tSmnN from the slave maximum PTP determiner 210 via connection 230 (FIG. 2).

[0196] Average phase determiner 216 determines, for example, by calculating or computing, an average phase φ from times tMmx1 to tMmxN, times tMmn1 to tMmnN, times tSmx1 to tSmxN, and times tSmn1 to tSmnN. For example, average phase determiner 216 calculates the absolute value of the difference between times tMmx1 and tSmx1 to determine a value Mxav1, calculates the absolute value of the difference between times tMmn1 and tSmn1 to determine a value Mnav1, and calculates the average of values Mxav1 and Mnav1 to determine an average phase Av1. As an example, average phase Av1 is the average phase during each of the first cycles of the master and slave RF signals described herein, such as RF signals 118 and 120 (FIG. 1A), from which values Mmx1, Mmn1, Smx1, and Smn1 are calculated.

[0197] Similarly, as another example, average phase determiner 216 calculates the absolute value of the difference between times tMmx2 and tSmx2 to determine a value Mxav2, calculates the absolute value of the difference between times tMmn2 and tSmn2 to determine a value Mnav2, and calculates the average of values Mxav2 and Mnav2 to determine an average phase Av2. As one example, average phase Av2 is the average phase during each second cycle of the master and slave RF signals described herein, such as RF signals 118 and 120 (FIG. 1A), for which values Mmx2, Mmn2, Smx2, and Smn2 are calculated.

[0198] As yet another example, the average phase determiner 216 calculates the absolute value of the difference between times tMmx3 and tSmx3 to determine the value Mxav3, calculates the absolute value of the difference between times tMmn3 and tSmn3 to determine the value Mnav3, and calculates the average value of values Mxav3 and Mnav3 to determine the average phase Av3.

[0199] As yet another example, the average phase determiner 216 calculates the absolute value of the difference between times tMmx(N-2) and tSmx(N-2) to determine the value Mxav(N-2), calculates the absolute value of the difference between times tMmn(N-2) and tSmn(N-2) to determine the value Mnav(N-2), and calculates the average value of values Mxav(N-2) and Mnav(N-2) to determine the average phase Av(N-2).

[0200] As another example, the average phase determiner 216 calculates the absolute value of the difference between times tMmx(N-1) and tSmx(N-1) to determine the value Mxav(N-1), calculates the absolute value of the difference between times tMmn(N-1) and tSmn(N-1) to determine the value Mnav(N-1), and calculates the average of values Mxav(N-1) and Mnav(N-1) to determine the average phase Av(N-1).

[0201] As yet another example, the average phase determiner 216 calculates the absolute value of the difference between times tMmxN and tSmxN to determine the value MxavN, calculates the absolute value of the difference between times tMmnN and tSmnN to determine the value MnavN, and calculates the average value of values MxavN and MnavN to determine the average phase AvN.

[0202] The average phase determiner 216 determines the average phase φ by determining the average value of the average phases Av1 to Avn for all N groups of the master sample data 118 and the slave sample data 120. For example, the average phase determiner 216 sums the average phases Av1 to Avn to determine a total value, and divides the total value by N to determine the average phase φ.

[0203] The average phase determiner 216 transmits the average phase φ to the data transmitter 134 (FIG. 2), which transmits the average phase φ to a processor, such as the processor 101 of the analysis controller 114 or the processor 105 of the process controller 116 (FIG. 2).

[0204] 3E illustrates one embodiment of master mean frequency determiner 350. Master mean frequency determiner 350 is an example of master mean frequency determiner 212 (FIG. 2). Master mean frequency determiner 350 includes sample counters (SC), numbered SC1, SC2, SC3, etc., through SC(N-2), SC(N-1), SCN (where N is an integer). For example, each sample counter SC1 through SCN is a digital counter formed by cascading flip-flops.

[0205] The master average frequency determiner 350 includes time counters (TC) TC1, TC2, TC3, etc., through time counters TC(N-2), TC(N-1), and TCN (where N is an integer). By way of example, each of the time counters TC1 through TCN is a digital counter formed by cascading flip-flops.

[0206] The master average frequency determiner 350 includes time multipliers (TM), TM1, TM2, TM3, etc., through time multipliers TM(N-2), TM(N-1), and TMN (where N is an integer). The master average frequency determiner 350 also includes frequency determiners F1, F2, F3, etc., through F(N-2), F(N-1), and FN (where N is an integer). Each frequency determiner F1 through FN is an inverter that calculates an inverted value. The master average frequency determiner 350 is coupled to an average frequency calculator AVFC. The average frequency calculator AVFC is coupled to the data transmitter 134 (FIG. 2).

[0207] Each sample counter is coupled to the master maximum PTP determiner 208 (FIG. 2) and to a corresponding time counter. For example, sample counter SC1 is coupled to time counter TC1, sample counter TC2 is coupled to time counter SC2, and so on until sample counter SCN is coupled to time counter TCN.

[0208] Also, each time counter is coupled to a corresponding time multiplier, e.g., time counter TC1 is coupled to time multiplier TM1, time counter TC2 is coupled to time multiplier TM2, and so on until time counter TCN is coupled to time multiplier TMN.

[0209] Each time multiplier is coupled to a corresponding frequency determiner. For example, time multiplier TM1 is coupled to frequency determiner F1, time multiplier TM2 is coupled to frequency determiner F2, and so on until time multiplier TMN is coupled to frequency determiner FN. Frequency determiners F1-FN are coupled to an average frequency calculator AVFC.

[0210] The sample counter SC1 receives a first group of master sample data 218 (FIG. 2) and counts a first number of samples in the first group between a maximum value Mmx1 and a minimum value Mmn1 within the first group. The sample counter SC1 provides the first number of samples to the time counter TC1. Similarly, the sample counter SC2 receives a second group of master sample data 218 (FIG. 2) and counts a second number of samples in the second group between a maximum value Mmx2 and a minimum value Mmn2 within the second group. The sample counter SCN receives an Nth group of master sample data 218 (FIG. 2) and counts an Nth number of samples in the Nth group between a maximum value MmxN and a minimum value MmnN within the Nth group.

[0211] Time counter TC1 receives the count of the first number of samples from sample counter SC1 and measures a first amount of time required to obtain the first number of samples by ADC 130. For example, time counter TC1 sends a request to ADC 130 (FIG. 1A) via a connection between time counter TC1 and ADC 130 to determine the time required to obtain two consecutive samples from the first number of samples. Upon receiving the time, time counter TC1 multiplies the time by the first number of samples to determine the first amount of time required to obtain the first number of samples by ADC 130.

[0212] Similarly, time counter TC2 receives the count of the second number of samples from sample counter SC2 and measures a second amount of time required to obtain the second number of samples by ADC 130. For example, time counter TC2 may send a request to ADC 130 via a connection between time counter TC2 and ADC 130 to determine the time required to obtain two consecutive samples from the second number of samples. Upon receiving the time, time counter TC2 multiplies the time by the second number of samples to determine the second amount of time.

[0213] Time counter TCN also receives the count of the Nth number of samples from sample counter SCN and measures the Nth amount of time required to obtain the Nth number of samples by ADC 130. For example, time counter TCN may send a request to ADC 130 via a connection between time counter TCN and ADC 130 to determine the time required to obtain two consecutive samples from the Nth number of samples. Upon receiving the time, time counter TCN multiplies the time by the Nth number of samples to determine the Nth amount of time.

[0214] Time multiplier TM1 receives a first time amount from time counter TC1 and multiplies the first time amount by 2 to produce a first time value associated with the first number of samples. Similarly, time multiplier TM2 receives a second time amount from time counter TC2 and multiplies the second time amount by 2 to produce a second time value, and time multiplier TMN receives an Nth time amount from time counter TCN and multiplies the second time amount by 2 to produce an Nth time value.

[0215] Frequency determiner F1 receives a first time value from time multiplier TM1 and inverts the first time value to calculate a first frequency value associated with the first number of samples, similarly, frequency determiner F2 receives a second time value from time multiplier TM2 and inverts the second time value to calculate a second frequency value associated with the second number of samples, and frequency determiner FN receives an Nth time value from time multiplier TMN and inverts the Nth time value to calculate an Nth frequency value associated with the Nth number of samples.

[0216] The average frequency calculator AVFC receives the first through Nth frequency values from the frequency determiners F1 through FN and calculates the average value of the N frequency values. For example, the average frequency calculator AVFC calculates the sum of the first through Nth frequency values and divides the sum by N to determine the master average frequency MAVF. The average frequency calculator AVFC provides the master average frequency MAVF to the data transmitter 134.

[0217] FIG. 3F-1 is one embodiment of a graph 302 illustrating group 304D, which has the largest amplitude of all of groups 304A, 304B, 304C, and 304D, and corresponding group 318D (FIG. 3F-2). Graph 302 includes a plot 304 of power versus time t. Groups 304A-304D are examples of any four consecutive groups 1-N of master sample data 218 (FIG. 2). Processor 101 or 105 determines that group 304D has the largest magnitude 306A and the smallest magnitude 306B. Maximum magnitude 306A is the largest value of all values in group 304D, and minimum magnitude 306B is the smallest value of all values in group 304D.

[0218] The processor 101 or 105 (FIG. 1A) determines that group 304D has the largest fluctuation. For example, the processor 101 or 105 calculates the difference between the maximum and minimum magnitudes for each of groups 304A-304D. The processor 101 or 105 further determines that the difference between maximum magnitude 306A and minimum magnitude 306B is the largest of all differences, thereby determining that group 304D has the largest fluctuation. Group 304D, which has the largest fluctuation of all of groups 304A-304D, may be referred to herein as the dominant master group. The maximum magnitude 306A within the dominant master group is referred to herein as the dominant master maximum value. Additionally, the minimum magnitude 306B within the dominant master group is referred to herein as the dominant master minimum value.

[0219] Furthermore, processor 101 or 105 determines that group 304C has the highest maximum size. For example, processor 101 or 105 determines that maximum size 310A of group 304C is the largest among the maximum sizes of groups 304A to 304D. Maximum size 310A within group 304C is referred to herein as the global master maximum value.

[0220] Furthermore, processor 101 or 105 determines that group 304B has the smallest minimum size. For example, processor 101 or 105 determines that group 304B's minimum size 312B is the smallest among the minimum sizes of groups 304A through 304D. Minimum size 312B within group 304B is referred to herein as the global master minimum.

[0221] Processor 101 or 105 determines time 308A when the first positive crossing occurs in group 304D, the dominant master group. Processor 101 or 105 determines a positive crossing for a group as the time when a change occurs from a negative value in the group to a positive value in the group. Processor 101 or 105 also determines time 308B when the first negative crossing occurs in group 304D. Processor 101 or 105 determines a negative crossing for a group as the time when a change occurs from a positive value in the group to a negative value in the group. Each time 308A and 308B is a location on the X-axis where the time is plotted. Time 308A is referred to herein as the master positive edge, and time 308B is referred to as the master negative edge.

[0222] Note that processor 101 or 105 may identify but ignore the remaining positive and negative crossings in each group 304A-304D. For example, processor 101 identifies a second positive crossing 314A and a second negative crossing 314B, but ignores crossings 314A and 314B.

[0223] Processor 101 or 105 further determines the sum of all widths for groups 304A-304D. For example, the width of group 304D is calculated by processor 101 as the time difference between times 308B and 308A. Processor 101 ignores the time differences between the remaining positive and negative crossings in group 304D. Similarly, the widths of groups 304A-304C are calculated. Processor 101 calculates the sum of all widths for groups 304A-304D. Note that the sum of all widths for groups 304A-304D is referred to herein as the total master width.

[0224] The processor 101 or 105 calculates the average master width based on the total master width. The processor 101 or 105 calculates the average master width by calculating the average of all widths of the groups 304A to 304D. For example, the processor 101 divides the calculated total master width based on the groups 304A to 304D and divides the total master width by 4 to determine the average master width.

[0225] Note that one or more of the dominant master maximum, global master maximum, dominant master minimum, global master minimum, master positive edge, master negative edge, total master width, and average master width are examples of compressed data as described herein, such as compressed data 135 (FIG. 1A).

[0226] In one embodiment, one or more of the maximum magnitude of each of groups 304A-304D, the minimum magnitude of each of groups 304A-304D, the time at which the first positive crossing occurs for each of groups 304A-304D, and the time at which the first negative crossing occurs for each of groups 304A-304D are examples of compressed data described herein, such as compressed data 135 (FIG. 1A).

[0227] In one embodiment, processor 101 or 105 determines a differential dominant master amplitude (DDMA) based on the maximum and minimum magnitudes 306A and 306B. For example, processor 101 calculates the difference between the maximum magnitude 306A and the minimum magnitude 306B and divides the difference by two to determine the DDMA. Furthermore, in this embodiment, processor 101 or 105 determines a differential global master amplitude (DGMA) based on amplitudes 310A and 312B. For example, processor 101 calculates the difference between the maximum amplitude 310A and the minimum amplitude 312B and divides the difference by two to determine the DGMA. Also, in this embodiment, processor 101 or 105 determines the absolute difference between times 308A and 308B or times 308B and 308A and multiplies the absolute difference by two to calculate the dominant master phase.

[0228] Furthermore, in this embodiment, the processor 101 or 105 determines the average master period based on the average master width. The processor 101 or 105 calculates the average master width based on the total master width and the number of widths in the groups 304A-304D. For example, the processor 101 calculates the average master width as the ratio of the total master width to the sum of the number of widths in the groups 304A-304D. To further illustrate, the processor 101 calculates the average master width as the ratio of the total master width to 4. In this example, to calculate the average master width, the processor 101 ignores positive crossings other than the first positive crossing in each group 304A-304D and ignores negative crossings other than the first negative crossing. In this example, the processor 101 calculates the average master period as the product of 2 and the average master width.

[0229] Additionally, in this embodiment, processor 101 or 105 counts the total number of clock cycles of TTL signal 222 ( FIG. 2 ) during which group 304D is generated by master sample group generator 204. Processor 101 or 105 further identifies the state within each clock cycle of TTL signal 222 to generate a total dominant master digital value. For example, processor 101 or 105 counts the number of times a logic level 1 is achieved during the period in which group 304D is generated and counts the number of times a logic level 0 is achieved during that period. Illustratively, processor 101 or 105 determines that the logic level of TTL signal 222 is greater than a preset threshold and thus determines the logic level to be 1. In this example, processor 101 or 105 determines that the logic level of TTL signal 222 is less than a preset threshold and thus determines the logic level to be 0. In this example, processor 101 or 105 counts the number of logic levels 1 or logic levels 0 to determine the total dominant master digital value.

[0230] In this embodiment, one or more of the differential dominant master amplitude, the differential global master amplitude, the dominant master phase, the average master period, and the total dominant master digital value are examples of compressed data as described herein, such as compressed data 135.

[0231] In one embodiment, processor 101 or 105 counts the total number of clock cycles of TTL signal 222 (FIG. 2) during which each remaining group 304A-304C is generated by master sample group generator 204. Processor 101 or 105 further identifies the state within each clock cycle of TTL signal 222 to generate a total master digital value for each of groups 304A-304C. For example, in a manner similar to that described above with reference to group 304D, processor 101 or 105 counts the number of times a logic level 1 is achieved during the time period during which each group 304A-304C is generated, and counts the number of times a logic level 0 is achieved during that time period. The total master digital value is an example of compressed data as described herein.

[0232] In one embodiment, instead of group 304B, group 304D has the global master minimum.

[0233] In one embodiment, instead of group 304C, group 304D has the global master maximum value.

[0234] FIG. 3F-2 is an embodiment of a graph 316 illustrating that group 318B does not correspond to group 304D (FIG. 3F-1) having magnitudes 306A and 306B. Graph 316 includes a plot 318 of power versus time t. Plot 318 includes groups 318A, 318B, 318C, and 318D, which are examples of any four consecutive groups 1 through N of slave sample data 220 (FIG. 2). Processor 101 or 105 determines that group 318B has a maximum magnitude 320A and a minimum magnitude 320B. Maximum value 320A is the maximum value of all values in group 318B, and minimum value 320B is the minimum value of all values in group 318B.

[0235] Note that group 318B, which has the largest and smallest magnitudes 320A and 320B, does not correspond to group 304D. For example, group 318B is sampled by ADC 130 second of groups 318A-318D to generate slave sampled data 220, and group 304D is sampled fourth of groups 304A-304D to generate master sampled data 218. Illustratively, group 318B is sampled at a different period of TTL signal 222 compared to the period at which group 304D is sampled. In this example, group 318B is sampled two clock cycles earlier than group 304D, and these clock cycles are of TTL signal 222. Rather, group 318D corresponds to group 304D. For example, group 318D is sampled by ADC 130 fourth of groups 318A-318D to generate slave sample data 220, and group 304D is sampled fourth of groups 304A-304D to generate master sample data 218. For example, group 318D is sampled during the same period of TTL signal 222 as group 304D is sampled. In this example, group 318D is sampled during the same clock cycle or cycles of TTL signal 222 as group 304D is sampled. For another example, the portion of the slave measurement signal from which group 318D is generated is output by the RF sensor during the same period as the portion of the master measurement signal is output by the RF sensor. In this example, group 304D is generated from the portion of the master measurement signal. Therefore, the maximum magnitude 322A and minimum magnitude 322B of group 318D, which corresponds to dominant group 304D, are analyzed by analysis controller 101 or process controller 105. The maximum magnitude 322A is the highest magnitude among all the magnitudes in the group 318D, and the minimum magnitude 322B is the lowest magnitude among all the magnitudes in the group 318D.

[0236] Processor 101 or 105 further determines that group 318B has the largest fluctuation. For example, processor 101 or 105 calculates the difference between the maximum and minimum magnitudes for each of groups 318A-318D. Processor 101 or 105 further determines that the difference between maximum magnitude 320A and minimum magnitude 320B is the largest of all differences, thereby determining that group 318B has the largest fluctuation. Group 318B, which has the largest fluctuation among all groups 318A-318D, may be referred to herein as the dominant slave group. The maximum magnitude 320A within the dominant slave group is referred to herein as the dominant slave maximum value. Additionally, the smallest magnitude 320B within the dominant slave group is referred to herein as the dominant slave minimum value.

[0237] Furthermore, processor 101 or 105 determines that group 318C has the highest maximum magnitude among groups 318A to 318D. For example, processor 101 or 105 determines that maximum magnitude 324A of group 318C is the largest among the maximum magnitudes of groups 318A to 318D. Maximum magnitude 324A within group 318C is referred to herein as the global slave maximum.

[0238] Furthermore, processor 101 or 105 determines that group 318A has the lowest minimum magnitude among groups 318A to 318D. For example, processor 101 or 105 determines that minimum magnitude 326B of group 318A is the smallest among the minimum magnitudes of groups 318A to 318D. Minimum magnitude 326B within group 318A is referred to herein as the global slave minimum.

[0239] Processor 101 or 105 determines time 328A at which the first positive crossing occurs in dominant slave group 318B. Processor 101 or 105 also determines time 328B at which the first negative crossing occurs in group 318B. Each time 328A and 328B is a location on the X-axis at which that time is plotted. Time 328A is referred to herein as the slave positive edge, and time 328B is referred to as the slave negative edge. Note that processor 101 or 105 can identify but ignore the remaining positive and negative crossings in each group 318A-318D, just as it can identify but ignore the remaining positive and negative crossings in each group 304A-304D.

[0240] Processor 101 or 105 further determines the sum of all widths for groups 318A-318D. For example, the width of group 318B is calculated by processor 101 as the time difference between times 328B and 328A. Processor 101 ignores the time differences between the remaining positive and negative crossings in group 318B. Similarly, the widths of the remaining groups 318A, 318C, and 318D are calculated. Processor 101 calculates the sum of all widths for groups 318A-318D. The sum of all widths for groups 318A-318D is referred to herein as the total slave width.

[0241] Processor 101 or 105 calculates the average slave width based on the total slave width. Processor 101 or 105 calculates the average slave width by calculating the average of all widths of groups 318A-318B. For example, processor 101 divides the calculated total slave width based on groups 318A-318D and divides the total slave width by 4 to determine the average slave width.

[0242] Note that one or more of the dominant slave maximum, global slave maximum, dominant slave minimum, global slave minimum, slave positive edge, slave negative edge, total slave width, and average slave width are examples of compressed data as described herein, such as compressed data 135.

[0243] In one embodiment, processor 101 or 105 calculates a corresponding maximum magnitude, a corresponding minimum magnitude, a corresponding time of occurrence of a positive edge crossing, and a corresponding time of occurrence of a negative edge crossing for one of groups 318A-318D. One of groups 318A-318D corresponds to the same number as the dominant master group. For example, processor 101 determines maximum magnitude 322A, minimum magnitude 322B, time 330A at which the first positive crossing occurs within group 318D, and time 330B at which the first negative crossing occurs within group 318D. Group 318D corresponds to group 304D. Note that one or more of the corresponding maximum magnitude, corresponding minimum magnitude, corresponding time of occurrence of a positive edge crossing, and corresponding time of occurrence of a negative edge crossing are examples of compressed data described herein, such as compressed data 135.

[0244] Note that although each graph 302 and 316 illustrates a zero power value at either the positive or negative crossing, in one embodiment, a DC offset is used instead of the zero power value, and the DC offset may be a negative or positive value.

[0245] In one embodiment, processor 101 or 105 determines a differential dominant slave amplitude (DDSA) based on the maximum and minimum magnitudes 320A and 320B. For example, processor 101 calculates the difference between the maximum magnitude 320A and the minimum magnitude 320B and divides the difference by two to determine the differential dominant slave amplitude. Furthermore, in this embodiment, processor 101 or 105 determines a differential global slave amplitude (DGSA) based on the amplitudes 324A and 326B. For example, processor 101 calculates the difference between the maximum amplitude 324A and the minimum amplitude 326B and divides the difference by two to determine the differential global slave amplitude. Also, in this embodiment, processor 101 or 105 determines the absolute difference between time 328A and time 328B, or between time 328B and time 328A, and multiplies the absolute difference by two to calculate the dominant slave phase.

[0246] Furthermore, in this embodiment, processor 101 or 105 determines the average slave cycle based on the average slave width. Processor 101 or 105 calculates the average slave width based on the total slave width and the number of widths in groups 318A-318D. For example, processor 101 calculates the average slave width as the ratio of the total slave width to the sum of the number of widths in groups 318A-318D. To further illustrate, processor 101 calculates the average slave width as the ratio of the total slave width to 4. In this example, to calculate the average slave width, processor 101 ignores positive crossings other than the first positive crossing and negative crossings other than the first negative crossing in each group 318A-318D. In this example, processor 101 calculates the average slave period as the product of 2 and the average slave width.

[0247] Additionally, in this embodiment, processor 101 or 105 counts the total number of clock cycles of TTL signal 222 ( FIG. 2 ) during which dominant slave group 318B is generated by slave sample group generator 206. Processor 101 or 105 further identifies the state within each clock cycle of TTL signal 222 to generate a total dominant slave digital value. For example, processor 101 or 105 counts the number of times a logic level of 1 is achieved on TTL signal 222 during the period in which group 318B is generated. In this example, processor 101 or 105 counts the number of times a logic level of 0 is achieved on TTL signal 222 during this period. Illustratively, processor 101 or 105 determines that the logic level of TTL signal 222 is greater than a preset threshold, thereby determining that the logic level is 1. In this example, processor 101 or 105 determines that the logic level of TTL signal 222 is less than a preset threshold, thereby determining that the logic level is zero. In this example, processor 101 or 105 counts the number of logic levels 1 or 0 to determine the total dominant slave digital value.

[0248] In this embodiment, one or more of the differential dominant slave amplitude, the differential global slave amplitude, the dominant slave phase, the average slave period, and the total dominant slave digital value are examples of compressed data as described herein, such as compressed data 135.

[0249] In one embodiment, processor 101 or 105 counts the total number of clock cycles of TTL signal 222 (FIG. 2) during which each of the remaining groups 318A, 318C, and 318D is generated by slave sample group generator 206. Processor 101 or 105 further identifies the state within each clock cycle of TTL signal 222 to generate a total slave digital value for each of groups 318A, 318C, and 318D. For example, in a manner similar to that described above with reference to group 318B, processor 101 or 105 counts the number of times a logic level 1 is achieved during the period in which each group 318A, 318C, and 318D is generated, and counts the number of times a logic level 0 is achieved during this period. In this example, the number of times equals the total slave digital value. The total slave digital value is an example of compressed data described herein, such as compressed data 135.

[0250] In one embodiment, one or more of the following are examples of total slave digital values as described herein: MMaxPTP, SMaxPTP, MAVF, φ, dominant master maximum, global master maximum, dominant master minimum, global master minimum, master positive edge, master negative edge, total master width, average master width, maximum magnitude of each group 304A-304C, minimum magnitude of each group 304A-304C, time when the first positive crossing occurs in each group 304A-304C, time when the first negative crossing occurs in each group 304A-304C, differential dominant master amplitude, differential global master amplitude, dominant master phase, average master period, The compressed data may include the total dominant master digital value, the total master digital value, the dominant slave maximum, the global slave maximum, the dominant slave minimum, the global slave minimum, the slave positive edge, the slave negative edge, the total slave width, the average slave width, the corresponding maximum magnitude within groups 318A-318D, the corresponding minimum magnitude within groups 318A-318D, the time of occurrence of the corresponding positive edge crossing within groups 318A-318D, the time of occurrence of the corresponding negative edge crossing within groups 318A-318D, the difference dominant slave amplitude, the difference global slave amplitude, the dominant slave phase, the average slave period, the total dominant slave digital value, and the total slave digital value. Examples of compressed data described herein include compressed data 135, 135A, 135B, 135C, 135D, 135E, 135F, 135G, and 157 (FIGS. 1C-1, 1C-2, 1E-1, and 1E-2).

[0251] In one embodiment, instead of group 318A, group 318B has the global slave minimum.

[0252] In one embodiment, instead of group 318C, group 318B has the global slave maximum value.

[0253] 4A is a diagram of one embodiment of a system 400 to illustrate the control of an RF generator 402 based on compressed data, as described herein. The system 400 includes an RF generator 402, a match 404, a motor system 406, a driver system 408, an analysis controller 114, and a process controller 116.

[0254] Examples of RF generator 402 include RF generator 109 (FIGS. 1A and 1B), or RF generator 109A (FIG. 1C-1), or RF generator 109B (FIG. 1C-1), or RF generator 109C (FIG. 1D), or RF generator 109D (FIG. 1D), etc. Examples of match 404 include match 111 (FIG. 1A), or match 111A (FIG. 1C-1), or match 111B (FIG. 1C-1), or match 164 (FIG. 1D), etc. For example, if RF generator 402 is RF generator 109, match 404 is match 111 coupled to RF generator 109, and if RF generator 402 is RF generator 109B, match 404 is match 111A coupled to RF generator 109B or match 164 coupled to RF generator 109B.

[0255] An example of the motor system 406 includes one or more electric motors, such as direct current (DC) motors or alternating current (AC) motors. Each electric motor includes a stator and a rotor. An example of the driver system 408 includes one or more drivers, such as one or more transistors. For example, one or more transistors of the drivers are coupled to each other.

[0256] The processor 101 of the analysis controller 114 is coupled to the driver system 408, which is coupled to the motor system 406. The processor 101 is also coupled to the RF generator 402. For example, the processor 101 is coupled to the digital signal processor of the RF generator via a transmission cable.

[0257] The motor system 406 is coupled to the match 404 via one or more mechanical connections, such as one or more rods, or a combination of two or more rods and one or more gears. For example, the motor of the motor system 406 is coupled to the plates of the capacitor of the match 404 via two rods and a gear between the two rods. The two rods are coupled to each other via the gear. As another example, the motor of the motor system 406 is coupled to a core surrounded by a coil of an inductor of the match 404. The motor is coupled to the core and changes the position of the core. The core and coil are components of the inductor.

[0258] Upon receiving the compressed data described herein from the data transmitter 134 (FIG. 1A) via the data transceiver 125 (FIG. 1A), the processor 101 determines to change one or more variables of operation of the RF generator 402. Examples of variables of the RF generator 402 include power or frequency. For example, upon determining that the slave maximum peak-to-peak value SMaxPTP is greater than a predetermined threshold and the master maximum peak-to-peak value MMaxPTP is lower than a predetermined limit, the processor 101 determines to increase the amount of power generated and supplied by the RF generator 402. As another example, upon determining that the master average frequency value MAVF is not within a predetermined range, the processor 101 controls the RF generator 402 to increase or decrease the frequency of operation of the RF generator 402 until the master average frequency value MAVF is within the predetermined range. As yet another example, upon determining that the average phase value φ is not within a predetermined range, the processor 101 controls the RF generator 402 to increase or decrease the frequency of operation of the RF generator 402 until the average phase value φ is within the predetermined range. In this manner, the variables of RF generator 402 are controlled by processor 101 until the master maximum peak-to-peak value MMaxPTP is within a predetermined range, the slave maximum peak-to-peak value SMaxPTP is within a predetermined range, the master average frequency value MAVF is within a predetermined range, the average phase value φ is within a predetermined range, or a combination of two or more thereof.

[0259] As another example, the processor 101 determines that the compressed data described herein corresponds to a first plasma control state, such as plasma impedance, and determines to modify one or more variables of the RF generator 402. Illustratively, a correspondence exists when a one-to-one relationship or link exists between the compressed data described herein and the first plasma control state. The one or more variables are modified until the processor 101 determines that the compressed data described herein corresponds to a second plasma control state. An example of a plasma impedance state is the level of impedance of the plasma in the plasma chamber 152. Impedance levels include impedance values within a predetermined range from each other. Also, the magnitude of one impedance level is exclusive of the magnitude of other impedance levels.

[0260] As yet another example, the processor 101 determines that the compressed data described herein corresponds to a first RF transition sequence, such as a sequence of states or levels of one of the variables of the RF generator 402, and determines to modify one or more of the variables of the RF generator 402. Illustratively, a correspondence exists when a one-to-one relationship or link exists between the compressed data described herein and the first RF transition sequence. One or more variables are modified until the processor 101 determines that the compressed data described herein corresponds to a second RF transition sequence. An example of an RF transition sequence is a change in the RF signal generated by the RF generator 402 from one power level to another during one clock cycle of a clock signal that the RF generator 402 receives from the processor 101. The RF transition sequence may include any number of power level changes during a clock cycle. The power level of the RF signal includes the magnitude of the peak-to-peak or zero-to-peak power of the RF signal, the magnitudes being within a predetermined range from each other. Furthermore, the magnitude of one power level is exclusive of the magnitude of another power level.

[0261] As yet another example, processor 101 determines that an RF trigger event has occurred by determining whether the master maximum peak-to-peak value MMaxPTP is greater than or less than a first predetermined master maximum peak-to-peak value, or whether the slave maximum peak-to-peak value SMaxPTP is greater than or less than a first predetermined slave maximum peak-to-peak value, or whether the master average frequency value MAVF is greater than or less than a first predetermined master average frequency value, or whether the average phase value φ is greater than or less than a first predetermined average phase value, or a combination thereof. Upon determining that an RF trigger event has occurred, processor 101 controls one or more variables of RF generator 402 until an RF trigger event no longer occurs.

[0262] As yet another example, the processor 101 determines that an RF precursor event has occurred by determining whether the master maximum peak-to-peak value MMaxPTP is greater than or less than a second predetermined master maximum peak-to-peak value, or whether the slave maximum peak-to-peak value SMaxPTP is greater than or less than a second predetermined slave maximum peak-to-peak value, or whether the master average frequency value MAVF is greater than or less than a second predetermined master average frequency value, or whether the average phase value φ is greater than or less than a second predetermined average phase value, or a combination thereof. An RF precursor event is an event that occurs before an RF trigger event. Illustratively, an RF precursor event is a warning that an RF trigger event will occur. Upon determining that an RF precursor event has occurred, the processor 101 controls one or more variables of the RF generator 402 until an RF precursor event no longer occurs.

[0263] As another example, the processor 101 determines that an RF fault event has occurred by determining whether the master maximum peak-to-peak value MMaxPTP is greater than or less than a third predetermined master maximum peak-to-peak value, whether the slave maximum peak-to-peak value SMaxPTP is greater than or less than a third predetermined slave maximum peak-to-peak value, whether the master average frequency value MAVF is greater than or less than a third predetermined master average frequency value, whether the average phase value φ is greater than or less than a third predetermined average phase value, or any combination thereof. Upon determining that an RF trigger fault has occurred, the processor 101 controls one or more variables of the RF generator 402 until an RF fault event no longer occurs. Examples of RF fault events include malfunctions of components of the plasma system or plasma tool described herein and arcing of plasma in the plasma chamber described herein. Examples of components of a plasma tool include an RF generator, an RF cable, a match, an RF transmission line, and a plasma chamber.

[0264] Similarly, upon receiving the compression data described herein, the processor 101 determines to change a variable, such as the capacitance or inductance, of the match 404. For example, the processor 101 sends a control signal to the driver system 408 to change the variable of the match 404. Upon receiving the control signal, the driver system 408 generates one or more current signals and provides the one or more current signals to the motor system 406. Upon receiving the one or more current signals, one or more motors of the motor system 406 operate to move one or more plates of one or more capacitors or change the position of one or more cores of one or more inductors of the match 404. The one or more capacitors of the match 404 are controlled to change the capacitance of the match 404, and the one or more inductors of the match 404 are controlled to change the inductance of the match 404. In this manner, the capacitance and / or inductance of the match 404 is controlled by the processor 101 until the compression data described herein falls within a predetermined range.

[0265] In one embodiment, instead of analysis controller 114 controlling RF generator 402 and / or match 404, process controller 116 controls RF generator 402 and / or match 404. For example, processor 105 is coupled to the digital signal processor of RF generator 402 and coupled to driver system 408 instead of processor 101. Processor 105 provides control signals to RF generator 402 and driver system 408 to control RF generator 402 and driver system 408 in the manner described above until the compressed data described herein is within a predetermined range.

[0266] 4B is a diagram of one embodiment of a system 410 to illustrate control of a gap 412 between the lower electrode 154 and the TCP coil 156. The system 410 includes a process controller 116, an analysis controller 114, a driver system 408, a motor system 406, and a plasma chamber 152.

[0267] The processor 101 is coupled to the driver system 408, and the motor system 406 is coupled to the lower electrode 154. For example, the motor system 406 is coupled to the lower electrode 154 via one or more of the mechanical connections exemplified above.

[0268] The processor 101 sends a control signal to the driver system 408. Upon receiving the control signal, the driver system 408 generates one or more current signals. The one or more current signals are received by the motor system 406, which operates in the manner described above to move the lower electrode vertically up or down to vary the gap 412 between the lower electrode 154 and the TCP coil 156. In this manner, the gap 412 is controlled by the processor 101 until the compressed data described herein falls within a predetermined range. For example, the gap 412 is controlled until the master maximum peak-to-peak value MMaxPTP falls within a predetermined range, the slave maximum peak-to-peak value SMaxPTP falls within a predetermined range, the master average frequency value MAVF falls within a predetermined range, or the average phase value φ falls within a predetermined range, or a combination of two or more thereof.

[0269] In one embodiment, plasma chamber 113 (FIG. 1A) or plasma chamber 168 (FIG. 1D) is used instead of plasma chamber 152. For example, the gap between two electrodes, such as the upper and lower electrodes of plasma chamber 113 or the lower electrode 154 and TCP coil 156A of plasma chamber 168, is controlled.

[0270] In one embodiment, instead of analysis controller 114 controlling gap 412, process controller 116 controls gap 412. For example, processor 105 is coupled to driver system 408 instead of processor 101. Processor 105 provides control signals to driver system 408 for controlling gap 412 in the manner described above.

[0271] 4C is a diagram of one embodiment of a system 420 to illustrate controlling pressure and gas flow in a plasma chamber 152. The system 420 includes a process controller 116, an analysis controller 114, a gas supply 422, a valve driver 424, a gas system controller 425, a valve 426, a pressure system controller 427, a plasma chamber 152, another valve driver 428, a pressure sensor 429, a valve driver 430, a valve 432, a valve 434, a vacuum pump 436, and another vacuum pump 438.

[0272] As used herein, examples of a gas supply include one or more gas containers or one or more gas sources, or one or more gas storage devices for storing one or more process gases. As used herein, examples of a valve driver include one or more transistors coupled to each other. As used herein, examples of a valve include a piston valve and a diaphragm valve.

[0273] The vacuum pumps 436 and 438 are disposed below the plasma chamber 152. For example, the vacuum pumps 436 and 438 are adjacent to the bottom wall of the plasma chamber 152. The valve 432 is disposed between the vacuum pump 436 and the interior volume of the housing of the plasma chamber 152. Furthermore, the valve 434 is disposed between the vacuum pump 438 and the interior volume of the plasma chamber 152. For example, the valves 432 and 434 are integrated into the bottom wall of the plasma chamber 152.

[0274] The processor 101 is coupled to a gas system controller 425 and a pressure system controller 427. The gas system controller 425 is coupled to a valve driver 424, which is coupled to a valve 426. The gas supply 422 is coupled to the interior volume of the housing of the plasma chamber 152 via a gas channel, such as a gas tube or gas pipe. The valve 426 is fitted within the gas channel.

[0275] The processor 101 is coupled to a pressure system controller 427, which is coupled to a valve driver 428, which is coupled to a valve 432. The pressure system controller 427 is also coupled to a valve driver 430, which is coupled to a valve 434. A pressure sensor 429 is coupled to a wall 470 of the plasma chamber 152 and is also coupled to the pressure system controller 427.

[0276] The processor 101 sends instructions to the gas system controller 425. In response to the instructions, the gas system controller 425 generates and sends control signals to the valve driver 424. Upon receiving the control signals, the valve driver 424 sends current signals to the valve 426. In response to receiving the current signals, the valve 426 opens or closes to increase, decrease, or otherwise control the supply of one or more process gases stored in the gas supply 422 to the interior volume of the plasma chamber 152 through the gas channels to process the substrate S.

[0277] Similarly, the processor 101 sends instructions to a pressure system controller 427. Upon receiving the instructions in addition to the pressure value, the pressure system controller 427 generates and sends a control signal to a valve driver 428. The pressure system controller 427 receives the pressure value within the plasma chamber 152 from a pressure sensor 429. Upon receiving the control signal, the valve driver 428 sends a current signal to a valve 432. In response to receiving the current signal, the valve 432 opens or closes to increase or decrease, etc., the output of substrate S processing residue from the interior volume of the plasma chamber 152 to outside the plasma chamber 152, into a vacuum pump 436 or an attached vessel. Examples of substrate S processing residue include process gas remaining in the plasma chamber 152 after processing the substrate S and residual plasma generated within the plasma chamber 152. Similarly, the processor 101 controls the valve 434 via the valve driver 430 to increase or decrease the output of the remaining processing residue of the substrate S from the internal volume of the plasma chamber 152 to the outside of the plasma chamber 152, into the vacuum pump 438 or a vessel attached thereto.

[0278] The valve 426 is controlled by the processor 101 in the manner described above to control the amount of pressure within the interior volume of the plasma chamber 152 and / or the amount of gas flow of one or more process gases into the interior volume of the plasma chamber 152. The amount of pressure and / or the amount of gas flow is controlled by controlling the valve 426 until the compression data described herein is within a predetermined range. For example, the amount of pressure and / or the amount of gas flow is controlled until the master maximum peak-to-peak value MMaxPTP is within a predetermined range, or the slave maximum peak-to-peak value SMaxPTP is within a predetermined range, or the master average frequency value MAVF is within a predetermined range, or the average phase value φ is within a predetermined range, or a combination of two or more thereof.

[0279] Similarly, instead of or in addition to controlling valve 426, one or more of valves 432 and 434 may be controlled by processor 101 in the manner described above to control the amount of pressure in the internal volume of plasma chamber 152 until the compression data falls within a predetermined range. For example, instead of or in addition to controlling valve 426, one or more of valves 432 and 434 may be controlled by processor 101 in the manner described above to control the amount of pressure in the internal volume of plasma chamber 152 until the master maximum peak-to-peak value MMaxPTP falls within a predetermined range, or until the slave maximum peak-to-peak value SMaxPTP falls within a predetermined range, or until the master average frequency value MAVF falls within a predetermined range, or until the average phase value φ falls within a predetermined range, or any combination of two or more thereof.

[0280] In one embodiment, instead of the analysis controller 114 controlling one or more of the valves 426, 432, and 434, the process controller 116 controls one or more of the valves 426, 432, and 434. For example, the processor 105 is coupled to the valve drivers 424, 428, and 430 instead of the processor 101. The processor 105 provides control signals to the valve driver 424 to control the gas flow and / or pressure within the interior volume of the plasma chamber 152. The processor 105 also provides control signals to the valve drivers 428 and 430 to control the pressure within the interior volume of the plasma chamber 152.

[0281] In one embodiment, plasma chamber 113 (FIG. 1A) or plasma chamber 168 (FIG. 1D) is used instead of plasma chamber 152. For example, the pressure within the interior volume of plasma chamber 113 or the interior volume of plasma chamber 168 is controlled. As another example, the amount of gas flow into the interior volume of plasma chamber 113 or the interior volume of plasma chamber 168 is controlled.

[0282] In some embodiments, the compressed data described herein facilitates rapid control synchronization of RF to improve matching, or to improve throughput and run-to-run or chamber-to-chamber repeatability through rapid transient operations, or to achieve synchronization of RF matching systems (>5 parts) through the analog domain, or to achieve tuning of gas flows. Gas flow and pressure change plasma impedance, and changes in gas flow and pressure are detectable through multiple measurement signals described herein.

[0283] 4D is a diagram of one embodiment of a system 450 to illustrate controlling the temperature in a plasma chamber 152. The system 450 includes the analysis controller 114, the process controller 116, a direct current (DC) power supply 452, a switch system 454, a switch system 458, a chamber heater system 460, a switch system 462, a window heater system 464, a DC power supply 466, a DC power supply 468, and the plasma chamber 152. The processor 101 is coupled to the switch systems 454, 458, and 462. The switch system 454 is coupled to the heater system 456 in the lower electrode 154 of the plasma chamber 152. The switch system 458 is coupled to the chamber heater system 460, and the switch system 462 is coupled to the window heater system 464.

[0284] The chamber heater system 460 is coupled to a wall 470 of the plasma chamber 152. Also, the window heater system 464 is coupled to the dielectric window 160.

[0285] As used herein, an example of a heater system includes one or more heater elements, such as one or more resistors. Another example of a heater system as used herein includes a heater array including a matrix of resistors. Examples of switch systems as described herein include one or more switches, such as one or more transistors.

[0286] DC power supply 452 is coupled to heater system 456 via switch system 454. Similarly, DC power supply 466 is coupled to chamber heater system 460 via switch system 458, and DC power supply 468 is coupled to window heater system 464 via switch system 462. Examples of DC power supplies as used herein include DC voltage sources.

[0287] The processor 101 sends an ON control signal to one or more of the switch systems 454, 458, and 462 to increase the temperature in the plasma chamber 152. Upon receiving the ON control signal, the switch system 454 connects the DC power supply 452 to one or more heater elements of the heater system 456, increasing the temperature in the plasma chamber 152. Similarly, upon receiving the ON control signal, the switch system 458 connects the DC power supply 466 to one or more heater elements of the chamber heater system 460 to heat the wall 470. The heated wall 470 increases the temperature in the plasma chamber 152. Also, upon receiving the ON control signal, the switch system 462 connects the DC power supply 468 to one or more heater elements of the window heater system 464 to heat the dielectric window 160. The heated dielectric window 160 increases the temperature in the plasma chamber 152.

[0288] Meanwhile, the processor 101 sends an OFF control signal to one or more of the switch systems 454, 458, and 462 to reduce the temperature in the plasma chamber 152. Upon receiving the OFF control signal, the switch system 454 disconnects the DC power supply 452 from one or more heater elements of the heater system 456 to cool the lower electrode 154. The cooling of the lower electrode 154 reduces the temperature in the plasma chamber 152. Similarly, upon receiving the OFF control signal, the switch system 458 disconnects the DC power supply 466 from one or more heater elements of the chamber heater system 460 to cool the wall 470. The cooling of the wall 470 reduces the temperature in the plasma chamber 152. Additionally, upon receiving the OFF control signal, the switch system 462 disconnects the DC power supply 468 from one or more heater elements of the window heater system 464 to cool the dielectric window 160. The cooling of the dielectric window 160 reduces the temperature in the plasma chamber 152. The temperature within the plasma chamber 152 is controlled, such as increased or decreased, until the processor 101 or 105 determines that the compression data described herein is within a predetermined range.

[0289] In one embodiment, the compressed data described herein facilitates over-temperature fault detection by detecting long RF on-time, or high RF power, or extremely high temperature, or high pressure, or low gas flow, or thermal runaway, or low temperature capability, or a combination thereof.

[0290] In one embodiment, the compressed data described herein is used to generate a local heating model, which can then be used to calculate the temperature within the plasma chamber 152 without using a temperature sensor, and to control the temperature within the plasma chamber 152 to cool the interior volume within the plasma chamber 152 to prevent etch degradation and reproducibility from high power.

[0291] It should be noted that the RF generator 402, or the match 404, or the gap 412, or the pressure in the plasma chamber 152, or the amount of gas flow to the plasma chamber 152, or the temperature in the plasma chamber 152, or a combination thereof, may be controlled to achieve a wafer processing benefit. Examples of achieving a wafer processing benefit include increasing the processing rate of the substrate S, or achieving uniformity in processing the substrate S, or a combination thereof. Examples of processing the substrate S include depositing material on the substrate S, or etching features in the substrate S, or sputtering the substrate S, or cleaning the substrate S, or a combination thereof.

[0292] In one embodiment, the processor 101 is coupled to the switch system 454 via a multiplexer.

[0293] In one embodiment, instead of the analysis controller 114 controlling the heater system 456, the process controller 116 controls the heater system 456. For example, the processor 105 is coupled to the switch system 454 instead of the processor 101. The processor 105 provides on and off control signals to the switch system 454 to increase or decrease, for example, control, the temperature within the interior volume of the plasma chamber 152.

[0294] In one embodiment, plasma chamber 113 (FIG. 1A) or plasma chamber 168 (FIG. 1D) is used instead of plasma chamber 152. For example, the temperature within the interior volume of plasma chamber 113 or the temperature within the interior volume of plasma chamber 168 is controlled.

[0295] FIG. 5 is a diagram of one embodiment of a system 500 to illustrate details of the plasma source 173. The system 500 includes the matchless plasma source 173, the connection 175, and the plasma chamber 113. The MPS 173 includes an input 502, an output 504, and a reactance circuit 506. Examples of the input 502 include a signal generator and a portion of a gate driver. Examples of the signal generator include a square wave oscillator that generates a square wave signal, such as a digital waveform or a pulse train. The square wave pulses between a first logic level, such as a high level or one, and a second logic level, such as a low level or zero. Examples of the output 504 include the remainder of the gate driver and a half-bridge transistor circuit. Additionally, an example of the reactance circuit 206 includes a variable capacitor. Another example of the reactance circuit 206 includes a fixed capacitor.

[0296] Input 502 is coupled to output 504, which is further coupled to reactance circuit 506. Reactance circuit 506 is coupled to electrode 115 via connection 175.

[0297] The input unit 202 generates a plurality of square wave signals and provides the square wave signals to the output unit 204. The output unit 204 generates an amplified square waveform from the plurality of square wave signals received from the input unit 202. Furthermore, the output unit 204 shapes the envelope, such as the peak-to-peak magnitude, of the amplified square waveform. For example, the input unit 502 provides a shaping control signal 508 to the output unit 504 to generate the envelope. The shaping control signal 508 has a plurality of voltage values for shaping the amplified square waveform.

[0298] The shaped amplified rectangular waveform is sent from output 504 to reactance circuit 506. Reactance circuit 506 filters out higher harmonics of the amplified rectangular waveform to generate RF signal 177, which is a shaped sinusoidal waveform having a fundamental frequency. The shaped sinusoidal waveform has a shaped envelope.

[0299] The shaped sinusoidal waveform is transmitted from reactance circuit 506 via connection 175 to electrode 115 for processing substrate S. One or more process materials, such as, for example, a fluorine-containing gas, an oxygen-containing gas, a nitrogen-containing gas, or a liquid for metal and dielectric deposition, are supplied to plasma chamber 115. Upon receiving the shaped sinusoidal waveform and the one or more process materials, a plasma is ignited in plasma chamber 113 to process substrate S. An example of an MPS 173 is shown in U.S. Patent No. 10,264,663, which is incorporated herein by reference in its entirety.

[0300] In some embodiments, the input section 502 includes a controller board having a signal generator and further includes a gate driver, and the output section includes a half-bridge transistor circuit, and the controller board includes a controller coupled to the signal generator to control the signal generator to generate a square wave signal at a predetermined frequency.

[0301] The embodiments described herein may be implemented in a variety of computer system configurations, including handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, etc. The embodiments may also be practiced in distributed computing environments where tasks are performed by remote processing hardware units that are linked through a network.

[0302] In some implementations, the controller is part of a system that may be part of the examples described above. Such systems may include semiconductor processing equipment, such as one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems are integrated with electronics for controlling pre-, during-, and post-processing operations of semiconductor wafers or substrates. This electronics is referred to as a "controller," which may control various components and subcomponents of one or more systems. Depending on the processing requirements and / or the type of system, the controller is programmed to control any of the processes disclosed herein, such as supply of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid supply settings, position and operation settings, wafer transfer into and out of the tool, and wafer transfer into and out of other transfer tools and / or load locks connected or interfacing with the system.

[0303] Broadly speaking, in various embodiments, a controller is defined as an electronic device having various integrated circuits, logic, memory, and / or software that, for example, receive instructions, issue instructions, control operations, enable cleaning operations, and enable endpoint measurement. Integrated circuits include chips that store program instructions in firmware format, chips defined as digital signal processors (DSPs), application-specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers (e.g., software) that execute the program instructions. Program instructions are instructions communicated to the controller in the form of various personalizations (or program files) that define operational parameters for performing a particular process on or for a semiconductor wafer or for a system. The operational parameters, in some embodiments, are part of a recipe defined by a process engineer to accomplish one or more processing steps during the manufacture of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer types.

[0304] The controller, in some embodiments, is part of or coupled to a computer that is integrated into, coupled to, or otherwise networked to the system, or a combination thereof. For example, the controller may be in the "cloud" or may be all or part of a host computer system in a fab that allows remote access to wafer processing. This computer provides remote access to the system to monitor the current progress of manufacturing operations, review the history of past manufacturing operations, review trends or performance metrics from multiple manufacturing operations, modify parameters of a current process, set up processing steps following a current process, or initiate a new process.

[0305] In some embodiments, a remote computer (e.g., a server) provides process recipes to the system over a network, including a local network or the Internet. The remote computer includes a user interface that allows for input or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data defining parameters for each process step performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed or the type of tool the controller is configured to interface with or control. Thus, as described above, the controller may be distributed, such as by including one or more individual controllers networked together and working toward a common purpose, such as the process or control described herein. An example of a distributed controller for such purposes includes one or more integrated circuits on a chamber that communicate with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer) combined to control the process on the chamber.

[0306] Without being limited thereto, in various embodiments, exemplary systems include plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, clean chambers or modules, bevel edge etch chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etch (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing systems associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0307] It is further noted that in some embodiments, the operations described above apply to several types of plasma chambers, such as plasma chambers including inductively coupled plasma (ICP) reactors, capacitively coupled plasma chambers, transformer coupled plasma chambers, capacitively coupled plasma reactors, conductor tools, dielectric tools, plasma chambers including electron cyclotron resonance (ECR) reactors, etc.

[0308] As described above, depending on the processing step or steps being performed by the tool, the controller may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, other controllers, or tools used in material transport to transport containers of wafers into and out of tool locations and / or load ports within a semiconductor fabrication factory.

[0309] With the above embodiments in mind, it should be understood that some of the embodiments employ various computer-implemented operations involving data stored in computer systems. These operations physically manipulate physical quantities. Any of the operations described herein that form part of the embodiments are useful machine operations.

[0310] Some of the embodiments also relate to a hardware unit or apparatus for performing these operations, which is specially configured for a special purpose computer. When defined as a special purpose computer, the computer is operable for a special purpose, but performs other processes, programs, or routines that are not part of the special purpose.

[0311] In some embodiments, these operations may be processed by a computer selectively activated or configured by one or more computer programs stored in a computer memory or cache, or obtained over a computer network. If the data is obtained over a computer network, the data may be processed by other computers on the computer network, e.g., a cloud of computing resources.

[0312] One or more embodiments may also be fabricated as computer-readable code on a non-transitory computer-readable medium. A non-transitory computer-readable medium is any data storage hardware unit, such as a memory device, that is subsequently read by a computer system. Examples of non-transitory computer-readable media include hard drives, network-attached storage (NAS), ROM, RAM, compact disc-ROMs (CD-ROMs), recordable CDs (CD-Rs), rewritable CDs (CD-RWs), magnetic tapes, and other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer-readable medium comprises tangible computer-readable media distributed over network-coupled computer systems such that the computer-readable code is stored and executed in a distributed manner.

[0313] It should be understood that although the method operations above have been described in a particular order, in various embodiments other housekeeping operations may be performed between operations, the method operations may be adjusted to occur at slightly different times, may be distributed within a system that allows the method operations to occur at various intervals, or may be performed in a different order than described above.

[0314] It should also be noted that in an embodiment, one or more features from any of the above-described embodiments may be combined with one or more features of any other embodiment without departing from the scope of the various embodiments described in this disclosure.

[0315] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of the appended claims. The present embodiments are therefore to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details set forth herein, but may be modified within the scope of the appended claims and their equivalents.

Claims

1. 1. A method for compressing data, comprising: receiving a plurality of measurement signals from one or more sensors coupled to a radio frequency (RF) transmission line of the plasma tool from an output of an RF generator to an electrode of the plasma tool; converting the plurality of measurement signals from analog format to digital format to provide sample data; processing the sample data to output compressed data; transmitting the compressed data to a controller for controlling the plasma tool; A method comprising:

2. 2. The method of claim 1, wherein receiving the plurality of measurement signals comprises: receiving a first electrical signal representative of a first parameter associated with the first RF signal; receiving a second electrical signal representative of a second parameter associated with the second RF signal; Including, converting the plurality of measurement signals sampling the first electrical signal to output a first plurality of sample sets including a first master sample set and a second master sample set; sampling the second electrical signal to output a second plurality of sample sets including a first slave sample set and a second slave sample set; Including, processing the sample data, determining that the first master sample set has the largest amplitude of the first master sample set and the second master sample set; identifying the first slave sample set as corresponding to the first master sample set; determining at least one of a maximum magnitude, a minimum magnitude, a time of a positive crossing, and a time of a negative crossing from the first slave sample set; A method comprising:

3. 2. The method of claim 1, wherein receiving the plurality of measurement signals comprises: receiving a first electrical signal representative of a first parameter associated with the first RF signal; receiving a second electrical signal representative of a second parameter associated with the second RF signal; Including, converting the plurality of measurement signals sampling the first electrical signal to output a first plurality of sample sets including a first master sample set and a second master sample set; sampling the second electrical signal to output a second plurality of sample sets including a first slave sample set and a second slave sample set; Including, processing the sample data, determining that the first master sample set has the largest swing between the first master sample set and the second master sample set; or determining a maximum size of the first master sample set; or determining, from the maximum magnitude of the first master sample set and the maximum magnitude of the second master sample set, that the maximum magnitude of the second master sample set is the largest; or determining a minimum size of the first master sample set; or determining that the minimum magnitude is the minimum of the minimum magnitude of the first master sample set and the minimum magnitude of the second master sample set; or determining the location of a positive crossing within the first master sample set; or determining the location of a negative crossing within the first master sample set; or determining the sum of the differences between the positive and negative crossings of the first master sample set and the second master sample set; or A combination of two or more of the above determinations A method comprising:

4. 2. The method of claim 1, wherein receiving the plurality of measurement signals comprises: receiving a first electrical signal representative of a first parameter associated with the first RF signal; receiving a second electrical signal representative of a second parameter associated with the second RF signal; Including, converting the plurality of measurement signals sampling the first electrical signal to output a first plurality of sample sets including a first master sample set and a second master sample set; sampling the second electrical signal to output a second plurality of sample sets including a first slave sample set and a second slave sample set; Including, processing the sample data, determining that the first slave sample set has the largest swing of the first slave sample set and the second slave sample set; or determining a maximum size of the first slave sample set; or determining, from the maximum magnitude of the first slave sample set and the maximum magnitude of the second slave sample set, that the maximum magnitude of the second slave sample set is the greatest; or determining a minimum size of the first slave sample set; or determining that the minimum magnitude is the minimum of the minimum magnitude of the first slave sample set and the minimum magnitude of the second slave sample set; or determining a location of a positive crossing within the first slave sample set; or determining a location of a negative crossing within the first slave sample set; or determining the sum of the differences between the positive and negative crossings of the first slave sample set and the second slave sample set; or A combination of two or more of the above determinations A method comprising:

5. 10. The method of claim 1, receiving the plurality of measurement signals; receiving a first electrical signal representative of a first parameter associated with the first RF signal; receiving a second electrical signal representative of a second parameter associated with the second RF signal; Including, converting the plurality of measurement signals sampling the first electrical signal to output a first plurality of sample sets; sampling the second electrical signal to output a second plurality of sample sets; Including, processing the sample data, determining a first maximum peak-to-peak value from the first plurality of sample sets; or determining a second maximum peak-to-peak value from the second plurality of sample sets; or determining a statistical frequency value from the first plurality of sample sets; or determining a statistical phase value from the first plurality of sample sets and the second plurality of sample sets; or A combination of two or more of the above determinations A method comprising:

6. 6. The method of claim 5, a sampling of the first electrical signal and a sampling of the second electrical signal are performed synchronously with a clock signal, and a determination of the first maximum peak-to-peak value, a determination of the second maximum peak-to-peak value, a determination of the statistical frequency value, and a determination of the statistical phase value are performed synchronously with the clock signal.

7. 6. The method of claim 5, subsequent use of the first plurality of sample sets and the second plurality of sample sets after processing the sample data to determine the first maximum peak-to-peak value, the second maximum peak-to-peak value, the statistical frequency value, and the statistical phase value; 20. A method comprising:

8. 6. The method of claim 5, the transmitting of the compressed data includes transmitting the first maximum peak-to-peak value, the second maximum peak-to-peak value, the statistical frequency value, and the statistical phase value to the controller for controlling the plasma tool based on one or more of the first maximum peak-to-peak value, the second maximum peak-to-peak value, the statistical frequency value, and the statistical phase value.

9. 6. The method of claim 5, the first RF signal is transmitted from the RF generator through an RF cable to an impedance matching circuit; the second RF signal is reflected from the plasma chamber through the impedance matching circuit toward the RF generator; method.

10. 6. The method of claim 5, the first RF signal is transmitted from the RF generator through an RF cable to an impedance matching circuit; the second RF signal is transmitted from the impedance matching circuit to a plasma chamber via an RF transmission line; method.

11. 6. The method of claim 5, processing the sample data includes determining a maximum value and a minimum value for each of the first plurality of sample sets; the first maximum peak-to-peak value is determined from maximum and minimum values determined from the first plurality of sample sets; processing the sample data includes determining a maximum value and a minimum value for each of the second plurality of sample sets; The method wherein the second maximum peak-to-peak value is determined from maximum and minimum values determined from the second plurality of sample sets.

12. 6. The method of claim 5, wherein the processing of the sample data comprises: determining a maximum value and a minimum value for each of the first plurality of sample sets; and determining, for each of the first plurality of sample sets, a time associated with the maximum value and a time associated with the minimum value, wherein the statistical frequency value is determined based on each time associated with each of the maximum values of the first plurality of sample sets and based on each time associated with each of the minimum values of the first plurality of sample sets.

13. 6. The method of claim 5, wherein the processing of the sample data comprises: determining a maximum value and a minimum value for each of the first plurality of sample sets; determining a maximum value and a minimum value for each of the second plurality of sample sets; determining, for each of the first plurality of sample sets, a time associated with the maximum value and a time associated with the minimum value; determining, for each of the second plurality of sample sets, a time associated with the maximum value and a time associated with the minimum value; a statistical phase value determined from each time associated with each of the maximum values of the first plurality of sample sets, each time associated with each of the maximum values of the second plurality of sample sets, each time associated with each of the minimum values of the first plurality of sample sets, and each time associated with each of the minimum values of the second plurality of sample sets.

14. 6. The method of claim 5, wherein the processing of the sample data comprises: determining, for each of the first plurality of sample sets, a time associated with a positive zero crossing and a time associated with a negative zero crossing; the statistical frequency value is determined based on each time associated with each of the positive zero crossings of the first plurality of sample sets and based on each time associated with each of the negative zero crossings of the first plurality of sample sets.

15. 6. The method of claim 5, wherein the processing of the sample data comprises: determining, for each of the first plurality of sample sets, a time associated with a positive zero crossing and a time associated with a negative zero crossing; determining, for each of the second plurality of sample sets, a time associated with a positive zero crossing and a time associated with a negative zero crossing; the statistical phase value is determined from each time associated with each positive zero crossing of the first plurality of sample sets, each time associated with each positive zero crossing of the second plurality of sample sets, each time associated with each negative zero crossing of the first plurality of sample sets, and each time associated with each negative zero crossing of the second plurality of sample sets.

16. 10. The method of claim 1, wherein the plasma tool comprises: a plasma control state determined based on the compressed data; or an RF transition sequence determined based on the compressed data; or an RF trigger event determined based on the compressed data; or an RF precursor event determined based on the compressed data; or an RF impairment event determined based on the compressed data; or combinations of these Control based on A method that facilitates achieving wafer processing benefits by controlling the plasma control state, or the RF trigger event, or pressure in the plasma chamber, or gas flow in the plasma chamber, or impedance matching circuit, or temperature in the plasma chamber, or control or gap in the plasma chamber, or a combination thereof.

17. 10. The method of claim 1, wherein one of the one or more sensors is coupled between an output of an impedance matching circuit and the electrode, and the impedance matching circuit is coupled to an output of the RF generator.

18. The method of claim 1 , wherein one of the one or more sensors is located within the RF generator.

19. The method of claim 1 , wherein one of the one or more sensors is disposed within a match coupled to the RF generator.

20. 1. An integrated compression system for compressing data, comprising: an analog-to-digital converter configured to receive a plurality of measurement signals from one or more sensors coupled to a radio frequency (RF) transmission path of the plasma tool from an output of an RF generator to an electrode of the plasma tool, and convert the plurality of measurement signals from an analog format to a digital format to provide sample data; a data compression unit coupled to the analog-to-digital converter and configured to output compressed data by processing the sample data; a transmitter coupled to the data compression unit and configured to transmit the compressed data to a controller for controlling the plasma tool; A compression integrated system, including:

21. 21. The compression integration system of claim 20, wherein the analog-to-digital converter for receiving the plurality of measurement signals comprises: receiving a first electrical signal representative of a first parameter associated with the first RF signal; configured to receive a second electrical signal representative of a second parameter associated with the second RF signal; To convert the plurality of measurement signals, the analog-to-digital converter sampling the first electrical signal to output a first plurality of sample sets including a first master sample set and a second master sample set; configured to sample the second electrical signal to output a second plurality of sample sets including a first slave sample set and a second slave sample set; To process the sample data, the data compression unit determining that the first master sample set has the largest amplitude of the first master sample set and the second master sample set; Identifying the first slave sample set as corresponding to the first master sample set; A compression synthesis system configured to determine at least one of a maximum magnitude, a minimum magnitude, a time of a positive crossing, and a time of a negative crossing from the first slave sample set.

22. 21. The compression integration system of claim 20, wherein the analog-to-digital converter for receiving the plurality of measurement signals comprises: receiving a first electrical signal representative of a first parameter associated with the first RF signal; configured to receive a second electrical signal representative of a second parameter associated with the second RF signal; To convert the plurality of measurement signals, the analog-to-digital converter sampling the first electrical signal to output a first plurality of sample sets including a first master sample set and a second master sample set; configured to sample the second electrical signal to output a second plurality of sample sets including a first slave sample set and a second slave sample set; To process the sample data, the data compression unit determining that the first master sample set has the largest swing between the first master sample set and the second master sample set; or determining a maximum size of said first master sample set; or determining from the maximum magnitude of the first master sample set and the maximum magnitude of the second master sample set that the maximum magnitude of the second master sample set is the largest; or determining a minimum size of the first master sample set; or determining that the minimum magnitude is the minimum of the minimum magnitude of the first master sample set and the minimum magnitude of the second master sample set; or determining the location of a positive crossing within said first master sample set; or determining the location of a negative crossing within said first master sample set; or determining the sum of the differences between the positive and negative crossings of the first master sample set and the second master sample set; or A compression synthesis system configured to perform a combination of two or more of said determinations.

23. 21. The compression integration system of claim 20, wherein the analog-to-digital converter for receiving the plurality of measurement signals comprises: receiving a first electrical signal representative of a first parameter associated with the first RF signal; configured to receive a second electrical signal representative of a second parameter associated with the second RF signal; To convert the plurality of measurement signals, the analog-to-digital converter sampling the first electrical signal to output a first plurality of sample sets including a first master sample set and a second master sample set; configured to sample the second electrical signal to output a second plurality of sample sets including a first slave sample set and a second slave sample set; To process the sample data, the data compression unit determining that the first slave sample set has the largest swing between the first slave sample set and the second slave sample set; or determining a maximum size of said first slave sample set; or determining from the maximum magnitude of the first slave sample set and the maximum magnitude of the second slave sample set that the maximum magnitude of the second slave sample set is the largest; or determining a minimum size of said first slave sample set; or determining that the minimum magnitude is the minimum of the minimum magnitude of the first slave sample set and the minimum magnitude of the second slave sample set; or determining the location of a positive crossing within said first slave sample set; or determining the location of a negative crossing within said first slave sample set; or determining the sum of the differences between the positive and negative crossings of the first slave sample set and the second slave sample set; or A compression synthesis system configured to perform a combination of two or more of said determinations.

24. 21. The compression and integration system of claim 20, wherein the analog-to-digital converter is configured to convert the plurality of measurement signals from analog format to digital format synchronously with a clock signal.

25. 21. The compression and integration system of claim 20, The analog-to-digital converter receives the plurality of measurement signals. receiving a first electrical signal representative of a first parameter associated with the first RF signal; configured to receive a second electrical signal representative of a second parameter associated with the second RF signal; To convert the plurality of measurement signals, the analog-to-digital converter sampling the first electrical signal to output a first plurality of sample sets; configured to sample the second electrical signal to output a second plurality of sample sets; To process the data, the data compression unit determining a first maximum peak-to-peak value from the first plurality of sample sets; or determining a second maximum peak-to-peak value from the second plurality of sample sets; or determining a statistical frequency value from the first plurality of sample sets; or determining a statistical phase value from the first plurality of sample sets and the second plurality of sample sets; or A compression synthesis system configured to perform a combination of two or more of said determinations.

26. 21. The compression and consolidation system of claim 20, wherein the data compression unit is configured to disable further use of the first plurality of sample sets and the second plurality of sample sets after determining the first maximum peak-to-peak value, the second maximum peak-to-peak value, the statistical frequency value, and the statistical phase value.

27. 21. The compression and synthesis system of claim 20, wherein the compressed data includes the first maximum peak-to-peak value, the second maximum peak-to-peak value, the statistical frequency value, and the statistical phase value.

28. 21. The compression and integration system of claim 20, the first RF signal is transmitted from the RF generator through an RF cable to an impedance matching circuit; A compression-integrated system, wherein the second RF signal is reflected from the plasma chamber through the impedance matching circuit toward the RF generator.

29. 21. The compression and integration system of claim 20, the first RF signal is transmitted from the RF generator through an RF cable to an impedance matching circuit; The compression integrated system, wherein the second RF signal is transmitted from the impedance matching circuit to a plasma chamber via an RF transmission line.

30. 21. The compression and integration system of claim 20, To process the sample data, the data compression unit is configured to determine a maximum value and a minimum value for each of the first plurality of sample sets; the first maximum peak-to-peak value is determined from the maximum and minimum values determined from the first plurality of sample sets; To process the sample data, the data compression unit is configured to determine a maximum value and a minimum value for each of the second plurality of sample sets; The compression synthesis system, wherein the second maximum peak-to-peak value is determined from the maximum and minimum values determined from the second plurality of sample sets.

31. 21. The compression and integration system of claim 20, To process the sample data, the data compression unit determining a maximum value and a minimum value for each of the first plurality of sample sets; configured to determine, for each of the first plurality of sample sets, a time associated with the maximum value and a time associated with the minimum value; 10. A compression synthesis system, wherein the statistical frequency values are determined based on each time associated with each of the maximum values of the first plurality of sample sets and based on each time associated with each of the minimum values of the first plurality of sample sets.

32. 21. The compression and integration system of claim 20, To process the sample data, the data compression unit determining a maximum value and a minimum value for each of the first plurality of sample sets; determining, for each of the first plurality of sample sets, a time associated with the maximum value and a time associated with the minimum value; determining a maximum value and a minimum value for each of the second plurality of sample sets; configured to determine, for each of the second plurality of sample sets, a time associated with the maximum value and a time associated with the minimum value; a compression synthesis system, wherein the statistical phase value is determined from each time associated with each of the maximum values of the first plurality of sample sets, each time associated with each of the maximum values of the second plurality of sample sets, each time associated with each of the minimum values of the first plurality of sample sets, and each time associated with each of the minimum values of the second plurality of sample sets.

33. 21. The compression and integration system of claim 20, to process the sample data, the data compression unit is configured to determine, for each of the first plurality of sample sets, a time associated with a positive zero crossing and a time associated with a negative zero crossing; the statistical frequency values are determined based on respective times associated with each of the positive zero crossings of the first plurality of sample sets and based on respective times associated with each of the negative zero crossings of the first plurality of sample sets.

34. 21. The compression and integration system of claim 20, To process the sample data, the data compression unit determining, for each of the first plurality of sample sets, a time associated with a positive zero crossing and a time associated with a negative zero crossing; configured to determine, for each of the second plurality of sample sets, a time associated with a positive zero crossing and a time associated with a negative zero crossing; a compression synthesis system, wherein the statistical phase value is determined from each time associated with each of the positive zero crossings of the first plurality of sample sets, each time associated with each of the positive zero crossings of the second plurality of sample sets, each time associated with each of the negative zero crossings of the first plurality of sample sets, and each time associated with each of the negative zero crossings of the second plurality of sample sets.

35. 1. A system for data compression, comprising: a radio frequency (RF) generator coupled to the RF path and configured to provide a first RF signal to the RF path; an RF sensor coupled to the RF path and configured to output a plurality of measurement signals by sensing the first RF signal and the second RF signal; a data integration system coupled to the RF sensor, converting the plurality of measurement signals from analog format to digital format to obtain sample data; outputting compressed data by processing the sample data; a data integration system configured to transmit the compressed data to a controller for controlling the system; Including, the system.

36. 36. The system of claim 35, wherein for receiving a plurality of measurement signals, the data integration system comprises: receiving a first electrical signal representative of a first parameter associated with the RF signal; configured to receive a second electrical signal representative of a second parameter associated with the RF signal; To convert the plurality of measurement signals, the data integration system comprises: sampling the first electrical signal to output a first plurality of sample sets; configured to sample the second electrical signal to output a second plurality of sample sets; To process the data, the data integration system: determining a first maximum peak-to-peak value from the first plurality of sample sets; or determining a second maximum peak-to-peak value from the second plurality of sample sets; or determining a statistical frequency value from the first plurality of sample sets; or determining a statistical phase value from the first plurality of sample sets and the second plurality of sample sets; or A system configured to perform a combination of two or more of said determinations.

37. 37. The system of claim 36, the data integration system is configured to disable subsequent use of the first plurality of sample sets and the second plurality of sample sets after determining the first maximum peak-to-peak value, the second maximum peak-to-peak value, the statistical frequency value, and the statistical phase value.

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