Manufacturing method for semiconductor device

Abstract

To enable enlargement of a substrate, form an oxide semiconductor layer with improved characteristics, enable manufacture of a transistor with desired high field effect mobility, and put a large display device, a high-performance semiconductor device, and the like into practical application.SOLUTION: A manufacturing method for a transistor 150, which is a semiconductor device, includes forming a gate electrode layer 101a on a substrate 100 having an insulating surface, forming a gate insulating layer 102 on the gate electrode layer, forming an oxide semiconductor layer 106a on the gate insulating layer, forming a source electrode layer and a drain electrode layer 108a and 108b on the oxide semiconductor layer, forming an insulating layer 112 including oxygen on the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, forming an insulating layer 116 including hydrogen on the insulating layer including oxygen, and then performing a heating process, thereby supplying hydrogen in the insulating layer including hydrogen to at least the oxide semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] A semiconductor device having a circuit that includes a semiconductor element such as a transistor as at least one element. For example, the present invention relates to power devices mounted on power supply circuits and memory devices. semiconductor integrated circuits including transistors, thyristors, converters, image sensors, etc., and liquid crystal display panels. The device is equipped with electro-optical devices such as LCD panels and light-emitting display devices with organic light-emitting elements as components. This relates to electronic devices.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] As typified by liquid crystal display devices, transistors formed on glass substrates are amorphous. It is made of amorphous silicon, polycrystalline silicon, etc. Although the resulting transistor has low field-effect mobility, it can be used on large glass substrates. In addition, although the field effect mobility of a transistor using polycrystalline silicon is high, it is difficult to use a glass substrate. However, it has the drawback that it is not suitable for large areas.

[0004] For a transistor using silicon, a transistor using an oxide semiconductor is manufactured. The technology is attracting attention for its application to electronic and optical devices. For example, as an oxide semiconductor, , zinc oxide, and In-Ga-Zn-O oxide were used to fabricate transistors, and The technology used for pixel switching elements is disclosed in Patent Documents 1 and 2. do. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0006] Larger display devices are also becoming more common. Even in home televisions, the diagonal of the display screen is 4. Televisions ranging from 0 to 50 inches are also becoming popular.

[0007] The field-effect mobility of transistors using conventional oxide semiconductors is 10 to 20 cm 2 / Vs Transistors using oxide semiconductors are superior to amorphous silicon transistors. Since the field effect mobility is 10 times higher than that of conventional MOS transistors, the pixel shift can be reduced even in large display devices. As a switching element, sufficient performance can be obtained.

[0008] However, when a transistor using an oxide semiconductor is used as a driving device of a semiconductor device, for example, a large There is a limit to its use as a switching element in a drive circuit for a display device or the like.

[0009] One aspect of the present invention is to provide an oxide semiconductor substrate having improved characteristics while enabling a substrate to have a large area. By forming a dielectric layer, it is possible to manufacture a transistor having a desired high field effect mobility, and a large One of the objectives is to put display devices and high-performance semiconductor devices into practical use. [Means for solving the problem]

[0010] In one embodiment of the present invention, in a transistor including an oxide semiconductor layer in a channel formation region, The insulating layer containing oxygen in contact with the oxide semiconductor layer and the insulating layer containing hydrogen in contact with the oxygen-containing insulating layer are The insulating layer containing the oxide semiconductor layer is stacked on the gate insulating layer. At least one of the interfaces between the oxide semiconductor layer and the insulating layer containing oxygen is provided with hydrogen in the insulating layer containing hydrogen. The present invention is characterized in that the characteristics of the transistor are improved by supplying the same.

[0011] Another embodiment of the present invention is a method for forming a gate electrode layer over a substrate having an insulating surface, A gate insulating layer is formed on the electrode layer, an oxide semiconductor layer is formed on the gate insulating layer, and an oxide semiconductor A source electrode layer and a drain electrode layer are formed over the conductor layer, and the oxide semiconductor layer, the source electrode layer, and a drain electrode layer, an insulating layer containing hydrogen is formed on the insulating layer, and then a heating By performing heat treatment, hydrogen in the insulating layer containing hydrogen is supplied to at least the oxide semiconductor layer. The present invention provides a method for manufacturing a semiconductor device, comprising the steps of:

[0012] Another embodiment of the present invention is a method for forming a gate electrode layer on an insulating layer after the insulating layer is formed. A method for manufacturing a semiconductor device is characterized in that a back gate electrode is formed in the overlapping region. .

[0013] Another embodiment of the present invention is a method for forming a gate electrode layer over a substrate having an insulating surface, A gate insulating layer is formed on the electrode layer, an oxide semiconductor layer is formed on the gate insulating layer, and an oxide semiconductor An insulating layer that functions as a channel protection layer is formed on a part of the conductor layer, and the oxide semiconductor layer and A source electrode layer and a drain electrode layer are formed on the insulating layer, and the insulating layer, the source electrode layer, and the drain electrode layer are formed on the insulating layer. After forming an insulating layer containing hydrogen on the drain electrode layer, a heat treatment is performed to remove the hydrogen. a semiconductor device comprising: a first insulating layer and a second insulating layer; a second insulating layer and a third insulating layer; This is a method for producing the above.

[0014] Another embodiment of the present invention is a method for forming an oxide semiconductor layer over a substrate having an insulating surface, A source electrode layer and a drain electrode layer are formed on the oxide semiconductor layer, and An insulating layer serving as a gate insulating layer is formed over the insulating layer and the drain electrode layer. A gate electrode layer is formed, and an insulating layer containing hydrogen is formed over the insulating layer and the gate electrode layer. By performing the heat treatment, hydrogen in the insulating layer containing hydrogen is supplied to the oxide semiconductor layer. The present invention provides a method for manufacturing a semiconductor device.

[0015] In one embodiment of the present invention, a transistor using an oxide semiconductor layer for a channel formation region can be provided. In the case of the oxide semiconductor layer, after reducing the hydrogen concentration in the oxide semiconductor layer, Then, heat treatment is performed to oxidize the oxygen vacancies in the oxide semiconductor layer, resulting in an i-type (intrinsic) semiconductor. After forming an oxide semiconductor layer that is almost i-type, hydrogen is an insulating layer including the oxide semiconductor layer, At least one of the interfaces between the oxide semiconductor layer and the insulating layer containing oxygen is formed by the water in the insulating layer containing hydrogen. The present invention is characterized in that it supplies a semiconductor material to improve the characteristics of the transistor. The i-type has a carrier density of 1×10 12 cm -3 less than 1.45 x 10 10 cm -3 This means that the amount is less than the amount of the

[0016] Another embodiment of the present invention is a method for forming a gate electrode layer over a substrate having an insulating surface, A gate insulating layer is formed on the electrode layer, an oxide semiconductor layer is formed on the gate insulating layer, and then a first The hydrogen concentration in the oxide semiconductor layer is reduced by the heat treatment in step 2, and a source electrode is formed on the oxide semiconductor layer. a source electrode layer and a drain electrode layer formed on the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; After forming an insulating layer containing oxygen on the oxide semiconductor layer, oxygen is supplied to the oxide semiconductor layer by second heat treatment. After forming an insulating layer containing hydrogen over the insulating layer containing oxygen, a third heat treatment is performed. and supplying hydrogen contained in the insulating layer to at least the oxide semiconductor layer. A method for manufacturing a semiconductor device.

[0017] Another embodiment of the present invention is a method for forming an insulating layer containing oxygen, and then forming a film on the insulating layer containing oxygen. and forming a back gate electrode in a region overlapping with the gate electrode layer. A method for fabricating the device.

[0018] Another embodiment of the present invention is a method for forming a gate electrode layer over a substrate having an insulating surface, A gate insulating layer is formed on the electrode layer, an oxide semiconductor layer is formed on the gate insulating layer, and then a first The heat treatment reduces the hydrogen concentration in the oxide semiconductor layer, and the hydrogen is deposited on part of the oxide semiconductor layer. After forming an insulating layer containing oxygen that functions as a channel protection layer, the insulating layer is oxidized by a second heat treatment. Oxygen is supplied to the oxide semiconductor layer, and a source electrode layer and a and forming a source electrode layer and a drain electrode layer on the insulating layer containing oxygen, the source electrode layer, and the drain electrode layer. After the insulating layer containing hydrogen is formed, a third heat treatment is performed to remove hydrogen from the insulating layer containing hydrogen. and supplying hydrogen to at least an oxide semiconductor layer. be.

[0019] In another embodiment of the present invention, after an oxide semiconductor layer is formed over a substrate having an insulating surface, The first heat treatment reduces the hydrogen concentration in the oxide semiconductor layer, and a source An electrode layer and a drain electrode layer are formed, and an oxide semiconductor layer, a source electrode layer, and a drain electrode layer are formed. An insulating layer containing oxygen that functions as a gate insulating layer is formed on the insulating layer, and then a second heat treatment is performed. oxygen is supplied to the oxide semiconductor layer, a gate electrode layer is formed over the insulating layer containing oxygen, and oxygen is supplied to the oxide semiconductor layer. After forming an insulating layer containing hydrogen over the insulating layer containing hydrogen and the gate electrode layer, a third heat treatment is performed. By performing the above process, at least hydrogen in the insulating layer containing hydrogen is supplied to the oxide semiconductor layer. The present invention provides a method for manufacturing a semiconductor device.

[0020] After forming an insulating layer containing hydrogen over the insulating layer containing oxygen in contact with the oxide semiconductor layer, By heat treating at a temperature of 250°C or higher and 450°C or lower, preferably 250°C or higher and 440°C or lower, the interface between the oxide insulating layer and the oxide semiconductor layer, the oxide semiconductor layer, and the oxide semiconductor layer and the oxide semiconductor layer containing oxygen It is possible to supply hydrogen to at least one of the interfaces of the insulating layer containing hydrogen. The supplied hydrogen terminates defects or dangling bonds in the oxide semiconductor layer. As a result, the on-state current and field-effect mobility of the transistor can be increased. It is possible to do this.

[0021] The heat treatment is performed in a furnace or by using the rapid thermal annealing method (RTA method). The RTA method is divided into two types: one that uses a lamp light source and one that moves the substrate through a heated gas to create a short circuit. The RTA method reduces the time required for heat treatment to less than 0.1 hours. It may also be possible to shorten the time.

[0022] The insulating layer containing oxygen is a silicon oxide layer formed by sputtering or CVD. A silicon oxynitride layer is preferred, and a silicon oxide layer formed by a sputtering method is particularly preferred. A silicon layer is more preferred.

[0023] The hydrogen-containing insulating layer is a silicon nitride layer formed by sputtering or CVD. A silicon nitride oxide layer, an aluminum nitride layer, or an aluminum nitride oxide layer is particularly preferred. At least silane and a gas containing nitrogen (typically, nitrogen gas, ammonia gas, etc.) are mixed. The silicon nitride layer or silicon oxynitride layer formed by the CVD method using the same gas as the source gas is It is preferable because it contains a relatively large amount of hydrogen atoms. and aluminum nitride layer formed by CVD using at least the above as raw material gas. The aluminum layer is preferable because it contains a relatively large amount of hydrogen atoms. The insulating layer containing hydrogen is an insulating layer containing more hydrogen than an insulating layer in contact with an oxide semiconductor layer. For example, the hydrogen concentration in an insulating layer containing hydrogen is 1×10 19 atoms / cm 3 More than 1×10 22 atoms / cm 3 It is preferable to do the following:

[0024] The oxide semiconductor layer is a metal oxide, and is a quaternary metal oxide, In-Sn-Ga-Zn- O-based, ternary metal oxides such as In-Ga-Zn-O-based, In-Sn-Zn-O-based, and I n-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al -Zn-O system, binary metal oxides such as In-Zn-O system, Sn-Zn-O system, and Al- Zn-O system, Zn-Mg-O system, Sn-Mg-O system, In-Mg-O system, In-O system, Sn-O based, Zn-O based, etc. can be used.

[0025] The oxide semiconductor layer is InMO3(ZnO) m It is possible to use materials expressed as (m>0) Here, M is one or more metal elements selected from Ga, Al, Mn, and Co. For example, M may be Ga, Ga and Al, Ga and Mn, or Ga and Co. There are some.

[0026] The oxide semiconductor layer is In-M X -Zn Y -O Z Acid expressed as (Y=0.5~5) M may be gallium (Ga) or aluminum (Al). It represents one or more elements selected from the group 13 elements such as fluorine (F) and boron (B). The contents of In, M, Zn, and O are arbitrary, and the content of M is zero (i.e., X=0). On the other hand, the contents of In and Zn are not zero. , In-Ga-Zn-O, In-Zn-O, etc.

[0027] The oxide semiconductor layer can have an amorphous structure or a structure including a crystalline region in an amorphous region. By making the oxide semiconductor layer amorphous, it is possible to reduce the variation in characteristics among multiple elements. In addition, when the oxide semiconductor layer has a structure in which a crystalline region is included in an amorphous region, the By doing so, a transistor having higher field-effect mobility and on-state current can be obtained. .

[0028] Furthermore, in a transistor in which an oxide semiconductor layer is used in a channel formation region, The temperature is 750°C or less, preferably 400°C or more and less than the strain point of the substrate, and the temperature is such that the substrate contains almost no hydrogen or moisture. In an atmosphere free from moisture (nitrogen atmosphere, oxygen atmosphere, dry air atmosphere) The first heat treatment is performed at a temperature of −40° C. or lower, preferably at a dew point of −50° C. or lower, to form an oxide. The hydrogen concentration in the semiconductor layer is reduced. Next, an insulating layer containing oxygen is formed in contact with the oxide semiconductor layer. After that, a second heat treatment (preferably a second heat treatment) is carried out in an inert gas atmosphere or an oxygen gas atmosphere. The oxide semiconductor layer is then heated at a temperature of 00°C or higher and 450°C or lower, for example, 250°C or higher and 350°C or lower. By supplying oxygen to the oxygen vacancies, an i-type (intrinsic semiconductor) or an oxide semiconductor that is very close to i-type is formed. Next, an insulating layer containing hydrogen is formed on the insulating layer containing oxygen, and the insulating layer is heated at 150° C. or higher for 4 By carrying out the third heat treatment at 50°C or less, preferably 250°C or more and 440°C or less, the gate the interface between the oxide insulating layer and the oxide semiconductor layer, the oxide semiconductor layer, and the oxide semiconductor layer and the oxide semiconductor layer containing oxygen and supplying hydrogen from the insulating layer containing hydrogen to at least one interface of the insulating layer containing the oxide semiconductor layer. By terminating defects or dangling bonds contained in the material with hydrogen, it is possible to improve the characteristics of the transistor. can.

[0029] In the first heat treatment, impurities such as moisture and hydrogen contained in the oxide semiconductor layer are reduced, and By purifying it, it becomes an i-type (intrinsic semiconductor) or an oxide semiconductor that is as close to i-type as possible. The oxide semiconductor layer is an i-type (intrinsic semiconductor) or an oxide semiconductor layer that is very close to i-type. The hydrogen concentration was measured by secondary ion mass spectrometry (SIMS). Spectroscopy) measurements show a value of 1×10 18 cm -3 The following is preferably is 1 x 10 16 cm -3 Below that, it is practically 0. Also, i-type (intrinsic semiconductor) The carrier density of an oxide semiconductor that is close to i-type can be measured by Hall effect measurement or CV measurement. (Capacitance-Voltage-Measurement) is 1 x 10 12 cm -3 less than 1.45 × 10 10 cm -3 is less than In other words, the carrier density of the oxide semiconductor layer is close to zero. The band gap of the oxide semiconductor (i-type) or the oxide semiconductor that is as close to i-type as possible is 2 eV or more, preferably 2 It is preferably 0.5 eV or more, and more preferably 3 eV or more.

[0030] Specifically, as described above, a transistor using a highly purified oxide semiconductor layer for a channel formation region is For example, the transistor has a channel width W of 1×10 4 The device has a channel length of 3 μm and a width of 1 μm. Even if the off-state current is 10 -13 A or less, subthreshold swing value (S value) is 0.1 Therefore, the gate electrode The off-state current when the voltage between the source electrode layer and the source electrode layer is almost zero, that is, the leakage current, This is significantly lower than that of a transistor using crystalline silicon. For example, in the case of an N-channel transistor, the off-state current is the voltage between the gate and source. This refers to the source-drain current when the voltage is -5V.

[0031] Another embodiment of the present invention is a semiconductor device including a gate electrode layer and a gate electrode layer formed over a substrate having an insulating surface. a gate insulating layer on the gate insulating layer, an oxide semiconductor layer on the gate insulating layer, and a source electrode on the oxide semiconductor layer. an insulating layer containing oxygen and in contact with the electrode layer or drain electrode layer and the oxide semiconductor layer; and an insulating layer containing hydrogen that is on and in contact with an insulating layer containing hydrogen.

[0032] The transistor may be a bottom gate type or a top gate type, A bottom-gate transistor may be a bottom-contact type. a gate insulating layer on the gate electrode layer; a gate insulating layer on the gate electrode layer; and a source electrode layer and a drain electrode layer over the oxide semiconductor layer.

[0033] A top-gate transistor has an oxide semiconductor layer on a substrate and a gate on the oxide semiconductor layer. an insulating layer; a gate electrode layer that is on the gate insulating layer and overlaps with the oxide semiconductor layer; and a source electrode The gate electrode layer and the drain electrode layer are also included.

[0034] A bottom-contact transistor has a gate electrode layer on the substrate and a gate an insulating layer, a source electrode layer and a drain electrode layer on the gate insulating layer, and The oxide semiconductor layer is on the gate electrode layer and overlaps the gate electrode layer on the gate insulating layer. and a body layer. [Effects of the Invention]

[0035] The on-state current and field-effect mobility of the transistor can be improved. and improving the on-current, thereby improving the on-off ratio of the transistor. Using such transistors, large-scale display devices and high-performance semiconductor devices can be realized. Manifest. [Brief explanation of the drawings]

[0036] [Figure 1] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 2] 1A to 1C are cross-sectional process diagrams illustrating one embodiment of the present invention. [Figure 3] 1A to 1C are cross-sectional process diagrams illustrating one embodiment of the present invention. [Figure 4] 1A to 1C are cross-sectional process diagrams illustrating one embodiment of the present invention. [Figure 5] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 6] 1A to 1C are cross-sectional process diagrams illustrating one embodiment of the present invention. [Figure 7] 1A to 1C are cross-sectional process diagrams illustrating one embodiment of the present invention. [Figure 8] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 9] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 10] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 11] FIG. 1 illustrates an example of an electronic device. [Figure 12] FIG. 1 illustrates an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0037] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and the embodiments and aspects thereof may be modified without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0038] The present invention is applicable to integrated circuits such as microprocessors and image processing circuits, RF tags, semiconductors, etc. The semiconductor device can be used to manufacture various semiconductor devices such as display devices. It refers to all devices that can function by utilizing semiconductor characteristics, including semiconductor display devices, semiconductor circuits, etc. All electronic devices are semiconductor devices. Semiconductor display devices include liquid crystal display devices, organic light-emitting devices, Light-emitting devices with light-emitting elements, such as OLEDs, in each pixel, electronic paper, and DMDs (Digital Micromirror Device), PDP (Plasma Display Panel), FED(Field Emission Display) y) and other semiconductor display devices that have circuit elements using semiconductor elements in their drive circuits is included in that category.

[0039] (Embodiment 1) In this embodiment, a structure of a transistor included in a semiconductor device according to one embodiment of the present invention will be described. In this embodiment, an inverted staggered transistor is used as the transistor. This article explains:

[0040] The transistor 150 shown in FIG. 1 has a gate electrode layer 101a formed on a substrate 100. A gate insulating layer 102 is formed on the gate electrode layer 101a. An oxide semiconductor layer 106a is formed as a channel formation region, and The source electrode layer and the drain electrode layer 108a and 108b are formed. An oxygen-containing insulating film is formed on the drain electrode layers 108a and 108b and the oxide semiconductor layer 106a. The insulating layer 112 containing oxygen is formed on the backside of the oxide semiconductor layer 106a. The insulating layer 112 is in contact with the oxide semiconductor layer 106a in the channel. An insulating layer 116 containing hydrogen is formed on the insulating layer 116 containing hydrogen. An interlayer insulating layer 118 may be formed to cover the transistor 150 described in this embodiment. The insulating layer 112 containing oxygen in contact with the oxide semiconductor layer 106a and the insulating layer 11 containing oxygen are 2 and an insulating layer 116 containing hydrogen in contact with the insulating layer 116.

[0041] The substrate 100 must have at least enough heat resistance to withstand subsequent heat treatment. The substrate 100 is made of glass produced by, for example, the fusion method or the float method. A glass substrate can be used when the temperature of the subsequent heat treatment is high. It is preferable to use a glass substrate having a strain point of 730°C or higher. Glass such as borosilicate glass, aluminoborosilicate glass, and barium borosilicate glass The material used is a material containing more barium oxide (BaO) than boron oxide. By mixing these two materials, more practical heat-resistant glass can be obtained, so the glass contains more BaO than B2O3. It is preferable to use a glass substrate.

[0042] Instead of the glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. Alternatively, a substrate made of an insulating material may be used. Alternatively, a substrate made of a crystallized glass may be used. Alternatively, a substrate in which an insulating layer is provided on the surface of a metal substrate such as a stainless alloy may be used.

[0043] In addition, substrates made of flexible synthetic resins such as plastic generally have a low heat resistance temperature. However, if it can withstand the processing temperatures in the subsequent manufacturing steps, it is possible to use a material such as a silicon dioxide film as the substrate 100. As a plastic substrate, polyethylene terephthalate (P Polyesters such as polyethersulfone (PES), polyethylene naphtha (PEP), Polyethylene terephthalate (PEN), Polycarbonate (PC), Polyether ether ketone (PEE K), polysulfone (PSF), polyetherimide (PEI), polyarylate (PA R), polybutylene terephthalate (PBT), polyimide, acrylonitrile butadiene Polystyrene resin, polyvinyl chloride, polypropylene, polyvinyl acetate, acrylic resin, etc. Examples include:

[0044] The gate electrode layer 101a is made of a material selected from the group consisting of molybdenum, titanium, chromium, tantalum, and tungsten. Neodymium, scandium, and other metal materials, and alloy materials containing these metal materials as the main components, are used. The conductive layer or nitride of these metals can be used as a single layer or a laminated layer. If the metal material can withstand the temperature of the heat treatment that will be performed in the subsequent process, Aluminum and copper can also be used. Aluminum and copper have problems with heat resistance and corrosion resistance. To avoid this, it is recommended to use it in combination with a high melting point metal material. Molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, etc. can be used.

[0045] For example, the gate electrode layer 101a having a two-layer laminated structure may be formed by depositing a molybdenum layer on an aluminum layer. Two-layer structure with a molybdenum layer laminated on top of a copper layer, or two-layer structure with a molybdenum layer laminated on top of a copper layer or a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is laminated on a copper layer, titanium nitride It is preferable to have a two-layer structure in which a layer and a molybdenum layer are laminated. The gate electrode layer 101a may be an aluminum layer, an aluminum-silicon alloy layer, an aluminum-silicon alloy layer, or an aluminum-silicon alloy layer. An aluminum-titanium alloy layer or an aluminum-neodymium alloy layer is used as the intermediate layer, and the titanium a tungsten layer, a tungsten nitride layer, a titanium nitride layer or a titanium layer stacked as upper and lower layers; It is preferable to have a structure.

[0046] In addition, the gate electrode layer 101a may be formed of indium oxide, an alloy of indium oxide and tin oxide, or indium oxide. zinc oxide alloy, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, By using a light-transmitting oxide conductive layer such as zinc gallium oxide, The thickness of the gate electrode layer 101a is 10 nm to 400 nm. nm, preferably 100 nm to 200 nm.

[0047] The gate insulating layer 102 may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an oxide layer. aluminum nitride layer, aluminum nitride layer, aluminum oxynitride layer, aluminum oxynitride layer The gate insulating layer may be a single layer or a stack of layers of tantalum oxide or tantalum oxide. The thickness of the edge layer 102 is not particularly limited, but may be, for example, 10 nm or more and 500 nm or less. This can be done.

[0048] The gate insulating layer 102 is made of hafnium silicate (HfSiO x ), nitrogen added Hafnium silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminium Laminate (HfAl x O y N z ), hafnium oxide, yttrium oxide, etc. By using high-k materials, gate leakage can be reduced. A silicon layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an alumina oxide layer. It may have a laminated structure with one or more aluminum layers.

[0049] The gate insulating layer 102 is formed by high density plasma CV using microwaves (2.45 GHz). By using a dense, high-quality insulating layer with high dielectric strength formed by the D method, The interface state between the conductor layer 106a and the gate insulating layer 102 is reduced to improve the interface characteristics. This is preferable because it can

[0050] The gate insulating layer 102 is formed by using an insulating layer made of a material with high barrier properties and a material containing nitrogen. Alternatively, an insulating layer such as a silicon oxide layer or a silicon oxynitride layer having a low ratio of In this case, the insulating layer such as a silicon oxide layer or a silicon oxynitride layer is an insulating layer having a barrier property and an oxide. As an insulating layer with high barrier properties, for example, a silicon nitride layer or a nitride oxide layer is formed between the semiconductor layers. The barrier layer may be a silicon dioxide layer, an aluminum nitride layer, or an aluminum nitride oxide layer. By using an insulating layer having such a structure, impurities in the atmosphere such as moisture or hydrogen or impurities contained in the substrate can be prevented. Impurities such as alkali metals and heavy metals contained in the gate insulating layer 102 and the oxide semiconductor layer 10 6a, or the interface between the oxide semiconductor layer 106a and another insulating layer and its vicinity. In addition, when a silicon oxide film having a low nitrogen ratio is formed in contact with the oxide semiconductor layer 106a, By forming an insulating layer such as a silicon oxide nitride layer, an insulating material with high barrier properties can be used. This can prevent the layer from being in direct contact with the oxide semiconductor layer.

[0051] The oxide semiconductor layer 106a is a metal oxide, and is a quaternary metal oxide, In—Sn—Ga -Zn-O system, ternary metal oxides such as In-Ga-Zn-O system and In-Sn-Zn- O-based, In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, S n-Al-Zn-O system, binary metal oxides In-Zn-O system, Sn-Zn-O system , Al-Zn-O system, Zn-Mg-O system, Sn-Mg-O system, In-Mg-O system, In -O-based, Sn-O-based, Zn-O-based, etc. can be used.

[0052] The oxide semiconductor layer 106a is made of InMO3(ZnO). m Using materials expressed as (m>0) Here, M is one or more selected from Ga, Al, Mn and Co. For example, M may be Ga, Ga and Al, Ga and Mn, or Ga and Examples include Co., Ltd.

[0053] The oxide semiconductor layer 106a is made of In-M X -Zn Y -O Z (Y=0.5~5) Here, M is gallium (Ga) or aluminum (A). It represents one or more elements selected from the group 13 elements such as aluminum (Al) and boron (B). The contents of In, M, Zn, and O are optional, and the content of M is zero (i.e., X On the other hand, the contents of In and Zn are not zero. Notations include In-Ga-Zn-O and In-Zn-O.

[0054] The oxide semiconductor layer 106a has an amorphous structure that does not contain a crystalline component or an amorphous structure that contains a crystalline region. As a structure having a crystalline region in an amorphous region, the following is a typical example: Generally, the grain size in the amorphous region is 1 nm or more and 20 nm or less (typically 2 nm or more and 4 nm or less). The oxide semiconductor layer 106a has an amorphous structure, so that the oxide semiconductor layer 106a has a crystalline region. This can reduce the variation in characteristics.

[0055] The source electrode layer and the drain electrode layer 108a and 108b are made of aluminum, chromium, copper, or tantalum. a metal element selected from the group consisting of tantalum, titanium, molybdenum, tungsten, and yttrium, is formed by alloys containing the above-mentioned metal elements as components, alloys combining the above-mentioned metal elements, etc. In addition, one or more of manganese, magnesium, zirconium, and beryllium The source electrode layer and the drain electrode layer may be made of a metal element selected from the group consisting of: The layers 108a and 108b may have a single layer structure or a laminated structure of two or more layers. For example, a single layer structure of an aluminum layer containing silicon, a titanium layer stacked on an aluminum layer, a two-layer structure with a titanium layer on a tungsten layer; a two-layer structure with a titanium layer on top of the titanium layer; A three-layer structure in which an aluminum layer is stacked on top of another layer, and then a titanium layer is formed on top of that. In addition to aluminum, titanium, tantalum, tungsten, molybdenum, and chromium , neodymium, scandium, or a layer of a combination of elements. Alternatively, an alloy layer or nitride layer of these may be used.

[0056] The source and drain electrode layers 108a and 108b are formed of indium tin oxide. layer, indium oxide layer containing tungsten oxide, indium zinc oxide layer containing tungsten oxide Lead oxide layer, indium oxide layer containing titanium oxide, indium tin oxide layer containing titanium oxide transparent layers such as an indium zinc oxide layer, an indium tin oxide layer doped with silicon oxide, etc. In addition, a conductive layer having a light-transmitting property and the conductive layer having a light-transmitting property may be applied. It may also have a laminated structure of metal elements.

[0057] The insulating layer 112 containing oxygen is a silicon oxide layer or a silicon oxynitride layer containing oxygen. The insulating layer 112 containing oxygen is formed by a sputtering method or a CVD method. It is preferable that the silicon oxide layer is formed by a sputtering method. More preferable.

[0058] The hydrogen-containing insulating layer 116 may be a silicon nitride layer, a silicon nitride oxide layer, or an aluminum nitride layer. For example, the insulating layer containing hydrogen is formed using an insulating layer containing hydrogen, such as an aluminum nitride oxide layer. The hydrogen concentration in the insulating layer 116 is 1×10 19 atoms / cm 3 More than 1×10 22 a toms / cm 3 The insulating layer 116 containing hydrogen is preferably formed by sputtering. It is preferable that the film is formed by a coating method or a CVD method. In particular, it is preferable that the film is formed by a gas containing silane and nitrogen. (Typically, nitrogen gas, ammonia gas, etc.) are used as raw material gases in the CVD method. a silicon nitride layer or silicon nitride oxide layer formed by aluminum hydride and nitride; The gas containing nitrogen (typically nitrogen gas, ammonia gas, etc.) is used as a raw material gas. The aluminum nitride layer and aluminum nitride oxide layer formed by the CVD method are formed by hydrogen atoms. It is preferable because it contains a relatively large amount of

[0059] The hydrogen in the hydrogen-containing insulating layer 116 is heated to 150° C. or higher and 450° C. or lower, preferably 250° C. or lower. By heat treatment at a temperature of 440° C. or lower, the oxide semiconductor layer 106a is diffused or The oxide semiconductor layer 106a is formed on the gate insulating layer 102 and the oxide semiconductor layer 106b. The interface between the oxide semiconductor layer 106a and the insulating layer 112 containing oxygen is At least one of the defects or dangling bonds in the oxide semiconductor layer 106a is terminated. As a result, the on-state current and field-effect mobility of the transistor are improved.

[0060] According to this embodiment, a transistor having high field-effect mobility and on-state current can be realized. Furthermore, a transistor with low off-state current, high field-effect mobility, and high on-state current can be realized. do.

[0061] (Embodiment 2) Next, a method for manufacturing a transistor 150, which is an example of a semiconductor device, will be described with reference to FIGS. 4 will be referred to for explanation.

[0062] First, a conductive layer 101 is formed over a substrate 100 (see FIG. 2A).

[0063] The substrate 100 may be any substrate having an insulating surface, and may be, for example, a glass substrate. The glass substrate is preferably an alkali-free glass substrate. Examples of the glass include aluminosilicate glass, aluminoborosilicate glass, and barium borate glass. The substrate 100 may be a glass material such as silicon dioxide glass. Insulating substrates made of insulators such as quartz substrates and sapphire substrates, and semiconductor substrates made of silicon and other semiconductor materials. The surface of a semiconductor substrate is covered with an insulating material, and the conductive material is made of a conductor such as metal or stainless steel. The surface of the substrate may be covered with an insulating material.

[0064] In addition, substrates made of flexible synthetic resins such as plastic generally have a low heat resistance temperature. However, if it can withstand the processing temperatures in the subsequent manufacturing steps, it is possible to use a material such as a silicon dioxide film as the substrate 100. As a plastic substrate, polyethylene terephthalate (P Polyesters such as polyethersulfone (PES), polyethylene naphtha (PEP), Polyethylene terephthalate (PEN), Polycarbonate (PC), Polyether ether ketone (PEE K), polysulfone (PSF), polyetherimide (PEI), polyarylate (PA R), polybutylene terephthalate (PBT), polyimide, acrylonitrile butadiene Polystyrene resin, polyvinyl chloride, polypropylene, polyvinyl acetate, acrylic resin, etc. Examples include:

[0065] The conductive layer 101 is formed by a PVD method such as a sputtering method, a plasma CVD method, or the like. The conductive layer 101 can be formed by using a CVD method. , copper, tantalum, titanium, molybdenum, tungsten, or the elements mentioned above It can be formed using an alloy containing the elements manganese, magnesium, zinc Alternatively, a material containing one or more of aluminum, tungsten, and beryllium may be used. Titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium Alternatively, a material containing one or more elements selected from the group consisting of aluminum and ammonium may be used.

[0066] The conductive layer 101 may be formed using a conductive metal oxide. Materials include indium oxide (In2O3), tin oxide (SnO2), and zinc oxide (ZnO). , indium oxide tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO) , indium oxide zinc oxide alloy (In2O3-ZnO), or these metal oxide materials The material may contain silicon or silicon oxide.

[0067] The conductive layer 101 may have a single-layer structure or a stacked structure of two or more layers. In one embodiment of the disclosed invention, after the conductive layer 101 is formed, a heat treatment is performed at a relatively high temperature. Therefore, it is desirable to form the conductive layer 101 using a material with high heat resistance. Suitable materials include titanium, tantalum, tungsten, and molybdenum. It is also possible to use polysilicon or the like in which the conductivity is increased by adding a pure element.

[0068] Next, the conductive layer 101 is selectively etched to form a gate electrode layer 101a. A gate insulating layer 102 is formed to cover the gate electrode layer 101a (see FIG. 2(B)).

[0069] For exposure when forming the mask used for etching, ultraviolet light, KrF laser light, or ArF laser light is used. It is preferable to use the following. In particular, when performing exposure with a channel length (L) of less than 25 nm, Extreme ultraviolet rays have extremely short wavelengths ranging from a few nm to a few tens of nm. It is preferable to use ultraviolet light to expose the mask. It has a high resolution and a large depth of focus, making it suitable for miniaturization.

[0070] The gate insulating layer 102 can be formed by a CVD method, a sputtering method, or the like. The gate insulating layer 102 may be formed of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or silicon oxide. It is preferable to form the film so as to contain aluminum, hafnium oxide, tantalum oxide, etc. The gate insulating layer 102 may have a single layer structure or a stacked layer structure. The thickness of the insulating layer 102 is not particularly limited, but is, for example, 10 nm or more and 500 nm or less. It is possible.

[0071] The gate insulating layer 102 is made of hafnium silicate (HfSiO x ), nitrogen added Hafnium silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminium Laminate (HfAl x O y N z ), hafnium oxide, yttrium oxide, etc. By using high-k materials, gate leakage can be reduced. A silicon layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an alumina oxide layer. It may have a laminated structure with one or more aluminum layers.

[0072] Note that it is desirable that the gate insulating layer 102 be formed so as not to contain hydrogen or water as much as possible. It's nice.

[0073] For example, when using a sputtering method, remove any remaining moisture in the processing chamber. It is desirable to form a gate insulating layer 102. In addition, in order to remove residual moisture in the processing chamber, For this purpose, adsorption pumps such as cryopumps, ion pumps, and titanium sublimation pumps are used. It is desirable to use a vacuum pump. A cryopump or the like may be used. The processing chamber is evacuated so that hydrogen, water, etc. are sufficiently removed. The concentration of impurities contained therein can be reduced.

[0074] In addition, the high-density plasma CVD method using microwaves (for example, 2.45 GHz) This is advantageous in that a high-quality gate insulating layer 102 with high dielectric strength can be formed without any additional steps. The close contact between the semiconductor layer and the high-quality gate insulating layer reduces the interface state and improves the interface characteristics. This is because it can be made into a preferable one. 11 / cm 3 More than plasma density It is preferable to use a high density plasma device capable of achieving high plasma density.

[0075] In this way, the interface characteristics between the gate insulating layer 102 and the oxide semiconductor layer 106a are improved. In addition, by eliminating impurities in oxide semiconductors, especially hydrogen and water, the gate bias and thermal Stress test (BT test: e.g., 85°C, 2 x 10 6 V / cm, 12 hours, etc.) Even if the temperature is low, it is possible to obtain a stable transistor with a stable threshold voltage (Vth) that does not fluctuate. .

[0076] Furthermore, when forming the gate insulating layer 102, impurities such as hydrogen and water are present at a concentration of about several ppm. It is desirable to use a high-purity gas in which the concentration is reduced to a low level (preferably, a concentration of about several ppb). stomach.

[0077] Next, the oxide semiconductor layer 106 is formed over the gate insulating layer 102 (see FIG. 2C).

[0078] The oxide semiconductor layer 106 is made of a quaternary metal oxide such as In—Sn—Ga—Zn—O, or a ternary metal oxide such as In—Sn—Ga—Zn—O. The metal oxides In-Ga-Zn-O, In-Sn-Zn-O, and In-Al- Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn-O and binary metal oxides such as In-Zn-O, Sn-Zn-O, and Al-Zn-O. Zn-Mg-O, Sn-Mg-O, In-Mg-O, and single-component metal oxides It can be formed using an In-O system, an Sn-O system, a Zn-O system, or the like.

[0079] Among these, In-Ga-Zn-O oxide semiconductor materials have a sufficiently high resistance in the absence of an electric field. It is possible to sufficiently reduce the electron current and the field effect mobility is high, so it is It is suitable as a semiconductor material for use in devices.

[0080] A typical example of an In-Ga-Zn-O oxide semiconductor material is InGaO3(ZnO). m (m>0). Also, M is used instead of Ga, and InMO3(Zn O) m There are oxide semiconductor materials that are written as (m>0), where M is gallium. (Ga), aluminum (Al), iron (Fe), nickel (Ni), manganese (Mn), It refers to one or more metal elements selected from the group consisting of cobalt (Co), etc. For example, M includes Ga, Ga and Al, Ga and Fe, Ga and Ni, and Ga and Mn. The above composition is derived from the crystal structure. Please note that this is merely an example.

[0081] In this embodiment, the oxide semiconductor layer 106 is an In—Ga—Zn—O-based oxide semiconductor. An amorphous oxide semiconductor layer is formed by a sputtering method using a film formation target. It shall be so decided.

[0082] An oxide for forming an In-Ga-Zn-O-based oxide semiconductor layer 106 by sputtering. The target for film formation of semiconductor compounds is In:Ga:Zn=1:x:y (x is 0 or more, y For example, In:Ga:Z n=1:1:1 [atom ratio] (x=1, y=1), (i.e., In2O3:Ga2O 3:ZnO=1:1:2 [molar ratio]) In addition, a target for forming an oxide semiconductor film may be used. An oxide semiconductor film deposition target having a composition ratio of 1:1:0.5 [atom ratio], or In:Ga:Zn=1:1:2[atom ratio], In:Ga:Zn=1:0:1[ato m ratio] (x=0, y=1) It is also possible.

[0083] The relative density of the oxide semiconductor in the oxide semiconductor film formation target is 80% or more, preferably 90% or more. 5% or more, and more preferably 99.9% or more. For forming oxide semiconductor films with high relative density By using a target, the oxide semiconductor layer 106 can be formed with a dense structure. is.

[0084] The oxide semiconductor layer 106 is formed in a rare gas (typically, argon) atmosphere or an oxygen atmosphere. It is preferable to use a mixed atmosphere of oxygen or a rare gas (typically argon) and oxygen. Specifically, impurities such as hydrogen, water, hydroxyl groups, and hydrides are present at concentrations of about several ppm. It is preferable to use a high-purity gas atmosphere in which the concentration has been reduced to a level of about several ppb. be.

[0085] When the oxide semiconductor layer 106 is formed, for example, the substrate is placed in a processing chamber maintained in a reduced pressure state. The substrate temperature is maintained at 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. Then, the sputtering gas from which hydrogen and water have been removed while removing the remaining moisture in the processing chamber. and the oxide semiconductor layer 106 is formed using the oxide semiconductor film formation target. The oxide semiconductor layer 106 is formed while the substrate is heated. It is possible to reduce impurities contained in the material. In addition, damage caused by sputtering is reduced. To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, titanium sublimation pumps, etc. Alternatively, a turbo pump with a cold trap may be used. The processing chamber is evacuated using a cryopump, and hydrogen and water are removed, so oxides The impurity concentration of the semiconductor layer 106 can be reduced.

[0086] The oxide semiconductor layer 106 is formed under the following conditions: The distance between the nozzles was 170 mm, the pressure was 0.4 Pa, the direct current (DC) power was 0.5 kW, and the ambient temperature was Oxygen (100% oxygen) atmosphere, or Argon (100% argon) atmosphere, or A mixed atmosphere of oxygen and argon can be used. When a DC power supply is used, the powdery substances (also called particles or dust) generated during film formation are The thickness of the oxide semiconductor layer 106 is preferably 2 nm. The thickness is set to 200 nm or more, preferably 5 nm or more and 30 nm or less. The appropriate thickness of the oxide semiconductor layer 106 varies depending on the semiconductor material and the intended use. The thickness may be selected depending on the material used and the application.

[0087] Before the oxide semiconductor layer 106 is formed by a sputtering method, argon gas is introduced. The deposits on the surface of the gate insulating layer 102 are removed by reverse sputtering, which generates plasma by introducing a Here, the reverse sputtering is a method of removing the sputtered material. Instead of bombarding the target with ions, the treatment surface is bombarded with ions. Therefore, it is a method of modifying the surface. In this method, a high frequency voltage is applied to the surface to be treated in an argon atmosphere to generate plasma near the substrate. In addition, instead of an argon atmosphere, an atmosphere of nitrogen, helium, oxygen, etc. can be used. An atmosphere may be applied.

[0088] Next, the oxide semiconductor layer 106 is processed by a method such as etching using a mask. An island-shaped oxide semiconductor layer 106a is formed (see FIG. 3A). The conductor layer 106a is formed in a region overlapping with the gate electrode layer 101a.

[0089] The oxide semiconductor layer can be etched by either dry etching or wet etching. Of course, both of them can be used in combination. The etching conditions (etching gas, etc.) can be adjusted to suit the material so that the desired shape can be etched. The etching solution, etching time, temperature, etc. are set appropriately.

[0090] As dry etching, parallel plate type RIE (Reactive Ion Etching) ng) method and ICP (Inductively Coupled Plasma) In this case, the etching conditions are (The amount of power applied to the coil-type electrode, the amount of power applied to the substrate-side electrode, the amount of power applied to the substrate-side electrode Temperature, etc. must be set appropriately.

[0091] Etching gases that can be used for dry etching include, for example, chlorine-containing gases ( Chlorine-based gases, such as chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), Carbon tetrachloride (CCl4, etc.) and gases containing fluorine (fluorine-based gases, e.g. For example, carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane (CHF3, etc.), hydrogen bromide (HBr), oxygen (O2), and A gas to which a rare gas such as uranium (He) or argon (Ar) is added may also be used.

[0092] The etching solution that can be used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Also, etching solutions such as ITO07N (Kanto Chemical Co., Ltd.) are used. Good too.

[0093] After that, the oxide semiconductor layer 106a is preferably subjected to heat treatment (first heat treatment). The first heat treatment removes excess hydrogen (water or hydroxyl groups) from the oxide semiconductor layer 106a. The structure of the oxide semiconductor layer is adjusted, and defects in the oxide semiconductor layer 106a are reduced. The temperature of the first heat treatment can be, for example, 400°C or higher and 750°C or lower, or The temperature must be above 400°C and below the distortion point of the substrate. If the compound semiconductor layer 106a is obtained, the heat treatment is not necessary.

[0094] The heat treatment is carried out by, for example, placing the substrate 100 in an electric furnace using a resistance heating element, and heating the substrate 100 in a nitrogen atmosphere. The oxide semiconductor layer 106a is heated in the atmosphere for 1 hour at 450° C. Do not allow it to come into contact with water or hydrogen.

[0095] Heat treatment equipment is not limited to electric furnaces, and may be heat conduction or heat radiation from a medium such as heated gas. For example, a GRTA (Gas Rap id Thermal Anneal) equipment, LRTA (Lamp Rapid The RTA (Rapid Thermal Anneal) equipment ) equipment can be used. The LRTA equipment uses halogen lamps, metal halide lamps, etc. , xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a lamp. The GRTA device is a device that performs heat treatment using high-temperature gas. The gas used is argon. or an inert gas such as nitrogen that does not react with the material to be treated by heat treatment. It is used.

[0096] For example, as the first heat treatment, the substrate is placed in an inert gas atmosphere heated to a high temperature of 650°C to 700°C. GRTA process involves placing a substrate in the chamber, heating it for a few minutes, and then removing the substrate from the inert gas atmosphere. GRTA treatment allows high-temperature heat treatment in a short time. Because it is a long-term heat treatment, it can be applied even to temperature conditions that exceed the heat resistance temperature of the substrate. For example, when using a glass substrate, the substrate may shrink at temperatures exceeding the heat resistance temperature (distortion point). However, this is not a problem if the heat treatment is performed for a short time. Alternatively, the inert gas may be replaced with a gas containing oxygen. This is because the heat treatment can reduce defects caused by oxygen deficiency.

[0097] The inert gas atmosphere is nitrogen or a rare gas (helium, neon, argon, etc.). It is desirable to use an atmosphere containing ) as the main component and not containing water, hydrogen, etc. For example, nitrogen and rare gases such as helium, neon, and argon introduced into a heat treatment device Purity should be 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher ( That is, the impurity concentration is set to 1 ppm or less, preferably 0.1 ppm or less.

[0098] By performing the above-described first heat treatment, hydrogen contained in the oxide semiconductor layer 106 is reduced. Preferably, hydrogen contained in the oxide semiconductor layer 106 is removed, and the main It is possible to achieve high purity so that impurities other than the components are not included as much as possible. The structure of the oxide semiconductor layer 106 that has been disturbed by the excess hydrogen atoms is adjusted. The hydrogen concentration in the oxide semiconductor layer 106 at this time is , 1×10 16 cm -3 The carrier density of the oxide semiconductor layer 106 is preferably as follows: The carrier density in a typical silicon wafer (1×10 14 / cm 3 (compared to the degree) , a sufficiently small value of carrier density (e.g., 1 × 10 12 / cm 3 Less than, more preferably , 1.45×10 10 / cm 3 It is preferable that the band gap is less than 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more.

[0099] In addition, when the drain voltage is in the range of 1V to 10V, the off-state current (gate The current that flows between the source and drain when the voltage between the source and drain is set to 0 V or less is When the length is 10 μm and the total thickness of the oxide semiconductor layer is 30 nm, -13 A or less, or the off-current density (off-current divided by the transistor channel width) is 1 00aA(a(a) is 10 -18 ) / μm or less, preferably 10 aA / μm or less The off-state current and the drain current can be set to 1 aA / μm or less, and more preferably 1 aA / μm or less. If the voltage value is known, the resistance value when the transistor is off (off resistance R) can be calculated from Ohm's law. If the cross-sectional area A of the channel formation region and the channel length L are known, then ρ = RA / The off-resistivity ρ can be calculated from the formula for L (R is the off-resistance). The off-resistivity is 1×1 0 9 Ω·m or more (or 1×10 10 Ω m), where the cross-sectional area A is the area of the channel When the film thickness of the formation area is d and the channel width is W, it can be calculated as A=dW. do.

[0100] When such a highly purified oxide semiconductor layer 106 is used for a channel formation region, The off-current of the transistor can be reduced. The off-current is determined by direct or indirect recombination. The oxide semiconductor layer has a wide band gap, so the flow is due to the generation and recombination of holes and electrons. However, since a large amount of thermal energy is required for electron excitation, direct and indirect recombination In the off state, the number of holes, which are minority carriers, is essentially zero, so Direct recombination and indirect recombination are unlikely to occur, and the off-state current can be reduced to an unlimited extent. The transistor has excellent characteristics, reducing the on-state current and improving the on-state current and field-effect mobility. It becomes a transistor.

[0101] As described above, the highly purified oxide semiconductor layer functions as a path, and carriers The electron affinity χ of the oxide semiconductor and the Fermi level, ideally the Fermi level coincides with the intrinsic Fermi level, and the source and drain By appropriately selecting the work function of the electrode and the oxide semiconductor layer, the carrier density of the oxide semiconductor layer can be reduced. In addition, it becomes possible to inject carriers from the source electrode and the drain electrode, and an n-type transistor A p-type transistor and a p-type transistor can be fabricated appropriately.

[0102] Furthermore, the intrinsic carrier density of a highly purified oxide semiconductor is extremely high compared to that of silicon. The intrinsic carrier density of silicon and oxide semiconductors is Fermi-Dirac distribution and It can be calculated from the approximate formula of the Boltzmann distribution, and the intrinsic carrier density of silicon, n i is 1.45 x 10 10 cm -3 , oxide semiconductor (here, In-Ga-Zn-O layer) Intrinsic carrier density n i is 1.2 x 10 -7 cm -3 The former is a more intrinsic carrier than the latter. Density is 10 17times larger. That is, the intrinsic carrier density of oxide semiconductors is is found to be extremely low.

[0103] Note that depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer 106, A part of the oxide semiconductor layer 106 is crystallized, and microcrystals or polycrystals are formed in the oxide semiconductor layer 106. In some cases, this may be the case.

[0104] The first heat treatment is performed on the oxide semiconductor layer 106 before it is processed into the island-shaped oxide semiconductor layer 106a. In this case, the substrate 100 is removed from the heating device after the first heat treatment. The wafer is then taken out and subjected to a photolithography process.

[0105] The first heat treatment has the effect of removing hydrogen and water, so the first heat treatment is called dehydration treatment. The dehydration treatment or the dehydrogenation treatment may be called hydrogenation treatment or the like. After the formation of the oxide semiconductor layer 106a, a source electrode layer or a drain electrode layer was stacked on the oxide semiconductor layer 106a. It is also possible to carry out the dehydration treatment at a timing such as after the dehydration treatment. The hydrogenation treatment may be carried out not only once but also multiple times.

[0106] Next, the conductive layer 108 is formed in contact with the oxide semiconductor layer 106a (see FIG. 3B). ).

[0107] The conductive layer 108 is formed by a PVD method such as a sputtering method, a plasma CVD method, or the like. The conductive layer 108 can be formed by using a CVD method. , copper, tantalum, titanium, molybdenum, tungsten, or the elements mentioned above It can be formed using an alloy containing the elements manganese, magnesium, zinc Alternatively, a material containing one or more of aluminum, tungsten, and beryllium may be used. Titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium Alternatively, a material containing one or more elements selected from the group consisting of aluminum and ammonium may be used.

[0108] The conductive layer 108 may be formed using a conductive metal oxide. Materials include indium oxide (In2O3), tin oxide (SnO2), and zinc oxide (ZnO). , indium oxide tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO) , indium oxide zinc oxide alloy (In2O3-ZnO), or these metal oxide materials The material may contain silicon or silicon oxide.

[0109] The conductive layer 108 may have a single-layer structure or a stacked structure of two or more layers. A three-layer structure in which an aluminum film is laminated on a titanium film, and a titanium film is laminated on the aluminum film. A layer structure, such as a molybdenum film on which an aluminum film is stacked and a molybdenum film on which an aluminum film is stacked, A three-layer laminate structure in which an aluminum film and a tungsten film are laminated can also be applied. Two-layer laminated structure with copper film and tungsten film, two-layer laminated structure with aluminum film It is also possible to use a two-layer structure in which a tungsten film and a molybdenum film are laminated. In the case of a single layer structure, for example, a single layer of titanium film If a single layer structure of titanium film is used, it is possible to obtain a good result during subsequent etching. In this example, the titanium film and the aluminum film are etched to form a tapered shape. A three-layer structure consisting of an aluminum film and a titanium film will be applied.

[0110] Note that a portion of the conductive layer 108 in contact with the oxide semiconductor layer 106a has an oxygen-removing effect. Materials with low affinity for oxygen (materials with low affinity for oxygen) may be used. For example, titanium nitride, tungsten nitride, platinum, etc. The structure of the conductive layer 108 is the same as that described above. Similarly, the conductive layer 108 may have a single layer structure or a stacked layer structure. For example, a two-layer structure of a titanium nitride film and a titanium film, a two-layer structure of a titanium nitride film and a tungsten film, Two-layer structure of titanium nitride film and copper-molybdenum alloy film, tantalum nitride film and tungsten film two-layer structure of tantalum nitride film and copper film, two-layer structure of titanium nitride film, tungsten film and titanium A three-layer structure of the membrane, etc. can be adopted.

[0111] By using a material with a low oxygen-extracting effect as described above for the conductive layer 108, the oxygen-extracting effect can be reduced. Prevents the oxide semiconductor layer from becoming n-type due to removal, and prevents transistors caused by uneven n-type The adverse effects on the characteristics can be suppressed.

[0112] As mentioned above, a material with high barrier properties such as a titanium nitride film or a tantalum nitride film is used as an oxide film. By using the insulating film in the portion in contact with the oxide semiconductor layer 106a, the intrusion of impurities into the oxide semiconductor layer 106a can be prevented. This suppresses the adverse effects on transistor characteristics.

[0113] Next, the conductive layer 108 is selectively etched to form the source or drain electrode layer 10 8a, a source electrode layer or a drain electrode layer 108b is formed (see FIG. 3C). An insulating layer is formed on the conductive layer 108, and the insulating layer is etched to form a source electrode layer or An insulating layer having substantially the same shape as the source electrode layer and the drain electrode layer is formed on the drain electrode layer. In this case, the capacitance between the source electrode layer or the drain electrode layer and the gate electrode layer is The amount of capacitance (so-called gate capacitance) can be reduced. It is used in the sense that they do not need to be identical, and includes the range in which they can be considered identical. For example, differences in the case where the layers are formed by a single etching process are acceptable. However, it is not necessary that the thicknesses be the same.

[0114] For exposure when forming the mask used for etching, ultraviolet light, KrF laser light, or ArF laser light is used. It is preferable to use the following. In particular, when performing exposure with a channel length (L) of less than 25 nm, Extreme ultraviolet rays have extremely short wavelengths ranging from a few nm to a few tens of nm. It is preferable to use ultraviolet light to expose the mask. Therefore, the channel length (L) of the transistor to be formed later can be It is also possible to make the channel length 10 nm or more and 1000 nm or less. By reducing the thickness, the operating speed can be improved. The transistors used have a small off-state current, which helps prevent increases in power consumption due to miniaturization. Cut.

[0115] When the conductive layer 108 is etched, the oxide semiconductor layer 106a is not removed. The materials and etching conditions are adjusted as appropriate. Therefore, in this step, a part of the oxide semiconductor layer 106a is etched, and the groove portion ( In some cases, the oxide semiconductor layer may have a recess.

[0116] In order to reduce the number of masks used and the number of processes, an exposure method is used in which the transmitted light has multiple intensities. A resist mask is formed using a multi-tone mask, which is a mask, and an etching process is performed using this. The resist mask formed using the multi-tone mask has a plurality of thicknesses. The shape becomes stepped, and the shape can be further deformed by ashing. It can be used for multiple etching processes. It is possible to form resist masks corresponding to at least two different patterns. This reduces the number of exposure masks and the corresponding photolithography process. This allows for simplification of the process.

[0117] Next, the insulating layer 112 containing oxygen is formed in contact with part of the oxide semiconductor layer 106a. The insulating layer 112 containing oxygen is formed by a CVD method or a sputtering method. The insulating layer 112 containing oxygen can be formed by a silicon oxide film or the like. , silicon oxide nitride, aluminum oxide, hafnium oxide, tantalum oxide, etc. In particular, a silicon oxide film formed by sputtering is preferred. Note that the insulating layer 112 containing oxygen may have either a single-layer structure or a stacked-layer structure. The thickness of the insulating layer 112 containing oxygen is not particularly limited, but may be, for example, 10 nm or more and 500 nm or less. Preferably, the thickness can be set to 50 nm or more and 200 nm or less.

[0118] The second heat treatment is preferably carried out in an inert gas atmosphere or an oxygen atmosphere. The temperature is 200°C or higher and 450°C or lower, preferably 250°C or higher and 350°C or lower. For example, the second heat treatment may be performed at 250° C. for 1 hour in a nitrogen atmosphere. As a result, oxygen is supplied to the oxide semiconductor layer 106a, and oxygen deficiency in the oxide semiconductor layer 106a is reduced. Reduce the loss and form an i-type (intrinsic semiconductor) or an oxide semiconductor layer that is as close to i-type as possible. Furthermore, when the second heat treatment is performed, the variation in the electrical characteristics of the transistors can be reduced. can be reduced.

[0119] Next, the insulating layer 116 containing hydrogen is formed over the insulating layer 112 containing oxygen, and then a third heat treatment is performed. The insulating layer 116 containing hydrogen is formed by a CVD method or a sputtering method. The insulating layer 116 containing hydrogen can be formed using a silicon nitride layer or the like. a silicon nitride oxide layer, an aluminum nitride layer, an aluminum nitride oxide layer, or the like. In particular, it is preferable to form the insulating layer using a gas containing silane and nitrogen (typically is formed by a CVD method using at least nitrogen gas, ammonia gas, etc. as raw material gas. a silicon nitride layer or silicon nitride oxide layer, which is formed by depositing aluminum hydride and a nitrogen-containing gas; CVD method using at least a gas containing a base material (typically nitrogen gas, ammonia gas, etc.) as a raw material gas. The aluminum nitride layer and aluminum nitride oxide layer formed by the above method contain a relatively large amount of hydrogen atoms. It is preferable because it contains a lot of

[0120] The third heat treatment is carried out in a nitrogen atmosphere at a temperature of 150° C. to 450° C., preferably 250° C. to 450° C. The temperature is set to 40° C. or less. The third heat treatment is not limited to a nitrogen atmosphere, but may be performed in an oxygen atmosphere, The treatment may be carried out in a rare gas atmosphere or a dry air atmosphere.

[0121] By the third heat treatment, hydrogen in the insulating layer 116 containing hydrogen is oxidized to at least the oxide semiconductor layer The oxide semiconductor layer 106a is diffused or supplied to the gate insulating layer 106a. The interface between the oxide semiconductor layer 102 and the oxide semiconductor layer 106a, the interface between the oxide semiconductor layer 106a and the oxygen-containing insulating layer Terminate any remaining defects or dangling bonds at at least one of the interfaces of the edge layer 112. The number of defects in the oxide semiconductor layer 106a is reduced. As a result, the on-state current and the electric field of the transistor are reduced. The supply of hydrogen by this heat treatment reduces defects sufficiently and results in i-type It is more effective when the treatment is performed on a thin oxide semiconductor layer.

[0122] Note that the conditions of the second heat treatment, the third heat treatment, or the material of the oxide semiconductor layer 106 may vary. Therefore, part of the oxide semiconductor layer 106 is crystallized, and the oxide semiconductor layer 106 contains microcrystals or crystals. In some cases, polycrystals may be formed.

[0123] Next, an interlayer insulating layer 118 may be formed on the insulating layer 116 containing hydrogen (see FIG. 4(C)). The interlayer insulating layer 118 can be formed by using a PVD method, a CVD method, or the like. Also, silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide The insulating layer can be formed using a material containing an inorganic insulating material such as aluminum or tantalum oxide. In the embodiment, the interlayer insulating layer 118 has a single-layer structure. However, the present invention is not limited to this, and a laminated structure of two or more layers may also be used.

[0124] It is desirable that the interlayer insulating layer 118 be formed so that its surface is flat. By forming the interlayer insulating layer 118 so that the surface is flat, it is possible to form an electrode on the interlayer insulating layer 118. This is because electrodes, wiring, etc. can be formed in a suitable manner.

[0125] As a result, the hydrogen contained in the insulating layer 116 containing hydrogen is diffused to form a transistor in which the defects are terminated. The Transista 150 is completed.

[0126] Next, another example of the structure of the semiconductor device according to this embodiment will be described with reference to FIG. The transistor 150 shown in FIG.

[0127] The transistor 150 illustrated in FIG. 5 has a structure in which a channel formation region of the oxide semiconductor layer 106a overlaps with the channel formation region of the oxide semiconductor layer 106a. An insulating layer 113 is provided in the region as a channel stopper.

[0128] A method for forming the insulating layer 113 provided as a channel stopper will be described. After the oxide semiconductor layer 106a shown in FIG. 3A is formed, the oxide semiconductor layer 106a is covered with a In this way, a material containing oxygen atoms, such as silicon oxide or silicon oxynitride, is used to form a sputtering film. An insulating film is formed by a deposition method or a CVD method. Then, the insulating film is selectively etched. By this etching, the insulating layer 113 can be formed. After the insulating layer 113 is formed, , the steps from FIG. 3(B) onwards can be referred to.

[0129] The insulating layer 113 is formed as a channel layer in a region overlapping with the channel formation region of the oxide semiconductor layer 106a. By providing the source electrode layer and the drain electrode layer 108a and 108b as a topper, Prevents damage during the formation of b (film reduction due to plasma during etching and etching agent) Therefore, the reliability of the transistor 150 can be improved.

[0130] A transistor having high field-effect mobility and on-state current can be fabricated by the method described in this embodiment. In addition, a transistor having a low off-state current, a high field-effect mobility, and a high on-state current can be realized. This can be achieved.

[0131] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0132] (Embodiment 3) In this embodiment mode, another example of the structure and manufacturing method of the semiconductor device according to the above embodiment mode will be described. In this embodiment, a top-gate transistor is used as the transistor. I will explain about Star.

[0133] <Structure of Semiconductor Device> First, a transistor 150, which is an example of the structure of a semiconductor device described in this embodiment, will be described. The transistor 150 shown in FIG. 6D has an oxide semiconductor layer 1 The source and drain electrode layers 108 and 109 are formed over the oxide semiconductor layer 106a. The source and drain electrode layers 108a and 108b are formed. An insulating layer 112 containing oxygen is formed to cover the oxide semiconductor layer 106a. The insulating layer 112 containing oxygen functions as a gate insulating layer. The insulating layer 112 is in contact with the oxide semiconductor layer 106a at the channel of the insulating layer 112. A gate electrode layer 114 is formed to overlap with the semiconductor layer 106a. An insulating layer 116 containing hydrogen is formed to cover the insulating layer 112 containing hydrogen and the gate electrode layer 114. An insulating layer 118 functioning as a planarization film is formed on the insulating layer 116 containing hydrogen. The transistor 150 described in this embodiment may include an oxide semiconductor layer 106a an insulating layer 112 containing oxygen in contact with the insulating layer 112 containing oxygen; and an insulating layer 112 containing hydrogen in contact with the insulating layer 112 containing oxygen. Note that a base film 116 is provided between the substrate 100 and the oxide semiconductor layer 106a. A functional insulating layer 102 may be formed.

[0134] <Method for manufacturing semiconductor device> Next, a method for manufacturing a transistor 150, which is an example of a semiconductor device, will be described with reference to FIGS. and explain.

[0135] First, an oxide semiconductor layer 104 is formed on a substrate 100 on which an insulating layer 102 serving as a base film is formed. After forming the oxide semiconductor layer 106a, a source electrode layer and a drain electrode layer are formed on the oxide semiconductor layer 106a. 108a and 108b are formed (see FIG. 6(A)).

[0136] As for the substrate 100, the substrate 100 in FIG. 2(A) can be referred to, and therefore a detailed description thereof will be omitted.

[0137] The insulating layer 102, which functions as a base film, is formed by a CVD method, a sputtering method, or the like. The insulating layer 102 can be formed using silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide. It is preferable to form the oxide so as to contain silicon oxide, aluminum oxide, hafnium oxide, and tantalum oxide. The insulating layer 102 may have a single layer structure or a multilayer structure. The thickness can be, for example, 10 nm or more and 500 nm or less. When using a process chamber such as a silicon dioxide gas, the insulating layer 102 is formed in a state where residual moisture in the process chamber is removed. It is preferable that:

[0138] The oxide semiconductor layer is formed on the substrate 100 or the insulating layer 102 by a sputtering method or the like. The material and method for forming the oxide semiconductor layer are the same as those for the oxide semiconductor layer 1 in FIG. 06a, so a detailed explanation will be omitted.

[0139] In this embodiment, the oxide semiconductor layer 106a is an In—Ga—Zn—O-based oxide semiconductor. An amorphous oxide semiconductor layer is formed by sputtering using a conductor film formation target. It will be decided.

[0140] Before forming the oxide semiconductor layer by a sputtering method, argon gas was introduced. Reverse sputtering is performed to generate plasma, and deposits on the surface of the insulating layer 102 are removed. preferable.

[0141] Next, the oxide semiconductor layer is processed by a method such as etching using a mask to form island-like The oxide semiconductor layer 106a is formed by dry etching. This can be done by either etching or wet etching, or a combination of both. The conditions for etching the oxide semiconductor layer can be referred to in Embodiment 2. Therefore, detailed explanation will be omitted.

[0142] Next, the oxide semiconductor layer 106a is subjected to first heat treatment (dehydration treatment, dehydrogenation treatment). The first heat treatment is preferably performed to remove water (hydroxyl group) from the oxide semiconductor layer 106a. The conditions of the first heat treatment are as follows: Since it is sufficient to refer to State 2, detailed explanation will be omitted.

[0143] Note that the first heat treatment is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer 106a. In this case, after the first heat treatment, the substrate 100 is removed from the heating device. Then, a photolithography process is carried out.

[0144] Next, the oxide semiconductor layer 106a and the source and drain electrode layers 108a and 108b are An insulating layer 112 is formed to cover the insulating layer 112 (see FIG. 6B).

[0145] The insulating layer 112 functions as a gate insulating layer. The insulating layer 112 is made of silicon oxide or The insulating layer 112 is preferably formed of silicon nitride or the like so as to contain oxygen atoms. It is preferable to form it by a deposition method or a CVD method.

[0146] Next, the oxide semiconductor layer 106a is preferably subjected to second heat treatment. By performing the treatment, oxygen in the insulating layer 112 containing oxygen is removed from the oxide semiconductor layer 106a The oxygen vacancies in the oxide semiconductor layer 106a are oxidized to form an i-type (intrinsic) or In this case, the oxide semiconductor layer 106a can be formed as close to i-type as possible. The second thermal treatment reduces the variation in the electrical characteristics of the transistors. As for the processing conditions, please refer to the second embodiment, and detailed explanation will be omitted.

[0147] Next, a gate electrode was formed over the insulating layer 112 containing oxygen so as to overlap with the oxide semiconductor layer 106a. The electrode layer 114 is formed (see FIG. 6(C)).

[0148] First, a conductive layer is formed on the insulating layer 112 containing oxygen by using a sputtering method or a CVD method. For the material and the method of forming the conductive layer, see the conductive layer 101 in FIG. After that, the conductive layer is selectively etched to form the gate The electrode layer 114 is formed.

[0149] Next, an insulating layer 116 containing hydrogen is formed to cover the gate electrode layer 114, and then planarized. An insulating layer 118 that functions as a film is formed (see FIG. 6(D)).

[0150] The insulating layer 116 containing hydrogen is made of silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide. The insulating layer 116 containing hydrogen is formed by sputtering. It is preferable to form the film by the coating method or the CVD method. In particular, it is preferable to form the film by the use of a gas containing silane and nitrogen (typically In general, it is formed by the CVD method using at least nitrogen gas, ammonia gas, etc. as raw material gas. Silicon nitride layer or silicon nitride oxide layer formed of aluminum hydride and nitrogen-containing CV using at least a gas containing nitrogen (typically nitrogen gas, ammonia gas, etc.) as the raw material gas. The aluminum nitride layer and aluminum nitride oxide layer formed by the D method are Note that the insulating layer 112 containing oxygen is preferably an insulating layer containing hydrogen so as to be in contact with the insulating layer 112 containing oxygen. It is preferable to form a border layer 116 .

[0151] Next, the oxide semiconductor layer 106a is subjected to third heat treatment. For details, please refer to the second embodiment, and detailed description will be omitted. As a result, hydrogen in the insulating layer 116 containing hydrogen is transferred to at least the oxide semiconductor layer 106a. , and the oxide semiconductor layer 106a and the oxide semiconductor layer 106a are diffused or supplied. the interface with the insulating layer 112 containing silicon, the interface between the oxide semiconductor layer 106a and the insulating layer 102, At least one of the defects or dangling bonds in the oxide semiconductor layer 10 is terminated. As a result, the on-current and field-effect mobility of the transistor are improved. do.

[0152] The insulating layer 118 can be formed by sputtering, CVD, or the like. The material and forming method of the insulating layer 118 can be seen in FIG. 4C. The explanation will be omitted.

[0153] Through the above steps, the transistor 150 including the oxide semiconductor layer 106a is completed.

[0154] In the transistor 150 according to this embodiment, the temperature is set to 400° C. or higher and 750° C. or lower, preferably The temperature is 400°C or higher and lower than the strain point of the substrate, and the atmosphere contains almost no hydrogen or moisture (nitrogen atmosphere). Atmosphere, oxygen atmosphere, dry air atmosphere (for example, dew point of -40°C or less, preferably The first heat treatment is performed at a temperature lower than the dew point of −50° C. or lower, and the hydrogen concentration of the oxide semiconductor layer 106a is reduced. Next, the insulating layer 112 containing oxygen is formed in contact with the oxide semiconductor layer 106a. After that, a second heat treatment is carried out in an inert gas atmosphere or an oxygen gas atmosphere (preferably 200 ℃ or more and 450 ℃ or less, for example, 250 ℃ or more and 350 ℃ or less), and the oxide semiconductor layer 106 Oxidize the oxygen vacancies in a to form an i-type (intrinsic semiconductor) or an oxide semiconductor layer that is as close to i-type as possible. Next, an insulating layer 116 containing hydrogen is formed over the insulating layer 112 containing oxygen. Then, a third heat treatment is carried out at a temperature of 150°C or higher and 450°C or lower, preferably 250°C or higher and 440°C or lower. By performing this, the interface between the insulating layer 102 and the oxide semiconductor layer 106a, the oxide semiconductor layer 106a and at least one of the interfaces between the oxide semiconductor layer 106a and the insulating layer 112 containing oxygen. hydrogen in the insulating layer 116 containing hydrogen is supplied to the oxide semiconductor layer 106a, and defects or By terminating the dangling bonds with hydrogen, the characteristics of the transistor can be improved.

[0155] The conditions of the first heat treatment, the second heat treatment, and the third heat treatment, or the oxide semiconductor layer 10 Depending on the material of the oxide semiconductor layer 106a, a part of the oxide semiconductor layer 106a may be crystallized, and the oxide semiconductor layer 10 In some cases, microcrystals or polycrystals may be formed in the oxide semiconductor layer 10. By making 6a have a structure having a crystalline region in an amorphous region, it is possible to obtain a higher field effect mobility. The oxide semiconductor layer 106a can be an amorphous transistor having a high on-state current. In the case of this structure, it is possible to reduce variations in characteristics among a plurality of elements.

[0156] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0157] (Fourth embodiment) In this embodiment mode, another example of the structure and manufacturing method of the semiconductor device according to the above embodiment mode will be described. and explain.

[0158] <Structure of Semiconductor Device> First, a transistor 150, which is an example of the structure of a semiconductor device described in this embodiment, will be described. The transistor 150 shown in FIG. 7D has a gate electrode layer 10 formed on a substrate 100. A gate insulating layer 102 is formed on the gate electrode layer 101a. An oxide semiconductor layer 106a is formed as a channel formation region on the insulating layer 102. Source and drain electrode layers 108a and 108b are formed over the conductor layer 106a. On the source and drain electrode layers 108a and 108b and the oxide semiconductor layer 106a The insulating layer 112 containing oxygen is formed on the oxide semiconductor layer. The insulating layer containing oxygen is in contact with the oxide semiconductor layer 106a at the back channel of the insulating layer 106a. A gate electrode layer 114 is formed over the oxide semiconductor layer 112 so as to overlap with the oxide semiconductor layer 106a. An insulating layer 116 containing hydrogen is formed to cover the gate electrode layer 114. An insulating layer 118 that functions as a planarization film may be formed on the insulating layer 116. The transistor 150 described in this embodiment has an oxide semiconductor layer 106a containing oxygen. The insulating layer 112 and the insulating layer 116 containing hydrogen are in contact with the insulating layer 112 containing oxygen. It is characterized by the following.

[0159] In this embodiment, the gate electrode layer 114 functions as a so-called back gate. By providing the gate electrode layer 114, it is possible to control the electric field in the oxide semiconductor layer 106a. This allows the electrical characteristics of the transistor 150 to be controlled. The gate electrode layer 114 is electrically connected to other wirings or electrodes and is given a certain potential. It may be insulated and in a floating state.

[0160] Incidentally, the "gate electrode" usually refers to a gate electrode whose potential can be intentionally controlled. In the specification, the term "gate electrode" is used even when the potential is not intentionally controlled. For example, for an isolated, floating conductive layer as described above, The gate electrode layer is also sometimes called a "gate electrode layer."

[0161] <Method for manufacturing semiconductor device> Next, a method for manufacturing a transistor 150, which is an example of a semiconductor device, will be described with reference to FIGS. and explain.

[0162] First, a gate electrode layer 101a is formed on a substrate 100, and then a gate electrode layer 101a is covered with a The gate insulating layer 102 is then formed on the gate insulating layer 102. After forming the oxide semiconductor layer 106a so as to overlap with the source electrode layer and the drain electrode layer 101a, Then, the inner electrode layers 108a and 108b are formed (see FIG. 7(A)). 2 and 3 can be referred to, so detailed explanations will be omitted.

[0163] Next, the oxide semiconductor layer 106a and the source and drain electrode layers 108a and 108b are An insulating layer 112 containing oxygen is formed to cover the insulating layer (see FIG. 7B). The material and forming method of 112 can be seen from FIG. 4(A), so detailed description will be omitted. do.

[0164] Next, the oxide semiconductor layer 106a is preferably subjected to second heat treatment. By performing the treatment, oxygen in the insulating layer 112 containing oxygen is removed from the oxide semiconductor layer 106a The oxygen vacancies in the oxide semiconductor layer 106a are oxidized to form an i-type (intrinsic) or In this case, the oxide semiconductor layer 106a can be formed as close to i-type as possible. The second thermal treatment reduces the variation in the electrical characteristics of the transistors. As for the processing conditions, please refer to the second embodiment, and detailed explanation will be omitted.

[0165] Next, a gate electrode was formed over the insulating layer 112 containing oxygen so as to overlap with the oxide semiconductor layer 106a. The electrode layer 114 is formed (see FIG. 7C). Materials and Forming Method of the Gate Electrode Layer 114 For details, please refer to the gate electrode layer 114 in FIG. 6(C), and detailed description thereof will be omitted. In this embodiment, the gate electrode layer 114 functions as a so-called back gate.

[0166] Next, an insulating layer 116 containing hydrogen is formed to cover the gate electrode layer 114, and then the insulating layer 118 is formed (see FIG. 7(D)).

[0167] The material and the method for forming the insulating layer 116 containing hydrogen are the same as those of the insulating layer 116 shown in FIG. 4B. Therefore, detailed description will be omitted.

[0168] Next, the oxide semiconductor layer 106a is subjected to third heat treatment. For details, please refer to the second embodiment, and detailed description will be omitted. As a result, hydrogen in the insulating layer 116 containing hydrogen is transferred to at least the oxide semiconductor layer 106a. , and the oxide semiconductor layer 106a and the oxide semiconductor layer 106a are diffused or supplied. the interface with the insulating layer 112 containing silicon, the interface between the oxide semiconductor layer 106a and the insulating layer 102, At least one of the defects or dangling bonds in the oxide semiconductor layer 10 is terminated. As a result, the on-current and field-effect mobility of the transistor are improved. do.

[0169] The material and the formation method of the insulating layer 118 can be referred to the insulating layer 118 in FIG. Detailed explanation will be omitted.

[0170] Through the above steps, the transistor 150 including the oxide semiconductor layer 106a is completed.

[0171] In the transistor 150 according to this embodiment, the temperature is set to 400° C. or higher and 750° C. or lower, preferably The temperature is 400°C or higher and lower than the strain point of the substrate, and the atmosphere contains almost no hydrogen or moisture (nitrogen atmosphere). Atmosphere, oxygen atmosphere, dry air atmosphere (for example, dew point of -40°C or less, preferably The first heat treatment is performed at a temperature lower than the dew point of −50° C. or lower, and the hydrogen concentration of the oxide semiconductor layer 106a is reduced. Next, the insulating layer 112 containing oxygen is formed in contact with the oxide semiconductor layer 106a. After that, a second heat treatment is carried out in an inert gas atmosphere or an oxygen gas atmosphere (preferably 200 ℃ or more and 450 ℃ or less, for example, 250 ℃ or more and 350 ℃ or less), and the oxide semiconductor layer 106 Oxidize the oxygen vacancies in a to form an i-type (intrinsic semiconductor) or an oxide semiconductor layer that is as close to i-type as possible. Next, an insulating layer 116 containing hydrogen is formed over the insulating layer 112 containing oxygen. Then, a third heat treatment is carried out at a temperature of 150°C or higher and 450°C or lower, preferably 250°C or higher and 440°C or lower. By this, the interface between the gate insulating layer 102 and the oxide semiconductor layer 106a, the oxide semiconductor layer 1 and at least one of the interfaces between the oxide semiconductor layer 106a and the insulating layer 112 containing oxygen. hydrogen in the insulating layer 116 containing hydrogen is supplied to the oxide semiconductor layer 106a, and defects in the oxide semiconductor layer 106a are removed. Alternatively, dangling bonds are terminated with hydrogen, whereby the characteristics of a transistor can be improved.

[0172] The conditions of the first heat treatment, the second heat treatment, and the third heat treatment, or the oxide semiconductor layer 10 Depending on the material of the oxide semiconductor layer 106a, a part of the oxide semiconductor layer 106a may be crystallized, and the oxide semiconductor layer 10 In some cases, microcrystals or polycrystals may be formed in the oxide semiconductor layer 10. By making 6a have a structure having a crystalline region in an amorphous region, it is possible to obtain a higher field effect mobility. The oxide semiconductor layer 106a can be an amorphous transistor having a high on-state current. In the case of this structure, it is possible to reduce variations in characteristics among a plurality of elements.

[0173] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0174] (Embodiment 5) In this embodiment mode, another example of the method for manufacturing the semiconductor device according to the above embodiment mode will be described. do.

[0175] First, a conductive layer is formed on a substrate having an insulating surface, and the conductive layer is selectively etched. Next, a gate insulating layer is formed to cover the gate electrode layer. The above steps can be performed in the same manner as in the second embodiment. Please refer to the following.

[0176] Next, an amorphous oxide semiconductor layer is formed on the gate insulating layer and is then etched or otherwise removed. Therefore, an island-shaped oxide semiconductor layer is formed. These steps are described in Embodiment 2. In this embodiment, the heat treatment of the oxide semiconductor layer in this step is is not performed.

[0177] Next, a conductive layer is formed so as to be in contact with the oxide semiconductor layer, and the conductive layer is selectively etched. The source electrode layer and the drain electrode layer are formed by the above steps. This can be done in the same way as above, so please refer to the relevant section.

[0178] Next, an insulating layer is formed in contact with part of the oxide semiconductor layer. In the process, hydrogen may be diffused from the insulating layer containing hydrogen and supplied to the oxide semiconductor layer. The insulating layer can be formed by a CVD method, a sputtering method, or the like. As described in Embodiment 2, an insulating layer containing oxygen is formed and then heat treatment is performed to form an oxide semiconductor film. Oxygen may be supplied to the layer, in which case, the same method as shown in the second embodiment may be used. This can be done by

[0179] Next, an insulating layer containing hydrogen is formed over the insulating layer, and then heat treatment is performed. The insulating layer can be formed by using a CVD method, a sputtering method, or the like. The edge layer may be a silicon nitride layer, a silicon oxynitride layer, an aluminum nitride layer, or an aluminum oxynitride layer. It is preferable to form the insulating layer using a hydrogen-containing insulating layer such as a silicon layer. The gas containing nitrogen (typically nitrogen gas, ammonia gas, etc.) is used as a raw material gas. Silicon nitride layer or silicon oxynitride layer formed by CVD method, and aluminum hydride and a gas containing nitrogen (typically, nitrogen gas, ammonia gas, etc.) Aluminum nitride layer and aluminum nitride oxide layer formed by CVD using raw material gas is preferred because it contains a relatively large number of hydrogen atoms.

[0180] The heat treatment is carried out in a nitrogen atmosphere at a temperature of 150°C to 450°C, preferably 250°C to 440°C. The temperature is set to 0°C or lower. The heat treatment is not limited to a nitrogen atmosphere, but may be performed in an oxygen atmosphere, a rare gas atmosphere, or the like. The heating may be carried out in a gas atmosphere or a dry air atmosphere.

[0181] By the heat treatment, hydrogen in the insulating layer containing hydrogen is diffused into at least the oxide semiconductor layer. and a gate insulating layer and an oxide semiconductor layer. Defects or imperfections remaining at at least one of the interface between the oxide semiconductor layer and the insulating layer containing oxygen This reduces defects in the oxide semiconductor layer and improves transistor characteristics. As a result, the on-state current and field-effect mobility of the transistor are improved.

[0182] From the above, we can conclude that the transistor is one in which defects are terminated by diffusing hydrogen contained in the insulating layer containing hydrogen. is completed.

[0183] Although a bottom-gate transistor is described in this embodiment, the present invention is not limited to this. The transistor may be a top gate type or a so-called back gate type. The transistor may have a structure including a gate.

[0184] A transistor having high field-effect mobility and on-state current can be fabricated by the method described in this embodiment. This can be achieved.

[0185] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0186] (Sixth embodiment) In this embodiment, a transistor is provided in which hydrogen is supplied to improve the on-current and field-effect mobility. The transistor is used in a pixel portion and a driver circuit to produce a semiconductor device having a display function. A case where a part of a driver circuit or a display device is manufactured will be described. Or the entire display can be formed on the same substrate as the pixel section to form a system-on-panel. Cut.

[0187] In this embodiment, a liquid crystal display device will be described as an example of a semiconductor device which is one embodiment of the present invention. First, the appearance and cross section of a liquid crystal display panel, which is one mode of a semiconductor device, will be described with reference to FIG. 8. FIG. 8 shows a hydrogen-supplied oxide material formed on a first substrate 4001. The transistors 4010 and 4011 each including the above semiconductor layer and the liquid crystal element 4013 are 4006 and the substrate 4006 are sealed with a sealant 4005. 8(B) corresponds to a cross-sectional view taken along line MN in FIG. 8(A).

[0188] A pixel portion 4002, a signal line driver circuit 4003, and a scanning A sealing material 4005 is provided so as to surround the line driver circuit 4004. A second substrate 4002 is disposed on the signal line driver circuit 4003 and the scanning line driver circuit 4004. 006 is provided. Therefore, the pixel portion 4002, the signal line driver circuit 4003, and the scanning line The driver circuit 4004 is formed on a first substrate 4001, a sealing material 4005, and a second substrate 4006. Therefore, it is sealed together with the liquid crystal layer 4008 .

[0189] A pixel portion 4002 and a signal line driver circuit 4003 are provided on a first substrate 4001. The scanning line driver circuit 4004 has a plurality of transistors. The transistor 4010 included in the scanning line driver circuit 4002 and the transistor 4010 included in the scanning line driver circuit 4004 The insulating layer 402 is formed on the transistors 4010 and 4011. 0, 4021 are provided.

[0190] The transistors 4010 and 4011 are made of the oxide semiconductor to which hydrogen is supplied, as described in the above embodiment. A transistor including a conductor layer can be applied. The transistors 4010 and 4011 are n-channel transistors.

[0191] The oxide semiconductor layer of the transistor 4011 for the driver circuit is formed over the insulating layer 4021. A conductive layer 4040 is provided in a position overlapping the panel formation region. By placing it in a position that overlaps with the channel formation region of the semiconductor layer, The amount of change in the threshold voltage of the transistor 4011 can be reduced. The potential of the gate electrode layer of the transistor 4011 may be the same as or different from that of the gate electrode layer of the transistor 4011. The conductive layer 4040 may also function as a second gate electrode layer. The potential may be GND, 0V, or floating.

[0192] In addition, a pixel electrode layer 4030 of the liquid crystal element 4013 is electrically connected to the transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is connected to the second substrate 4006. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 are overlapped. The portion where the pixel electrode layer 4030 is formed corresponds to the liquid crystal element 4013. The layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between edge layers 4032 and 4033 .

[0193] The second substrate 4006 can be made of glass or plastic.

[0194] The spacers 4035 are columnar spacers obtained by selectively etching an insulating layer. The distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 is controlled. A spherical spacer may also be used. The layer 4031 is electrically connected to a common potential line provided on the same insulating substrate as the transistor 4010. Also, by using a common connection part, the pair of substrates are connected via conductive particles disposed between the substrates. The counter electrode layer 4031 and the common potential line can be electrically connected by the conductive particles. The molecule is contained in the sealing material 4005 .

[0195] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 1 msec. sec or less, and because it is optically isotropic, alignment treatment is not required, and viewing angle dependency is small. stomach.

[0196] In addition, when a liquid crystal that exhibits a blue phase is used, rubbing treatment of the alignment film is not required. This prevents electrostatic damage caused by the soldering process, and prevents the LCD display from being damaged during the manufacturing process. This reduces the number of defects and damages to the device, thereby improving the productivity of liquid crystal display devices. In particular, in a transistor including an oxide semiconductor layer, the influence of static electricity can The electrical characteristics of the transistor may fluctuate significantly and deviate from the design range. Use of a blue phase liquid crystal material in a liquid crystal display device having transistors using a nitride semiconductor layer - Patents.com In addition, when a blue phase is used, it is not limited to the configuration of FIG. The electrode layer corresponding to the polar layer 4031 is formed on the same substrate side as the pixel electrode layer 4030. A so-called transverse electric field mode configuration may also be used.

[0197] Although the liquid crystal display device shown in this embodiment is an example of a transmissive liquid crystal display device, a reflective liquid crystal display device may also be used. The display device may be a display device or a semi-transmissive liquid crystal display device.

[0198] In addition, in the liquid crystal display device described in this embodiment mode, a polarizing plate is provided on the outer side (viewing side) of the substrate, and An example is shown in which a colored layer (color filter) and an electrode layer used for a display element are provided on the side in this order. The polarizing plate may be provided on the inner side of the substrate. Also, a laminated structure of the polarizing plate and the colored layer is also applicable to this embodiment. There are no limitations, and the thickness may be appropriately determined depending on the materials of the polarizing plate and the colored layer and the manufacturing process conditions. If necessary, a light-shielding layer that functions as a black matrix may be provided.

[0199] In this embodiment, in order to reduce the surface irregularities caused by the transistor, To improve the reliability of the transistor, an insulating layer is used to protect the transistor and act as a planarizing insulating layer. The insulating layer 4020, the insulating layer 4014, and the insulating layer 4021 are used to cover the insulating layer 4020. The protective layer is used to prevent the intrusion of polluting impurities such as organic matter, metals, and water vapor floating in the air. The protective layer is formed by sputtering silicon oxide. layer, silicon nitride layer, silicon oxynitride layer, silicon nitride oxide layer, aluminum oxide layer, aluminum nitride layer Aluminum nitride layer, aluminum oxynitride layer, or aluminum nitride oxide layer, or a laminated layer. Just do that.

[0200] Here, a laminate of insulating layers is formed as a protective layer. Then, a silicon oxide layer is formed by sputtering. By doing so, oxygen is added to the oxide semiconductor layer in contact with the protective layer, and oxygen vacancies can be reduced. .

[0201] Further, an insulating layer 4014 is formed as the second layer of the protective layer. As 14, a silicon nitride layer containing hydrogen is formed using a plasma CVD method, and then heat treatment is performed. When a silicon nitride layer is used as a protective layer, hydrogen is diffused into the oxide semiconductor layer. Ions such as sodium penetrate into the semiconductor region and change the electrical characteristics of the transistor. This can be suppressed.

[0202] An insulating layer 4021 is formed as a planarizing insulating layer. Heat-resistant organic compounds such as amide, acrylic, benzocyclobutene, polyamide, and epoxy. In addition to the above organic materials, low-k materials can also be used. , siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. In addition, by laminating multiple insulating layers made of these materials, the insulating layer 4021 may be formed.

[0203] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive material can be used.

[0204] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or Various signals and potentials to be applied to the pixel portion 4002 are supplied from an FPC 4018 .

[0205] In this embodiment, the connection terminal electrode 4015 is connected to the pixel electrode layer 40 of the liquid crystal element 4013. 30, and the terminal electrode 4016 is formed from the same conductive layer as the transistors 4010 and 4011. The source electrode layer and the drain electrode layer are formed of the same conductive layer as the source electrode layer and the drain electrode layer.

[0206] The connection terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive layer 4019. are electrically connected.

[0207] If necessary, a color filter is provided corresponding to each pixel. A polarizing plate and a diffusing plate are provided on the outside of the first and second substrates 4001 and 4006. The source is composed of cold cathode fluorescent lamps and LEDs, forming a liquid crystal display module.

[0208] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-Plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) Switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) refrigeration mode, FLC (Ferroelectric Liquid d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0209] Through the above steps, a liquid crystal display device can be manufactured.

[0210] The transistor including the oxide semiconductor layer to which hydrogen is supplied, which is described in the above embodiment, has high electric potential. Since the semiconductor has a field effect mobility, it can be used to manufacture a liquid crystal display device as in this embodiment. This makes it possible to realize a liquid crystal display device with excellent display characteristics.

[0211] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0212] (Embodiment 7) The appearance and cross section of a light-emitting display panel (also called a light-emitting panel) which corresponds to one form of a semiconductor device are shown. This will be explained with reference to FIG. 9. FIG. 9 shows an oxygen film formed on a first substrate and supplied with hydrogen. The transistor and the light emitting element including the nitride semiconductor layer are sandwiched between the second substrate and the transistor and the light emitting element by a sealing material. 9(B) is a cross-sectional view of the panel taken along line HI in FIG. 9(A). Equivalent.

[0213] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. 3b and the scanning line driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealing material 4505, and a second substrate 4506. The seal is sealed together with the filler 4507 by the sealant. Packaging (enclosing) with a highly airtight protective film or covering material that minimizes outgassing is preferred.

[0214] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b each have a plurality of transistors. 9B, a transistor 4510 included in a pixel portion 4502 and a signal line driver circuit 4 illustrates a transistor 4509 included in the circuit 4503a.

[0215] The transistors 4509 and 4510 are high-mobility transistors including an oxide semiconductor layer to which hydrogen is supplied. In this embodiment, a transistor 4509 , 4510 is an n-channel transistor.

[0216] The channel of the oxide semiconductor layer of the transistor 4509 for the driver circuit is formed over the insulating layer 4544. A conductive layer 4540 is provided in a position overlapping with the hole formation region. The potential of the gate electrode layer of the transistor 4509 may be the same as or different from that of the gate electrode layer of the transistor 4509. The conductive layer 4540 can also function as a gate electrode layer of the gate electrode ... It may be D, 0V, or floating.

[0217] The transistor 4509 has an insulating layer in contact with a semiconductor layer including a channel formation region as a protective insulating layer. The insulating layer 4541 is formed on the insulating layer 112 shown in the previous embodiment. The protective insulating layer 4514 may be formed over the insulating layer 4541 using a material and a method similar to those of the insulating layer 4541. The protective insulating layer 4514 is formed in the same manner as the insulating layer 116 described in the above embodiment. Here, the protective insulating layer 4514 is formed by a PCVD method. A silicon nitride layer is formed.

[0218] Further, a planarization insulating layer for reducing surface unevenness of the transistor is formed over the protective insulating layer 4514. A functional insulating layer 4544 is formed. As the insulating layer 4544, the insulating layer shown in Embodiment 6 is used. The planarization insulating layer 4544 may be formed using a material and a method similar to those of the edge layer 4021. Acrylic is used as the material.

[0219] Further, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the transistor 4510. The light-emitting element 4511 is configured with a first electrode layer 4517, an electroluminescent layer 45 12, the second electrode layer 4513 has a stacked structure, but is not limited to the structure shown. The configuration of the light emitting element 4511 can be changed appropriately according to the direction of the light extracted from 4511. This can be done.

[0220] The partition wall 4520 is formed using an organic resin layer, an inorganic insulating layer, or organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable that the surface is an inclined surface having a continuous curvature.

[0221] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers stacked. It may be possible to do so.

[0222] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511. A protective layer may be formed on the partition wall 4513 and the partition wall 4520. The protective layer may be a silicon nitride layer, A silicon nitride oxide layer, a DLC layer, or the like can be formed.

[0223] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are transmitted through the FPC 4518a, 4518b, and It is supplied by b.

[0224] The connection terminal electrode 4515 is formed on the same conductive layer as the first electrode layer 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed from the source voltage of the transistors 4509 and 4510. The electrode layer and the drain electrode layer are formed from the same conductive layer.

[0225] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive layer 4519. are electrically connected to each other.

[0226] The substrate located in the direction in which light is extracted from the light emitting element 4511 must be light-transmitting. In this case, use a glass plate, plastic plate, polyester film or acrylic film. A light-transmitting material such as polyethylene is used.

[0227] In addition to inert gases such as nitrogen and argon, filler 4507 can also be used as UV-curable resin. It can be made of oil or thermosetting resin, and PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. For example, nitrogen can be used as a filler. That's fine.

[0228] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0229] Through the above steps, a light-emitting display device (display panel) can be manufactured.

[0230] The transistor including the oxide semiconductor layer to which hydrogen is supplied, which is described in the above embodiment, has high electric potential. Since the semiconductor has a field effect mobility, it can be used to manufacture a light emitting display device as in this embodiment. This makes it possible to realize a light emitting display device with excellent display characteristics.

[0231] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0232] (Embodiment 8) An example of electronic paper will be shown as one mode of the semiconductor device.

[0233] The transistor in which the on-current and field-effect mobility are improved by supplying hydrogen is It can also be used in electronic paper, which drives electronic ink using elements electrically connected to the elements. Electronic paper is also called an electrophoretic display (electrophoretic display), It is as easy to read as paper, and consumes less power, is thinner, and is lighter than other display devices. This has the advantage that

[0234] Electrophoretic displays can be of various types, for example, those having a positive charge. Microcapsules containing first particles and second particles having a negative charge are dissolved in a solvent or is dispersed in a solute, and by applying an electric field to the microcapsules, The particles in the microcapsules are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is measured. The first particles or the second particles may contain a dye, In the absence of an electric field, the particles do not move. are different (including colorless).

[0235] Thus, electrophoretic displays allow materials with high dielectric constants to migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect.

[0236] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Color display is also possible by using color filters or particles containing pigments.

[0237] Furthermore, the microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. By applying an electric field to the cells, a display can be achieved. For example, the active matrix using the transistor to which hydrogen is supplied, which is described in the above embodiment, A metal substrate can be used.

[0238] The first particles and the second particles in the microcapsules may be made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from magnetochromic materials, magnetophoretic materials, or a composite material thereof It can be formed using

[0239] FIG. 10 shows an active matrix electronic paper as an example of a semiconductor device. The transistor 581 used in the semiconductor device is the same as the transistor shown in the previous embodiment. The insulating layer 584 is a high-mobility transistor supplied with hydrogen. The insulating film containing hydrogen is provided to supply hydrogen to the oxide semiconductor material.

[0240] The electronic paper in Figure 10 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. and a potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying by controlling the orientation of spherical particles by generating a liquid crystal.

[0241] The transistor 581 on the substrate 580 is a bottom-gate transistor, and the semiconductor layer The source electrode layer or drain electrode layer of the transistor 581 is covered with an insulating layer 583 that is in contact with the The electrode layer is a first electrode layer 587 and insulating layers 583, 584, 585. The first electrode layer 587 and the second electrode layer 596 are electrically connected to each other. Between the black region 590a and the white region 588, there are spherical particles. 90b, which includes a cavity 594 therearound that is filled with a liquid. The periphery of the tee 594 is filled with a filler 595 such as resin (see FIG. 10).

[0242] The first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. The second electrode layer 588 is a common potential The conductive particles disposed between the pair of substrates are electrically connected to the wiring by using the common connection part. The second electrode layer 588 and a common potential line can be electrically connected via the wiring.

[0243] Also, instead of the twist ball, an electrophoretic element can be used. and a diameter of 10 μm to 20 μm that contains positively charged white particles and negatively charged black particles. Microcapsules of about 0 μm in size are used. When an electric field is applied by the first and second electrode layers, the microcapsules turn white. White particles and black particles move in opposite directions, allowing the display to be white or black. The display element that applies this principle is an electrophoretic display element, which is generally called electronic paper. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lights are not required. It also consumes little power and the display can be seen even in dimly lit places. Even if power is not supplied to the display unit, the image that has been displayed can be retained. Therefore, the semiconductor device with a display function (simply a display device, or a device equipped with a display device) is The ability to preserve the displayed image even when the device (also known as a semiconductor device) is moved away This becomes possible.

[0244] Through the above steps, electronic paper can be produced.

[0245] In this embodiment, a so-called electronic paper The transistor has high field-effect mobility, By manufacturing electronic paper, electronic paper with excellent display characteristics can be realized.

[0246] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0247] (Embodiment 9) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). As the electronic device, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras digital photo frames, mobile phones (also called mobile phones or mobile phone devices), portable Examples include game machines, mobile information terminals, sound reproduction devices, and large game machines such as pachinko machines. do.

[0248] In this embodiment, an electronic device equipped with the display device obtained in any one of the sixth to eighth embodiments is provided. An example of the device will be described with reference to FIGS.

[0249] FIG. 11(A) shows a notebook-type personal computer manufactured by mounting at least a display device as a component. It is a personal computer, and it has a main body 3001, a housing 3002, a display unit 3003, a keyboard 3004, and a 004, etc. The liquid crystal display device shown in the sixth embodiment is a notebook type. The personal computer has

[0250] FIG. 11(B) shows a portable information terminal (P DA), and the main body 3021 includes a display unit 3023, an external interface 3025, Operation buttons 3024 and the like are provided. A stylus 3022 is also provided as an accessory for operation. Note that the portable information terminal includes the light-emitting display device described in Embodiment 7.

[0251] FIG. 11(C) shows an electronic book manufactured by mounting the electronic paper shown in the eighth embodiment as a component. FIG. 11(C) shows an electronic book 2700. For example, the electronic book 2700 The device is made up of two housings, housing 2701 and housing 2703. The housing 2703 is integrated with a shaft 2711, and is opened around the shaft 2711. This configuration allows the book to be opened and closed like a paper book. It becomes possible.

[0252] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a sentence is displayed on the right display unit (display unit 2705 in FIG. 11C), and An image can be displayed on the display portion (the display portion 2707 in FIG. 11C).

[0253] FIG. 11C shows an example in which an operation unit and the like are provided in the housing 2701. For example, The housing 2701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The back of the housing may be provided with a keyboard, a pointing device, etc. External connection terminals (earphone terminal, USB terminal, AC adapter and USB) on the front or side It is equipped with a terminal that can be connected to various cables such as USB cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have the function of an electronic dictionary. It may also be possible to use the following.

[0254] The electronic book 2700 may also be configured to be able to send and receive information wirelessly. The desired book data can be purchased and downloaded from the e-book server. is also possible.

[0255] FIG. 11(D) shows a mobile phone manufactured by mounting at least a display device as a component. It consists of two housings, housing 2800 and housing 2801. Housing 2801 has a display Panel 2802, speaker 2803, microphone 2804, pointing device 2806, a camera lens 2807, an external connection terminal 2808, etc. The housing 2800 contains a solar cell 2810 for charging the portable information terminal, an external memory slot, The housing 2801 is provided with a built-in antenna.

[0256] The display panel 2802 is equipped with a touch panel, and the image displayed in FIG. The multiple operation keys 2805 are indicated by dotted lines. It also has a boost circuit to boost the voltage required for each circuit.

[0257] The display direction of the display panel 2802 changes appropriately depending on the usage mode. The camera lens 2807 is located on the same surface as the camera lens 2802, so video calls are possible. The speaker 2803 and microphone 2804 are not limited to voice calls, but also to video calls, Recording and playback are possible. Furthermore, the housing 2800 and the housing 2801 can be slid apart. As shown in 11(D), it can be folded from the unfolded state to the overlapped state, making it suitable for carrying. This makes it possible to miniaturize the device.

[0258] The external connection terminal 2808 can be connected to various cables such as AC adapters and USB cables. It is possible to charge the battery and to communicate data with a personal computer, etc. By inserting a recording medium into the memory slot 2811, it is possible to store and transfer a larger amount of data. do.

[0259] In addition to the above functions, even if the device has infrared communication function, TV reception function, etc. good.

[0260] FIG. 11(E) shows a digital camera manufactured by mounting at least a display device as one component. It includes a main body 3051, a display unit (A) 3057, an eyepiece 3053, an operation switch 3054, and a display It is composed of a display unit (B) 3055, a battery 3056, etc.

[0261] 12 shows a television device 9600. The television device 9600 has a housing A display unit 9603 is built into the 9601. The display unit 9603 displays images. In this case, the housing 9601 is supported by a stand 9605. This shows the progress.

[0262] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the information displayed on the display 9603 is In addition, the remote control operation device 9610 can operate the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0263] The television device 9600 is configured to include a receiver, a modem, and the like. It can receive more general TV broadcasts and can also receive them via wired or wireless modems. By connecting to a communication network, it can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0264] The display portion 9603 includes the transistor shown in the above embodiment as a switching element of a pixel. A plurality of display units 9603 are arranged, and the display unit 9603 and the display unit 9603 are formed on the same insulating substrate as the driving circuit. A high mobility transistor shown in the embodiment is arranged.

[0265] This embodiment mode can be freely combined with any one of Embodiment Modes 1 to 8. [Explanation of symbols]

[0266] 100 boards 101 Conductive layer 102 Insulating layer 106 Oxide semiconductor layer 108 Conductive layer 112 Insulating layer 113 Insulating layer 116 Insulating Layer 114 gate electrode layer 118 Insulating Layer 150 transistors 101a gate electrode layer 106a Oxide semiconductor layer 108a Drain electrode layer 580 board 581 Transistor 583 Insulating Layer 584 Insulating Layer 587 Electrode layer 588 Electrode layer 594 Cavity 595 Filling material 596 PCB 2700 e-books 2701 Case 2703 Housing 2705 Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation Key 2725 Speaker 2800 chassis 2801 Case 2802 Display panel 2803 Speaker 2804 Microphone 2805 Operation Key 2806 Pointing Device 2807 Camera lenses 2808 External connection terminal 2810 solar cell 2811 external memory slot 3001 main unit 3002 Case 3003 Display section 3004 Keyboard 3021 Main Unit 3022 stylus 3023 Display section 3024 Operation button 3025 External Interface 3051 Main Unit 3053 Eyepiece 3054 Operation switch 3055 Display section (B) 3056 Battery 3057 Display section (A) 4001 board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 board 4008 Liquid crystal layer 4010 transistor 4011 transistor 4013 Liquid crystal element 4014 Insulation layer 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive layer 4020 Insulation layer 4021 Insulation layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4040 Conductive layer 4501 Circuit Board 4502 Pixel section 4505 Sealing material 4506 board 4507 Filling material 4509 Transistor 4510 transistor 4511 Light-emitting element 4512 Electroluminescent layer 4513 Electrode layer 4514 Protective insulation layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4519 Anisotropic conductive layer 4520 Bulkhead 4540 Conductive layer 4541 Insulation layer 4544 Insulation layer 590a black area 590b White area 9600 Television Equipment 9601 Housing 9603 Display section 9605 Stand 9607 Display section 9609 Operation Key 9610 Remote Control Machine 4503a Signal line driver circuit 4504a Scanning line driver circuit 4518a FPC

Claims

[Claim 1] forming an oxide semiconductor layer; forming a first insulating layer containing oxygen over the oxide semiconductor layer; a second insulating layer containing nitrogen and aluminum, or oxygen and aluminum, or nitrogen, oxygen, and aluminum, formed over the first insulating layer, and then heat treatment is performed at a temperature of 150° C. or higher and 450° C. or lower.

Images