Semiconductor device and method for manufacturing semiconductor device

Abstract

To improve recovery characteristics by more effectively suppressing hole injection into a diode part in a reverse conducting IGBT (RC-IGBT).SOLUTION: In a RC-IGBT 1, an IGBT part 3 includes a first semiconductor layer 16 of a first conductivity type, a plurality of first trenches 5 formed in the first semiconductor layer, a body layer 9 of a second conductivity type sandwiched between the plurality of first trenches and formed on the first semiconductor layer, and a source layer 11 of the first conductivity type sandwiched between the plurality of first trenches and formed on the body layer. A diode 4 includes the first semiconductor layer and a plurality of second trenches 5 formed in the first semiconductor layer, and also includes a first portion sandwiched between the plurality of second trenches and having the body layer formed on the first semiconductor layer, and a second portion sandwiched between the plurality of second trenches and having a Schottky barrier junction SBD formed by contacts in the first semiconductor layer and the first semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device structure and a manufacturing method thereof, and in particular to a technique that is effective when applied to a reverse conducting IGBT (RC-IGBT) in which an IGBT and a diode are built into the same chip. [Background technology]

[0002] IGBTs (Insulated Gate Bipolar Transistors), which are capable of high-power, high-speed switching, are widely used in a wide range of applications, from industrial to consumer, and even automotive applications, including motor control inverters for electric vehicles and trains, and inverter circuits for induction cookware, washing machines, and air conditioners.

[0003] In many IGBT applications, there is a mode in which a freewheeling current flows from the emitter to the collector. Conventionally, to accommodate this freewheeling operation, a freewheeling diode is connected in anti-parallel to the IGBT on a separate chip.

[0004] In recent years, reverse conducting IGBTs (RC-IGBTs), which combine an IGBT and a freewheel diode on a single chip, have become increasingly popular. A reverse conducting IGBT incorporates a freewheel diode into the IGBT chip, and a diode is connected in reverse parallel to the IGBT to perform freewheeling operation.

[0005] As background art in this technical field, for example, there is a technique such as that disclosed in Patent Document 1. Patent Document 1 discloses "a technique for suppressing gate interference in an RC-IGBT employing a diode structure with a Schottky connection."

[0006] In Patent Document 1, n-type pillar layers (24a, 24b) are provided in the diode section, and a Schottky barrier diode is built in, thereby suppressing hole injection into the pn diode.

[0007] Furthermore, Patent Document 2 discloses a "semiconductor device with a short recovery time."

[0008] In Patent Document 2, a connection region 16 is provided in the diode portion, and a lower end 16d and an n - Layer 21 has a structure in which a Schottky barrier diode is built in. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-165541 [Patent Document 2] Japanese Patent Application Laid-Open No. 2017-55079 Summary of the Invention [Problem to be solved by the invention]

[0010] Reverse conducting IGBTs (RC-IGBTs) have the advantage of reducing chip size by allowing the termination areas of the IGBT and diode to be shared, and reducing thermal resistance because losses generated in the IGBT or diode areas are dissipated throughout the entire chip.

[0011] On the other hand, since the IGBT and diode are fabricated on the same chip, simultaneous optimization of each chip is difficult, and controlling the lifetime of the diode is particularly difficult, making it difficult to reduce the diode injection and recovery loss.

[0012] In the above-mentioned Patent Document 1, an n-pillar layer is formed to incorporate a Schottky barrier diode in the diode section of the RC-IGBT. However, in order to form this pillar layer, in addition to the normal process for forming the diode section of the RC-IGBT, an additional photolithography step and ion implantation step are required to form the n-pillar layer. Furthermore, since the n-pillar layer is provided inside the p-body layer, miniaturization is difficult, which poses a problem of limitations on characteristic improvement.

[0013] In addition, in the above-mentioned Patent Document 2, a connection region is provided in the diode section, and n - Although a contact layer is provided between the layers, there is no p-body layer in the diode section, so when the breakdown voltage is maintained, the electric field concentrates at the corners of the connection area, raising concerns about a decrease in breakdown voltage and an increase in leakage current.

[0014] Therefore, an object of the present invention is to provide a semiconductor device and a manufacturing method thereof that can more effectively suppress hole injection into the diode portion and improve recovery characteristics in a reverse conducting IGBT (RC-IGBT) that incorporates an IGBT and a diode on the same chip. [Means for solving the problem]

[0015] In order to solve the above-mentioned problems, the present invention provides a semiconductor device having an IGBT and a diode on the same chip, wherein the IGBT has a first semiconductor layer of a first conductivity type, a plurality of first trenches formed in the first semiconductor layer, a body layer of a second conductivity type sandwiched between the plurality of first trenches and formed on the first semiconductor layer, and a source layer of the first conductivity type sandwiched between the plurality of first trenches and formed on the body layer; and the diode has the first semiconductor layer and a plurality of second trenches formed in the first semiconductor layer, and has a first portion sandwiched between the plurality of second trenches and having the body layer formed on the first semiconductor layer, and a second portion sandwiched between the plurality of second trenches and having a Schottky barrier junction formed by contacts between the first semiconductor layer and the first semiconductor layer.

[0016] The present invention also provides a method for forming a semiconductor substrate having a main surface including the steps of: (a) forming a plurality of first trenches in a first region of the main surface of the semiconductor substrate and forming a plurality of second trenches in a second region; (b) sequentially depositing an insulating film and an electrode film in each of the first trenches and the second trenches, and forming a gate electrode in the first trench by photolithography and dry etching, and forming an electrode in the second trench; (c) selectively forming a mask between some of the second trenches on the second region; and (d) implanting p-type impurities into the main surface of the semiconductor substrate excluding the first trenches and the second trenches. (e) forming an interlayer insulating film on the main surface of the semiconductor substrate and forming a contact hole by photolithography and dry etching that penetrates the interlayer insulating film and exposes the p-body layer and the semiconductor substrate between the first trench and the second trench; and (f) forming a metal film on the main surface of the semiconductor substrate so as to fill the contact hole and forming a contact by photolithography and dry etching, wherein a Schottky barrier junction is formed between the semiconductor substrate and the contact between the second trench. [Effects of the Invention]

[0017] According to the present invention, it is possible to realize a semiconductor device and a manufacturing method thereof that can more effectively suppress hole injection into the diode portion and improve recovery characteristics in a reverse conducting IGBT (RC-IGBT) that has an IGBT and a diode built into the same chip.

[0018] Problems, configurations, and effects other than those described above will become apparent from the following description of the embodiments. [Brief explanation of the drawings]

[0019] [Figure 1] 1 is a diagram schematically illustrating a cross-sectional structure of a reverse conducting IGBT according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a perspective view of the reverse conducting IGBT of FIG. [Figure 3A] 2A to 2C are diagrams illustrating a manufacturing process of the reverse conducting IGBT of FIG. [Figure 3B] FIG. 3B is a diagram showing the manufacturing process following FIG. 3A. [Figure 3C] FIG. 3C is a diagram showing the manufacturing process following FIG. 3B. [Figure 3D] FIG. 3D is a diagram showing the manufacturing process following FIG. 3C. [Figure 3E] FIG. 3B is a diagram showing the manufacturing process subsequent to FIG. 3D. [Figure 3F] FIG. 3C is a diagram showing the manufacturing process subsequent to FIG. 3E. [Figure 4] FIG. 4 is a diagram schematically illustrating a cross-sectional structure of a reverse conducting IGBT according to a second embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0020] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are designated by the same reference numerals, and detailed description of overlapping parts will be omitted. [Example]

[0021] First Embodiment A semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 3F.

[0022] Fig. 1 is a diagram schematically showing the cross-sectional structure of a reverse conducting IGBT (RC-IGBT) of this embodiment. Fig. 2 is a perspective view of the reverse conducting IGBT 1 of Fig. 1. Figs. 3A to 3F are diagrams showing the manufacturing process of the reverse conducting IGBT 1 of Fig. 1. Note that in Fig. 2, the interlayer insulating film 12, front surface electrode 15, and back surface electrode 20 of Fig. 1 are omitted to make the structure easier to understand.

[0023] As shown in FIGS. 1 and 2, a reverse conducting IGBT (RC-IGBT) 1 of this embodiment is configured by incorporating an IGBT section 3 and a diode section 4 in the same chip.

[0024] Reverse conducting IGBT1 is -The semiconductor device has a plurality of trenches 5 formed in the main surface of a semiconductor substrate (silicon substrate) 2. A plurality of trenches 5 are formed in each of the region where the IGBT section 3 is formed and the region where the diode section 4 is formed, and further, a trench 5 is also formed in the boundary region between the IGBT section 3 and the diode section 4.

[0025] The interval between the trenches 5 formed in the diode section 4 has a portion with a width W1 and a portion with a width W2 narrower than the width W1 (W1>W2) for reasons that will be described later.

[0026] An insulating film (silicon oxide film) 6 is formed inside each trench 5 so as to cover the bottom and side surfaces of the trench 5.

[0027] In the region where the IGBT section 3 is formed, p-body layers 9 are formed on the main surface of the semiconductor substrate 2 on both sides of the trench 5 so as to sandwich the trench 5 therebetween.

[0028] Inside the trench 5 of the IGBT section 3, a gate electrode (polysilicon electrode) 7 is formed with an insulating film (silicon oxide film) 6 interposed therebetween.

[0029] Furthermore, inside the trench 5 of the diode portion 4, an emitter electrode (polysilicon electrode) 8 is formed with an insulating film (silicon oxide film) 6 interposed therebetween.

[0030] In the region where the IGBT section 3 is formed, a p-body layer 9 is formed on the main surface of the semiconductor substrate 2 between the trenches 5, in a manner sandwiched between the trenches 5. In addition, an n + A layer 11 is formed.

[0031] On the other hand, in the region where the diode portion 4 is formed, there are a portion where the p-body layer 9 is formed on the main surface of the semiconductor substrate 2 between the trenches 5 in a manner sandwiched between the trenches 5, and a portion where the p-body layer 9 is not formed between the trenches 5 and is the n-type semiconductor substrate 2. - There is a portion where layer 16 is present.

[0032] The main surface of the semiconductor substrate 2 is provided with an n-type IGBT section 3. + An interlayer insulating film 12 is formed to cover the layer 11, the insulating film 6, and the gate electrode 7 in the trench 5, and also to cover the p-body layer 9 of the diode portion 4, the insulating film 6, and the emitter electrode 8 in the trench 5.

[0033] The interlayer insulating film 12 is provided with a p-type body layer 12 of the IGBT section 3 and the diode section 4, an n-type body layer 12 of the diode section 4, and a n-type body layer 12 of the IGBT section 3 and the diode section 4. - A contact hole 13 is formed down to the layer 16 .

[0034] A surface electrode 15 is formed on the interlayer insulating film 12 so as to cover the interlayer insulating film 12. The surface electrode 15 is also embedded inside the contact hole 13, and forms a contact 14 for the IGBT section 3 and the diode section 4. In each p body layer 9 where the bottom of the contact hole 13 is located, a p + A layer 10 is formed.

[0035] An n-buffer layer 17 is formed on the back surface side of the semiconductor substrate 2. A p-layer 18 is further formed outside the n-buffer layer 17 of the IGBT section 3, and an n-layer 19 is further formed outside the n-buffer layer 17 of the diode section 4. + The p-layer 18 and the n-layer 19 are formed. + Further outside the layer 19, a back electrode 20 is formed.

[0036] The reverse conducting IGBT (RC-IGBT) 1 of this embodiment is configured as described above, and in the diode section 4, the p-body layer 9 (p-type anode layer) is not provided in a part of the region, and the n - n-type semiconductor substrate (silicon substrate) 2 -A Schottky barrier diode (SBD) having a direct Schottky contact with layer 16 is provided. Unlike Patent Document 2, a p-layer is not provided in the SBD region, which reduces the p-layer area of the anode, thereby realizing low injection and reduced recovery loss of the diode.

[0037] In addition, n - Since the contact 14 is provided directly in the layer 16, there is a concern that the electric field concentration at the corners of the contact 14 may reduce the breakdown voltage and increase the leakage current. However, by making the trench spacing (W2) connected to the emitter electrode 8 smaller than the spacing (W1) of a normal IGBT or pn diode (W1>W2), the electric field at the corners of the SBD contact 14 can be alleviated and the breakdown voltage can be maintained.

[0038] A method for manufacturing the reverse conducting IGBT (RC-IGBT) 1 of FIGS. 1 and 2 will be described with reference to FIGS. 3A to 3F.

[0039] First, as shown in FIG. 3A, - A plurality of trenches 5 are formed in the main surface of a mold semiconductor substrate (silicon substrate) 2. At this time, the trenches 5 are formed in the region where the IGBT section 3 is to be formed, the region where the diode section 4 is to be formed, and the boundary region between the IGBT section 3 and the diode section 4.

[0040] Next, as shown in FIG. 3B, an insulating film (silicon oxide film) 6 and a polysilicon film (polysilicon electrodes 7, 8) are formed in this order on the main surface of the semiconductor substrate 2 so as to fill the trench 5 of the IGBT section 3, the trench 5 of the diode section 4, and the trench 5 in the boundary region between the IGBT section 3 and the diode section 4. Then, by photolithography and dry etching, a gate electrode 7 is formed in the trench 5 of the IGBT section 3, and an emitter electrode 8 is formed in the trench 5 of the diode section 4.

[0041] Next, as shown in FIG. 3C, a mask is selectively formed between each trench 5, each insulating film 6, and some of the trenches 5 in the region where the diode portion 4 is to be formed, and a p-body layer 9 is formed on the main surface of the semiconductor substrate 2 by ion implantation of p-type impurities.

[0042] Furthermore, n-type impurity ions are implanted into the main surface of the semiconductor substrate 2, forming n + Layer 11 is formed.

[0043] Next, as shown in FIG. 3D , an interlayer insulating film 12 is formed on the main surface of the semiconductor substrate 2, and contact holes 13 are formed by photolithography and dry etching to penetrate the interlayer insulating film 12 and expose the p-body layer 9 and the semiconductor substrate 2 between the trenches 5 in the IGBT section 3 and the diode section 4.

[0044] Next, as shown in FIG. 3E, after the contact holes 13 exposing the semiconductor substrate 2 are covered with a mask, p-type impurity ions are implanted through the contact holes 13 to form p-type impurity ions at the bottom of the contact holes 13. + A layer 10 is formed.

[0045] Next, as shown in FIG. 3F, a metal film is formed on the main surface of the semiconductor substrate 2 so as to fill the contact hole 13, and the contact 14 and the surface electrode 15 are formed by photolithography and dry etching.

[0046] Then, the n-buffer layer 17, the p-layer 18, and the n + The layer 19 and the back electrode 20 are formed, completing the structure of the reverse conducting IGBT (RC-IGBT) 1 shown in FIG.

[0047] As described above, the reverse conducting IGBT (RC-IGBT) 1 of this embodiment is a semiconductor device having the IGBT section 3 and the diode section 4 in the same chip. The IGBT section 3 has a first conductivity type first semiconductor layer (n - layer 16) and the first semiconductor layer (n - A plurality of trenches 5 are formed in the first semiconductor layer (n- a second conductivity type body layer (p body layer 9) formed on the body layer (p body layer 9) and a first conductivity type source layer (n + layer 11), and the diode section 4 has a first semiconductor layer (n - layer 16) and the first semiconductor layer (n - The semiconductor device is configured to have a first portion having a plurality of trenches 5 formed in the first semiconductor layer (n-layer 16), a body layer (p-body layer 9) sandwiched between the plurality of trenches 5 and formed on the first semiconductor layer (n-layer 16), and a second portion having a Schottky barrier junction formed by the first semiconductor layer (n-layer 16) and contacts 14 in the first semiconductor layer.

[0048] Furthermore, the interval (W2) between the trenches 5 in the second portion is configured to be narrower than the interval (W1) between the trenches 5 in the first portion.

[0049] Moreover, the first portions and the second portions are arranged alternately.

[0050] This makes it possible to more effectively suppress hole injection into the diode section and improve recovery characteristics in a reverse conducting IGBT (RC-IGBT) that incorporates an IGBT and diode on the same chip. [Example]

[0051] Second Embodiment A semiconductor device according to a second embodiment of the present invention will be described with reference to FIG.

[0052] FIG. 4 is a diagram showing a schematic cross-sectional structure of a reverse conducting IGBT (RC-IGBT) of this embodiment, which corresponds to a modification of the first embodiment (FIG. 1).

[0053] In the reverse conducting IGBT (RC-IGBT) 1 of Example 1 (FIG. 1), in the diode section 4, portions having a p body layer 9 between trenches 5 and portions having a Schottky barrier junction (SBD) between trenches 5 are alternately arranged, whereas in this example, as shown in FIG. 4, the portions having a p body layer 9 between trenches 5 are arranged more frequently than the portions having a Schottky barrier junction (SBD) between trenches 5 so that the ratio of the portions having a Schottky barrier junction (SBD) between trenches 5 to the portions having a p body layer 9 between trenches 5 is 1:2 or more, which is different from Example 1 (FIG. 1). The other configurations are the same as those of Example 1 (FIG. 1).

[0054] The ratio between the portion having the p-body layer 9 between the trenches 5 and the portion having the Schottky barrier junction (SBD) between the trenches 5 may be changed depending on the desired characteristics of the reverse conducting IGBT (RC-IGBT) 1.

[0055] The present invention is not limited to the above-described embodiments and includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations. [Explanation of symbols]

[0056] 1…Reverse conduction IGBT (RC-IGBT) 2...Semiconductor substrate (silicon substrate) 3…IGBT section 4...Diode section 5...Trench 6...Insulating film (silicon oxide film) 7...Gate electrode (polysilicon electrode) 8...Emitter electrode (polysilicon electrode) 9...p body layer 10...p+ layer 11...n + layer 12...Interlayer insulating film 13...Contact hole 14...Contact 15…Surface electrode 16...n - layer 17...n buffer layer 18...p layer 19...n + layer 20...Back electrode.

Claims

1. A semiconductor device having an IGBT and a diode on the same chip, The IGBT includes a first semiconductor layer of a first conductivity type; a plurality of first trenches formed in the first semiconductor layer; a body layer of a second conductivity type sandwiched between the plurality of first trenches and formed on the first semiconductor layer; a first conductivity type source layer sandwiched between the plurality of first trenches and formed on the body layer, The diode includes the first semiconductor layer and a plurality of second trenches formed in the first semiconductor layer; a first portion sandwiched between the plurality of second trenches and including the body layer formed on the first semiconductor layer; a second portion sandwiched between the plurality of second trenches and having a Schottky barrier junction between the first semiconductor layer and a contact in the first semiconductor layer.

2. 2. The semiconductor device according to claim 1, The semiconductor device according to claim 1, wherein the spacing between the second trenches in the second portion is narrower than the spacing between the second trenches in the first portion.

3. 2. The semiconductor device according to claim 1, The semiconductor device is characterized in that the first portions and the second portions are arranged alternately.

4. 2. The semiconductor device according to claim 1, A semiconductor device, characterized in that the first portions are arranged in greater numbers than the second portions so that the ratio of the arrangement of the first portions to the arrangement of the second portions is 1:2 or more.

5. (a) forming a plurality of first trenches in a first region of a major surface of a semiconductor substrate and a plurality of second trenches in a second region; (b) forming an insulating film and an electrode film in this order in each of the first trench and the second trench, and forming a gate electrode in the first trench and an electrode in the second trench by photolithography and dry etching; (c) selectively forming a mask between some of the second trenches on the second region; (d) forming a p-body layer on the main surface of the semiconductor substrate excluding the first trench and the second trench by ion implantation of p-type impurities; (e) forming an interlayer insulating film on the main surface of the semiconductor substrate, and forming, by photolithography and dry etching, contact holes that penetrate the interlayer insulating film and expose the p-body layer and the semiconductor substrate between the first trench and the second trench; (f) forming a metal film on the main surface of the semiconductor substrate so as to fill the contact hole, and forming a contact by photolithography and dry etching; and a Schottky barrier junction formed between the semiconductor substrate and the contact between the second trenches;

6. 6. The method for manufacturing a semiconductor device according to claim 5, a first region formed on the first insulating film and a second region formed on the second insulating film;

7. 6. The method for manufacturing a semiconductor device according to claim 5, (c) a distance between the second trenches in a portion where the mask is formed is narrower than a distance between the second trenches in a portion where the mask is not formed.

8. 6. The method for manufacturing a semiconductor device according to claim 5, (c) a step of forming a mask on a semiconductor device by alternating the areas where the mask is not formed and the areas where the mask is formed.

9. 6. The method for manufacturing a semiconductor device according to claim 5, (c) a width of a portion of the second region where the mask is not formed is wider than a width of a portion of the second region where the mask is formed.

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