Electronic module and electronic apparatus

Abstract

To provide a technique which is advantageous for increasing a transmission speed of a signal.SOLUTION: An electronic module comprises a first wiring board, a first semiconductor device which is mounted on the first wiring board, a second wiring board which overlaps the first wiring board in a first direction, a second semiconductor device which is mounted on the second wiring board, and a wiring member which connects the first wiring board and the second wiring board. The wiring member includes a first wiring terminal and a second wiring terminal. The first semiconductor device includes a first signal terminal and a second signal terminal. The first signal terminal is electrically connected to the second semiconductor device via the first wiring terminal. The second signal terminal is electrically connected to the second semiconductor device via the second wiring terminal. The first wiring terminal and the second wiring terminal overlap the first semiconductor device in the first direction. The first wiring terminal and the second wiring terminal are disposed between a virtual first plane and a virtual second plane.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to electronic modules and electronic devices. [Background technology]

[0002] Electronic devices such as digital cameras, smartphones, and mobile PCs are equipped with electronic modules that contain multiple semiconductor devices. Electronic modules are typically designed to have a three-dimensional mounting structure in which two wiring boards are stacked, thereby reducing the mounting area.

[0003] For example, Patent Document 1 discloses a structure in which multiple memory modules are mounted in a module socket. Each of the multiple memory modules has a module substrate and multiple memories mounted on the module substrate. The multiple memories are arranged at the four corners of the module substrate, and the central part of the module substrate without any memory is connected to the module socket.

[0004] Patent Document 2 discloses a semiconductor module including two wiring boards, a frame body disposed between the two wiring boards, and a semiconductor device disposed in a hollow portion formed by the two wiring boards and the frame body. That is, the frame body is disposed so as to surround the outer periphery of the semiconductor device disposed in the hollow portion.

[0005] Patent Document 3 discloses an electronic module including two wiring boards, a plurality of intermediate connection members disposed between the two wiring boards, and semiconductor elements mounted on each of the wiring boards. Patent Document 4 discloses an electronic device including a substrate and a first electronic component, a connection support portion disposed between the substrate and the first electronic component, the connection support portion electrically connecting the substrate and the first electronic component and supporting the first electronic component on the substrate, and a second electronic component mounted on the substrate. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-8695 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-287820 [Patent Document 3] Patent Publication No. 2022-19542 [Patent Document 4] International Publication No. 2013 / 153717 Summary of the Invention [Problem to be solved by the invention]

[0007] In recent years, the operating speed of semiconductor devices has improved significantly. However, if the transmission characteristics of signals transmitted through signal wiring are low, it is not possible to increase the signal transmission speed. Therefore, it is necessary to limit the operating speed of the semiconductor device to match the achievable signal transmission speed. Therefore, in order to effectively utilize the performance of semiconductor devices, it is necessary to improve the transmission characteristics of signals transmitted through signal wiring.

[0008] The present disclosure provides a technique that is advantageous for increasing the signal transmission speed. [Means for solving the problem]

[0009] A first aspect of the present disclosure includes a first wiring board, a first semiconductor device mounted on the first wiring board, a second wiring board overlapping the first wiring board in a first direction perpendicular to a main surface of the first wiring board, a second semiconductor device mounted on the second wiring board, and a wiring member disposed between the first wiring board and the second wiring board and connecting the first wiring board and the second wiring board, the wiring member having a plurality of wiring terminals, the first semiconductor device having a plurality of signal terminals electrically connected to the second semiconductor device via the plurality of wiring terminals of the wiring member, and a first signal terminal of the plurality of signal terminals of the first semiconductor device being a first signal terminal of the wiring member. an electronic module, characterized in that the first semiconductor device is electrically connected to the second semiconductor device via a first wiring terminal among the plurality of wiring terminals, and a second signal terminal among the plurality of signal terminals of the first semiconductor device is electrically connected to the second semiconductor device via a second wiring terminal among the plurality of wiring terminals of the wiring member, and in the first direction, the first wiring terminal and the second wiring terminal overlap the first semiconductor device, and the first wiring terminal and the second wiring terminal are arranged between an imaginary first plane that is perpendicular to the main surface and intersects with the first signal terminal, and an imaginary second plane that is parallel to the first plane and intersects with the second signal terminal.

[0010] A second aspect of the present disclosure provides a semiconductor device including a first wiring board, a first semiconductor device mounted on the first wiring board, a second wiring board overlapping the first wiring board in a first direction perpendicular to a main surface of the first wiring board, a second semiconductor device mounted on the second wiring board, and a wiring member disposed between the first wiring board and the second wiring board and connecting the first wiring board and the second wiring board, the wiring member having a plurality of wiring terminals, the first semiconductor device having a plurality of signal terminals electrically connected to the second semiconductor device via the plurality of wiring terminals of the wiring member, a first signal terminal of the plurality of signal terminals is electrically connected to the second semiconductor device via a first wiring terminal of the plurality of wiring terminals of the wiring member, and a second signal terminal of the plurality of signal terminals of the first semiconductor device is electrically connected to the second semiconductor device via a second wiring terminal of the plurality of wiring terminals of the wiring member, and in the first direction, the first wiring terminal and the second wiring terminal overlap the first semiconductor device, and in the first direction, the first signal terminal and the second signal terminal do not overlap the wiring member.

[0011] A third aspect of the present disclosure is an electronic module comprising: a first wiring board; a first semiconductor device mounted on the first wiring board; a second wiring board overlapping the first wiring board in a first direction perpendicular to a main surface of the first wiring board; a second semiconductor device mounted on the second wiring board; a third semiconductor device mounted on the first wiring board; and a wiring member arranged between the first wiring board and the second wiring board and connecting the first wiring board and the second wiring board, wherein the wiring member has a first portion located between the first semiconductor device and the second wiring board in the first direction and a second portion located between the third semiconductor device and the second wiring board in the first direction, and the first semiconductor device is electrically connected to the second semiconductor device via the first portion, and the third semiconductor device is electrically connected to the second semiconductor device via the second portion. [Effects of the Invention]

[0012] According to the present disclosure, a technique that is advantageous for increasing the signal transmission speed is provided. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a schematic cross-sectional view of a camera, which is an image capturing device, as an example of an electronic device according to a first embodiment. [Figure 2] FIG. 2 is an explanatory diagram of an image processing module according to the first embodiment. [Figure 3] 1A is a plan view showing the layout relationship of a memory, a wiring board, and wiring members of an image processing module according to the first embodiment, and FIG. 1B is a plan view showing the layout relationship of an image processing engine, a memory, a wiring board, and wiring members according to the first embodiment. [Figure 4] 3A and 3B are plan views showing the arrangement of memories and wiring members according to the first embodiment. [Figure 5] 3A and 3B are explanatory diagrams showing the positional relationship between a memory, a wiring board, and a wiring member according to the first embodiment. [Figure 6] 1A is an explanatory diagram of the distance between two terminals according to the first embodiment, and FIG. 1B is an explanatory diagram of the wiring length between two terminals according to the first embodiment. [Figure 7] 10 is a graph showing signal transmission characteristics in the signal wiring of the first embodiment, comparative example 1, and comparative example 2. [Figure 8] 10 is a plan view showing the arrangement relationship of an image processing engine, a memory, a wiring board, and wiring members of an image processing module according to a second embodiment. FIG. [Figure 9] 10A is a plan view showing the arrangement relationship of a memory, a wiring board, and a wiring member of an image processing module according to a second embodiment, and FIG. 10B is an explanatory diagram showing the positional relationship of a memory, a wiring board, and a wiring member of an image processing module according to the second embodiment. [Figure 10] FIG. 11 is an explanatory diagram of an image processing module, which is an example of an electronic module according to a third embodiment. [Figure 11] FIG. 10 is an explanatory diagram of an image processing module which is an example of an electronic module according to a fourth embodiment. [Figure 12]10A is a plan view showing the layout relationship of a memory, a wiring board, and wiring members of an image processing module according to a fourth embodiment, and FIG. 10B is a plan view showing the layout relationship of an image processing engine, a memory, a wiring board, and wiring members according to the fourth embodiment. [Figure 13] 10(a) and 10(b) are plan views showing the arrangement relationship of a memory and a wiring member according to a fourth embodiment. [Figure 14] FIG. 11 is an explanatory diagram of an image processing module, which is an example of an electronic module according to a fifth embodiment. [Figure 15] 10(a) and 10(b) are explanatory diagrams of an image processing module of Comparative Example 1. FIG. [Figure 16] 10(a) and 10(b) are explanatory diagrams of an image processing module of Comparative Example 2. FIG. [Figure 17] 1A is an explanatory view of the wiring member according to the first embodiment, and FIG. 1B is an explanatory view of the wiring member according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0014] Exemplary embodiments of the present disclosure will be described in detail below with reference to the drawings. In each drawing, the same components are designated by the same reference numerals, and duplicated descriptions will be omitted. In the following embodiments, directions are indicated by an XYZ coordinate system, which is a Cartesian coordinate system. The X-axis, Y-axis, and Z-axis are mutually orthogonal. The positive direction of the Z-axis is, for example, the optical axis direction.

[0015] [First embodiment] FIG. 1 is a schematic cross-sectional view of a camera 600, which is an imaging device as an example of an electronic device according to the first embodiment. The camera 600 is a digital camera with interchangeable lenses, and a lens unit (lens barrel) 602 including a lens is detachably attached to the camera 600. The camera 600 includes an exterior casing 611, and an image processing module 100 and a sensor module 900, which are arranged inside the exterior casing 611. The image processing module 100 and the sensor module 900 are each electronic modules including a printed circuit board. The image processing module 100 and the sensor module 900 are electrically connected by a flexible printed wiring board 400. A battery (not shown) is provided inside the exterior casing 611.

[0016] The sensor module 900 includes an image sensor 901 and a printed wiring board 902. The image sensor 901 is mounted on the printed wiring board 902. The image sensor 901 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor or a CCD (Charge Coupled Device) image sensor. The image sensor 901 has a function of converting light incident via the lens unit 602 into an electrical signal.

[0017] The image processing module 100 includes an image processing engine 22, a memory 21, a power supply circuit 15, and a plurality of capacitors 14. The image processing engine 22 is, for example, a digital signal processor, and is an image processing device that acquires an electrical signal from an image sensor 901, performs processing to correct the acquired electrical signal, and generates image data. The memory 21 is, for example, a storage device such as a DRAM such as DDR (Double Data Rate) 5 or a flash memory. The image processing engine 22 also functions as a memory controller that controls the memory 21. The image processing engine 22 can save image data in the memory 21 and read image data saved in the memory 21.

[0018] The image processing engine 22 and the memory 21 are each composed of a semiconductor device. The memory 21 is an example of a first semiconductor device, and the image processing engine 22 is an example of a second semiconductor device. Each of the image processing engine 22 and the memory 21 is a semiconductor package including a semiconductor integrated circuit, and may be, for example, a BGA (Ball Grid Array) or an LGA (Land Grid Array). Note that the semiconductor package is preferably one of these types, but is not limited to these types. For example, any type of semiconductor package can be used, such as a QFP (Quad Flat Package), a QFN (Quad Flat Non-leaded Package), a QFJ (Quad Flat J-leaded Package), or a CSP (Chip Size Package).

[0019] The power supply circuit 15 is configured to supply power to each of the image processing engine 22 and the memory 21 from a battery (not shown) via power supply lines including a power line and a ground line of the image processing module 100 .

[0020] Fig. 2 is an explanatory diagram of the image processing module 100 according to the first embodiment. Fig. 2 schematically shows a cross section of the image processing module 100 along the XZ plane.

[0021] The image processing engine 22 has a plurality of terminals 220 arranged in a matrix at intervals along the XY plane. The plurality of terminals 220 of the image processing engine 22 include a plurality of signal terminals 221 and a plurality of power supply terminals 222 which are power supply terminals or ground terminals.

[0022] The memory 21 has a plurality of terminals 210 arranged in a matrix at intervals along the XY plane. The plurality of terminals 210 of the memory 21 include a plurality of signal terminals 211 and a plurality of power supply terminals 212 which are power supply terminals or ground terminals.

[0023] Each capacitor 14 is a bypass capacitor for stabilizing the power supply voltage supplied to the image processing engine 22, and is provided between the power supply terminal and ground terminal of the image processing engine 22.

[0024] Image processing module 100 includes wiring board 11, which is a memory board (sub-board), and wiring board 12, which is a main board. Wiring board 11 is an example of a first wiring board, and wiring board 12 is an example of a second wiring board. Each of wiring boards 11 and 12 is a rigid printed wiring board. Memory 21 is mounted on wiring board 11, and image processing module 100 and capacitor 14 are mounted on wiring board 12. Note that power supply circuit 15 shown in FIG. 1 may be mounted on wiring board 12.

[0025] Wiring board 11 has main surface 111, which is a mounting surface, and main surface 112, which is also a mounting surface. Main surface 112 is the main surface opposite main surface 111. Main surface 111 is an example of a first main surface, and main surface 112 is an example of a second main surface.

[0026] Wiring board 12 has main surface 121, which is a mounting surface, and main surface 122, which is also a mounting surface. Main surface 122 is the main surface opposite to main surface 121. Main surface 121 is an example of a third main surface, and main surface 122 is an example of a fourth main surface.

[0027] In the first embodiment, the direction perpendicular to main surface 111 is the Z direction. The Z direction includes the positive direction of the Z axis and the negative direction of the Z axis. Wiring board 11 and wiring board 12 are arranged at a distance from each other in the Z direction. In the Z direction, main surface 112 of wiring board 11 faces main surface 121 of wiring board 12. The Z direction is an example of a first direction. The X direction and the Y direction are directions perpendicular to the Z direction. The Y direction is a direction perpendicular to the X direction. The X direction is an example of a second direction, and the Y direction is an example of a third direction.

[0028] Here, main surfaces 111, 112, 121, and 122 are substantially parallel to one another. Therefore, the direction perpendicular to main surface 111 of wiring board 11 is substantially the same as the direction perpendicular to main surface 112 of wiring board 11, the direction perpendicular to main surface 121 of wiring board 12, and the direction perpendicular to main surface 122 of wiring board 12. The Z direction is also the direction in which image processing module 100 is viewed from above. Furthermore, viewing in the Z direction, i.e., viewing from above, also means viewing from a perspective in the Z direction. Furthermore, the expression "in the Z direction" can include "viewed in the Z direction."

[0029] In the Z direction, wiring board 11 overlaps wiring board 12. In other words, wiring board 12 overlaps wiring board 11 in the Z direction.

[0030] In the first embodiment, the size of wiring board 11 is smaller than the size of wiring board 12 in the Z direction. At least a portion of wiring board 11 overlaps a portion of wiring board 12 in the Z direction. In the first embodiment, the entirety of wiring board 11 overlaps a portion of wiring board 12 in the Z direction. In other words, a portion of wiring board 12 overlaps the entirety of wiring board 11 in the Z direction.

[0031] Memory 21 is mounted on main surface 111 of wiring board 11. Image processing engine 22 is mounted on main surface 121 of wiring board 12. Multiple capacitors 14 are mounted on main surface 122 of wiring board 12. Each capacitor 14 is preferably disposed near image processing engine 22. In the first embodiment, each capacitor 14 overlaps image processing engine 22 in the Z direction. Note that the multiple capacitors 14 may include a capacitor 14 that does not overlap image processing engine 22 in the Z direction. Also, some of the multiple capacitors 14 overlap wiring board 11 in the Z direction. Also, some of the multiple capacitors 14 overlap memory 21 in the Z direction.

[0032] In the first embodiment, memory 21 is surface-mounted on main surface 111 of wiring board 11. Image processing engine 22 is surface-mounted on main surface 121 of wiring board 12. Capacitor 14 is a chip component, and is surface-mounted on main surface 122 of wiring board 12.

[0033] Image processing module 100 includes wiring member 31 that is disposed between wiring board 11 and wiring board 12 and electrically and mechanically connects wiring board 11 to wiring board 12. Specifically, wiring member 31 is disposed between main surface 112 of wiring board 11 and main surface 121 of wiring board 12 and electrically and mechanically connects main surface 112 of wiring board 11 to main surface 121 of wiring board 12.

[0034] FIG. 17(a) is an explanatory diagram of a wiring member 31 according to a first embodiment. FIG. 17(a) schematically illustrates a cross section of the wiring member 31, and also illustrates the wiring board 11 and the wiring board 12 that are soldered to the wiring member 31. The wiring member 31 has a bonding surface 315, which is a first bonding surface (mounting surface), and a bonding surface 316, which is a second bonding surface (mounting surface) opposite the bonding surface 315. The bonding surface 315 of the wiring member 31 is electrically and mechanically connected to the main surface 112 of the wiring board 11 by a plurality of bonding members, and the bonding surface 316 of the wiring member 31 is electrically and mechanically connected to the main surface 121 of the wiring board 12 by a plurality of bonding members. Each bonding member is, for example, solder. The wiring member 31 also functions as a spacer between the wiring board 11 and the wiring board 12. In the first embodiment, the wiring member 31 is formed of a rigid wiring board. The wiring member 31 is an example of a first wiring member.

[0035] 2, the distance H1 in the Z direction between the main surface 112 of the wiring board 11 and the main surface 121 of the wiring board 12 is larger than the height H2 in the Z direction of the image processing engine 22. The wiring member 31 and the image processing engine 22 are disposed adjacent to each other in the X direction. That is, the image processing engine 22 overlaps the wiring board 11 in the Z direction. The height H3 in the Z direction of the capacitor 14 is smaller than the height H2 in the Z direction of the image processing engine 22.

[0036] The multiple terminals 210 of the memory 21 include multiple signal terminals 211. In FIG. 2, one of the multiple signal terminals 211 is labeled with a reference symbol. The multiple terminals 220 of the image processing engine 22 include multiple signal terminals 221. In FIG. 2, one of the multiple signal terminals 221 is labeled with a reference symbol. The multiple signal terminals 211 are electrically connected to the multiple signal terminals 221 by multiple signal wirings S, respectively. FIG. 2 illustrates one of the multiple signal wirings S. The signal wiring S illustrated in FIG. 2 has the longest wiring length among the multiple signal wirings S. The multiple signal wirings S can be used for data transmission between the image processing engine 22 and the memory 21. That is, a digital signal is transmitted to each of the multiple signal wirings S.

[0037] Each signal wiring S is arranged across wiring board 11, wiring member 31, and wiring board 12. That is, each signal wiring S includes a conductor included in wiring board 11, a conductor included in wiring member 31, and a conductor included in wiring board 12. That is, the wiring path of each signal wiring S from memory 21 to image processing engine 22 passes through wiring member 31.

[0038] Fig. 3(a) is a plan view showing the arrangement relationship of the memory 21, wiring board 11, and wiring member 31 of the image processing module 100 according to the first embodiment. Fig. 3(b) is a plan view showing the arrangement relationship of the image processing engine 22, memory 21, wiring board 11, and wiring member 31 according to the first embodiment. Figs. 4(a) and 4(b) are plan views showing the arrangement relationship of the memory 21 and wiring member 31 according to the first embodiment. Note that Fig. 4(b) shows a bonding surface 315 of the wiring member 31.

[0039] 3(a), wiring board 11 and memory 21 are rectangular in the Z direction (as viewed in the Z direction), and the size of wiring board 11 is equal to or greater than the size of memory 21. As viewed in the Z direction, memory 21 may be square, but in the first embodiment, it is rectangular. As viewed in the Z direction, the four corners of memory 21 may be sharp, rounded, or curved.

[0040] In the first embodiment, the longitudinal direction of the memory 21 is the X direction, and the lateral direction of the memory 21 is the Y direction. Alternatively, the longitudinal direction of the memory 21 may be the Y direction, and the lateral direction of the memory 21 may be the X direction.

[0041] In the Z direction, wiring member 31 overlaps with center C1 of memory 21. Center C1 is the point where two diagonal lines of memory 21 intersect when viewed in the Z direction. As shown in FIG. 3(a), wiring member 31 has a quadrangular shape when viewed in the Z direction, and the size of wiring member 31 is smaller than the size of wiring board 11. In addition, in the Z direction, wiring member 31 entirely overlaps with a portion of wiring board 11.

[0042] The memory 21 has a rectangular outer shape when viewed in the Z direction, and therefore has four sides 215, 216, 217, and 218. Of the four sides 215 to 218, the two opposite sides 215 and 217 are long sides, and the two opposite sides 216 and 218 are short sides. That is, each of the sides 215 and 217 is the longest side included in the memory 21. Each of the sides 215 and 217 extends in the X direction, and each of the sides 216 and 218 extends in the Y direction. That is, the sides 215 and 217 are parallel to each other, and the sides 216 and 218 are parallel to each other. The sides 216 and 218 are perpendicular to the sides 215 and 217.

[0043] The wiring member 31 is formed in a rectangular parallelepiped or flat plate shape. As shown in FIGS. 4(b) and 17(a), the wiring member 31 has a plurality of terminals 310 arranged on a bonding surface 315 and a plurality of terminals 319 arranged on a bonding surface 316. The wiring member 31 has an insulating substrate 301. The insulating substrate 301 is a rigid insulating substrate having a rectangular parallelepiped or flat plate shape. A plurality of through holes penetrating the insulating substrate 301 in the Z direction are defined in the insulating substrate 301, and a via conductor is disposed in each of the plurality of through holes, connecting a corresponding terminal 310 of the plurality of terminals 310 to a corresponding terminal 319 of the plurality of terminals 319. Each of the plurality of via conductors is disposed in the through hole so as to extend from a first end face to a second end face of the insulating substrate 301 in the Z direction.

[0044] As shown in FIG. 4(b), the wiring member 31 has a quadrangular shape in the Z direction (as viewed in the Z direction). As viewed in the Z direction, the wiring member 31 may have a square shape, but in the first embodiment, it has a rectangular shape. As viewed in the Z direction, the four corners of the wiring member 31 may be sharp, rounded, or curved. In the first embodiment, the longitudinal direction of the wiring member 31 is the Y direction, and the lateral direction of the wiring member 31 is the X direction.

[0045] In Fig. 3(b), a plurality of terminals 220 of the image processing engine 22 are schematically illustrated by solid lines. In Fig. 4(a), a plurality of terminals 210 of the memory 21 are schematically illustrated by solid lines. In Fig. 4(b), a plurality of terminals 310 of the wiring member 31 are schematically illustrated by solid lines.

[0046] As shown in FIG. 4(a), the multiple terminals 210 of the memory 21 are arranged in a matrix at intervals in a direction along the XY plane. The multiple terminals 210 include multiple signal terminals 211 and multiple power supply terminals 212, which are power supply terminals or ground terminals. The signal terminals 211 are terminals for inputting or outputting signals. The power supply terminals 212 are terminals to which a voltage (potential difference between the power supply potential and the ground potential) required for operation of the memory 21 is applied. In FIG. 4(a), white circles represent signal terminals 211, and gray circles represent power supply terminals 212.

[0047] As shown in FIG. 4(b), the multiple terminals 310 of the wiring member 31 are arranged in a matrix with gaps between them in the direction along the XY plane. Although not shown, the multiple terminals 319 are also arranged in a matrix with gaps between them in the direction along the XY plane. The multiple terminals 310 include multiple wiring terminals 311 and multiple wiring terminals 312. Each wiring terminal 311 is used as part of the signal wiring S. Each wiring terminal 312 is used as part of the power supply wiring or ground wiring for supplying power to the memory 21. In FIG. 4(b), the white circles represent the wiring terminals 311, and the gray circles represent the wiring terminals 312.

[0048] 17(a), the plurality of terminals 319 includes a plurality of wiring terminals 313. Each wiring terminal 319 is used as a part of the signal wiring S.

[0049] 3(b), the multiple terminals 220 of the image processing engine 22 are arranged in a matrix at intervals in a direction along the XY plane. The multiple terminals 220 include multiple signal terminals 221 and multiple power supply terminals 222 which are power supply terminals or ground terminals. The signal terminals 221 are terminals for inputting or outputting signals. The power supply terminals 222 are terminals to which a voltage (potential difference between the power supply potential and the ground potential) required for operation of the image processing engine 22 is applied.

[0050] As shown in FIG. 3(b), the size of the image processing engine 22 is equal to or larger than the size of the memory 21 when viewed in the Z direction.

[0051] 3(b), the multiple terminals 220 of the image processing engine 22 are equally divided into two areas A1 and A2. For example, when viewed in the Z direction, a virtual plane V0 is defined that passes through the center points of two opposite sides of the rectangular image processing engine 22 extending in the X direction and is perpendicular to the two sides. The plane V0 is, for example, a YZ plane. That is, the plane is perpendicular to the main surface 111 of the wiring board 11. The area closer to the wiring member 31 with respect to the plane V0 is defined as area A1, and the area farther from the wiring member 31 with respect to the plane V0 is defined as area A2. Area A1 includes a terminal group 225 consisting of four or more terminals 220 out of the multiple terminals 220. Area A2 includes a terminal group 226 consisting of four or more terminals 220 out of the multiple terminals 220.

[0052] The terminal group 225 includes two or more signal terminals 221 and two or more power supply terminals 222. The terminal group 226 includes two or more signal terminals 221 and two or more power supply terminals 222. Each signal terminal 211 of the memory 21 is electrically connected to a corresponding one of the signal terminals 221 included in the terminal group 225 by a signal wiring S.

[0053] In this way, the plurality of signal terminals 211 of the memory 21 are electrically connected to the image processing engine 22 via the plurality of wiring terminals 311 of the wiring member 31, respectively.

[0054] Solder is used to join memory 21 and wiring board 11. Solder is also used to join image processing engine 22 and wiring board 12. Solder is also used to join wiring member 31 and wiring board 11, and to join wiring member 31 and wiring board 12.

[0055] Each of the plurality of terminals 210 of the memory 21 includes a pad (or a land). Each of the plurality of terminals 220 of the image processing engine 22 includes a pad (or a land). Each of the plurality of terminals 310 on the bonding surface 315 of the wiring member 31 includes a pad (or a land). Each of the plurality of terminals 319 on the bonding surface 316 of the wiring member 31 includes a pad (or a land).

[0056] A plurality of terminals 210 included in memory 21 and a plurality of pads included in main surface 111 of wiring board 11 are each joined by solder. A plurality of terminals 220 included in image processing engine 22 and a plurality of pads included in main surface 121 of wiring board 12 are each joined by solder.

[0057] Furthermore, a plurality of pads included on main surface 112 of wiring board 11 and a plurality of terminals 310 of wiring member 31 are respectively joined by solder. Further, a plurality of pads included on main surface 121 of wiring board 12 and a plurality of terminals 319 of wiring member 31 are respectively joined by solder.

[0058] Furthermore, two electrodes of each of the plurality of capacitors 14 and two pads included on main surface 122 of wiring board 12 are respectively joined by solder.

[0059] 17(a), wiring member 31 has a plurality of wiring terminals 311 included in bonding surface 315, a plurality of wiring terminals 313 included in bonding surface 316, and a plurality of wires 314 connecting the plurality of wiring terminals 311 and the plurality of wiring terminals 313, respectively. The plurality of wiring terminals 311 form a first wiring terminal group, the plurality of wiring terminals 313 form a second wiring terminal group, and the plurality of wires 314 form a wiring group. Each of the plurality of wires 314 is connected to wiring board 11 via a corresponding one of the plurality of wiring terminals 311. Furthermore, each of the plurality of wires 314 is connected to wiring board 12 via a corresponding one of the plurality of wiring terminals 313.

[0060] Here, the "plurality of wiring terminals" in the claims may be either the plurality of wiring terminals 311 of the first wiring terminal group or the plurality of wiring terminals 313 of the second wiring terminal group. In the first embodiment, the "plurality of wiring terminals" refers to the plurality of wiring terminals 311.

[0061] For ease of manufacturing wiring member 31, wiring 314 is preferably a conductor disposed in a through hole as described above, but is not limited to the above configuration. Fig. 17(b) is an explanatory diagram of a modified wiring member 31. Fig. 17(b) schematically illustrates a cross section of wiring member 31 of the modified example. Also, wiring board 11 and wiring board 12 joined to wiring member 31 by solder are schematically illustrated. The modified wiring member 31 will be described below.

[0062] Each wiring 314 of the wiring group may have one or more via conductors and conductor patterns included in one or more inner wiring layers, as shown in Fig. 17(b). Each wiring 314 may have a complex connection structure, as shown in Fig. 17(b).

[0063] Here, an image processing module of a comparative example will be described. FIGS. 15(a) and 15(b) are explanatory diagrams of an image processing module 100X of a comparative example 1. FIG. 15(a) shows a schematic plan view of the image processing module 100X of the comparative example 1, and FIG. 15(b) shows a schematic cross-sectional view of the image processing module 100X of the comparative example 1. In FIGS. 15(a) and 15(b), an image processing engine 22 and a memory 21 are mounted flat on a single wiring board 12X. Note that a plurality of capacitors 14 are mounted on the main surface of the wiring board 12X opposite to the main surface on which the image processing engine 22 is mounted.

[0064] The memory 21 has a plurality of signal terminals 211. The terminal group 225 of the image processing engine 22 has a plurality of signal terminals 221. The wiring board 12X has a plurality of signal wirings SX. The plurality of signal terminals 221 of the terminal group 225 are each connected to a plurality of signal terminals 211 by a plurality of signal wirings SX. Note that, although the signal wirings SX are wired in a straight line in FIG. 15(a), they may be wired in a serpentine manner to bypass pads, vias, etc. FIG. 15(b) illustrates one of the plurality of signal wirings SX. The signal wiring SX shown in FIG. 15(b) has the longest wiring length among the plurality of signal wirings SX.

[0065] 15(b), the wiring length L' of the signal wiring SX is the sum of the wiring length A' on the image processing engine 22 side and the wiring length B' on the memory 21 side. Note that the wiring length B' on the memory 21 side is longer than the length of the side 215, which is the long side of the memory 21. For example, the wiring length B' is approximately the length of the diagonal of the memory 21.

[0066] 16(a) and 16(b) are explanatory diagrams of an image processing module 100Y of Comparative Example 2. FIG. 16(a) shows a schematic cross-sectional view of the image processing module 100Y of Comparative Example 2, and FIG. 16(b) shows a schematic plan view of the image processing module 100Y of Comparative Example 2. The image processing module 100Y of Comparative Example 2 has a stacked structure. Because the image processing module 100Y of Comparative Example 2 has a stacked structure, it is smaller than the image processing module 100X of Comparative Example 1.

[0067] The memory 21 is mounted on a wiring board 11Y, and the image processing engine 22 is mounted on a wiring board 12Y. The wiring board 11Y and the wiring board 12Y are connected by two wiring members 31Y. The two wiring members 31Y are arranged on both sides of the image processing engine 22 in the X direction with a gap between them. In other words, when viewed in the Z direction, the image processing engine 22 is located between the two wiring members 31Y. When viewed in the Z direction, the memory 21 is also located between the two wiring members 31Y.

[0068] In Comparative Example 2, multiple signal wirings SY are arranged across wiring board 11Y, one wiring member 31Y, and wiring board 12X. Multiple signal terminals 221 in terminal group 225 are each connected to multiple signal terminals 211 by multiple signal wirings SY. Figure 16(a) shows one of the multiple signal wirings SY. The signal wiring SY shown in Figure 16(a) has the longest wiring length among the multiple signal wirings SY.

[0069] The wiring length L" of the signal wiring SY shown in FIG. 16(a) is the sum of the wiring length A" on the image processing engine 22 side, the wiring length B" on the memory 21 side, and the wiring length C" in the height direction of the wiring member 31Y. Note that the wiring length B" on the memory 21 side is longer than the length of the side 215, which is the long side of the memory 21. The wiring length A" on the image processing engine 22 side shown in FIG. 16(a) is approximately the same as the wiring length A' on the image processing engine 22 side shown in FIG. 15(b). The wiring length B" on the memory 21 side is approximately the same as the wiring length B' on the memory 21 side shown in FIG. 15(b) or is longer than the wiring length B' by the width of the wiring member 31Y in the X direction.

[0070] Therefore, the wiring length L" of the signal wiring SY shown in FIG. 16(a) includes the wiring length C" and is therefore longer than the wiring length L' of the signal wiring SX shown in FIG. 15(b). Because the wiring length L" of the signal wiring SY is longer, the digital signal transmitted through the signal wiring SY deteriorates. In other words, the image processing module 100X of Comparative Example 2 is smaller than the image processing module 100Y of Comparative Example 1, but has inferior signal transmission characteristics to the image processing module 100Y of Comparative Example 1.

[0071] On the other hand, as shown in Figure 2, in the first embodiment, the wiring length L of the signal wiring S is the sum of the wiring length A on the image processing engine 22 side, the wiring length B on the memory 21 side, and the wiring length C in the height direction of the wiring member 31.

[0072] When comparing the wiring length L with the wiring length L" shown in Figure 16(a), the wiring length A on the image processing engine 22 side is approximately the same as the wiring length A" on the image processing engine 22 side. Furthermore, the wiring length C of the wiring member 31 is approximately the same as the wiring length C" of the wiring member 31Y. On the other hand, the wiring length B on the memory 21 side is shorter than the wiring length B" on the memory 21 side, and is approximately half of the wiring length B". Therefore, the wiring length L of the signal wiring S is shorter than the wiring length L" of the signal wiring SY in Comparative Example 2, which improves the wiring characteristics and enables faster signal transmission.

[0073] When comparing the wiring length L with the wiring length L' shown in FIG. 15(b), the wiring length A on the image processing engine 22 side is approximately the same as the wiring length A' on the image processing engine 22 side. On the other hand, the sum of the wiring lengths B and C can be made shorter than the wiring length B' on the memory 21 side. In this case, the wiring length L of the signal wiring S is shorter than the wiring length L' of the signal wiring SX of Comparative Example 1, improving the wiring characteristics and enabling faster signal transmission. Furthermore, when viewed in the Z direction, the occupation area of the image processing module 100 is smaller than the occupation area of the image processing module 100X of Comparative Example 1.

[0074] 5(a) and 5(b) are explanatory diagrams of the positional relationship between memory 21, wiring board 11, and wiring member 31 according to the first embodiment. Fig. 5(a) shows a plan view of memory 21, wiring board 11, and wiring member 31. Fig. 5(b) shows a cross-sectional view of wiring board 11 and wiring member 31.

[0075] In the Z direction, wiring member 31 is disposed at a position overlapping center C1 of memory 21. Also, a virtual plane V10 is defined that intersects with the center of side 215 and the center of side 217, which are the long sides of memory 21. Plane V10 is a plane that is perpendicular to main surface 111 of wiring board 11.

[0076] Of the multiple signal terminals 211 of the memory 21, one of the signal terminals 211 located on the side of the side 218 with respect to the plane V10 is referred to as the signal terminal 2111. Of the signal terminals 211 located on the side of the side 218 with respect to the plane V10, the signal terminal 2111 is the terminal farthest from the plane V10. The signal terminal 2111 is an example of a first signal terminal.

[0077] Of the multiple signal terminals 211 of the memory 21, one of the signal terminals 211 located on the side of the side 216 with respect to the plane V10 is designated as the signal terminal 2112. Of the signal terminals 211 located on the side of the side 216 with respect to the plane V10, the signal terminal 2112 is the terminal farthest from the plane V10. The signal terminal 2112 is an example of a second signal terminal.

[0078] That is, of the plurality of signal terminals 211, the two signal terminals that are separated by the greatest distance in the X direction, which is the direction in which the sides 215 and 217 extend, are defined as the signal terminals 2111 and 2112.

[0079] Of the multiple signal wirings S, the signal wiring connected to the signal terminal 2111 is referred to as the signal wiring S1. The signal wiring S1 is an example of a first signal wiring. The signal wiring S1 includes a corresponding wiring terminal 3111 of the multiple wiring terminals 311 of the wiring member 31. The wiring terminal 3111 is an example of a first wiring terminal.

[0080] Of the multiple signal wirings S, the signal wiring connected to the signal terminal 2112 is referred to as the signal wiring S2. The signal wiring S2 is an example of a second signal wiring. The signal wiring S2 includes a corresponding wiring terminal 3112 among the multiple wiring terminals 311 of the wiring member 31. The wiring terminal 3112 is an example of a second wiring terminal.

[0081] As described above, the signal terminal 2111 of the memory 21 is electrically connected to the image processing engine 22 via the wiring terminal 3111 of the wiring member 31. In addition, the signal terminal 2112 of the memory 21 is electrically connected to the image processing engine 22 via the wiring terminal 3112 of the wiring member 31.

[0082] 5(a) and 5(b), in the first embodiment, the wiring terminals 3111 and 3112 overlap the memory 21 in the Z direction. Furthermore, the signal terminals 2111 and 2112 do not overlap the wiring member 31 in the Z direction.

[0083] 5(a), the wiring terminals 3111 and 3112 are disposed between a virtual plane V1 and a virtual plane V2. The virtual plane V1 is an example of a virtual first plane. The virtual plane V2 is an example of a virtual second plane.

[0084] In the first embodiment, the wiring member 31 is disposed between the planes V1 and V2, away from the planes V1 and V2. That is, the entire wiring member 31 is disposed between the planes V1 and V2. The plane V1 is a plane perpendicular to the main surface 111 and intersects with the signal terminal 2111. The plane V2 is a plane perpendicular to the main surface 111 and intersects with the signal terminal 2112. When viewed in the Z direction, the plane V1 intersects with the center of the signal terminal 2111, and the plane V2 intersects with the center of the signal terminal 2112. The planes V1 and V2 are parallel to each other. The planes V1 and V2 do not coincide with each other. The planes V1 and V2 do not intersect with the wiring member 31. In the first embodiment, the planes V10, V1, and V2 are parallel to each other and do not coincide with each other. In the first embodiment, the planes V0, V10, V1, and V2 are parallel to each other and do not coincide with each other.

[0085] Furthermore, the distance D1 between the wiring terminals 3111 and 3112 is narrower than the distance D2 between the signal terminals 2111 and 2112. In other words, the distance D2 is wider than the distance D1. Note that the distance D1 is also the linear distance between the wiring terminals 3111 and 3112 when viewed in the Z direction. The distance D2 is also the linear distance between the signal terminals 2111 and 2112 when viewed in the Z direction.

[0086] Plane V1 and plane V2 may be defined in any way as long as they are parallel to each other, but typically, they are preferably planes perpendicular to the line segment connecting signal terminal 2111 and signal terminal 2112. In this case, distance D2 is the distance in the direction perpendicular to planes V1 and V2. Distance D1 is preferably the distance in the direction perpendicular to planes V1 and V2.

[0087] On the other hand, in Comparative Example 2, as shown in FIG. 16(b), the entire wiring member 31Y does not overlap the memory 21 in the Z direction. Of the multiple signal wirings SY, the signal wiring connected to the signal terminal 2111 of the memory 21 is referred to as signal wiring S1Y. The signal wiring S1Y includes a wiring terminal 3111Y of the wiring member 31Y. Furthermore, of the multiple signal wirings SY, the signal wiring connected to the signal terminal 2112 is referred to as signal wiring S2Y. The signal wiring S2Y includes a wiring terminal 3112Y of the wiring member 31Y. The distance between the wiring terminal 3111Y and the wiring terminal 3112Y is approximately the same as the distance D1.

[0088] Among the multiple signal terminals 211, the signal terminal 2111 is the terminal farthest from the wiring member 31Y. Among the multiple signal terminals 211, the signal terminal 2112 is the terminal closest to the wiring member 31Y. Note that in FIG. 16(b), the wiring path of the signal wiring S1Y included in the wiring board 11Y is illustrated as a straight line, but the wiring path of the signal wiring S1Y included in the wiring board 11Y may be meandering to bypass pads, vias, etc. Similarly, the wiring path of the signal wiring S2Y included in the wiring board 11Y is illustrated as a straight line, but the wiring path of the signal wiring S2Y included in the wiring board 11Y may be meandering to bypass pads, vias, etc.

[0089] In this way, the wiring member 31Y (i.e., the wiring terminals 3111Y, 3112Y) is not present between the planes V1 and V2, but is arranged outside the region between the planes V1 and V2. Therefore, the length of the wiring path of the signal wiring S1Y of the comparative example 2 included in the wiring board 11Y is longer than the length in the X direction which is the longitudinal direction of the memory 21, i.e., the length L1 of the side 215 (217) which is the long side.

[0090] In contrast, in the first embodiment, the length of the wiring path of the signal wiring S1 included in the wiring board 11 can be approximately half the length L1 in the longitudinal direction of the memory 21. Furthermore, the length of the wiring path of the signal wiring S2 included in the wiring board 11 can be approximately half the length L1 in the longitudinal direction of the memory 21. Therefore, the wiring path of each of the multiple signal wirings S can be shortened.

[0091] 5(a), the wiring path of signal wiring S1 included in wiring board 11 is shown as a straight line, but the wiring path of signal wiring S1 included in wiring board 11 may be meandering to bypass pads, vias, etc. Also, in FIG. 5(a), the wiring path of signal wiring S2 included in wiring board 11 is shown as a straight line, but the wiring path of signal wiring S2 included in wiring board 11 may be meandering to bypass pads, vias, etc.

[0092] FIG. 6(a) is an explanatory diagram of the distance between two terminals 211, 311 according to the first embodiment. The signal terminals 211 of the memory 21 and the wiring terminals 311 of the wiring member 31 each have a plurality of pairs of two terminals 211, 311 electrically connected to each other by a signal wiring S. At least one of the plurality of pairs has the maximum distance D0 between the two terminals 211, 311. FIG. 6(a) illustrates one pair of the plurality of pairs that has the maximum distance D0. The maximum distance D0 is the linear distance between the two terminals 211, 311 when viewed in the Z direction. In other words, the maximum distance D0 is the linear distance between the two terminals 211, 311 in a direction along the XY plane.

[0093] The maximum distance D0 is shorter than the maximum length L1 among the lengths of the sides 215 to 218 of the scale 21. That is, the side 215 (217), which is the long side, has the longest length among the multiple sides 215 to 218. The maximum distance D0 is also shorter than the length L1 of the side 215 (217).

[0094] FIG. 6(b) is an explanatory diagram of the wiring lengths of two terminals 211 and 311 according to the first embodiment. The plurality of signal terminals 211 of the memory 21 and the plurality of wiring terminals 311 of the wiring member 31 have a plurality of pairs of two terminals 211 and 311 that are electrically connected to each other by a signal wiring S. At least one of the plurality of pairs has the maximum wiring length L0 between the two terminals 211 and 311. In FIG. 6(b), one pair having the maximum wiring length L0 among the plurality of pairs is illustrated. The maximum wiring length L0 is the length of the path between the two terminals 211 and 311 when viewed in the Z direction. That is, in the maximum wiring length L0, the length of the via is omitted.

[0095] The maximum wiring length L0 is shorter than the maximum length L1 among the lengths of the sides 215 to 218 of the memory 21. That is, the long side, side 215 (217), has the maximum length among the plurality of sides 215 to 218. And the maximum wiring length L0 is shorter than the length L1 of side 215 (217).

[0096] Also, in order to reduce the difference in wiring length between the wiring length between the signal terminal 2111 and the wiring terminal 3111 and the wiring length between the signal terminal 2112 and the wiring terminal 3112 shown in FIG. 5(a), the difference Dd between the distance D5 between the signal terminal 2111 and the wiring terminal 3111 and the distance D6 between the signal terminal 2112 and the wiring terminal 3112 is preferably as small as possible.

[0097] The distance D5 is the straight-line distance between the signal terminal 2111 and the wiring terminal 3111 when viewed in the Z direction, and the distance D6 is the straight-line distance between the signal terminal 2112 and the wiring terminal 3112 when viewed in the Z direction. And the difference Dd is preferably smaller than the distance D2 between the signal terminal 2111 and the signal terminal 2112, and more preferably smaller than the distance D1 between the wiring terminal 3111 and the wiring terminal 3112. That is, it is preferable that Dd = |D5 - D6| < D2, and it is more preferable that Dd = |D5 - D6| < D1.

[0098] Also, the distances D5 and D6 may be greater than the distance D1, but in order to reduce the signal delay, it is preferably as small as possible. That is, the distances D5 and D6 are preferably smaller than the distance D2. That is, it is preferable that D5, D6 > D1, and it is also preferable that D5, D6 < D2.

[0099] Also, even when the distance D5 is the maximum distance D0 described above, it is preferable that Dd = |D5 - D6| < D2, and it is more preferable that Dd = |D5 - D6| < D1. Also, it is preferable that Dd = |D5 - D6| < D2, and it is more preferable that Dd = |D5 - D6| < D1.

[0100] Also, even when the distance D6 is the maximum distance D0 described above or the distance between the second longest terminals, it is preferable that Dd = |D5 - D6| < D2, and it is more preferable that Dd = |D5 - D6| < D1. Also, it is preferable that Dd = |D5 - D6| < D2, and it is more preferable that Dd = |D5 - D6| < D1.

[0101] Note that although the distances D0, D5, and D6 have been described as the straight-line distances when viewed in the Z direction, they may be distances considering the thickness of the wiring board 11.

[0102] Here, an example of the size of each member of the image processing module 100 will be described. The length of one side of the image processing engine 22 is about 15 to 20 mm. The length of one side of the memory 21 is about 10 to 20 mm. The length of the wiring member 31 in the longitudinal direction (Y direction) is about the same as the length of one side of the image processing engine 22, which is about 15 to 20 mm. The length of the wiring member 31 in the short side direction (X direction) is about 3 to 5 mm. The height of the wiring member 31 in the Z direction is about 0.5 to 5.0 mm. The maximum wiring length of the signal wiring SX in Comparative Example 1 is about 25 mm. The maximum wiring length of the signal wiring SY in Comparative Example 2 is about 30 mm. The maximum wiring length of the signal wiring S in the first embodiment is about 20 mm when the height of the wiring member 31 is about 2 mm, for example.

[0103] Fig. 7 is a graph showing the signal transmission characteristics in the signal wiring of each of the first embodiment, comparative example 1, and comparative example 2. The vertical axis of the graph shown in Fig. 7 represents the signal transmission characteristics in the signal wiring in dB. The closer the dB value is to 0, the better the signal transmission characteristics are. The horizontal axis represents frequency, and 0 to 10 GHz is shown.

[0104] 7, reference numeral 51 denotes the signal transmission characteristics of the signal wiring S of the first embodiment, reference numeral 52 denotes the signal transmission characteristics of the signal wiring SX of the comparative example 1, and reference numeral 53 denotes the signal transmission characteristics of the signal wiring SY of the comparative example 2. Fig. 7 shows the results of an experiment in which the wiring length of the signal wiring SY of the comparative example 2 was approximately 30 mm, the wiring length of the signal wiring SX of the comparative example 1 was approximately 25 mm, and the wiring length of the signal wiring S of the first embodiment was approximately 20 mm. When a transmission characteristic of -2 dB or more at 1 multiplication is required for high-speed signal transmission, the image processing engine 22 operates at an operating speed of less than 4 GHz in the comparative example 2 and less than 5 GHz in the comparative example 1, but an operating speed of up to approximately 8 GHz is possible in the first embodiment.

[0105] According to the first embodiment, the transmission characteristics of the signal transmitted through the signal wiring S are improved, thereby increasing the transmission speed of the signal through the signal wiring S. In this way, according to the first embodiment, a technique advantageous for increasing the transmission speed of the signal is provided.

[0106] 2 and 3(a), in the first embodiment, the image processing engine 22 overlaps with the wiring board 11 in the Z direction. Specifically, a portion of the image processing engine 22 overlaps with the wiring board 11 in the Z direction. That is, at least a portion of the image processing engine 22 is disposed in the space between the wiring board 11 and the wiring board 12. As a result, the image processing engine 22 is closer to the wiring member 31, which further reduces the size of the image processing module 100 and shortens the wiring length of the signal wiring S. This further improves the signal transmission characteristics and enables the signal transmission speed to be increased.

[0107] 3(b), in the first embodiment, the multiple terminals 220 of the image processing engine 22 have a signal terminal 221 that overlaps the wiring board 11 in the Z direction. That is, the multiple signal terminals 221 of the image processing engine 22 include at least one signal terminal 221 that overlaps the wiring board 11. The signal terminal 221 that overlaps the wiring board 11 is electrically connected to one of the multiple signal terminals 211 of the memory 21 shown in FIG. 4(a) by a signal wiring S. In the first embodiment, the signal terminal 221 included in the terminal group 225 is electrically connected to one of the multiple signal terminals 211 of the memory 21 by the signal wiring S. In the image processing module 100, the wiring length of the signal wiring S is shortened, and the signal transmission speed can be increased.

[0108] In the X direction, it is preferable that at least one of the signal terminals 221 included in the image processing engine 22, or in the first embodiment, at least one of the signal terminals 221 included in the terminal group 225, overlaps the memory 21. This allows the signal wiring S to be further shortened.

[0109] In addition, it is preferable that at least one of the plurality of capacitors 14 overlaps with wiring board 11 in the X direction. Furthermore, it is more preferable that at least one of the plurality of capacitors 14 overlaps with memory 21 in the X direction.

[0110] [Second embodiment] A second embodiment of the present disclosure will be described. Below, elements with the same reference symbols as those in the first embodiment will have substantially the same configurations and functions as those described in the first embodiment unless otherwise specified, and differences from the first embodiment will be mainly described.

[0111] Fig. 8 is a plan view showing the positional relationship between the image processing engine 22, memory 21, wiring board 11, and wiring member 31 of the image processing module 100A according to the second embodiment. Fig. 9(a) is a plan view showing the positional relationship between the memory 21, wiring board 11, and wiring member 31 of the image processing module 100A according to the second embodiment. Fig. 9(b) is an explanatory diagram showing the positional relationship between the memory 21, wiring board 11, and wiring member 31 of the image processing module 100A according to the second embodiment.

[0112] In the second embodiment, the image processing module 100 in the camera 600 shown in FIG. 1 is replaced with an image processing module 100A. In the second embodiment, the image processing module 100A includes two memories 21 mounted on a wiring board 11. One of the two memories 21 is an example of a first semiconductor device, and the other of the two memories 21 is an example of a third semiconductor device. That is, the image processing module 100A of the second embodiment differs from the image processing module 100 of the first embodiment in that it includes two memories 21. The configuration of the other components and the relative positions of the components are as described in the first embodiment.

[0113] The two memories 21 are electrically connected to the image processing engine 22 via a wiring member 31. The two memories 21 are mounted on the main surface 111 of the wiring board 11 at an interval in the Y direction, which is the short-side direction of each memory 21. The wiring member 31 overlaps the two memories 21 in the Z direction. In the second embodiment, the wiring member 31 overlaps the centers C1 of the two memories 21. In the Z direction, the wiring board 11 and each of the two memories 21 overlap one of the signal terminals 221 of the image processing engine 22. The relationship between the imaginary planes V1, V2, and V10 and the terminals 2111, 2112, 3111, and 3112 shown in FIG. 9(b) is also as described in the first embodiment.

[0114] In the second embodiment, the wiring member 31 has a first portion 351 located between one of the two memories 21 and the wiring board 12 in the Z direction, and a second portion 352 located between the other of the two memories 21 and the wiring board 12 in the Z direction. One of the two memories 21 is electrically connected to the image processing engine 22 via the first portion 351, and the other of the two memories 21 is electrically connected to the image processing engine 22 via the second portion 352.

[0115] The side surface of the insulating substrate of the wiring member 31 surrounds a group of wires connecting one of the two memories 21 to the image processing engine 22 and a group of wires connecting the other of the two memories 21 to the image processing engine 22. In other words, the group of wires connecting the two memories 21 to the image processing engine 22 is provided on the wiring member 31 supported by a common insulating substrate.

[0116] The two memories 21 may have the same configuration (type) or different configurations (types). For example, the two memories 21 may have different configurations (types), such as one having a storage capacity of 1 GB and the other having a storage capacity of 2 GB.

[0117] The second embodiment provides the same effects as the first embodiment. That is, the second embodiment provides a technique that is advantageous for increasing the signal transmission speed, similar to the first embodiment.

[0118] [Third embodiment] A third embodiment of the present disclosure will be described. Hereinafter, elements with the same reference symbols as those in the first or second embodiment will have substantially the same configurations and functions as those described in the first or second embodiment unless otherwise specified, and differences from the first and second embodiments will be mainly described.

[0119] Fig. 10 is an explanatory diagram of an image processing module 100B which is an example of an electronic module according to the third embodiment. Fig. 10 schematically shows a cross section of the image processing module 100B along the XZ plane.

[0120] 1, an image processing module 100 is replaced with an image processing module 100B. The image processing module 100B of the third embodiment differs from the image processing module 100 of the first embodiment in the arrangement of the image processing engine 22 and capacitors 14. That is, in the third embodiment, the image processing engine 22 is mounted on the main surface 122 of the wiring board 12, and the plurality of capacitors 14 are mounted on the main surface 121.

[0121] In the Z direction, the plurality of capacitors 14 overlaps the image processing engine 22. In the Z direction, at least a portion of the image processing engine 22 and at least one of the plurality of capacitors 14 overlap the wiring board 11. In other words, at least one of the plurality of capacitors 14 is disposed in a space (area) sandwiched between the wiring boards 11 and 12.

[0122] Height H3 in the Z direction of capacitor 14 is smaller than height H2 in the Z direction of image processing engine 22. Therefore, in the third embodiment, distance H1' in the Z direction between main surface 112 of wiring board 11 and main surface 121 of wiring board 12 (i.e., the height in the Z direction of wiring member 31) can be made smaller than distance H1 shown in Fig. 2. As a result, according to the third embodiment, the same effects as those of the first embodiment can be achieved, and image processing module 100B can be made smaller than image processing module 100 of the first embodiment.

[0123] In the third embodiment, in the Z direction, at least a portion of the image processing engine 22 and at least one of the plurality of capacitors 14 overlap the memory 21. This allows the image processing module 100B to be further miniaturized.

[0124] In the third embodiment, as in the first embodiment, the image processing module 100B is described as including one memory 21 mounted on the wiring board 11, but the present invention is not limited to this. For example, as in the second embodiment, the image processing module 100B may be provided with a plurality of (for example, two) memories 21 mounted on the wiring board 11.

[0125] [Fourth embodiment] A fourth embodiment of the present disclosure will be described. Hereinafter, elements with the same reference symbols as those in the first, second, or third embodiment will have substantially the same configurations and functions as those described in the first, second, or third embodiment unless otherwise specified, and differences from the first, second, and third embodiments will be mainly described.

[0126] Fig. 11 is an explanatory diagram of an image processing module 100C which is an example of an electronic module according to the fourth embodiment, and Fig. 11 schematically shows a cross section of the image processing module 100C along the XZ plane.

[0127] 1, an image processing module 100 is replaced with an image processing module 100C. In addition to the configuration of image processing module 100 of the first embodiment, image processing module 100C of the fourth embodiment includes wiring board 13, which is an example of a third wiring board, memory 23, which is an example of a fourth semiconductor device, and wiring member 32, which is an example of a second wiring member.

[0128] The side surface of the insulating substrate of the wiring member 31 surrounds the multiple wires of the wiring member 31, and the side surface of the insulating substrate of the wiring member 32 surrounds the multiple wires of the wiring member 32, and the wiring members 31 and 32 are provided separately.

[0129] The memory 23 is a storage device such as a DRAM such as DDR5 or a flash memory. The image processing engine 22 also functions as a memory controller that controls the memory 23. The image processing engine 22 can save image data in the memory 23 and read image data saved in the memory 23.

[0130] The memories 23 are each composed of a semiconductor device. The memories 23 are semiconductor packages including semiconductor integrated circuits, and may be, for example, BGA or LGA. The semiconductor package is preferably one of these types, but is not limited to these types. For example, any type of semiconductor package can be used, such as QFP, QFN, QFJ, or CSP. The memories 23 are preferably of the same type (configuration) as the memories 21, but may be of a different type (configuration) from the memories 21.

[0131] The memory 23 has a plurality of terminals 230 arranged in a matrix at intervals along the XY plane. The plurality of terminals 230 of the memory 23 include a plurality of signal terminals 231 and a plurality of power supply terminals 232 which are power supply terminals or ground terminals.

[0132] Wiring board 13 is a memory board (sub-board). Wiring board 13 is a rigid printed wiring board. Memory 23 is mounted on wiring board 13.

[0133] Wiring board 13 has main surface 131, which is a mounting surface, and main surface 132, which is also a mounting surface. Main surface 132 is the main surface opposite to main surface 131. Main surface 131 is an example of a fifth main surface, and main surface 132 is an example of a sixth main surface.

[0134] Wiring board 13 and wiring board 12 are disposed at an interval in the Z direction. In the Z direction, main surface 132 of wiring board 13 faces main surface 121 of wiring board 12.

[0135] Here, main surfaces 111, 112, 121, 122, 131, and 132 are substantially parallel to one another. Therefore, the direction perpendicular to main surface 111 of wiring board 11 is substantially the same as the direction perpendicular to main surface 131 of wiring board 13 and the direction perpendicular to main surface 132 of wiring board 13.

[0136] In the Z direction (as viewed in the Z direction), wiring board 13 overlaps wiring board 12. In other words, wiring board 12 overlaps wiring board 13 in the Z direction.

[0137] In the fourth embodiment, the size of wiring board 13 is smaller than the size of wiring board 12 in the Z direction. At least a portion of wiring board 13 overlaps a portion of wiring board 12 in the Z direction. In the fourth embodiment, the entirety of wiring board 13 overlaps a portion of wiring board 12 in the Z direction. In other words, a portion of wiring board 12 overlaps the entirety of wiring board 13 in the Z direction.

[0138] Memory 23 is mounted on main surface 131 of wiring board 13. Image processing engine 22 is mounted on main surface 121 of wiring board 12. Multiple capacitors 14 are mounted on main surface 122 of wiring board 12. Each capacitor 14 is preferably disposed near image processing engine 22. In the fourth embodiment, each capacitor 14 overlaps image processing engine 22 in the Z direction. Note that the multiple capacitors 14 may include a capacitor 14 that does not overlap image processing engine 22 in the Z direction. Also, some of the multiple capacitors 14 overlap wiring board 13 in the Z direction. Also, some of the multiple capacitors 14 overlap memory 23 in the Z direction.

[0139] In the fourth embodiment, memory 23 is surface-mounted on main surface 131 of wiring board 13. Image processing engine 22 is surface-mounted on main surface 121 of wiring board 12. Capacitor 14 is a chip component, and is surface-mounted on main surface 122 of wiring board 12.

[0140] Wiring member 32 is disposed between wiring board 13 and wiring board 12, and electrically and mechanically connects wiring board 13 and wiring board 12. Specifically, wiring member 32 is disposed between main surface 132 of wiring board 13 and main surface 121 of wiring board 12, and electrically and mechanically connects main surface 132 of wiring board 13 and main surface 121 of wiring board 12.

[0141] Wiring member 32 has bonding surface 325, which is a third bonding surface, and bonding surface 326, which is a fourth bonding surface (mounting surface) opposite bonding surface 325. Bonding surface 325 of wiring member 32 is electrically and mechanically connected to main surface 132 of wiring board 13 by a plurality of bonding members, and bonding surface 326 of wiring member 32 is electrically and mechanically connected to main surface 121 of wiring board 12 by a plurality of bonding members. Each bonding member is, for example, solder. Wiring member 32 also functions as a spacer between wiring board 13 and wiring board 12. In the fourth embodiment, wiring member 32 is formed of a rigid wiring board.

[0142] A distance H4 in the Z direction between the main surface 132 of the wiring board 13 and the main surface 121 of the wiring board 12 is larger than a height H2 in the Z direction of the image processing engine 22. The wiring member 32 and the image processing engine 22 are disposed adjacent to each other in the X direction. That is, in the X direction, the wiring member 32 is disposed on the opposite side of the image processing engine 22 from the side of the wiring member 31. In the Z direction, the image processing engine 22 overlaps the wiring board 13. A height H3 in the Z direction of the capacitor 14 is smaller than a height H2 in the Z direction of the image processing engine 22.

[0143] The multiple terminals 230 of the memory 23 include multiple signal terminals 231. In FIG. 11, one of the multiple signal terminals 231 is assigned a reference symbol. The multiple signal terminals 231 of the memory 23 are electrically connected to the multiple signal terminals 221 of the image processing engine 22 via multiple signal wirings S'. FIG. 11 illustrates one of the multiple signal wirings S'. The signal wiring S' illustrated in FIG. 11 has the longest wiring length among the multiple signal wirings S'. The multiple signal wirings S' can be used for data transmission between the image processing engine 22 and the memory 23. That is, a digital signal is transmitted to each of the multiple signal wirings S'.

[0144] Each signal wiring S' is arranged across wiring board 13, wiring member 32, and wiring board 12. That is, each signal wiring S' includes a conductor included in wiring board 13, a conductor included in wiring member 32, and a conductor included in wiring board 12. That is, the wiring path of each signal wiring S' from memory 23 to image processing engine 22 passes through wiring member 32.

[0145] Fig. 12(a) is a plan view showing the arrangement relationship of the memory 23, wiring board 13, and wiring member 32 of the image processing module 100C according to the fourth embodiment. Fig. 12(b) is a plan view showing the arrangement relationship of the image processing engine 22, memories 21 and 23, wiring boards 11 and 13, and wiring members 31 and 32 according to the fourth embodiment. Figs. 13(a) and 13(b) are plan views showing the arrangement relationship of the memory 23 and wiring member 32 according to the fourth embodiment. Note that Fig. 13(b) shows the bonding surface 325 of the wiring member 32.

[0146] 12(a), wiring board 13 and memory 23 are rectangular in the Z direction (as viewed in the Z direction), and the size of wiring board 13 is equal to or larger than the size of memory 23. As viewed in the Z direction, memory 23 may be square, but in the fourth embodiment, it is rectangular. As viewed in the Z direction, the four corners of memory 23 may be sharp, rounded, or curved.

[0147] In the fourth embodiment, the longitudinal direction of the memory 23 is the X direction, and the lateral direction of the memory 23 is the Y direction. Alternatively, the longitudinal direction of the memory 23 may be the Y direction, and the lateral direction of the memory 23 may be the X direction.

[0148] In the Z direction, wiring member 32 overlaps center C2 of memory 23. Center C2 is the point where two diagonal lines of memory 23 intersect when viewed in the Z direction. Also, as shown in FIG. 12(a), wiring member 32 has a quadrangular shape when viewed in the Z direction, and the size of wiring member 32 is smaller than the size of wiring board 13. Then, in the Z direction, wiring member 32 entirely overlaps with a portion of wiring board 13.

[0149] The memory 23 has a rectangular outer shape when viewed in the Z direction, and therefore has four sides 235, 236, 237, and 238. Of the four sides 235 to 238, the two opposite sides 235 and 237 are long sides, and the two opposite sides 236 and 238 are short sides. That is, each of the sides 235 and 237 is the longest side included in the memory 23. Each of the sides 235 and 237 extends in the X direction, and each of the sides 236 and 238 extends in the Y direction. That is, the sides 235 and 237 are parallel to each other, and the sides 236 and 238 are parallel to each other. The sides 236 and 238 are perpendicular to the sides 235 and 237.

[0150] The wiring member 32 is formed in a rectangular parallelepiped or flat plate shape. As shown in FIG. 13(b), the wiring member 32 has a plurality of terminals 320 arranged on a bonding surface 325 and a plurality of terminals (not shown) arranged on a bonding surface 326. The wiring member 32 has an insulating substrate 302. The insulating substrate 302 is a rigid insulating substrate having a rectangular parallelepiped or flat plate shape. A plurality of through holes penetrating the insulating substrate 302 in the Z direction are defined in the insulating substrate 302. A via conductor serving as wiring is arranged in each of the through holes. Each of the plurality of via conductors is arranged in the through hole so as to extend from a third end face to a fourth end face in the Z direction of the insulating substrate 302. Each of the plurality of via conductors is electrically connected to a corresponding terminal 320 of the plurality of terminals 320 on the bonding surface 325 and a corresponding terminal of the plurality of terminals on the bonding surface 326.

[0151] 13(b), the wiring member 32 has a quadrangular shape in the Z direction (as viewed in the Z direction). As viewed in the Z direction, the wiring member 32 may have a square shape, but in the fourth embodiment, it has a rectangular shape. As viewed in the Z direction, the four corners of the wiring member 32 may be sharp, rounded, or curved. In the fourth embodiment, the longitudinal direction of the wiring member 32 is the Y direction, and the lateral direction of the wiring member 32 is the X direction.

[0152] In Fig. 12(b), a plurality of terminals 220 of the image processing engine 22 are schematically illustrated by solid lines. In Fig. 13(a), a plurality of terminals 230 of the memory 23 are schematically illustrated by solid lines. In Fig. 13(b), a plurality of terminals 320 of the wiring member 32 are schematically illustrated by solid lines.

[0153] As shown in FIG. 13(a), the multiple terminals 230 of the memory 23 are arranged in a matrix at intervals in a direction along the XY plane. The multiple terminals 230 include multiple signal terminals 231 and multiple power supply terminals 232 which are power supply terminals or ground terminals. The signal terminals 231 are terminals for inputting or outputting signals. The power supply terminals 232 are terminals to which a voltage (potential difference between the power supply potential and the ground potential) required for operation of the memory 23 is applied. In FIG. 13(a), white circles represent signal terminals 231, and gray circles represent power supply terminals 232.

[0154] As shown in FIG. 13(b), the multiple terminals 320 on the bonding surface 325 of the wiring member 32 are arranged in a matrix with gaps between them in the direction along the XY plane. Although not shown, the multiple terminals on the bonding surface 326 are also arranged in a matrix with gaps between them in the direction along the XY plane. The multiple terminals 320 include multiple wiring terminals 321 and multiple wiring terminals 322. Each wiring terminal 321 is used as part of the signal wiring S'. Each wiring terminal 322 is used as part of the power supply wiring or ground wiring for supplying power to the memory 23. In FIG. 13(b), the white circles represent the wiring terminals 321, and the gray circles represent the wiring terminals 322.

[0155] 12(b), when viewed in the Z direction, the size of the image processing engine 22 is equal to or larger than the size of the memory 23. Each signal terminal 211 (FIG. 11) of the memory 21 is electrically connected to a corresponding one of the signal terminals 221 included in the terminal group 225 by a signal wiring S. Furthermore, each signal terminal 231 of the memory 23 is electrically connected to a corresponding one of the signal terminals 221 included in the terminal group 226 by a signal wiring S'.

[0156] In this way, the plurality of signal terminals 231 of memory 23 are electrically connected to image processing engine 22 via the plurality of wiring terminals 321 of wiring member 32. Solder is used to join memory 23 and wiring board 13. Solder is also used to join wiring member 32 and wiring board 13, and to join wiring member 32 and wiring board 12.

[0157] Each of the plurality of terminals 230 of the memory 23 includes a pad (or a land). Each of the plurality of terminals 220 of the image processing engine 22 includes a pad (or a land). Each of the plurality of terminals 320 on the bonding surface 325 of the wiring member 32 includes a pad (or a land). Each of the plurality of terminals on the bonding surface 326 of the wiring member 32 includes a pad (land).

[0158] A plurality of terminals 230 included in memory 23 are joined by solder to a plurality of pads included on main surface 131 of wiring board 13. A plurality of pads included on main surface 132 of wiring board 13 are joined by solder to a plurality of terminals 230 included on bonding surface 325 of wiring member 32. A plurality of pads included on main surface 121 of wiring board 12 are joined by solder to a plurality of terminals included on bonding surface 326 of wiring member 32.

[0159] Furthermore, two electrodes of each of the plurality of capacitors 14 and two pads included on main surface 122 of wiring board 12 are respectively joined by solder.

[0160] In the Z direction, wiring member 32 is disposed at a position overlapping center C2 of memory 23. Also, a virtual plane V20 is defined that intersects with the center of side 235 and the center of side 237, which are the long sides of memory 23. Plane V20 is a plane that is perpendicular to main surface 131 of wiring board 13.

[0161] Of the multiple signal terminals 231 of the memory 23, one of the signal terminals 231 located on the side of the side 236 with respect to the plane V20 is referred to as the signal terminal 2311. Of the signal terminals 231 located on the side of the side 236 with respect to the plane V20, the signal terminal 2311 is the terminal farthest from the plane V20. The signal terminal 2311 is an example of a third signal terminal.

[0162] Of the multiple signal terminals 231 of the memory 23, one of the signal terminals 231 located on the side of the side 238 with respect to the plane V20 is designated as the signal terminal 2312. Of the signal terminals 231 located on the side of the side 238 with respect to the plane V20, the signal terminal 2312 is the terminal farthest from the plane V20. The signal terminal 2312 is an example of a fourth signal terminal.

[0163] That is, of the plurality of signal terminals 231, the two signal terminals that are separated by the greatest distance in the X direction, which is the direction in which the sides 235 and 237 extend, are defined as the signal terminals 2311 and 2312.

[0164] Of the multiple signal wirings S', the signal wiring connected to the signal terminal 2311 is referred to as signal wiring S3. The signal wiring S3 is an example of a third signal wiring. The signal wiring S3 includes a corresponding wiring terminal 3211 among the multiple wiring terminals 321 of the wiring member 32. The wiring terminal 3211 is an example of a third wiring terminal.

[0165] Of the multiple signal wirings S', the signal wiring connected to the signal terminal 2312 is referred to as signal wiring S4. The signal wiring S4 is an example of a fourth signal wiring. The signal wiring S4 includes a corresponding wiring terminal 3212 among the multiple wiring terminals 321 of the wiring member 32. The wiring terminal 3212 is an example of a fourth wiring terminal.

[0166] As described above, the signal terminal 2311 of the memory 23 is electrically connected to the image processing engine 22 via the wiring terminal 3211 of the wiring member 32. In addition, the signal terminal 2312 of the memory 23 is electrically connected to the image processing engine 22 via the wiring terminal 3212 of the wiring member 32.

[0167] 12(a), in the fourth embodiment, the wiring terminals 3211 and 3212 overlap the memory 23 in the Z direction. Furthermore, the signal terminals 2311 and 2312 do not overlap the wiring member 32 in the Z direction.

[0168] 12(a), the wiring terminals 3211 and 3212 are disposed between a virtual plane V3 and a virtual plane V4. The virtual plane V3 is an example of a virtual third plane. The virtual plane V4 is an example of a virtual fourth plane.

[0169] In the fourth embodiment, the wiring member 32 is disposed between the planes V3 and V4, away from the planes V3 and V4. That is, the entire wiring member 32 is disposed between the planes V3 and V4. The plane V3 is a plane perpendicular to the main surface 131 and intersects with the signal terminal 2311. The plane V4 is a plane perpendicular to the main surface 131 and intersects with the signal terminal 2312. When viewed in the Z direction, the plane V3 intersects with the center of the signal terminal 2311, and the plane V4 intersects with the center of the signal terminal 2312. The planes V3 and V4 are parallel to each other. The planes V3 and V4 do not coincide with each other. Furthermore, the planes V3 and V4 do not intersect with the wiring member 32. In the fourth embodiment, the planes V20, V3, and V4 are parallel to each other and do not coincide with each other. Furthermore, in the fourth embodiment, the planes V0, V20, V3, and V4 are parallel to each other and do not coincide with each other.

[0170] Furthermore, the distance D3 between the wiring terminals 3211 and 3212 is narrower than the distance D4 between the signal terminals 2311 and 2312. In other words, the distance D4 is wider than the distance D3. Note that the distance D3 is also the linear distance between the wiring terminals 3211 and 3212 when viewed in the Z direction. The distance D4 is also the linear distance between the signal terminals 2311 and 2312 when viewed in the Z direction.

[0171] Plane V3 and plane V4 may be defined in any way as long as they are parallel to each other, but typically, they are preferably planes perpendicular to the line segment connecting signal terminal 2311 and signal terminal 2312. In this case, distance D4 is the distance in a direction perpendicular to planes V3 and V4. Distance D3 is also preferably the distance in a direction perpendicular to planes V3 and V4.

[0172] In the fourth embodiment, the length of the wiring path of signal wiring S3 included in wiring board 13 may be approximately half the length L2 in the longitudinal direction of memory 23. Furthermore, the length of the wiring path of signal wiring S4 included in wiring board 13 may be approximately half the length L2 in the longitudinal direction of memory 23. Therefore, the wiring path of each of the multiple signal wirings S' can be shortened.

[0173] 12(a), the wiring path of signal wiring S3 included in wiring board 13 is shown as a straight line, but the wiring path of signal wiring S3 included in wiring board 13 may be meandering to bypass pads, vias, etc. Also, in FIG. 12(a), the wiring path of signal wiring S4 included in wiring board 13 is shown as a straight line, but the wiring path of signal wiring S4 included in wiring board 13 may be meandering to bypass pads, vias, etc.

[0174] The signal terminals 231 of the memory 23 and the wiring terminals 321 of the wiring member 32 each include a plurality of pairs of two terminals 231, 321 electrically connected to each other by a signal wiring S'. At least one of the plurality of pairs has a maximum distance D0' between the two terminals 231, 321. The maximum distance D0' is the linear distance between the two terminals 231, 321 when viewed in the Z direction. In other words, the maximum distance D0' is the linear distance between the two terminals 231, 321 in a direction along the XY plane.

[0175] The maximum distance D0' is shorter than the maximum length L2 among the lengths of the sides 235 to 238 of the memory 23. That is, the side 235 (237), which is the long side, has the longest length among the multiple sides 235 to 238. The maximum distance D0' is shorter than the length L2 of the side 235 (237). In the fourth embodiment, the memory 23 has the same configuration as the memory 21, and therefore the length L2 is the same as the length L1 shown in FIG. 5(a).

[0176] The plurality of signal terminals 231 of the memory 23 and the plurality of wiring terminals 321 of the wiring member 32 have a plurality of pairs of two terminals 231, 321 electrically connected to each other by a signal wiring S'. At least one of the plurality of pairs has the maximum wiring length between the two terminals 231, 321. The maximum wiring length is the length of the path between the two terminals 231, 321 when viewed in the Z direction. In other words, the length of the via is omitted from the wiring length.

[0177] The maximum wiring length is shorter than the maximum length L2 among the lengths of the sides 235 to 238 of the memory 23. That is, the side 235 (237), which is the long side, has the longest length among the multiple sides 235 to 238. The maximum wiring length is shorter than the length L2 of the side 235 (237).

[0178] In addition, in order to reduce the difference between the wiring length between the signal terminal 2311 and the wiring terminal 3211 shown in Figure 12(a) and the wiring length between the signal terminal 2312 and the wiring terminal 3212, it is preferable that the difference Dd' between the distance D5' between the signal terminal 2311 and the wiring terminal 3211 and the distance D6' between the signal terminal 2312 and the wiring terminal 3212 is as small as possible.

[0179] The distance D5' is the straight-line distance between the signal terminal 2311 and the wiring terminal 3211 when viewed in the Z direction, and the distance D6' is the straight-line distance between the signal terminal 2312 and the wiring terminal 3212 when viewed in the Z direction. And the difference Dd' is preferably smaller than the distance D4 between the signal terminal 2311 and the signal terminal 2312, and more preferably smaller than the distance D3 between the wiring terminal 3211 and the wiring terminal 3212. That is, it is preferable that Dd' = |D5' - D6'| < D4, and more preferably Dd' = |D5' - D6'| < D3.

[0180] Also, the distances D5', D6' may be larger than the distance D3, but in order to reduce the signal delay, it is preferably as small as possible. That is, the distances D5', D6' are preferably smaller than the distance D4. That is, it is preferable that D5', D6' > D3, and it is also preferable that D5', D6' < D4.

[0181] Also, even when the distance D5' is the maximum distance D0' described above, it is preferable that Dd' = |D5' - D6'| < D4, and more preferably Dd' = |D5' - D6'| < D3. Also, it is preferable that Dd' = |D5' - D6'| < D4, and more preferably Dd' = |D5' - D6'| < D3.

[0182] Also, even when the distance D6' is the maximum distance D0' described above or the distance between the second-longest terminals, it is preferable that Dd' = |D5' - D6'| < D4, and more preferably Dd' = |D5' - D6'| < D3. Also, it is preferable that Dd' = |D5' - D6'| < D4, and more preferably Dd' = |D5' - D6'| < D3.

[0183] Note that although the distances D0', D5', D6' have been described as straight-line distances when viewed in the Z direction, they may be distances considering the thickness of the wiring board 13.

[0184] According to the fourth embodiment, the signal wiring S' can be shortened, thereby improving the transmission characteristics of the signal transmitted through the signal wiring S'. This makes it possible to increase the transmission speed of the signal through the signal wiring S'. Thus, according to the fourth embodiment, a technique advantageous for increasing the signal transmission speed is provided.

[0185] Furthermore, in the fourth embodiment, the image processing engine 22 overlaps the wiring board 13 in the Z direction. Specifically, a portion of the image processing engine 22 overlaps the wiring board 13 in the Z direction. That is, at least a portion of the image processing engine 22 is disposed in the space between the wiring board 13 and the wiring board 12. As a result, the image processing engine 22 is closer to the wiring member 32, which further reduces the size of the image processing module 100C and shortens the wiring length of the signal wiring S'. This further improves the signal transmission characteristics and enables the signal transmission speed to be increased.

[0186] 12(b), in the fourth embodiment, the multiple terminals 220 of the image processing engine 22 have a signal terminal 221 that overlaps the wiring board 13 in the Z direction. That is, the multiple signal terminals 221 of the image processing engine 22 include at least one signal terminal 221 that overlaps the wiring board 13. The signal terminal 221 that overlaps the wiring board 13 is electrically connected to one of the multiple signal terminals 231 of the memory 23 shown in FIG. 13(a) by a signal wiring S'. In the fourth embodiment, the signal terminal 221 included in the terminal group 226 is electrically connected to one of the multiple signal terminals 231 of the memory 23 by the signal wiring S'. In the image processing module 100C, the wiring length of the signal wiring S' is shortened, and the signal transmission speed can be increased.

[0187] In the X direction, it is preferable that at least one of the signal terminals 221 included in the image processing engine 22, or in the fourth embodiment, at least one of the signal terminals 221 included in the terminal group 226, overlaps the memory 23. This allows the signal wiring S' to be further shortened.

[0188] In addition, it is preferable that at least one of the plurality of capacitors 14 overlaps with wiring board 13 in the X direction. Furthermore, it is more preferable that at least one of the plurality of capacitors 14 overlaps with memory 23 in the X direction.

[0189] In the fourth embodiment, the image processing module 100C includes one memory 23 mounted on the wiring board 13. However, the present invention is not limited to this. For example, similar to the second embodiment, the image processing module 100C may include two memories 23 mounted on the wiring board 13. In this case, one of the two memories 23 may be a fourth semiconductor device, and the other of the two memories 23 may be a fifth semiconductor device. The two memories 23 are electrically connected to the image processing engine 22 via the wiring member 32. The wiring relationship between the two memories 23 and the image processing engine 22 via the wiring member 32 is substantially the same as the connection relationship between the two memories 21 and the image processing engine 22 via the wiring member 31. The two memories 23 may have the same configuration (type) or different configurations (types). For example, the two memories 23 may have different configurations (types), such as one having a storage capacity of 1 GB and the other having a storage capacity of 2 GB.

[0190] Moreover, the wiring members 31 and 32 of the fourth embodiment can be modified in the same manner as the wiring member 31 of the modified example of the first embodiment.

[0191] [Fifth embodiment] A fifth embodiment of the present disclosure will be described. Below, elements with the same reference symbols as those in the first, second, third, or fourth embodiment will have substantially the same configurations and functions as those described in the first, second, third, or fourth embodiment unless otherwise specified, and differences from the first, second, third, and fourth embodiments will be mainly described.

[0192] Fig. 14 is an explanatory diagram of an image processing module 100D which is an example of an electronic module according to the fifth embodiment. Fig. 14 schematically shows a cross section of the image processing module 100D along the XZ plane.

[0193] In the fifth embodiment, an image processing module 100D is used instead of the image processing module 100 in the camera 600 shown in Fig. 1. The image processing module 100D of the fifth embodiment differs from the image processing module 100C of the fourth embodiment in the arrangement of the image processing engine 22 and the capacitors 14. That is, in the fifth embodiment, the image processing engine 22 is mounted on the main surface 122 of the wiring board 12, and the plurality of capacitors 14 are mounted on the main surface 121.

[0194] In the Z direction, the plurality of capacitors 14 overlaps the image processing engine 22. In the Z direction, at least a portion of the image processing engine 22 and at least one of the plurality of capacitors 14 overlap the wiring board 11. In other words, at least one of the plurality of capacitors 14 is disposed in a space (area) sandwiched between the wiring boards 11 and 12.

[0195] Furthermore, in the Z direction, at least a portion of the image processing engine 22 and at least one of the plurality of capacitors 14 overlap with the wiring board 13. In other words, at least one of the plurality of capacitors 14 is disposed in a space (area) sandwiched between the wiring boards 13 and 12.

[0196] Height H3 in the Z direction of capacitor 14 is smaller than height H2 in the Z direction of image processing engine 22. Therefore, in the fifth embodiment, distance H1' in the Z direction between main surface 112 of wiring board 11 and main surface 121 of wiring board 12 (i.e., the height in the Z direction of wiring member 31) can be made smaller than distance H1 shown in FIG. 2. Furthermore, in the fifth embodiment, distance H4' in the Z direction between main surface 132 of wiring board 13 and main surface 121 of wiring board 12 (i.e., the height in the Z direction of wiring member 32) can be made smaller than distance H4 shown in FIG. 11. As a result, according to the fifth embodiment, the same effects as those of the first and fourth embodiments can be achieved, and image processing module 100D can be made smaller than image processing module 100C of the fourth embodiment.

[0197] In the fifth embodiment, in the Z direction, at least a portion of the image processing engine 22 and at least one of the plurality of capacitors 14 overlap with the memory 21. Furthermore, in the Z direction, at least a portion of the image processing engine 22 and at least one of the plurality of capacitors 14 overlap with the memory 23. This allows the image processing module 100D to be further miniaturized.

[0198] In the fifth embodiment, as in the fourth embodiment, the image processing module 100D is described as including one memory 23 mounted on the wiring board 13, but the present invention is not limited to this. For example, as in the second embodiment, the image processing module 100D may be provided with two memories 23 mounted on the wiring board 13.

[0199] [Other variations] The present disclosure is not limited to the above-described embodiments, and many modifications of the embodiments are possible within the technical concept of the present disclosure. For example, at least two of the above-described embodiments and modifications may be combined. Furthermore, the effects described in the present embodiments are merely a list of the most preferable effects resulting from the embodiments of the present disclosure, and the effects of the embodiments of the present disclosure are not limited to those described in the present embodiments.

[0200] In the above-described embodiment, the first semiconductor device is a memory and the second semiconductor device is an image processing engine, but this is not a limitation. The configurations of the above-described embodiment are applicable to any electronic module in which signal transmission occurs between the first and second semiconductor devices via signal wiring. Furthermore, the third semiconductor device is a memory, but this is not a limitation. The configurations of the above-described embodiment are applicable to any electronic module in which signal transmission occurs between the third and second semiconductor devices via signal wiring. For example, the semiconductor device is not limited to an image processing module, but may also be an information processing module, a communication module, an imaging module, a control module, or a display module. The semiconductor device to be mounted may be an imaging device (image sensor), a display device (display), a storage device (memory), a communication device, a processing device (processor), a control device (controller), or a power supply device, and at least two of these may be appropriately combined and connected via wiring members.

[0201] The electronic devices to which the above-described embodiments can be applied may be information devices such as smartphones and personal computers, or communication devices such as modems and routers. Alternatively, the electronic devices may be office equipment such as printers and copiers, medical equipment such as X-ray machines and endoscopes, industrial equipment such as robots and semiconductor manufacturing equipment, or transportation equipment such as vehicles, airplanes, and ships. The electronic devices of the present embodiments allow semiconductor devices to be densely mounted in a limited space within the exterior, which is useful for miniaturizing the electronic devices and improving their performance.

[0202] The disclosure of this specification includes not only what is explicitly described in this specification, but also all matters that can be understood from this specification and the drawings attached hereto. The disclosure of this specification also includes the complement of the individual concepts described in this specification. In other words, if this specification states, for example, that "A is B," it can be said that this specification discloses that "A is not B," even if it omits the statement that "A is not B." This is because when "A is B," it is assumed that the case where "A is not B" is taken into consideration.

[0203] The disclosure of the above embodiments includes the following sections.

[0204] (Section 1) a first wiring board; a first semiconductor device mounted on the first wiring board; a second wiring board overlapping the first wiring board in a first direction perpendicular to a main surface of the first wiring board; a second semiconductor device mounted on the second wiring board; a wiring member disposed between the first wiring board and the second wiring board and connecting the first wiring board and the second wiring board; the wiring member has a plurality of wiring terminals, the first semiconductor device has a plurality of signal terminals electrically connected to the second semiconductor device via the plurality of wiring terminals of the wiring member, a first signal terminal of the plurality of signal terminals of the first semiconductor device is electrically connected to the second semiconductor device via a first wiring terminal of the plurality of wiring terminals of the wiring member; a second signal terminal of the first semiconductor device is electrically connected to the second semiconductor device via a second wiring terminal of the wiring member; the first wiring terminal and the second wiring terminal overlap the first semiconductor device in the first direction; the first wiring terminal and the second wiring terminal are disposed between an imaginary first plane that is orthogonal to the main surface and intersects with the first signal terminal, and an imaginary second plane that is parallel to the first plane and intersects with the second signal terminal; 1. An electronic module comprising:

[0205] (Section 2) a first wiring board; a first semiconductor device mounted on the first wiring board; a second wiring board overlapping the first wiring board in a first direction perpendicular to a main surface of the first wiring board; a second semiconductor device mounted on the second wiring board; a wiring member disposed between the first wiring board and the second wiring board and connecting the first wiring board and the second wiring board; the wiring member has a plurality of wiring terminals, the first semiconductor device has a plurality of signal terminals electrically connected to the second semiconductor device via the plurality of wiring terminals of the wiring member, a first signal terminal of the plurality of signal terminals of the first semiconductor device is electrically connected to the second semiconductor device via a first wiring terminal of the plurality of wiring terminals of the wiring member; a second signal terminal of the first semiconductor device is electrically connected to the second semiconductor device via a second wiring terminal of the wiring member; the first wiring terminal and the second wiring terminal overlap the first semiconductor device in the first direction; In the first direction, the first signal terminal and the second signal terminal do not overlap the wiring member. 1. An electronic module comprising:

[0206] (Section 3) a distance between the first wiring terminal and the second wiring terminal is narrower than a distance between the first signal terminal and the second signal terminal; Item 3. An electronic module according to item 1 or 2, characterized in that:

[0207] (Section 4) a difference between a distance between the first signal terminal and the first wiring terminal and a distance between the second signal terminal and the second wiring terminal is smaller than a distance between the first wiring terminal and the second wiring terminal; 4. The electronic module according to any one of items 1 to 3, characterized in that:

[0208] (Section 5) a difference between a distance between the first signal terminal and the first wiring terminal and a distance between the second signal terminal and the second wiring terminal is smaller than a distance between the first signal terminal and the second signal terminal; 5. The electronic module according to any one of items 1 to 4, characterized in that:

[0209] (Section 6) a distance between the first signal terminal and the first wiring terminal and a distance between the second signal terminal and the second wiring terminal are smaller than an interval between the first signal terminal and the second signal terminal; 6. An electronic module according to any one of items 1 to 5, characterized in that:

[0210] (Section 7) a distance between the first signal terminal and the first wiring terminal and a distance between the second signal terminal and the second wiring terminal are greater than a distance between the first wiring terminal and the second wiring terminal; 7. The electronic module according to any one of items 1 to 6, characterized in that:

[0211] (Section 8) In the first direction, the first signal terminal and the second signal terminal do not overlap the wiring member. Item 1. An electronic module according to item 1.

[0212] (Section 9) the wiring member is spaced apart from the first plane and the second plane and is disposed between the first plane and the second plane. Item 9. An electronic module according to any one of items 1 to 8, characterized in that:

[0213] (Section 10) the plurality of signal terminals of the first semiconductor device and the plurality of wiring terminals of the wiring member include a plurality of pairs of two terminals electrically connected to each other; At least one of the plurality of pairs has a maximum distance between the two terminals; the maximum distance is shorter than the maximum length of the sides of the first semiconductor device; 10. An electronic module according to any one of items 1 to 9, characterized in that:

[0214] (Section 11) the plurality of signal terminals of the first semiconductor device and the plurality of wiring terminals of the wiring member include a plurality of pairs of two terminals electrically connected to each other; At least one of the plurality of pairs has a maximum wiring length between the two terminals, the maximum wiring length is shorter than the maximum length of the sides of the first semiconductor device; 11. An electronic module according to any one of items 1 to 10, characterized in that:

[0215] (Section 12) a first wiring board; a first semiconductor device mounted on the first wiring board; a second wiring board overlapping the first wiring board in a first direction perpendicular to a main surface of the first wiring board; a second semiconductor device mounted on the second wiring board; a third semiconductor device mounted on the first wiring board; a wiring member disposed between the first wiring board and the second wiring board and connecting the first wiring board and the second wiring board; the wiring member has a first portion located between the first semiconductor device and the second wiring board in the first direction, and a second portion located between the third semiconductor device and the second wiring board in the first direction, the first semiconductor device is electrically connected to the second semiconductor device via the first portion, and the third semiconductor device is electrically connected to the second semiconductor device via the second portion; 1. An electronic module comprising:

[0216] (Section 13) In the first direction, the wiring member overlaps with a center of the first semiconductor device. 13. An electronic module according to any one of items 1 to 12, characterized in that:

[0217] (Section 14) In the first direction, the second semiconductor device overlaps the first wiring board. Item 14. An electronic module according to any one of items 1 to 13, characterized in that:

[0218] (Section 15) the second semiconductor device has a signal terminal overlapping the first wiring board in the first direction; the signal terminal of the second semiconductor device is electrically connected to any one of the plurality of signal terminals of the first semiconductor device; Item 15. An electronic module according to any one of items 1 to 14, characterized in that:

[0219] (Section 16) In the first direction, the signal terminal of the second semiconductor device overlaps with the first semiconductor device. Item 16. An electronic module according to item 15, characterized in that:

[0220] (Section 17) the main surface of the first wiring board is a first main surface, the first semiconductor device is mounted on the first main surface of the first wiring board, the wiring member is bonded to a second main surface of the first wiring board opposite to the first main surface, and is bonded to a third main surface of the second wiring board. Item 17. An electronic module according to any one of items 1 to 16, characterized in that:

[0221] (Section 18) the second semiconductor device is mounted on the third main surface of the second wiring board; Item 18. An electronic module according to item 17, characterized in that:

[0222] (Section 19) further comprising a capacitor mounted on a fourth main surface of the second wiring board opposite to the third main surface, Item 19. Electronic module according to item 18, characterized in that

[0223] (Section 20) the capacitor overlaps the second semiconductor device in the first direction; 20. An electronic module according to item 19, characterized in that:

[0224] (Section 21) the second semiconductor device is mounted on a fourth main surface of the second wiring board opposite to the third main surface; 21. An electronic module according to any one of items 17 to 20, characterized in that:

[0225] (Section 22) further comprising a capacitor mounted on the third main surface of the second wiring board; Item 22. An electronic module according to item 21, characterized in that:

[0226] (Section 23) In the first direction, the capacitor overlaps with at least one of the second semiconductor device, the first wiring board, and the first semiconductor device. Item 23. An electronic module according to item 22, characterized in that:

[0227] (Section 24) further comprising a third semiconductor device mounted on the first wiring board; the third semiconductor device is electrically connected to the second semiconductor device via the wiring member; 12. An electronic module according to any one of items 1 to 11, characterized in that:

[0228] (Section 25) the first semiconductor device is a memory device, The second semiconductor device is a processing device. 25. An electronic module according to any one of items 1 to 24, characterized in that:

[0229] (Section 26) the wiring member is a first wiring member, a third wiring board overlapping the second wiring board in the first direction; a fourth semiconductor device mounted on the third wiring board; a second wiring member disposed between the third wiring board and the second wiring board and connecting the third wiring board and the second wiring board; the second wiring member has a plurality of wiring terminals, the fourth semiconductor device has a plurality of signal terminals electrically connected to the second semiconductor device via the plurality of wiring terminals of the second wiring member, a third signal terminal of the plurality of signal terminals of the fourth semiconductor device is electrically connected to the second semiconductor device via a third wiring terminal of the plurality of wiring terminals of the second wiring member; a fourth signal terminal of the plurality of signal terminals of the fourth semiconductor device is electrically connected to the second semiconductor device via a fourth wiring terminal of the plurality of wiring terminals of the second wiring member; the third wiring terminal and the fourth wiring terminal overlap the fourth semiconductor device in the first direction; the third wiring terminal and the fourth wiring terminal are disposed between an imaginary third plane that is orthogonal to the main surface and intersects with the third signal terminal, and an imaginary fourth plane that is parallel to the third plane and intersects with the fourth signal terminal. Item 1. An electronic module according to item 1.

[0230] (Section 27) the wiring member is a first wiring member, a third wiring board overlapping the second wiring board in the first direction; a fourth semiconductor device mounted on the third wiring board; a second wiring member disposed between the third wiring board and the second wiring board and connecting the third wiring board and the second wiring board; the second wiring member has a plurality of wiring terminals, the fourth semiconductor device has a plurality of signal terminals electrically connected to the second semiconductor device via the plurality of wiring terminals of the second wiring member, a third signal terminal of the plurality of signal terminals of the fourth semiconductor device is electrically connected to the second semiconductor device via a third wiring terminal of the plurality of wiring terminals of the second wiring member; a fourth signal terminal of the plurality of signal terminals of the fourth semiconductor device is electrically connected to the second semiconductor device via a fourth wiring terminal of the plurality of wiring terminals of the second wiring member; the third wiring terminal and the fourth wiring terminal overlap the first semiconductor device in the first direction; In the first direction, the third signal terminal and the fourth signal terminal do not overlap the second wiring member. Item 3. An electronic module according to item 2.

[0231] (Section 28) the wiring member is a first wiring member, a third wiring board overlapping the second wiring board in the first direction; a fourth semiconductor device mounted on the third wiring board; a second wiring member disposed between the third wiring board and the second wiring board and connecting the third wiring board and the second wiring board; the fourth semiconductor device is electrically connected to the second semiconductor device via the second wiring member; Item 13. An electronic module according to item 12, characterized in that:

[0232] (Section 29) further comprising a fifth semiconductor device mounted on the third wiring board; the fifth semiconductor device is electrically connected to the second semiconductor device via the second wiring member; Item 29. Electronic module according to item 28, characterized in that

[0233] (Section 30) The exterior and and an electronic module according to any one of items 1 to 29, arranged inside the exterior. An electronic device characterized by: [Explanation of symbols]

[0234] S1...signal wiring (first signal wiring), S2...signal wiring (second signal wiring), V1...plane (first plane), V2...plane (second plane), 11...wiring board (first wiring board), 12...wiring board (second wiring board), 21...memory (first semiconductor device), 22...image processing engine (second semiconductor device), 31...wiring member, 100...image processing module (electronic module), 600...camera (electronic device), 2111...signal terminal (first signal terminal), 2112...signal terminal (second signal terminal), 3111...wiring terminal (first wiring terminal), 3112...wiring terminal (second wiring terminal)

Claims

1. a first wiring board; a first semiconductor device mounted on the first wiring board; a second wiring board overlapping the first wiring board in a first direction perpendicular to a main surface of the first wiring board; a second semiconductor device mounted on the second wiring board; a wiring member disposed between the first wiring board and the second wiring board and connecting the first wiring board and the second wiring board; the wiring member has a plurality of wiring terminals, the first semiconductor device has a plurality of signal terminals electrically connected to the second semiconductor device via the plurality of wiring terminals of the wiring member, a first signal terminal of the plurality of signal terminals of the first semiconductor device is electrically connected to the second semiconductor device via a first wiring terminal of the plurality of wiring terminals of the wiring member; a second signal terminal of the first semiconductor device is electrically connected to the second semiconductor device via a second wiring terminal of the wiring member; the first wiring terminal and the second wiring terminal overlap the first semiconductor device in the first direction; the first wiring terminal and the second wiring terminal are disposed between an imaginary first plane that is orthogonal to the main surface and intersects with the first signal terminal, and an imaginary second plane that is parallel to the first plane and intersects with the second signal terminal; 1. An electronic module comprising:

2. a first wiring board; a first semiconductor device mounted on the first wiring board; a second wiring board overlapping the first wiring board in a first direction perpendicular to a main surface of the first wiring board; a second semiconductor device mounted on the second wiring board; a wiring member disposed between the first wiring board and the second wiring board and connecting the first wiring board and the second wiring board; the wiring member has a plurality of wiring terminals, the first semiconductor device has a plurality of signal terminals electrically connected to the second semiconductor device via the plurality of wiring terminals of the wiring member, a first signal terminal of the plurality of signal terminals of the first semiconductor device is electrically connected to the second semiconductor device via a first wiring terminal of the plurality of wiring terminals of the wiring member; a second signal terminal of the first semiconductor device is electrically connected to the second semiconductor device via a second wiring terminal of the wiring member; the first wiring terminal and the second wiring terminal overlap the first semiconductor device in the first direction; In the first direction, the first signal terminal and the second signal terminal do not overlap the wiring member.

1. An electronic module comprising:

3. a distance between the first wiring terminal and the second wiring terminal is narrower than a distance between the first signal terminal and the second signal terminal; 3. An electronic module according to claim 1 or 2.

4. a difference between a distance between the first signal terminal and the first wiring terminal and a distance between the second signal terminal and the second wiring terminal is smaller than a distance between the first wiring terminal and the second wiring terminal; 3. An electronic module according to claim 1 or 2.

5. a difference between a distance between the first signal terminal and the first wiring terminal and a distance between the second signal terminal and the second wiring terminal is smaller than a distance between the first signal terminal and the second signal terminal; 3. An electronic module according to claim 1 or 2.

6. a distance between the first signal terminal and the first wiring terminal and a distance between the second signal terminal and the second wiring terminal are smaller than an interval between the first signal terminal and the second signal terminal; 3. An electronic module according to claim 1 or 2.

7. a distance between the first signal terminal and the first wiring terminal and a distance between the second signal terminal and the second wiring terminal are greater than a distance between the first wiring terminal and the second wiring terminal; 3. An electronic module according to claim 1 or 2.

8. In the first direction, the first signal terminal and the second signal terminal do not overlap the wiring member.

2. The electronic module of claim 1.

9. the wiring member is disposed between the first plane and the second plane and away from the first plane and the second plane; 2. The electronic module of claim 1.

10. the plurality of signal terminals of the first semiconductor device and the plurality of wiring terminals of the wiring member include a plurality of pairs of two terminals electrically connected to each other; At least one of the plurality of pairs has a maximum distance between the two terminals, the maximum distance is shorter than the maximum length of the sides of the first semiconductor device; 3. An electronic module according to claim 1 or 2.

11. the plurality of signal terminals of the first semiconductor device and the plurality of wiring terminals of the wiring member include a plurality of pairs of two terminals electrically connected to each other; At least one of the plurality of pairs has a maximum wiring length between the two terminals, the maximum wiring length is shorter than the maximum length of the sides of the first semiconductor device; 3. An electronic module according to claim 1 or 2.

12. a first wiring board; a first semiconductor device mounted on the first wiring board; a second wiring board overlapping the first wiring board in a first direction perpendicular to a main surface of the first wiring board; a second semiconductor device mounted on the second wiring board; a third semiconductor device mounted on the first wiring board; a wiring member disposed between the first wiring board and the second wiring board and connecting the first wiring board and the second wiring board; the wiring member has a first portion located between the first semiconductor device and the second wiring board in the first direction, and a second portion located between the third semiconductor device and the second wiring board in the first direction, the first semiconductor device is electrically connected to the second semiconductor device via the first portion, and the third semiconductor device is electrically connected to the second semiconductor device via the second portion.

1. An electronic module comprising:

13. In the first direction, the wiring member overlaps with a center of the first semiconductor device.

13. An electronic module according to claim 1, 2 or 12.

14. the second semiconductor device overlaps the first wiring board in the first direction; 13. An electronic module according to claim 1, 2 or 12.

15. the second semiconductor device has a signal terminal overlapping the first wiring board in the first direction; the signal terminal of the second semiconductor device is electrically connected to any one of the plurality of signal terminals of the first semiconductor device; 3. An electronic module according to claim 1 or 2.

16. In the first direction, the signal terminal of the second semiconductor device overlaps with the first semiconductor device.

16. The electronic module of claim 15.

17. the main surface of the first wiring board is a first main surface, the first semiconductor device is mounted on the first main surface of the first wiring board, the wiring member is bonded to a second main surface of the first wiring board opposite to the first main surface, and is bonded to a third main surface of the second wiring board; 13. An electronic module according to claim 1, 2 or 12.

18. the second semiconductor device is mounted on the third main surface of the second wiring board; 18. The electronic module of claim 17.

19. a capacitor mounted on a fourth main surface of the second wiring board opposite to the third main surface, 20. The electronic module of claim 18.

20. the capacitor overlaps the second semiconductor device in the first direction; 20. The electronic module of claim 19.

21. the second semiconductor device is mounted on a fourth main surface of the second wiring board opposite to the third main surface; 18. The electronic module of claim 17.

22. further comprising a capacitor mounted on the third main surface of the second wiring board; 22. The electronic module of claim 21.

23. In the first direction, the capacitor overlaps with at least one of the second semiconductor device, the first wiring board, and the first semiconductor device.

23. The electronic module of claim 22.

24. further comprising a third semiconductor device mounted on the first wiring board; the third semiconductor device is electrically connected to the second semiconductor device via the wiring member; 3. An electronic module according to claim 1 or 2.

25. the first semiconductor device is a memory device, the second semiconductor device is a processing device; 13. An electronic module according to claim 1, 2 or 12.

26. the wiring member is a first wiring member, a third wiring board overlapping the second wiring board in the first direction; a fourth semiconductor device mounted on the third wiring board; a second wiring member disposed between the third wiring board and the second wiring board and connecting the third wiring board and the second wiring board; the second wiring member has a plurality of wiring terminals, the fourth semiconductor device has a plurality of signal terminals electrically connected to the second semiconductor device via the plurality of wiring terminals of the second wiring member, a third signal terminal of the fourth semiconductor device is electrically connected to the second semiconductor device via a third wiring terminal of the second wiring member; a fourth signal terminal of the plurality of signal terminals of the fourth semiconductor device is electrically connected to the second semiconductor device via a fourth wiring terminal of the plurality of wiring terminals of the second wiring member; the third wiring terminal and the fourth wiring terminal overlap the fourth semiconductor device in the first direction; the third wiring terminal and the fourth wiring terminal are disposed between an imaginary third plane that is orthogonal to the main surface and intersects with the third signal terminal, and an imaginary fourth plane that is parallel to the third plane and intersects with the fourth signal terminal; 2. The electronic module of claim 1.

27. the wiring member is a first wiring member, a third wiring board overlapping the second wiring board in the first direction; a fourth semiconductor device mounted on the third wiring board; a second wiring member disposed between the third wiring board and the second wiring board and connecting the third wiring board and the second wiring board; the second wiring member has a plurality of wiring terminals, the fourth semiconductor device has a plurality of signal terminals electrically connected to the second semiconductor device via the plurality of wiring terminals of the second wiring member, a third signal terminal of the fourth semiconductor device is electrically connected to the second semiconductor device via a third wiring terminal of the second wiring member; a fourth signal terminal of the plurality of signal terminals of the fourth semiconductor device is electrically connected to the second semiconductor device via a fourth wiring terminal of the plurality of wiring terminals of the second wiring member; the third wiring terminal and the fourth wiring terminal overlap the first semiconductor device in the first direction; In the first direction, the third signal terminal and the fourth signal terminal do not overlap the second wiring member.

3. The electronic module of claim 2.

28. the wiring member is a first wiring member, a third wiring board overlapping the second wiring board in the first direction; a fourth semiconductor device mounted on the third wiring board; a second wiring member disposed between the third wiring board and the second wiring board and connecting the third wiring board and the second wiring board; the fourth semiconductor device is electrically connected to the second semiconductor device via the second wiring member; 13. The electronic module of claim 12.

29. further comprising a fifth semiconductor device mounted on the third wiring board; the fifth semiconductor device is electrically connected to the second semiconductor device via the second wiring member; 29. The electronic module of claim 28.

30. The exterior and and an electronic module according to claim 1, 2, 8, 9, 12, 26, 27, 28 or 29, disposed inside the outer casing. An electronic device characterized by:

Images