Information processing device

Abstract

To provide a novel information processing device with minimal signal transmission delay and low power consumption.SOLUTION: A memory device has a first layer, a second layer, and a third layer. A circuit is provided on the first layer. A memory cell unit is provided on the second layer. A first electrode is provided on the third layer. The circuit has a function of switching between reading and writing first data or second data to the memory cell unit. At least one portion of the second layer is stacked above the first layer. At least one portion of the third layer is stacked above the second layer. An arithmetic device has a fourth layer and a fifth layer. A central processing unit is provided on the fourth layer. A second electrode is provided on the fifth layer. At least one portion of the fifth layer is stacked above the fourth layer. The circuit is electrically connected to the central processing unit via the first and second electrodes.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an information processing device, and more particularly to an information processing device having a storage device (also called a semiconductor storage device or memory) that utilizes semiconductor characteristics and an arithmetic unit.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, an imaging device, a display device, a light-emitting device, a power storage device, a memory device, a display system, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. [Background technology]

[0003] For many years, hard disk drives (HDDs) have been used primarily as non-volatile storage devices in information processing devices such as personal computers (PCs), servers, and data centers. However, in recent years, solid state drives (SSDs), which are lightweight, have no physical moving parts, and can read and write data at high speeds, have become increasingly popular.

[0004] Most SSDs are configured using NAND-type universal memory (also called flash memory) and a controller. NAND-type universal memory is a non-volatile storage device that stores data electrically. SSD cache memory (also called buffer memory) uses DRAM (Dynamic Random Access Memory) and SRAM (Static RAM), and DRAM and SRAM are volatile storage devices. Note that storage devices that utilize semiconductor characteristics, such as DRAM, SRAM, and NAND-type universal memory, are referred to as semiconductor storage devices (also called memories) in this specification.

[0005] Meanwhile, transistors having an oxide semiconductor or metal oxide in a channel formation region of the transistor (also referred to as oxide semiconductor transistors or OS (Oxide Semiconductor) transistors) are known. OS transistors have attracted attention because they have a characteristic that their drain current (also referred to as off-current) is extremely small when the transistor is in an off state (see, for example, Non-Patent Documents 1 and 2). DRAM is a storage device in which a memory cell is composed of one transistor and one capacitor, and stores data by accumulating charge in the capacitor. Therefore, by using an OS transistor in a DRAM memory cell, stored data can be retained for a long time.

[0006] Furthermore, oxide semiconductors have been found to have a c-axis aligned crystalline (CAAC) structure and a nanocrystalline (nc) structure, which are neither single-crystalline nor amorphous (see Non-Patent Documents 1 and 3). Non-Patent Documents 1 and 3 disclose techniques for manufacturing transistors using oxide semiconductors having a CAAC structure. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “Properties of crystalline In-Ga-Zn-oxide semiconductor and its transistor characteristics,” Jpn.J.Appl.Phys.,vol.53,04ED18(2014). [Non-patent document 2] K. Kato et al., “Evaluation of Off-State Current Characteristics of Transistor Using Oxide Semiconductor Material, Indium-Gallium-Zinc Oxide,” Jpn.J.Appl.Phys., vol. 51, 021201 (2012). [Non-patent document 3] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-patent document 4] S. Maeda et al., “A 20ns-Write 45ns-Read and 1014-Cycle Endurance Memory Module Composed of 60nm Crystalline Oxide Semiconductor Transistors”, ISSCC 2018, SESSION 30, EMERGING MEMORIES, 30.4, p.484-486 Summary of the Invention [Problem to be solved by the invention]

[0008] Semiconductor memory devices such as DRAM, SRAM, and NAND-type universal memory are manufactured using a process separate from that of the central processing unit (CPU). Because the number of wires required to connect the semiconductor memory device to the CPU is limited, high-speed data transmission using standards such as the Dual Inline Memory Module (DIMM) is required. If the distance between the semiconductor memory device and the CPU is large, the parasitic capacitance or resistance of the wires increases, which can result in higher power consumption.

[0009] Furthermore, NAND-type universal memory, a semiconductor memory device, requires high voltages for writing and erasing, and it is difficult to fabricate NAND-type universal memory and cache memory such as DRAM or SRAM on the same chip because the fabrication processes for the two are different.

[0010] An object of one embodiment of the present invention is to provide a data processing device in which a NAND semiconductor memory device and a CPU can be connected with short wiring.Another object of one embodiment of the present invention is to provide a data processing device that can reduce power consumption.Another object of one embodiment of the present invention is to provide a data processing device with a novel configuration in which the speed of writing and reading data in a NAND semiconductor memory device can be switched.Another object of one embodiment of the present invention is to provide a data processing device with a novel configuration.

[0011] It should be noted that one embodiment of the present invention does not necessarily have to solve all of the above problems, but may solve at least one of the problems. Furthermore, the description of the above problems does not preclude the existence of other problems. Problems other than these will become apparent from the description in the specification, claims, drawings, etc., and other problems can be extracted from the description in the specification, claims, drawings, etc. [Means for solving the problem]

[0012] One embodiment of the present invention is an information processing device including a memory device and an arithmetic unit. The memory device has a first layer and a second layer. The first layer includes a circuit. The second layer includes a memory cell unit. The circuit has a function of switching between reading and writing first data or second data to the memory cell unit. The memory cell unit has a function of retaining the stored first data or second data when power is not supplied. At least a part of the second layer is stacked above the first layer. The arithmetic unit is provided in the first layer. The arithmetic unit has a central processing unit and an accelerator. The accelerator executes product-sum operations for performing inference processing based on a neural network.

[0013] In one embodiment of the present invention, it is preferable that the information processing device has a circuit including a data write circuit and a data read circuit, the data write circuit including a first write circuit that writes first data and a second read circuit that writes second data, and the data read circuit including a first read circuit that reads the first data and a second read circuit that reads the second data.

[0014] In one aspect of the present invention, the information processing device is preferably such that the first data is binary data and the second data is ternary or higher value data.

[0015] In one embodiment of the present invention, it is preferable that the data processing device include a first layer having an SOI substrate, a circuit having a first transistor formed in the SOI substrate, a memory cell portion having a second transistor, and the second transistor having a metal oxide in a channel formation region.

[0016] In one embodiment of the present invention, it is preferable that the data processing device include a first layer having a single crystal silicon substrate, a circuit having a first transistor formed in the single crystal silicon substrate, a memory cell portion having a second transistor, and the second transistor having a metal oxide in a channel formation region.

[0017] One aspect of the present invention is a supercomputer including the information processing device described above and a plurality of switch ports, wherein the information processing device is electrically connected to the plurality of switch ports. [Effects of the Invention]

[0018] One embodiment of the present invention can provide a data processing device in which a NAND semiconductor memory device and a CPU can be connected with short wiring. Another embodiment of the present invention can provide a data processing device that can reduce power consumption. Another embodiment of the present invention can provide a data processing device with a novel configuration that can switch the speed of writing and reading data in a NAND semiconductor memory device. Another embodiment of the present invention can provide a data processing device with a novel configuration.

[0019] It should be noted that one embodiment of the present invention does not necessarily have to solve all of the above problems, but may solve at least one of the problems. Furthermore, the description of the above problems does not preclude the existence of other problems. Problems other than these will become apparent from the description in the specification, claims, drawings, etc., and other problems can be extracted from the description in the specification, claims, drawings, etc. [Brief explanation of the drawings]

[0020] [Figure 1] 1A and 1B are perspective schematic views showing an example of the configuration of an information processing device. [Figure 2] FIG. 2 is a block diagram illustrating an example of the configuration of an information processing device. [Figure 3] FIG. 3 is a block diagram illustrating an example of the configuration of an information processing device. [Figure 4] Fig. 4A is a circuit diagram showing an example of the configuration of a string, and Figs. 4B to 4E are circuit diagrams showing an example of the configuration of a memory element. [Figure 5] 5A to 5D are circuit diagrams showing configuration examples of memory elements. [Figure 6]Figure 6A is a timing chart illustrating a write operation, and Figure 6B is a timing chart illustrating a read operation. [Figure 7] 7A and 7B are block diagrams showing configuration examples of an information processing device. [Figure 8] 8A and 8B are diagrams showing various information processing devices for each hierarchical level. [Figure 9] FIG. 9 is a schematic perspective view showing an example of the configuration of an information processing device. [Figure 10] 10A and 10B are perspective schematic views showing configuration examples of an information processing device. [Figure 11] 11A and 11B are a block diagram and a perspective schematic diagram showing an example of the configuration of an information processing device. [Figure 12] FIG. 12 is a schematic perspective view and a block diagram showing an example of the configuration of an information processing device. [Figure 13] FIG. 13 is a block diagram illustrating an example of the configuration of an information processing device. [Figure 14] 14A and 14B are perspective schematic views showing configuration examples of an information processing device. [Figure 15] 15A to 15C are block diagrams showing configuration examples of an information processing device. [Figure 16] FIG. 16 is a cross-sectional view showing an example of the configuration of a transistor. [Figure 17] FIG. 17 is a diagram illustrating an example of the configuration of an information processing device. [Figure 18] 18A and 18B are diagrams illustrating an application example of an integrated circuit. [Figure 19] Fig. 19A is a perspective view showing an example of a semiconductor wafer, Fig. 19B is a perspective view showing an example of a chip, and Figs. 19C and 19D are perspective views showing an example of an electronic component. [Figure 20] 20A to 20J are perspective views or schematic diagrams illustrating an example of an electronic device. [Figure 21] 21A to 21E are perspective views or schematic diagrams illustrating an example of an electronic device. [Figure 22] 22A to 22C are diagrams illustrating an example of an electronic device. [Figure 23] FIG. 23 is a diagram illustrating an example of an electronic device. [Figure 24] Figure 24 is an image diagram of factory automation. DETAILED DESCRIPTION OF THE INVENTION

[0021] The following describes an embodiment of the present invention. However, one embodiment of the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention should not be interpreted as being limited to the description of the embodiment shown below.

[0022] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0023] In the drawings, the same elements or elements having similar functions, elements made of the same material, or elements formed at the same time may be given the same reference numerals, and repeated description thereof may be omitted.

[0024] In this specification, for example, the power supply potential VDD may be abbreviated to potential VDD, VDD, etc. This also applies to other components (for example, signals, voltages, circuits, elements, electrodes, wiring, etc.).

[0025] Furthermore, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "_2", "[n]", "[m,n]", etc. may be added to the symbol. For example, the second wiring GL is written as wiring GL[2].

[0026] (Embodiment 1) In this embodiment, a configuration example of an information processing device according to one embodiment of the present invention will be described.

[0027] 1A is a perspective schematic diagram showing a configuration example of an information processing device 100 according to one embodiment of the present invention. The information processing device 100 includes a layer 10, layers 20_1 to 20_t (t is an integer of 2 or greater), a layer 30, and wiring EW. The wiring EW corresponds to a member provided in an opening extending from an upper layer to a lower layer, for example, a member constituting a memory element or an electrode such as a plug.

[0028] As shown in FIG. 1A, the information processing device 100 has a structure in which at least a portion of layer 20_1 is stacked above layer 10, at least a portion of layer 20_k+1 (k is an integer greater than or equal to 1-1) is stacked above layer 20_k, and at least a portion of layer 30 is stacked above layer 20_t.

[0029] In the information processing device 100, the layer 10, the layers 20_1 to 20_t, and the layer 30 constitute a memory device, and the layer 10 constitutes an arithmetic unit. Here, the memory device may be, for example, a NAND-type OS memory using a three-dimensional OS transistor. Note that the OS transistor is a transistor having a metal oxide in a channel formation region.

[0030] The layer 10, layers 20_1 to 20_t, and layer 30 are each provided with a circuit that can function by utilizing semiconductor characteristics, with the layer 10 being provided with a circuit OSC and a circuit CPU, which will be described later, and the layers 20_1 to 20_t being provided with a memory cell unit MCL, which will be described later. The layer 30 is a wiring layer in which wiring is formed. The memory device described above corresponds to the memory cell unit MCL. The arithmetic device described above corresponds to the circuit OSC and the circuit CPU.

[0031] 1B is a perspective schematic diagram in which layers 20_1 to 20_t and wiring EW relating to layer 20 are omitted from FIG. 1A, and shows the positional relationship between the circuit OSC, the circuit CPU, and the memory cell unit MCL. Note that in the drawings described in this specification and the like, the flow of main signals is indicated by arrows or lines, and power supply lines and the like may be omitted.

[0032] The circuit OSC functions as a drive circuit or a control circuit for the memory cell unit MCL. The circuit OSC includes a write circuit, a read circuit, etc. The circuit OSC writes and reads data to and from a plurality of memory elements (memory cells) provided in the layers 20_1 to 20_t of the memory cell unit MCL.

[0033] The circuit CPU has the function of performing arithmetic processing on data to be written to the memory cell unit MCL or data read from the memory cell unit MCL. Data arithmetic processing is performed by an arithmetic circuit included in the circuit CPU. The circuit CPU is also called a central processing unit or central processing device.

[0034] The circuit OSC and the circuit CPU are configured using transistors formed on a substrate SUB. The substrate SUB may be, for example, a single-crystal semiconductor substrate made of silicon, silicon carbide, or the like, a polycrystalline semiconductor substrate, or a compound semiconductor substrate made of silicon germanium, or the like. The substrate SUB may also be an SOI substrate or a semiconductor substrate on which semiconductor elements such as strained transistors or FIN-type transistors are provided, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like. Furthermore, the substrate SUB may also be a flexible substrate. In this embodiment, a case where a single-crystal silicon substrate is used as the substrate SUB will be described. A transistor having silicon in its channel formation region is called a Si transistor.

[0035] The circuit OSC and the memory cell unit MCL are electrically connected by wiring EW and layer 30. The wiring EW has a function of electrically connecting the circuit OSC and layer 30, and a function of electrically connecting the memory cells included in the memory cell unit MCL and layer 30. The wiring EW can be one or more types of wiring selected from a signal line, a power supply line that supplies a constant potential, a bit line (such as a write bit line or a read bit line), and a word line.

[0036] The circuit OSC and the circuit CPU are electrically connected using wiring formed on the substrate SUB. The information processing device 100 has features such as a short data transfer distance between the circuit OSC, the circuit CPU, and the memory cell unit MCL, which reduces signal transmission delay and enables high-speed operation, and suppresses increases in power consumption due to parasitic capacitance, etc. Furthermore, the memory cell unit MCL is provided above and overlaps the circuit OSC and the circuit CPU, which suppresses increases in the circuit area of the information processing device 100.

[0037] Next, an example of the configuration of the circuit CPU, the circuit OSC, and the memory cell unit MCL will be described. Fig. 2 is a block diagram showing an example of the configuration of the circuit CPU, the circuit OSC, and the memory cell unit MCL.

[0038] The memory cell unit MCL includes a memory cell array having a plurality of strings SRG. The strings SRG are electrically connected to wirings BL.

[0039] The channel formation region of the transistor constituting the memory cell of the string SRG preferably has one or more materials selected from the above, such as silicon, germanium, gallium arsenide, silicon carbide (SiC), metal oxide, etc.

[0040] In particular, when the channel formation region contains one or more metal oxides selected from indium, an element M (such as aluminum, gallium, yttrium, or tin), and zinc, the metal oxide may function as a wide-gap semiconductor, and a transistor containing the metal oxide in its channel formation region has a very small off-state current. In other words, the leakage current of a transistor in an off state can be reduced, allowing stored data to be retained even when power is not supplied. As a result, the power consumption of a data processing device may be reduced. Furthermore, since an analog potential corresponding to the retained data can be retained, binary (1-bit) data or multi-value (multi-bit) data of 3 or more values can be retained.

[0041] The wiring WL, wiring BL, and wiring CL shown in FIG. 2 correspond to the wiring EW shown in FIGS. 1A and 1B. The wiring WL is a plurality of word lines, and each of the wirings WL is electrically connected to a memory element included in the string SRG for each row. The wiring BL is a plurality of bit lines, and each of the wirings BL is electrically connected to a memory element included in the string SRG for each column. The wiring CL is a power supply line.

[0042] 2, the memory cell portion MCL has a configuration in which one string SRG is electrically connected to one wiring BL, but one embodiment of the present invention is not limited to this. For example, as shown in FIG. 3, the memory cell portion MCL may have a configuration in which multiple strings SRG are electrically connected to one wiring BL. Note that the block diagram in FIG. 3 illustrates only the memory cell portion MCL and a part of the circuit OSC.

[0043] The circuit OSC includes, for example, a circuit PRPH and a power supply circuit PS. The circuit CPU includes, for example, a command decoder CD and an arithmetic circuit PU. Although one arithmetic circuit PU is shown, multiple arithmetic circuits may be provided to form a multi-core system.

[0044] The control circuit CTR is included in the circuit CPU. There is no clear distinction between the control circuit CTR and the command decoder CD of the circuit CPU. In other words, part of the control circuit CTR can share part of the circuit CPU. The control circuit CTR has the function of accessing the circuit PRPH to write data to the memory cell unit MCL and the function of reading data from the memory cell unit MCL. The control circuit CTR also has the function of accessing the arithmetic circuit PU and the command decoder CD to input and output data.

[0045] When a write command and data are input, the control circuit CTR writes the data to the memory cell unit MCL as binary data. Next, the control circuit CTR can read the written binary data from the memory cell unit MCL and write the read data to the memory cell unit MCL as multi-level data. In other words, the memory cell unit MCL also functions as a cache memory for the memory cell unit MCL. Note that the control circuit CTR may also have a function to write multi-level data directly to the memory cell unit MCL when the memory access frequency is low, for example.

[0046] When a read command is input, the control circuit CTR reads binary or multi-valued data from the memory cell unit MCL and outputs it as binary data to the arithmetic circuit PU and command decoder CD. The arithmetic circuit PU and command decoder CD can input and output data converted into digital signals. Note that the write command and read command include an address signal.

[0047] The control circuit CTR may also have a function of detecting and correcting errors (also called ECC: Error Check and Correct) when reading data from the memory cell unit MCL. The memory cell unit MCL can also function as a cache memory when the control circuit CTR detects and corrects errors. Note that the signals processed by the control circuit CTR and the functions of the control circuit CTR are not limited to these, and other signals may be input (or output) as needed, and the control circuit CTR may have other functions.

[0048] The control circuit CTR can read data written as binary data or multi-valued data from the memory cell unit MCL via the wiring EW. The read data can be written back to the memory cell unit MCL via the wiring EW. Signals input / output between the memory cell unit MCL and the circuit CPU travel via the wiring EW, which shortens the distance the data travels. Note that the number of wirings that transmit signals input / output between the memory cell unit MCL and the circuit CPU is preferably 75 or more.

[0049] The information processing device 100 can use the memory cell unit MCL as a cache memory. The distance that data travels between the memory cell unit MCL and the circuit OSC, and between the circuit OSC and the circuit CPU, is short. This results in small signal transmission delays, high-speed operation, and the ability to suppress increases in power consumption due to parasitic capacitance, etc.

[0050] The circuit PRPH includes, for example, a circuit WLD, a circuit BLD, and a circuit CVC. The circuit WLD functions as a word line driver circuit and is electrically connected to the wiring WL. The circuit BLD functions as a bit line driver circuit and is electrically connected to the wiring BL. The circuit CVC functions as a power supply that generates and outputs a constant potential and is electrically connected to the wiring CL.

[0051] The circuit CPU includes, as other components of the control circuit CTR, a command decoder CD and an arithmetic circuit PU, for example. While one arithmetic circuit PU is shown, multiple arithmetic circuits PU may be provided to form a multi-core system. When the command is to read data, the command decoder CD generates a memory address. The memory address is provided to the circuit OSC. The circuit OSC controls the circuit PRPH to read data from the memory cell unit MCL. The read data is provided to the arithmetic circuit PU. When the command is to write data, the command decoder CD transfers data from a memory cell in the memory cell unit MCL or a register in the arithmetic circuit PU to a memory cell in the memory cell unit MCL. The transferred data may be processed by the arithmetic circuit PU. The generated memory address is not only converted from a logical address to a physical address, but can also be converted to avoid bad blocks. The circuit CPU has the function of realizing normally-off operation. When backing up data in the registers in the arithmetic circuit PU, the values of the registers in the circuit CPU are written to the memory cell unit MCL via the circuit OSC.

[0052] Next, an example of the circuit configuration of the string SRG of the memory cell unit MCL will be described.

[0053] 4A shows a circuit diagram of a string SRG included in the memory cell unit MCL. The string SRG includes a plurality of memory elements 410 between a transistor 431 and a transistor 432. FIG. 4B shows a circuit diagram of the memory element 410. The memory element 410 includes a transistor 411 and a transistor 412.

[0054] In this embodiment and the like, the first memory element 410 is referred to as a memory element 410[1], and the nth (n is an integer equal to or greater than 3) memory element 410 is referred to as a memory element 410[n]. The ith (i is an integer equal to or greater than 2 and less than n) memory element 410 is referred to as a memory element 410[i]. Note that when describing matters common to the memory elements 410[1] to 410[n], the memory element 410 may simply be referred to as a "memory element 410."

[0055] In this embodiment and the like, the transistor 411 included in the first memory element 410 is referred to as transistor 411[1], the transistor 411 included in the i-th memory element 410 is referred to as transistor 411[i], and the transistor 411 included in the n-th memory element 410 is referred to as transistor 411[n]. Note that when describing matters common to the transistors 411[1] to 411[n], the transistor 411 may be simply referred to as "transistor 411." The transistor 412 and a node 413, which will be described later, are also referred to in the same manner as the transistor 411.

[0056] An example of the circuit configuration of the string SRG shown in FIG. 4A will be described in detail. One of the source and drain of a transistor 411[1] included in a memory element 410[1] is electrically connected to a wiring WBL, and the other is electrically connected to a node 413[1]. The gate of the transistor 411[1] is electrically connected to a terminal 421[1]. One of the source and drain of a transistor 412[1] is electrically connected to the other of the source and drain of a transistor 431, and the other is electrically connected to one of the source or drain of a transistor 412[2]. The gate of the transistor 412[1] is electrically connected to a node 413[1]. The backgate of the transistor 412[1] is electrically connected to a terminal 422[1].

[0057] One of the source and drain of the transistor 431 is electrically connected to a wiring RBL, and the other is electrically connected to one of the source and drain of the transistor 412[1]. The gate of the transistor 431 is electrically connected to a terminal 433. Note that the wiring WBL and the wiring RBL correspond to the wiring BL shown in FIG. 2, and the wiring WBL is used when writing data, and the wiring RBL is used when reading data.

[0058] One of the source and the drain of the transistor 411[2] included in the memory element 410[2] is electrically connected to the node 413[1], and the other is electrically connected to the node 413[2]. The gate of the transistor 411[2] is electrically connected to the terminal 421[2]. One of the source and the drain of the transistor 412[2] is electrically connected to the other of the source and the drain of the transistor 412[1], and the gate is electrically connected to the node 413[2]. The backgate of the transistor 412[2] is electrically connected to the terminal 422[2].

[0059] One of the source and drain of the transistor 411[i] included in the memory element 410[i] is electrically connected to a node 413[i-1] (not shown), and the other is electrically connected to the node 413[i]. The gate of the transistor 411[i] is electrically connected to a terminal 421[i]. One of the source and drain of the transistor 412[i] is electrically connected to one or the other of the source and drain of the transistor 412[i-1] (not shown). The gate of the transistor 412[i] is electrically connected to the node 413[i], and the backgate of the transistor 412[i] is electrically connected to a terminal 422[i].

[0060] One of the source and the drain of the transistor 411[n] included in the memory element 410[n] is electrically connected to a node 413[n-1] (not shown). The other of the source and the drain of the transistor 411[n] is electrically connected to the node 413[n]. The gate of the transistor 411[n] is electrically connected to a terminal 421[n].

[0061] One of the source and the drain of the transistor 412[n] is electrically connected to one or the other of the source and the drain of the transistor 412[n-1] (not shown). The other of the source and the drain of the transistor 412[n] is electrically connected to the transistor 432. The gate of the transistor 412[n] is electrically connected to the node 413[n], and the back gate of the transistor 412[n] is electrically connected to the terminal 422[n].

[0062] The other of the source and the drain of the transistor 432 is electrically connected to the wiring SL. The gate of the transistor 432 is electrically connected to the terminal 434.

[0063] 4A has n memory elements 410 between transistors 431 and 432, with transistors 411[1] to 411[n] connected in series with adjacent transistors sharing the source and drain. Transistors 412[1] to 412[n] are also connected in series with adjacent transistors sharing the source and drain.

[0064] In this way, a structure in which memory elements 410 are connected in a row while adjacent transistors share the source and drain may be called a "string," "cell string," or "memory cell string." For example, one string SRG may be called "one string" or simply a "string." Note that the "string," "cell string," and "memory cell string" may also be referred to as a unit.

[0065] The memory element 410 (see FIG. 4B) has a function of holding a potential (charge) written to the node 413. Specifically, a voltage that turns on the transistor 411 is supplied from a terminal 421 to the gate of the transistor 411, and a charge for setting the node 413 to a predetermined voltage is supplied to the node 413 via the source and drain of the transistor 411. Then, a voltage that turns off the transistor 411 is supplied from the terminal 421 to the gate of the transistor 411. By turning off the transistor 411, the charge written to the node 413 can be held.

[0066] The semiconductor layers of the transistor 411 and the transistor 412 can be formed using a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or a combination of these. Examples of semiconductor materials include silicon and germanium. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors may also be used. The same applies to the transistors 431 and 432.

[0067] Note that the semiconductor layers used in the transistor may be stacked. When the semiconductor layers are stacked, semiconductors having different crystal states or different semiconductor materials may be used for the respective layers.

[0068] In particular, the transistor 411 is preferably an OS transistor. An oxide semiconductor has a band gap of 2 eV or more, and therefore has an extremely low off-state current. When an OS transistor is used as the transistor 411, charge written to the node 413 can be held for a long period of time. When an OS transistor is used as the transistor 411, the memory element 410 can be called an "OS memory."

[0069] OS memory can retain written information for more than one year, or even more than ten years, even if the power supply is cut off, so OS memory can also be considered non-volatile memory.

[0070] Furthermore, since the amount of charge written into the OS memory is unlikely to change over a long period of time, the OS memory can hold not only binary (1 bit) data but also multi-value (multi-bit) data (information).

[0071] Furthermore, because OS memory writes charge to nodes via OS transistors, it does not require the high voltages required by conventional NAND universal memories, enabling high-speed write operations. Furthermore, OS memory does not require the erase operation required before rewriting data, as is done with NAND universal memories. Furthermore, because no charge is injected or extracted from the floating gate or charge trapping layer, OS memory allows for virtually unlimited data write and read operations. OS memory exhibits less degradation than conventional NAND universal memories, making it highly reliable.

[0072] In addition, OS memory does not involve atomic-level structural changes like magnetoresistive random access memory (MRAM) or resistive random access memory (ReRAM), and therefore has better rewrite endurance than magnetoresistive random access memory and resistive random access memory.

[0073] Furthermore, the off-state current of OS transistors hardly increases even in high-temperature environments. Specifically, the off-state current hardly increases even in ambient temperatures above room temperature and below 200°C. Furthermore, the on-state current is unlikely to decrease even in high-temperature environments. Storage devices including OS memory operate stably and with high reliability even in high-temperature environments. Furthermore, OS transistors have a high dielectric strength voltage between the source and drain. By using OS transistors as transistors that make up the OS memory, it is possible to realize information processing devices that operate stably and with high reliability even in high-temperature environments.

[0074] 4C, a transistor having a back gate may be used as the transistor 411 included in the memory element 410. In FIG. 4C, the gate and back gate of the transistor 411 are electrically connected to each other.

[0075] 4D , a capacitor 425 may be provided between the node 413 and the terminal 423. When the capacitor 425 is provided, it is preferable to supply a fixed potential to the terminal 423. By providing the capacitor 425, it is possible to suppress potential fluctuations at the node 413 and improve the reliability of the string SRG. In particular, when multi-level information is stored in the memory element 410, it is preferable to provide the capacitor 425 in the memory element 410.

[0076] 4E, transistors having back gates may be used as the transistors 431 and 432. In FIG. 4E, the gates and back gates of the transistors 431 and 432 are electrically connected to each other.

[0077] 5A, OS transistors may be used as both transistors 411 and 412 included in the memory element 410. In FIG. 5A, the OS transistors 411 and 412 are indicated by the symbol "OS."

[0078] 5B, an OS transistor may be used as the transistor 411 included in the memory element 410, and a Si transistor may be used as the transistor 412. In FIG. 5A, the transistor 411, which is an OS transistor, is denoted by the symbol "OS," and the transistor 412, which is a Si transistor, is denoted by the symbol "Si."

[0079] 5C, a Si transistor may be used as the transistor 411 included in the memory element 410, and an OS transistor may be used as the transistor 412. In FIG. 5C, the transistor 411, which is a Si transistor, is denoted by the symbol "Si," and the transistor 412, which is an OS transistor, is denoted by the symbol "OS."

[0080] 5D, Si transistors may be used as both transistors 411 and 412 included in the memory element 410. In FIG. 5D, the transistors 411 and 412, which are Si transistors, are indicated by the symbol "Si."

[0081] An example of the operation of the string SRG will be described with reference to the drawings. In this embodiment, a string SRG including four storage elements 410 will be described as an example.

[0082] 6A is a timing chart illustrating a write operation. In FIG. 6A, an example of an operation in which an H potential is written to the memory element 410[1], the memory element 410[2], and the memory element 410[4], and an L potential is written to the memory element 410[3] is described. Note that the wirings WL[1] to WL[4] correspond to wirings connected to the terminal 421 as shown in FIG. 4D. Note that the wirings CL[1] to CL[4] correspond to wirings connected to the terminal 423 when a capacitor 425 is provided between the node 413 and the terminal 423 as shown in FIG. 4D.

[0083] In an initial state, an L potential is written to the memory elements 410[1] to 410[4]. Also, an L potential is supplied to the wirings WL[1] to WL[4], the wirings CL[1] to CL[4], the terminal 433, the terminal 434, the wiring SL, and the wiring RBL.

[0084] In the period T1, an H potential is supplied to the wirings WL[1] to WL[4] and the wiring WBL. As a result, the potentials of the nodes 413[1] to 413[4] become H potentials. Therefore, the transistors 412[1] to 412[4] are turned on.

[0085] In the period T2, an L potential is supplied to the wiring WL[4]. Then, the transistor 411[4] is turned off, and the charge written to the node 413[4] is held. Here, a charge corresponding to an H potential is held. In addition, an L potential is supplied to the wiring WBL. Then, the potentials of the nodes 413[1] to 413[3] become L potential. Therefore, the transistors 412[1] to 412[3] are turned off.

[0086] In period T3, an L potential is supplied to the wiring WL[3]. Then, the transistor 411[3] is turned off, and the charge written to the node 413[3] is held. Here, a charge corresponding to the L potential is held. Also, an H potential is supplied to the wiring WBL. Then, the potentials of the node 413[1] and the node 413[2] become H potentials. Therefore, the transistor 412[1] and the transistor 412[2] are turned on.

[0087] In the period T4, an L potential is supplied to the wiring WL[2]. Then, the transistor 411[2] is turned off, and the charge written to the node 413[2] is held. Here, a charge equivalent to an H potential is held.

[0088] In the period T5, an L potential is supplied to the wiring WL[1]. Then, the transistor 411[1] is turned off, and the charge written to the node 413[1] is held. Here, a charge corresponding to an H potential is held. In this manner, data can be written to the memory elements 410[1] to 410[4].

[0089] 6B is a timing chart illustrating a read operation. In FIG. 6B, an example of a read operation of information stored in the memory element 410[2] among the information stored in the memory elements 410[1] to 410[4] will be described. It is assumed that an H potential is stored in the memory element 410[2].

[0090] In the period T6, an H potential is supplied to the wirings CL[1] to CL[4] and the terminal 433 to turn on the transistors 412[1] to 412[4] and the transistor 431. In addition, the H potential is precharged to the wiring RBL to put the wiring RBL in a floating state.

[0091] In the period T7, the L potential is supplied to the wiring CL[2]. Since the H potential is held at the node 413[2], the transistor 412[2] remains on.

[0092] In a period T8, an H potential is supplied to the terminal 434 to turn on the transistor 432. Since the transistors 412[1] to 412[4] are all on, the wiring RBL and the wiring SL are electrically connected, and the potential of the wiring RBL changes to an L potential.

[0093] Note that when the potential of the node 413[2] is an L potential, supplying an L potential to the wiring CL[2] turns off the transistor 412[2]. In this case, even when the transistor 432 is turned on, the potential of the wiring RBL remains an H potential. By knowing the change in the potential of the wiring RBL, the data stored in the memory element 410 can be known.

[0094] That is, in the period T7, the potential of the wiring CL corresponding to the memory element 410 from which data is to be read is set to the L potential, so that data held in the memory element 410 can be read.

[0095] In the period T9, an L potential is supplied to the wirings CL[1] to CL[4], the terminal 433, and the terminal 434. As a result, the transistor 412[1], the transistor 412[2], the transistor 412[4], the transistor 431, and the transistor 432 are turned off.

[0096] The memory cell unit MCL having the string SRG shown in this embodiment and the like functions as a NAND type memory device.

[0097] In addition, by storing data that is frequently rewritten in the storage element 410 close to the wiring WBL, the time required to write (rewrite) the data can be shortened. In other words, the data writing (rewriting) speed can be increased. By operating in this manner, the 3D OS NAND, which will be described later, can be operated as a temporary storage device like RAM.

[0098] The circuit BLD included in the circuit OSC will be described in more detail. Fig. 7A is a block diagram showing a configuration example of a part of the circuit OSC. Fig. 7A illustrates not only the circuit OSC but also the control circuit CTR of the circuit CPU. Fig. 7A omits the power supply circuit PS and the like from the circuit OSC shown in Fig. 2, and more specifically illustrates a configuration example of the circuit BLD and the signal flow within the circuit OSC.

[0099] The circuit BLD may have, for example, a column decoder COD, a write circuit WC, a sense amplifier SA, and an output circuit OPC.

[0100] The column decoder COD has a function of selecting a wiring BL electrically connected to a memory element to be written or read in response to an address signal AD received from the control circuit CTR. Here, the address signal AD is an internal signal of the circuit OSC. The address signal AD is also sent to the circuit WLD. The circuit WLD has a function of driving the wiring WL and has a function of selecting a wiring WL electrically connected to a memory element to be written or read in response to the address signal AD.

[0101] The write circuit WC has a function of supplying a potential corresponding to a data signal WD supplied from the control circuit CTR to a wiring BL selected by the column decoder COD. Here, the data signal WD is an internal signal of the circuit OSC.

[0102] The sense amplifier SA amplifies the data signal read from the line BL. The amplified data signal is output as a data signal RD to the control circuit CTR via the output circuit OPC. The control circuit CTR outputs a signal corresponding to the data signal RD to the arithmetic circuit PU or the command decoder CD.

[0103] Note that the components of the circuit BLD are not limited to these, and other components may be added as needed, or unnecessary components may be removed.Furthermore, the functions of the circuit BLD are not limited to these, and other functions may be included, or unnecessary functions may be removed.

[0104] FIG. 7B is a block diagram for explaining a configuration for switching between binary data and multi-valued data to be written to the string SRG, and for switching between binary data and multi-valued data to be read from the string SRG.

[0105] In FIG. 7B, the sense amplifier SA described in FIG. 7A includes a binary data sense amplifier BSA for reading binary data and a multilevel data sense amplifier MSA for reading multilevel data. FIG. 7B also illustrates a latch circuit LAT for temporarily holding data. The binary data sense amplifier BSA can be a DRAM write circuit. The multilevel data sense amplifier MSA can be an A / D converter circuit or the like capable of converting analog signals to digital signals.

[0106] 7B also includes a binary data write circuit BWC for writing binary data to the write circuit WC described in FIG. 7A, and a multilevel data write circuit MWC for writing multilevel data. The binary data write circuit BWC can be a DRAM write circuit. The multilevel data write circuit MWC can be a D / A converter circuit or the like capable of converting digital signals to analog signals.

[0107] This section explains the operation when performing high-speed writes and reads, such as when using the string SRG as cache memory. For example, if a command to be executed by the circuit CPU is stored as multi-valued data, it is converted to binary data using instruction branch prediction or similar. The binary data is read from the string SRG in block units by the circuit CPU and temporarily stored in the latch circuit LAT. From the binary data stored in the latch circuit LAT, the data at the desired address value can be transferred to the arithmetic circuit PU and command decoder CD of the circuit CPU.

[0108] When rewriting data, if the binary data in the latch circuit LAT does not contain the value of the desired address, the data to be rewritten is read into the latch circuit LAT. The value of the desired address is rewritten in the latch circuit LAT and written back to the string SRG. When rewriting data in a memory element above the string SRG, the data is copied for each block of the string SRG. The latch circuit LAT does not need to have the same capacity as one block.

[0109] Generally, various memory devices are used in semiconductor devices such as computers depending on the application. Figure 8A shows the various memory devices used in semiconductor devices by layer. The higher the layer, the faster the operating speed of the memory device is required, while the lower the layer, the larger the memory capacity and higher the recording density are required. Figure 8A shows, from the top layer, memory integrated as a register in a processing unit such as a CPU, SRAM, DRAM, and 3D NAND memory.

[0110] In this specification, a NAND type universal memory with a three-dimensional structure using OS transistors is referred to as "3D OS NAND." Also, a NAND type universal memory with a three-dimensional structure using Si transistors is referred to as "3D NAND." For example, the information processing device 100 described above includes a storage device that is a 3D OS NAND.

[0111] Because 3D OS NAND is randomly accessible and the OS transistors have very low off-state current, 3D OS NAND can retain written information for more than a year, or even more than a decade, even after power is removed, so 3D OS NAND can be considered non-volatile memory.

[0112] In addition, since the amount of written charge in 3D OS NAND is less likely to change over a long period of time, 3D OS NAND can store not only binary (1 bit) information but also multi-value (multi-bit) information.

[0113] Furthermore, because 3D OS NAND writes charge to nodes via OS transistors, it does not require the high voltages required by conventional NAND universal memory, enabling high-speed write operations. Furthermore, 3D OS NAND does not require the erase operation required before rewriting data, as is done with NAND universal memory. Furthermore, because there is no charge injection or extraction into or from the floating gate or charge trapping layer, 3D OS NAND allows for virtually unlimited data write and read operations. Compared to conventional NAND universal memory, 3D OS NAND exhibits less degradation and higher reliability.

[0114] In addition, 3D OS NAND does not involve atomic-level structural changes like magnetoresistive random access memory (MRAM) or resistive random access memory (ReRAM), and therefore has better rewrite endurance than magnetoresistive random access memory (MRAM) and resistive random access memory (ReRAM).

[0115] Furthermore, the off-state current of OS transistors hardly increases even in high-temperature environments. Specifically, the off-state current hardly increases even in ambient temperatures above room temperature and below 200°C. Furthermore, the on-state current is less likely to decrease even in high-temperature environments. Storage devices that include OS memory operate stably and with high reliability even in high-temperature environments. Furthermore, OS transistors have a high dielectric strength voltage between the source and drain. By using OS transistors as the transistors that make up 3D OS NAND, it is possible to realize information processing devices that operate stably and with high reliability even in high-temperature environments.

[0116] The memory embedded as a register in a CPU or other processing unit is frequently accessed by the processing unit because it is used to temporarily store the results of calculations. Therefore, a faster operating speed is required than a larger memory capacity. Registers also have the function of storing setting information for the processing unit.

[0117] SRAM is used, for example, in caches. Caches have the function of duplicating and storing a portion of the data stored in main memory. By duplicating frequently used data and storing it in the cache, the speed of accessing the data can be increased. The storage capacity required for caches is smaller than that of main memory, but they are required to operate at a faster speed than main memory. In addition, data rewritten in the cache is duplicated and supplied to main memory.

[0118] DRAM is used, for example, as a main memory. The main memory has the function of storing programs, data, etc. read from storage. The recording density of DRAM is approximately 0.1 to 0.3 Gbit / mm 2 is.

[0119] 3D NAND memory is used, for example, in storage. Storage has the function of storing data that needs to be stored for a long period of time, various programs used in processing units, etc. Therefore, storage requires a large memory capacity and high recording density rather than an operating speed. The recording density of memory devices used in storage is approximately 0.6 to 6.0 Gbit / mm 2 is.

[0120] An information processing device according to one embodiment of the present invention has a high operating speed and is capable of long-term data retention. The storage device included in the information processing device according to one embodiment of the present invention can be suitably used as a storage device located in a boundary area 901 that includes both a tier where a cache is located and a tier where a main memory is located. The storage device included in the information processing device according to one embodiment of the present invention can also be suitably used as a storage device located in a boundary area 902 that includes both a tier where a main memory is located and a tier where a storage is located.

[0121] Furthermore, the storage device included in the information processing device according to an embodiment of the present invention can be suitably used in both the tier where the main memory is located and the tier where the storage is located. Furthermore, the storage device included in the information processing device according to an embodiment of the present invention can be suitably used in the tier where the cache is located. Figure 8B shows various tiers of information processing devices different from those shown in Figure 8A.

[0122] 8B shows, from the top layer, a memory integrated as a register in a processing unit such as a CPU, an SRAM used as a cache, and a 3D OS NAND. The storage device included in the information processing device according to one embodiment of the present invention can be used for the cache, main memory, and storage. Note that when a high-speed memory with a speed of 1 GHz or higher is required as the cache, the cache is integrated into the processing unit such as a CPU.

[0123] Furthermore, as shown in FIG. 9, an information processing device 110 according to one embodiment of the present invention includes a circuit CPU, a circuit OSC, and a memory cell unit MCL that is a 3D OS NAND having a function as a cache memory. As shown in FIG. 9, multiple information processing devices 110 can be managed from a host 150. Each information processing device 110 has a processing function and can perform parallel writing and reading to the NAND type universal memory and the cache memory. In other words, as shown in FIG. 9, by having the host 150 manage multiple information processing devices 110, an information processing device that realizes non-von Neumann computing can be constructed.

[0124] 10A is a perspective schematic diagram showing a configuration example of an information processing device 110M according to an embodiment of the present invention. The information processing device 110M includes a layer 10, layers 20_1 to 20_t (t is an integer of 2 or more), a layer 30, and wiring EW.

[0125] The configurations of the layer 10, layers 20_1 to 20_t, layer 30, and wiring EW are shown in FIG. 1A, and detailed description thereof will be omitted.

[0126] The layer 10 and layers 20_1 to 20_t are provided with circuits that can function by utilizing semiconductor characteristics, with the layer 10 being provided with a circuit OSC, a circuit CPU, and a circuit GPU, and the layers 20_1 to 20_t being provided with a memory cell unit MCL. The layer 30 is a wiring layer in which wiring is formed. In the layer 10, the arithmetic units correspond to the circuit OSC, the circuit CPU, and the circuit GPU.

[0127] FIG. 10B is a perspective schematic diagram in which the layers 20_1 to 20_t and the wiring EW relating to the layer 20 are omitted from FIG. 10A, and shows the positional relationship between the circuit OSC, the circuit CPU, the circuit GPU, and the memory cell unit MCL.

[0128] The configurations of the circuit OSC, the circuit CPU, and the memory cell unit MCL are the same as those in the first embodiment, and detailed description thereof will be omitted.

[0129] The circuit GPU has a function of performing arithmetic processing on data to be written to the memory cell unit MCL or data read from the memory cell unit MCL. Data arithmetic processing is performed by an arithmetic circuit included in the circuit GPU. The circuit GPU is a circuit that mainly performs multiply-accumulate processing. By having a GPU, the information processing device 110M can efficiently perform inference processing based on an artificial neural network. The circuit GPU is also called an accelerator.

[0130] In addition, inference processing based on an artificial neural network is optimized for data with a bit depth of preferably 32 bits or less, more preferably 16 bits or less, and even more preferably 8 bits or less, rather than calculations using data with a large bit depth such as 64 bits, thereby achieving low power consumption without reducing calculation accuracy.

[0131] The circuit GPU, like the circuit OSC and the circuit CPU, is configured using transistors formed on the substrate SUB.

[0132] Similar to the circuit OSC and the circuit CPU, the circuit GPU and the memory cell unit MCL are electrically connected by the wiring EW and the layer 30. The wiring EW has a function of electrically connecting the circuit GPU and the layer 30, and a function of electrically connecting the memory cells included in the memory cell unit MCL and the layer 30.

[0133] The circuit GPU is electrically connected to the circuit OSC and the circuit CPU using wiring formed on the substrate SUB. The information processing device 110M has features such as a short data transfer distance between the circuit GPU and the memory cell unit MCL, which reduces signal transmission delay and enables high-speed operation, and suppresses increases in power consumption due to parasitic capacitance, etc. Furthermore, the memory cell unit MCL is provided above and overlaps the circuit GPU, which suppresses increases in the circuit area of the information processing device 110M.

[0134] In the information processing device 110M, since an increase in circuit area can be suppressed, the number of circuit GPUs can be increased and arranged. Since the number of circuits (number of cores) performing calculations in the circuit GPU can be increased, the frequency of the signal for driving the circuit GPU can be lowered. In addition, the power supply voltage for driving the circuit GPU can be reduced. As a result, the power consumption required for calculations can be reduced by a factor of several tens.

[0135] Next, a configuration example of the circuit GPU will be described below. Fig. 11A is a block diagram for explaining a configuration example of the circuit GPU.

[0136] The circuit GPU has a plurality of arithmetic circuits PE for performing calculations. As described above, the arithmetic circuit PE preferably has a circuit specialized for multiply-accumulate calculations. By using this circuit configuration, input data D is multiplied by a plurality of arithmetic circuits PE having circuits such as a multiplier circuit MULT, an adder circuit ADD, and a multiply-accumulate circuit ADD+MULT. IN Each circuit in the arithmetic circuit PE can be configured with Si transistors. IN is the data stored in the string SRG of the memory cell unit MCL. Each string SRG can be connected to one of the plurality of arithmetic circuits PE via wiring EW. The output data D obtained by the sum-of-products arithmetic process OUT may be configured to output to the circuit CPU or the memory cell unit MCL.

[0137] 11B is a perspective schematic diagram for explaining the positional relationship between the strings SRG of the memory cell unit MCL and the plurality of arithmetic circuits PE. The plurality of arithmetic circuits PE provided on the substrate SUB can be provided overlapping the strings SRG of the memory cell unit MCL via the wirings EW.

[0138] The sum-of-products operation in inference processing requires a large amount of data, which requires a huge bandwidth (data transfer rate). As shown in the configuration of Figure 11B, a wide bandwidth can be secured by placing the string SRG of the memory cell unit MCL on the arithmetic circuit PE. In addition, the distance between circuits can be shortened, which increases the transfer speed of multiple data. As a result, the power consumption required for the sum-of-products operation in inference processing can be reduced by a factor of several tens.

[0139] Furthermore, in the data processing device 110M of one embodiment of the present invention, the string SRG included in the memory cell unit MCL can be arranged on the circuit CPU and the circuit OSC, not just the circuit GPU. Therefore, as shown in the perspective schematic diagram and block diagram in FIG. 12, a wide bandwidth can be ensured not only for the circuit GPU, but also for the circuit CPU and the circuit OSC.

[0140] As described above, by combining a plurality of information processing devices 110M according to one embodiment of the present invention, the present invention can be applied to a data center or a supercomputer that can be managed from a host 150, as illustrated in FIG. 13. The information processing devices 110M are electrically connected to a switch board SWB. The information processing devices 110M can be switched by the plurality of switch boards SWB. As illustrated in FIG. 13, the plurality of information processing devices 110M can perform parallel data writing and reading in each of the information processing devices 110M. This makes it possible to realize a supercomputer that achieves low power consumption and improved calculation speed.

[0141] 13, the information processing device 110M can reduce the circuit area within the circuit GPU. Specifically, the number of information processing devices 110M, which are calculation nodes, can be reduced. Therefore, the power consumption required for transmitting and receiving data can be reduced by a factor of several tens.

[0142] In addition to reducing power consumption in the above-mentioned calculations, reducing power consumption by specializing in product-sum calculations during inference processing, and reducing power consumption by miniaturizing circuit area, by optimizing computer architecture, software, and driving methods, it is possible to reduce the power consumption of existing data centers or supercomputers by a factor of one thousand.

[0143] Note that this embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification.

[0144] (Embodiment 2) In this embodiment, a configuration example of an information processing device according to one embodiment of the present invention will be described.

[0145] 14A is a schematic perspective view showing a configuration example of an information processing device 100A according to an embodiment of the present invention. The information processing device 100A includes a layer 10, layers 20_1 to 20_t (t is an integer of 2 or more), a layer 30, a layer 40, and wiring EW.

[0146] As shown in FIG. 14A, the information processing device 100A has a structure in which a layer 20_1 is stacked above a layer 10, a layer 20_k+1 (k is an integer greater than or equal to 1 and less than or equal to t-1) is stacked above a layer 20_k, a layer 30 is stacked above a layer 20_t, and a layer 40 is stacked above a layer 30.

[0147] The configurations of the layer 10, the layers 20_1 to 20_t, the layer 30, and the wiring EW are the same as those in the first embodiment, and detailed description thereof will be omitted.

[0148] Furthermore, in the information processing device 100A, the layer 40 has a plurality of electrodes for electrical connection to a separately fabricated circuit CPU. The electrodes can be microbumps made of copper or aluminum. By using the electrodes for connection between metal electrodes, the information processing device 100A can be bonded to a substrate on which the circuit CPU has electrodes.

[0149] The layer 10 and the layers 20_1 to 20_t are provided with circuits that can function by utilizing the semiconductor characteristics, with the circuit OSC being provided in the layer 10 and the memory cell units MCL being provided in the layers 20_1 to 20_t. The layer 30 is a wiring layer in which wiring is formed.

[0150] FIG. 14B is a perspective schematic diagram in which the layers 20_1 to 20_t and the wiring EW relating to the layer 20 are omitted from FIG. 14A, and shows the positional relationship of the layer 40 including the circuit OSC, the memory cell unit MCL, and a plurality of electrodes CEL1.

[0151] The configurations of the circuit OSC and the memory cell unit MCL are the same as those in the first embodiment, and detailed description thereof will be omitted.

[0152] Next, a configuration example of the information processing device 100A including the electrode CEL1 will be described. Fig. 15A is a block diagram showing a configuration example of the information processing device 100A.

[0153] 15A, the information processing device 100A has an electrode CEL1, a circuit OSC, and a memory cell unit MCL. As described in the first embodiment, the circuit OSC has a function of performing arithmetic processing on data to be written to or read from the memory cell unit MCL. The electrode CEL1 is an electrode for retrieving data to be written to or read from the memory cell unit MCL.

[0154] 15B, a configuration example of an information processing device 200A including a circuit CPU will be described. FIG 15B is a block diagram showing a configuration example of the information processing device 200A.

[0155] 15B, the information processing device 200A has an electrode CEL2 and a circuit CPU (also referred to as a central processing unit). As described in the first embodiment, the circuit CPU has a function of performing arithmetic processing when data to be written to the memory cell unit MCL or data read from the memory cell unit MCL is provided via the electrode CEL2. The electrode CEL2 is an electrode for retrieving data via the electrode CEL1 of the information processing device 100A.

[0156] The information processing device 100A of this embodiment shown in Fig. 15A is used in combination with the information processing device 200A shown in Fig. 15B. Specifically, as shown in Fig. 15C, the electrode CEL1 and the electrode CEL2 are bonded together (the position indicated by the arrow in Fig. 15C), thereby providing an information processing device 300A with reduced power consumption.

[0157] Note that this embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification.

[0158] (Embodiment 3) In this embodiment, a configuration example of the transistors constituting the information processing device 100 described in the above embodiment will be described. Fig. 16 shows a cross-sectional configuration example of the layer 10 and the layer 20. In this embodiment, a single crystal silicon substrate is used for the substrate SUB, and the layer 20 is a configuration example of 3D OS NAND.

[0159] In layer 10 shown in FIG. 16, a transistor 300 is provided on a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 made of part of the substrate 311, a low-resistance region 314a functioning as a source region or a drain region, and a low-resistance region 314b.

[0160] In the transistor 300, the top surface and the side surfaces in the channel width direction of the semiconductor region 313 are covered with a conductor 316 via an insulator 315. By forming the transistor 300 as a fin type in this way, the effective channel width is increased, thereby improving the on-state characteristics of the transistor 300. Furthermore, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 300.

[0161] The transistor 300 may be either a p-channel type or an n-channel type.

[0162] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low-resistance region 314a that serves as the source region or drain region, and the low-resistance region 314b preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single-crystal silicon. Alternatively, they may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaN (gallium nitride), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, or the like.

[0163] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0164] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, metal material, alloy material, or metal oxide material, such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0165] Since the work function is determined by the conductor material, the Vth of the transistor can be adjusted by changing the conductor material. Specifically, it is preferable to use materials such as titanium nitride and tantalum nitride for the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use metal materials such as tungsten and aluminum as the conductor in a laminated form, and tungsten is particularly preferable in terms of heat resistance.

[0166] Note that the transistor 300 illustrated in FIG. 16 is just an example, and the structure is not limited to this, and an appropriate transistor may be used depending on the circuit configuration or driving method.

[0167] An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order over the transistor 300.

[0168] The insulators 320, 322, 324, and 326 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.

[0169] The insulator 322 may function as a planarizing film that flattens steps caused by the transistor 300 or the like provided thereunder. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve flatness.

[0170] The insulator 324 is preferably a film having a barrier property that prevents hydrogen and / or impurities from diffusing from the substrate 311 or the transistor 300 to the layer 20 .

[0171] An example of a film having barrier properties against hydrogen is silicon nitride formed by CVD. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor of layer 20 may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between layer 20 and layer 10. Specifically, a film that suppresses hydrogen diffusion is a film that desorbs a small amount of hydrogen.

[0172] The amount of desorbed hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS) analysis. For example, the amount of desorbed hydrogen from the insulator 324 is calculated as 10×10 per area of the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in TDS analysis. 15 atoms / cm 2 Less than or equal to 5 x 10 15 atoms / cm 2 The following is fine.

[0173] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low relative dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0174] Conductors 328, 330, and the like are embedded in insulators 320, 322, 324, and 326. Conductors 328 and 330 function as plugs or wiring. Conductors that function as plugs or wiring may be collectively designated by the same reference numeral. In this specification, the wiring and the plug connecting to the wiring may be integral. That is, a portion of the conductor may function as the wiring, and a portion of the conductor may function as the plug.

[0175] The materials for each plug and wiring (such as the conductor 328 and the conductor 330) can be a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, and can be used in a single layer or a laminated layer. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and conductivity, are preferably used, and tungsten is preferred. Alternatively, they are preferably formed from a low-resistance conductive material such as aluminum or copper. The use of a low-resistance conductive material can reduce the wiring resistance.

[0176] 16, a wiring layer may be provided on the insulator 326 and the conductor 330. For example, it is preferable to provide an insulator having a barrier property against hydrogen, similar to the insulator 324, on the insulator 326 and the conductor 330, and to form a conductor having a barrier property against hydrogen on the insulator. By forming a conductor having a barrier property against hydrogen in an opening of the insulator having a barrier property against hydrogen, the layer 20 and the layer 10 can be separated by the barrier layer, and diffusion of hydrogen from the layer 10 to the layer 20 can be suppressed.

[0177] As a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like can be used. Furthermore, by stacking tantalum nitride and highly conductive tungsten, the diffusion of hydrogen from the transistor 300 can be suppressed while maintaining the conductivity of the wiring. In this case, a structure in which the tantalum nitride layer having a barrier property against hydrogen is in contact with an insulator having a barrier property against hydrogen is preferable. Note that in FIG. 16, an insulator 350 having a barrier property against hydrogen is provided on the insulator 326 and the conductor 330.

[0178] In the layer 20 shown in FIG. 16, the storage element included in the three-dimensional NAND memory element has, as an example, a transistor RTr, a transistor WTr, and a capacitance CS.

[0179] 16 is provided above the layer 10. The layer 20 includes, above the layer 10, insulators 211 to 215, insulators 240 to 242, conductors 221, 222, conductors 250 to 252, semiconductors 231, and semiconductors 232.

[0180] The insulator 240 is provided above the layer 10. For this reason, the insulator 350 located below the insulator 240 is preferably formed by a film formation method that provides good flatness. Also, it is preferable that the insulator 350 has been subjected to CMP processing.

[0181] For example, a material containing silicon oxide or silicon oxynitride can be used as the insulator 240. Also, for example, an insulator containing a material selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, tantalum, etc. can be used in a single layer or a stacked layer.

[0182] The insulator 241 is provided by being laminated on the insulator 240. As the insulator 241, for example, a material that can be used for the insulator 240 can be used.

[0183] Furthermore, a conductor 250 is embedded in the insulator 240, and a conductor 251 is embedded in the insulator 241. The conductors 250 and 251 function as plugs or wiring. Furthermore, for the conductors that function as plugs or wiring shown in FIG. 16, multiple structures may be collectively assigned the same reference numeral. Furthermore, in this specification, the wiring and the plug that connects to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0184] The conductor 250 and the conductor 251 can be made of, for example, a material that can be used for the conductor 328 and the conductor 330 .

[0185] The insulator 211 is provided on the insulator 241. The conductor 221 is provided on the insulator 211. The insulator 212 is provided on the conductor 221. The conductor 222 is provided on the insulator 212. That is, the insulator 211, the conductor 221, the insulator 212, and the conductor 222 are stacked in this order (these are referred to as a stack). The layer 20 shown in FIG. 16 has as many stacks as there are memory elements included in one string.

[0186] 16 , openings are provided in the insulator 211, the conductor 221, the insulator 212, and the conductor 222 by forming a resist mask, etching, or the like. At this time, the conductor 221 is selectively removed so that a recess is formed by the insulator 211, the conductor 221, and the insulator 212. In this case, the conductor 221 is preferably made of a material that has a higher etching rate than the insulator 211, the insulator 212, and the conductor 222.

[0187] The resist mask can be formed by, for example, lithography, printing, inkjet printing, or the like. When the resist mask is formed by the inkjet printing, a photomask is not used, and therefore the manufacturing cost can be reduced. The etching process may be a dry etching process, a wet etching process, or both.

[0188] In the opening formed by the etching process, an insulator 213, a semiconductor 231, an insulator 214, an insulator 215, a semiconductor 232, an insulator 216, and a conductor 223 are formed in this order.

[0189] As one example, it is preferable to use a film having a barrier property that prevents diffusion of hydrogen and / or impurities as the insulators 211 and 212. Therefore, for example, the same material as the insulator 240 can be used as the insulators 211 and 212.

[0190] For the conductor 221 and the conductor 222, it is preferable to use, for example, a material that can be applied to the conductor 251. In particular, for the conductor 221 and the conductor 222, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water or hydrogen.

[0191] On the side surface of the opening formed by the etching process described above, an insulator 213 and a semiconductor 231 are formed in this order. Also, an insulator 214 is formed so as to fill the recess of the opening.

[0192] As a method for forming the insulator 214, for example, first, the insulator 214 is formed on the side surface of the opening to the extent that the recess of the opening is filled, and then a portion of the insulator 214 is removed by etching so that the insulator 214 remains in the recess and the semiconductor 231 is exposed.

[0193] The insulator 213 can be, for example, silicon oxide or silicon oxynitride. Alternatively, the insulator 213 can be, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium. Alternatively, the insulator 213 can be an insulator formed by stacking these materials.

[0194] It is preferable to use a metal oxide as the semiconductor 231. For example, a metal oxide such as In-M-Zn oxide (wherein the element M is one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, tin, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used as the semiconductor 231. Alternatively, an In-Ga oxide or an In-Zn oxide may be used as the semiconductor 231. In the present embodiment, it is assumed hereinafter that a metal oxide is used as the semiconductor 231.

[0195] Furthermore, before forming the insulator 214, the formed semiconductor 231 can be subjected to heat treatment in an oxygen atmosphere, thereby supplying oxygen to the metal oxide of the semiconductor 231. Then, after forming the insulator 214, a process of supplying impurities or the like to the metal oxide of the semiconductor 231 can be performed, thereby reducing the resistance of the region exposed to the opening of the semiconductor 231. In other words, the region of the semiconductor 231 in contact with the insulator 214 becomes a high-resistance region, and the region of the semiconductor 231 not in contact with the insulator 214 becomes a low-resistance region.

[0196] Furthermore, examples of the process of supplying impurities and the like to the metal oxide of the semiconductor 231 include forming a conductor on the side surface of the opening after filling the recess of the opening with the insulator 214, and then removing the conductor. When the conductive film comes into contact with the metal oxide of the semiconductor 231, metal elements contained in the conductive film may diffuse into the semiconductor 231 and form a metal compound with the constituent elements of the semiconductor 231. This metal compound forms a low-resistance region in the semiconductor 231.

[0197] The insulator 214 is preferably not a component that forms a compound with a component contained in the semiconductor 231 at or near the interface with the previously formed semiconductor 231. Specifically, for example, silicon oxide or the like can be used as the insulator 214.

[0198] Thereafter, an insulator 215, a semiconductor 232, an insulator 216, and a conductor 223 are formed in this order on the surfaces on which the insulators 213 and 214 have been formed. Note that the formation of the conductor 223 is assumed to fill the openings provided in the stacked body.

[0199] For the insulators 215 and 216, it is preferable to use, for example, a material that can be used for the insulator 213.

[0200] As the semiconductor 232, it is preferable to use, for example, a metal oxide described in Embodiment 5, similar to the semiconductor 231. In particular, it is preferable to use a CAAC-OS, which will be described later, as the metal oxide. For example, when polycrystalline silicon is used for the semiconductor 231 and the semiconductor 232, crystal grain boundaries that may be formed in the polycrystalline silicon may increase the electron trap density, which may result in significant variations in transistor characteristics. On the other hand, since no clear crystal grain boundaries are observed in the CAAC-OS, it is possible to suppress variations in transistor characteristics.

[0201] For the conductor 223, it is preferable to use, for example, a material that can be used for the conductor 251. In particular, it is preferable to use, for the conductor 223, a conductive material that has a function of suppressing the permeation of impurities such as water or hydrogen.

[0202] An insulator 242 is provided on the top of the formed string. For the insulator 242, for example, a material that can be used for the insulator 240 can be used.

[0203] Furthermore, a conductor 252 is embedded in the insulator 242. The conductor 252 functions as a plug or wiring. For example, a material applicable to the conductors 328 and 330 can be used as the conductor 252. Furthermore, a conductor 386 is embedded in the insulators 382 and 384. For example, a material applicable to the insulator 240 can be used as the insulator 382 and 384. The conductor 386 functions as a plug or wiring. For example, a material applicable to the conductors 328 and 330 can be used as the conductor 386.

[0204] The wiring WL shown in FIG. 2 corresponds to the conductor 221 and the conductor 222, and the conductor 221 is used when writing data, and the conductor 222 is used when reading data.

[0205] Therefore, a capacitor CS is formed in which the conductor 222 serves as one electrode, the region of the insulator 213 in contact with the conductor 222 serves as a dielectric, and the region of the semiconductor 231 overlapping with the conductor 222 serves as the other electrode. A transistor RTr is formed in which the region of the semiconductor 231 overlapping with the conductor 222 serves as a gate, the region of the insulator 215 overlapping with the conductor 222 serves as a gate insulating film, the region of the semiconductor 232 overlapping with the conductor 222 serves as a channel formation region, the region of the insulator 216 overlapping with the conductor 222 serves as a gate insulating film, and the region of the conductor 223 overlapping with the conductor 222 serves as a back gate. A transistor WTr is formed in which the conductor 221 serves as a gate, the insulator 213 overlapping with the conductor 221 serves as a gate insulating film, and the region of the semiconductor 231 overlapping with the conductor 221 serves as a channel formation region.

[0206] The insulators, conductors, semiconductors, and the like disclosed in this specification can be formed by PVD (Physical Vapor Deposition) or CVD (Chemical Vapor Deposition). Examples of PVD include sputtering, resistance heating evaporation, electron beam evaporation, and PLD (Pulsed Laser Deposition). Examples of CVD include plasma CVD and thermal CVD. Examples of thermal CVD include MOCVD (Metal Organic Chemical Vapor Deposition) and ALD (Atomic Layer Deposition).

[0207] Thermal CVD is a film formation method that does not use plasma, and therefore has the advantage of not generating defects due to plasma damage. Thermal CVD may be performed by simultaneously feeding source gas and oxidizing agent into a chamber, setting the chamber at atmospheric or reduced pressure, and causing a reaction near or on the substrate, resulting in deposition on the substrate.

[0208] Alternatively, the ALD method may be used to deposit a film by sequentially introducing source gases into a chamber under atmospheric or reduced pressure and repeating this gas introduction sequence. For example, two or more source gases may be sequentially supplied to the chamber by switching between switching valves (also called high-speed valves). To prevent mixing of the multiple source gases, an inert gas (e.g., argon or nitrogen) may be introduced simultaneously with or after the first source gas, followed by the second source gas. When an inert gas is introduced simultaneously, the inert gas acts as a carrier gas, and may also be introduced simultaneously with the introduction of the second source gas. Alternatively, instead of introducing an inert gas, the first source gas may be evacuated by vacuum evacuation before the second source gas is introduced. The first source gas adsorbs onto the substrate surface to form a first thin layer, which then reacts with the second source gas introduced later, forming a thin film. Repeating this gas introduction sequence multiple times until the desired thickness is achieved allows for the formation of a thin film with excellent step coverage. The thickness of the thin film can be adjusted by changing the number of times the gas introduction sequence is repeated, allowing for precise film thickness adjustment, making this method suitable for fabricating fine FETs.

[0209] Thermal CVD methods such as MOCVD and ALD can form various films, including metal films, semiconductor films, and inorganic insulating films, as disclosed in the embodiments described above. For example, when forming an In-Ga-Zn-O film, trimethylindium (In(CH3)3), trimethylgallium (Ga(CH3)3), and dimethylzinc (Zn(CH3)2) are used. Furthermore, the combinations are not limited to these, and triethylgallium (Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (Zn(C2H5)2) can be used instead of dimethylzinc.

[0210] For example, when forming a hafnium oxide film using a film formation system that uses ALD, two types of gases are used: a source gas made by vaporizing a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide, hafnium amide such as tetrakisdimethylamidohafnium (TDMAH, Hf[N(CH3)2]4)), and ozone (O3) as an oxidizer. Other materials include tetrakis(ethylmethylamido)hafnium.

[0211] For example, when forming an aluminum oxide film using a film formation system that uses ALD, two types of gases are used: a source gas made by vaporizing a liquid containing a solvent and an aluminum precursor compound (such as trimethylaluminum (TMA, Al(CH3)3)), and H2O as an oxidizer. Other materials include tris(dimethylamido)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate).

[0212] For example, when forming a silicon oxide film using a film formation apparatus that uses ALD, hexachlorodisilane is adsorbed onto the surface to be filmed, and radicals of oxidizing gas (O2, dinitrogen monoxide) are supplied to react with the adsorbed material.

[0213] For example, when forming a tungsten film using an ALD deposition system, WF6 gas and B2H6 gas are introduced in sequence and repeatedly to form an initial tungsten film, and then WF6 gas and H2 gas are introduced in sequence and repeatedly to form the tungsten film. Note that SiH4 gas may be used instead of B2H6 gas.

[0214] For example, when forming an oxide semiconductor film, such as an In-Ga-Zn-O film, using a film formation system using ALD, In(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form an In-O layer, then Ga(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form a GaO layer, and then Zn(CH3)2 gas and O3 gas are sequentially and repeatedly introduced to form a ZnO layer. Note that the order of these layers is not limited to this example. Mixed oxide layers such as In-Ga-O layers, In-Zn-O layers, and Ga-Zn-O layers may also be formed using these gases. While HO gas obtained by bubbling water with an inert gas such as Ar may be used instead of O3 gas, it is preferable to use O3 gas that does not contain H. Furthermore, In(CH3)3 gas may be replaced with In(C2H5)3 gas. Furthermore, Ga(CH3)3 gas may be replaced with Ga(C2H5)3 gas. Furthermore, Zn(CH3)2 gas may also be used. Although the above description has been given of a film formation apparatus that uses ALD as an example of a thermal CVD method, the present invention is not limited to this and may be a film formation apparatus that uses plasma-enhanced ALD (PEALD).

[0215] By using this structure, in a data processing device having an OS transistor, fluctuations in electrical characteristics can be suppressed and reliability can be improved. Alternatively, an OS transistor with a large on-state current can be provided. Alternatively, an OS transistor with a small off-state current can be provided. Alternatively, miniaturization or high integration can be achieved in a data processing device having an OS transistor.

[0216] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0217] (Fourth embodiment) In this embodiment, an example of operation will be described when part of the calculations of a program executed by the circuit CPU (hereinafter also referred to as the CPU) described in the above embodiment is executed by a circuit GPU (hereinafter also referred to as the GPU or accelerator).

[0218] FIG. 17 is a diagram illustrating an example of an operation when part of the calculations of a program executed by a CPU is executed by an accelerator.

[0219] The host program is executed by the CPU (step S1).

[0220] When the CPU confirms an instruction to reserve a data area required for performing calculations using the accelerator in the memory unit (step S2), the CPU reserves the data area in the memory unit (step S3).

[0221] Next, the CPU transmits input data from the main memory to the memory unit (step S4). The memory unit receives the input data and stores the input data in the area secured in step S2 (step S5).

[0222] When the CPU confirms the instruction to start the kernel program (step S6), the accelerator starts executing the kernel program (step S7).

[0223] Immediately after the accelerator starts executing the kernel program, the CPU may be switched from a state performing calculations to a PG (power gating) state (step S8). In this case, the CPU is switched from the PG state to a state performing calculations immediately before the accelerator finishes executing the kernel program (step S9). By keeping the CPU in the PG state during the period from step S8 to step S9, power consumption and heat generation of the entire semiconductor device can be suppressed.

[0224] When the accelerator finishes executing the kernel program, the output data is stored in the memory unit (step S10).

[0225] After the execution of the kernel program is completed, if the CPU confirms an instruction to send the output data stored in the memory unit to the main memory (step S11), the output data is sent to the main memory and stored in the main memory (step S12).

[0226] When the CPU confirms an instruction to release the data area secured on the memory unit (step S13), the area secured on the memory unit is released (step S14).

[0227] By repeating the above operations from step S1 to step S14, it is possible to suppress the power consumption and heat generation of the CPU and accelerator, while allowing the accelerator to execute part of the calculations of the program executed by the CPU.

[0228] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0229] (Embodiment 5) In this embodiment, a moving object to which the information processing device 100 described in the above embodiment can be applied will be described with reference to FIG.

[0230] Fig. 18A shows an external view of an automobile as an example of a moving body. Fig. 18B is a simplified diagram of data exchange within the automobile. The automobile 790 has a plurality of cameras 791 and the like. The automobile 790 also has various sensors (not shown) such as infrared radar, millimeter-wave radar, and laser radar.

[0231] In the automobile 790, an integrated circuit 690 to which the information processing device 100 described in the first embodiment can be applied can be used for a camera 791, etc. In the automobile 790, a plurality of images acquired by the camera 791 in a plurality of imaging directions 792 are processed by the integrated circuit 690 to which the information processing device 100 described in the first embodiment can be applied, and the plurality of images are analyzed collectively by a host controller 694, etc. via a bus 693, etc., to determine surrounding traffic conditions such as the presence or absence of guardrails and pedestrians, thereby enabling autonomous driving. The automobile 790 can also be used in systems that provide road guidance, hazard prediction, etc.

[0232] In the integrated circuit 690, the obtained image data is subjected to arithmetic processing such as neural networks, making it possible to perform processes such as increasing the image resolution, reducing image noise, facial recognition (for security purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reducing reflected glare.

[0233] Although an automobile is described above as an example of a moving body, the moving body is not limited to an automobile. For example, moving bodies may include trains, monorails, ships, and flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets). A computer according to one embodiment of the present invention may be applied to these moving bodies to provide a system using artificial intelligence.

[0234] (Sixth embodiment) In this embodiment, an example of a semiconductor wafer on which the information processing device or the like shown in the above embodiment is formed, and an example of an electronic component in which the information processing device is incorporated will be described.

[0235] First, an example of a semiconductor wafer on which an information processing device or the like is formed will be described with reference to FIG. 19A.

[0236] 19A includes a wafer 4801 and a plurality of circuit portions 4802 provided on the upper surface of the wafer 4801. Note that on the upper surface of the wafer 4801, a portion where the circuit portions 4802 are not present is a spacing 4803, which is a region for dicing.

[0237] The semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 in a previous process. After that, the surface of the wafer 4801 opposite to the surface on which the plurality of circuit portions 4802 are formed may be ground to thin the wafer 4801. This process reduces warping of the wafer 4801 and allows for miniaturization of the component.

[0238] The next step is the dicing process. Dicing is performed along scribe lines SCL1 and SCL2 (sometimes called dicing lines or cutting lines) indicated by dashed lines. To facilitate the dicing process, spacing 4803 is preferably arranged so that multiple scribe lines SCL1 are parallel to each other, multiple scribe lines SCL2 are parallel to each other, and scribe lines SCL1 and SCL2 are perpendicular to each other.

[0239] By performing a dicing process, chips 4800a as shown in FIG. 19B can be cut out from semiconductor wafer 4800. Chip 4800a has wafer 4801a, circuit portion 4802, and spacing 4803a. It is preferable to make spacing 4803a as small as possible. In this case, it is sufficient that the width of spacing 4803 between adjacent circuit portions 4802 is approximately the same length as the cutting margin of scribe line SCL1 or the cutting margin of scribe line SCL2.

[0240] Note that the shape of the element substrate of one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in Figure 19A. For example, the semiconductor wafer may have a rectangular shape. The shape of the element substrate can be changed as appropriate depending on the manufacturing process and the apparatus for manufacturing the element.

[0241] 19C is a perspective view of an electronic component 4700 and a substrate (mounting substrate 4704) on which the electronic component 4700 is mounted. The electronic component 4700 shown in FIG. 19C includes a chip 4800a in a mold 4711. A data processing device according to one embodiment of the present invention or the like can be used as the chip 4800a.

[0242] 19C omits some parts to show the interior of electronic component 4700. Electronic component 4700 has lands 4712 on the outside of mold 4711. Lands 4712 are electrically connected to electrode pads 4713, and electrode pads 4713 are electrically connected to chip 4800a via wires 4714. Electronic component 4700 is mounted on, for example, a printed circuit board 4702. A plurality of such electronic components are combined and electrically connected on printed circuit board 4702 to complete mounted board 4704.

[0243] 19D shows a perspective view of electronic component 4730. Electronic component 4730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). Electronic component 4730 has an interposer 4731 provided on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and multiple information processing devices 4710 provided on interposer 4731.

[0244] The information processing device 4710 may be, for example, a chip 4800a, the information processing device described in the above embodiment, or a high bandwidth memory (HBM). The semiconductor device 4735 may be an integrated circuit such as a CPU, a GPU, an FPGA, or a memory device. In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics.

[0245] A ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used for the package substrate 4732. A silicon interposer, a resin interposer, or the like can be used for the interposer 4731.

[0246] The interposer 4731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 4731 also functions to electrically connect the integrated circuits provided on the interposer 4731 to electrodes provided on the package substrate 4732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 4731, and the integrated circuits and the package substrate 4732 are electrically connected using the through electrodes. In addition, in a silicon interposer, TSVs (Through Silicon Vias) can also be used as through electrodes.

[0247] It is preferable to use a silicon interposer as the interposer 4731. Since a silicon interposer does not require an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of a silicon interposer can be formed using a semiconductor process, it is easy to form fine wiring that is difficult to form with a resin interposer.

[0248] HBM requires many interconnects to achieve a wide memory bandwidth. Therefore, the interposer that implements HBM requires fine and high-density interconnects. Therefore, it is preferable to use a silicon interposer for implementing HBM.

[0249] Furthermore, SiP, MCM, etc. that use silicon interposers are less likely to experience a decrease in reliability due to differences in the expansion coefficient between the integrated circuit and the interposer. Furthermore, because the silicon interposer has a highly flat surface, poor connections between the integrated circuit mounted on the silicon interposer and the silicon interposer are less likely to occur. Silicon interposers are particularly preferable for 2.5D packages (2.5-dimensional packaging), which place multiple integrated circuits side-by-side on an interposer.

[0250] A heat sink (heat sink) may be provided overlapping the electronic component 4730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 4731. For example, in the electronic component 4730 shown in this embodiment, it is preferable to align the height of the data processing device 4710 and the height of the semiconductor device 4735.

[0251] In order to mount electronic component 4730 on another substrate, electrodes 4733 may be provided on the bottom of package substrate 4732. Fig. 19D shows an example in which electrodes 4733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 4732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 4733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 4732, PGA (Pin Grid Array) mounting can be achieved.

[0252] The electronic component 4730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), or a quad flat non-leaded package (QFN).

[0253] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0254] (Embodiment 7) In this embodiment, an application example of an information processing device according to one embodiment of the present invention will be described.

[0255] An information processing device according to one embodiment of the present invention can be applied to, for example, various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital still cameras, video cameras, recording / playback devices, navigation systems, game consoles, etc.). It can also be used in image sensors, IoT (Internet of Things) terminal devices, healthcare, etc. Note that the term "computer" as used herein includes tablet computers, notebook computers, desktop computers, and large-scale computers such as server systems.

[0256] 20A to 20J and 21A to 21E illustrate examples of electronic devices including a memory device according to one embodiment of the present invention, each of which includes an electronic component 4700 or an electronic component 4730 including the data processing device.

[0257] 20A is a mobile phone (smartphone), which is one type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As input interfaces, a touch panel is provided on the display unit 5511 and buttons are provided on the housing 5510.

[0258] The information terminal 5500, by applying the information processing device according to one embodiment of the present invention, can hold temporary files (for example, caches when using a web browser) generated when an application is executed.

[0259] 20B illustrates an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, operation switches 5903 and 5904, a band 5905, and the like.

[0260] Like the information terminal 5500 described above, the wearable terminal can store temporary files generated when an application is executed by applying an information processing device according to one embodiment of the present invention.

[0261] 20C shows a desktop information terminal 5300. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display unit 5302, and a keyboard 5303.

[0262] Like the information terminal 5500 described above, the desktop information terminal 5300 can store temporary files generated when an application is executed by applying an information processing device according to one embodiment of the present invention.

[0263] 20A to 20C are taken as examples of electronic devices, but information terminals other than smartphones, wearable terminals, and desktop information terminals can also be applied. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0264] 20D also illustrates an electric refrigerator-freezer 5800 as an example of an electrical appliance. Electric refrigerator-freezer 5800 has a housing 5801, a refrigerator compartment door 5802, a freezer compartment door 5803, etc. For example, electric refrigerator-freezer 5800 is an IoT-compatible electric refrigerator-freezer.

[0265] An information processing device according to one embodiment of the present invention can be applied to the electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 can transmit and receive information such as food ingredients stored in the electric refrigerator-freezer 5800 and expiration dates of the food ingredients to an information terminal or the like via the Internet. The electric refrigerator-freezer 5800 can store a temporary file generated when transmitting the information in a storage device included in the information processing device.

[0266] In this example, an electric refrigerator-freezer has been described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0267] 20E illustrates a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0268] FIG. 20F further illustrates a stationary game console 7500, which is an example of a game console. The stationary game console 7500 includes a main unit 7520 and a controller 7522. The controller 7522 can be connected to the main unit 7520 wirelessly or via a cable. Although not shown in FIG. 20F, the controller 7522 can include a display unit that displays game images, a touch panel that serves as an input interface other than buttons, a stick, a rotary knob, a sliding knob, or the like. The shape of the controller 7522 is not limited to the shape shown in FIG. 20F, and the shape of the controller 7522 may be modified in various ways depending on the genre of the game. For example, in a shooting game such as an FPS (First Person Shooter), a controller shaped like a gun with a trigger as a button can be used. In a music game, for example, a controller shaped like a musical instrument or musical equipment can be used. Furthermore, the stationary game console may not use a controller, but may instead be equipped with a camera, depth sensor, microphone, etc., and be operated by the game player's gestures and / or voice.

[0269] Furthermore, the images of the above-mentioned game machine can be output by a display device such as a television device, a display for a personal computer, a game display, or a head-mounted display.

[0270] A low-power portable game machine 5200 or a low-power stationary game machine 7500 can be realized by applying the information processing device described in the above embodiment to the portable game machine 5200 or the stationary game machine 7500. Furthermore, low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0271] Furthermore, by applying the information processing device described in the above embodiment to the portable game console 5200 or the stationary game console 7500, temporary files and the like required for calculations that occur during game execution can be stored.

[0272] 20E shows a portable game machine as an example of a game machine. Also, FIG. 20F shows a home-use stationary game machine. Note that the electronic device of one embodiment of the present invention is not limited to this. Examples of the electronic device of one embodiment of the present invention include an arcade game machine installed in an entertainment facility (such as an arcade or amusement park) and a pitching machine for batting practice installed in a sports facility.

[0273] The information processing device described in the above embodiment can be applied to a vehicle, which is a moving body, and to the vicinity of the driver's seat of the vehicle.

[0274] FIG. 20G illustrates an automobile 5700 as an example of a moving object.

[0275] An instrument panel that provides various information by displaying a speedometer, tachometer, mileage, fuel gauge, gear status, air conditioning settings, etc. may be provided around the driver's seat of the automobile 5700. A display device that shows this information may also be provided around the driver's seat.

[0276] In particular, the display device can compensate for the view obstructed by pillars and the blind spot of the driver's seat by displaying an image from an imaging device (not shown) provided on the automobile 5700, thereby improving safety. That is, by displaying an image from an imaging device provided on the outside of the automobile 5700, it is possible to compensate for the blind spot and improve safety.

[0277] The information processing device described in the above embodiment can temporarily store information, and therefore, for example, the information processing device can be used to temporarily store information required in an automatic driving system for the automobile 5700, a system that provides road guidance, hazard prediction, and the like. The display device may be configured to display temporary information such as road guidance and hazard prediction. In addition, the display device may be configured to store video from a driving recorder installed in the automobile 5700.

[0278] Although an automobile is described above as an example of a moving body, the moving body is not limited to an automobile. For example, moving bodies can include trains, monorails, ships, and flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets).

[0279] The information processing device described in the above embodiment can be applied to a camera.

[0280] 20H shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, operation switches 6243, a shutter button 6244, etc., and is also equipped with a detachable lens 6246. Note that, although the digital camera 6240 is configured such that the lens 6246 can be detached from the housing 6241 and replaced, the lens 6246 and the housing 6241 may be integrated. The digital camera 6240 may also be configured such that a strobe device, a viewfinder, etc. can be separately attached.

[0281] A low-power digital camera 6240 can be realized by applying the information processing device described in the above embodiment to the digital camera 6240. Furthermore, low power consumption can reduce heat generation from the circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0282] The information processing device described in the above embodiment can be applied to a video camera.

[0283] 20I shows a video camera 6300, which is an example of an imaging device. The video camera 6300 has a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, and the like. The operation switch 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0284] When recording video captured by the video camera 6300, it is necessary to encode the video according to the data recording format. By using the information processing device described above, the video camera 6300 can store temporary files generated during encoding.

[0285] The information processing device described in the above embodiment can be applied to an implantable cardioverter defibrillator (ICD).

[0286] 20J is a cross-sectional schematic diagram showing an example of an ICD. ICD main body 5400 has at least a battery 5401, electronic components 4700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0287] The ICD body 5400 is surgically placed in the body, and the two wires are passed through the subclavian vein 5405 and superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0288] The ICD main body 5400 functions as a pacemaker and paces the heart when the heart rate falls outside a specified range. If the heart rate does not improve with pacing (fast ventricular tachycardia, ventricular fibrillation, etc.), treatment with an electric shock is administered.

[0289] The ICD main body 5400 must constantly monitor the heart rate in order to properly perform pacing and administer electric shocks. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. The ICD main body 5400 can also store in the electronic component 4700 heart rate data acquired by the sensor, the number of pacing treatments performed, the duration, and so on.

[0290] Furthermore, the antenna 5404 can receive power, which is then charged into the battery 5401. Furthermore, the ICD main body 5400 can improve safety by having multiple batteries. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can continue to function, so the ICD main body 5400 can also function as an auxiliary power source.

[0291] In addition to the antenna 5404 that can receive power, an antenna that can transmit physiological signals may be provided, and a system for monitoring cardiac activity may be configured in which physiological signals such as pulse rate, respiratory rate, heart rate, and body temperature can be confirmed on an external monitor device.

[0292] The information processing device described in the above embodiment can be applied to computers such as PCs and extended devices for information terminals.

[0293] Figure 21A shows an example of such an expansion device: a portable expansion device 6100 that is external to a PC and equipped with a chip capable of storing information. The expansion device 6100 can store information using the chip by connecting to a PC via, for example, a USB (Universal Serial Bus). Note that while Figure 21A shows a portable expansion device 6100, the expansion device according to one aspect of the present invention is not limited to this; for example, it may be a relatively large expansion device equipped with a cooling fan or the like.

[0294] The expansion device 6100 has a housing 6101, a cap 6102, a USB connector 6103, and a board 6104. The board 6104 is housed in the housing 6101. The board 6104 is provided with circuits that drive the information processing device described in the above embodiment. For example, the board 6104 is equipped with an electronic component 4700 and a controller chip 6106. The USB connector 6103 functions as an interface for connecting to an external device.

[0295] The information processing device described in the above embodiment can be applied to an SD card that can be attached to electronic devices such as information terminals and digital cameras.

[0296] FIG. 21B is a schematic diagram of the external appearance of an SD card, and FIG. 21C is a schematic diagram of the internal structure of the SD card. The SD card 5110 has a housing 5111, a connector 5112, and a board 5113. The connector 5112 functions as an interface for connecting to an external device. The board 5113 is housed in the housing 5111. An information processing device is provided on the board 5113. For example, an electronic component 4700 and a controller chip 5115 are attached to the board 5113. Note that the circuit configurations of the electronic component 4700 and the controller chip 5115 are not limited to those described above, and the circuit configurations may be changed as appropriate depending on the situation. For example, the write circuit, row driver, read circuit, and the like provided in the electronic component may be incorporated into the controller chip 5115 rather than the electronic component 4700.

[0297] The capacity of the SD card 5110 can be increased by providing the electronic component 4700 also on the back side of the substrate 5113. A wireless chip with a wireless communication function may be provided on the substrate 5113. This allows wireless communication between an external device and the SD card 5110, and enables reading and writing of data from and to the electronic component 4700.

[0298] The information processing device described in the above embodiment can be applied to an SSD that can be attached to electronic devices such as information terminals.

[0299] FIG. 21D is a schematic diagram of the external appearance of an SSD, and FIG. 21E is a schematic diagram of the internal structure of the SSD. The SSD 5150 has a housing 5151, a connector 5152, and a board 5153. The connector 5152 functions as an interface for connecting to an external device. The board 5153 is housed in the housing 5151. An information processing device is provided on the board 5153. For example, an electronic component 4700, a memory chip 5155, and a controller chip 5156 are attached to the board 5153. The capacity of the SSD 5150 can be increased by providing an electronic component 4700 on the back side of the board 5153 as well. A work memory is incorporated in the memory chip 5155. For example, a DRAM chip may be used for the memory chip 5155. A processor, an ECC circuit, etc. are incorporated in the controller chip 5156. The circuit configurations of the electronic component 4700, the memory chip 5155, and the controller chip 5156 are not limited to those described above, and may be changed as appropriate depending on the situation. For example, the controller chip 5156 may also be provided with a memory that functions as a work memory.

[0300] 22A is an example of a large-scale computer. The computer 5600 has a rack 5610 housing a plurality of rack-mounted computers 5620. The computer 5600 may also be called a supercomputer.

[0301] Computer 5620 can have the configuration shown in the perspective view of Fig. 22B, for example. In Fig. 22B, computer 5620 has motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. PC card 5621 is inserted into slot 5631. In addition, PC card 5621 has connection terminal 5623, connection terminal 5624, and connection terminal 5625, which are each connected to motherboard 5630.

[0302] PC card 5621 shown in FIG. 22C is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. PC card 5621 includes board 5622. Board 5622 includes connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that FIG. 22C illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for these semiconductor devices, the following descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 may be referred to.

[0303] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of a motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0304] Connection terminals 5623, 5624, and 5625 can be interfaces for supplying power to PC card 5621, inputting signals, and the like. They can also be interfaces for outputting signals calculated by PC card 5621, and the like. Examples of standards for connection terminals 5623, 5624, and 5625 include USB, SATA (Serial ATA), and SCSI (Small Computer System Interface). Examples of standards for outputting video signals from connection terminals 5623, 5624, and 5625 include HDMI (registered trademark).

[0305] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0306] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA (Field Programmable Gate Array), a GPU, and a CPU. For example, the electronic component 4730 can be used as the semiconductor device 5627.

[0307] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring on the board 5622. The semiconductor device 5628 can be, for example, a memory device. The electronic component 4700 can be used as the semiconductor device 5628.

[0308] The computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0309] By using a data processing device of one embodiment of the present invention in the various electronic devices described above, the electronic devices can be made smaller, faster, or consume less power. Furthermore, since the data processing device of one embodiment of the present invention consumes less power, heat generation from the circuit can be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using a data processing device of one embodiment of the present invention, electronic devices that operate stably even in high-temperature environments can be realized. Therefore, the reliability of the electronic devices can be improved.

[0310] Next, a configuration example of a computer system applicable to the calculator 5600 will be described. Fig. 23 is a diagram illustrating a configuration example of a computer system 7000. The computer system 7000 is configured to include software and hardware. Note that the hardware included in a computer system may be referred to as an information processing device.

[0311] The software that makes up the computer system 7000 includes an operating system including device drivers, middleware, various development environments, AI-related application programs (AI applications), and application programs unrelated to AI.

[0312] The device driver includes an application program for controlling an auxiliary storage device, a display device, a printer, and other externally connected devices.

[0313] The hardware constituting the computer system 7000 includes a first processor, a second processor, a first storage device, etc. The second processor also includes a second storage device.

[0314] The first processing unit may be, for example, a central processing unit such as a Noff OS CPU. The Noff OS CPU has a storage means (e.g., nonvolatile memory) using OS transistors, and has a function of storing necessary information in the storage means and stopping the power supply to the central processing unit when operation is not required. Using a Noff OS CPU as the first processing unit can reduce the power consumption of the computer system 7000.

[0315] The second arithmetic processing device may be, for example, a GPU or an FPGA. Preferably, an AI OS Accelerator is used as the second arithmetic processing device. The AI OS Accelerator is configured using OS transistors and has arithmetic means such as a product-sum operation circuit. The AI OS Accelerator consumes less power than a general GPU. By using the AI OS Accelerator as the second arithmetic processing device, the power consumption of the computer system 7000 can be reduced.

[0316] It is preferable to use an information processing device according to one embodiment of the present invention as the first and second processing devices. For example, it is preferable to use an information processing device having a 3D OS NAND type storage device. The 3D OS NAND type storage device can function as a cache, a main memory, and a storage. Furthermore, using an information processing device having a 3D OS NAND type storage device makes it easy to realize a non-von Neumann type computer system.

[0317] By configuring the semiconductor device constituting the hardware with a semiconductor device including an OS transistor, it becomes easy to monolithically integrate the hardware including the central processing unit, the processing unit, and the storage device. Monolithic integration of the hardware not only makes it possible to reduce the size, weight, and thickness of the hardware, but also facilitates further reduction in power consumption.

[0318] An information processing device according to an aspect of the present invention can be suitably used in a small-scale system such as an IoT terminal device (also called an endpoint microcomputer) in the IoT field, for example.

[0319] FIG. 24 shows an image diagram of factory automation as an application example of an endpoint microcomputer. A factory 884 is connected to a cloud 883 via an Internet line. Furthermore, the cloud 883 is connected to a home 881 and an office 882 via the Internet line. The Internet line may be a wired communication system or a wireless communication system. For example, in the case of a wireless communication system, an information processing device according to one embodiment of the present invention may be used as a communication device to perform wireless communication in accordance with a communication standard such as a fourth-generation mobile communication system (4G) or a fifth-generation mobile communication system (5G). Furthermore, the factory 884 may be connected to factories 885 and 886 via the Internet line.

[0320] The factory 884 has a master device (control device) 831. The master device 831 has a function of connecting to a cloud 883 and transmitting and receiving information. The master device 831 is also connected to a plurality of industrial robots 842 included in IoT terminal devices 841 via an M2M (Machine to Machine) interface 832. As the M2M interface 832, for example, industrial Ethernet ("Ethernet" is a registered trademark), which is a type of wired communication method, or local 5G, which is a type of wireless communication method, may be used.

[0321] A factory manager can connect to a factory 884 via a cloud 883 from a home 881 or office 882 to know the operating status, etc. He can also check for incorrect or missing items, give instructions on where to put them, measure takt time, etc.

[0322] In recent years, the introduction of IoT into factories has been progressing worldwide under the name of "smart factories." In smart factory cases, there have been reported cases where endpoint microcomputers are used not only for simple inspection and auditing but also for fault detection and anomaly prediction.

[0323] In many cases, small-scale systems such as endpoint microcontrollers consume less power overall during operation, which can significantly reduce power consumption during standby. On the other hand, in the embedded field of IoT, quick response is sometimes required, and by using an information processing device according to one embodiment of the present invention, fast recovery from standby can be achieved.

[0324] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0325] (Notes regarding the present specification) The above-described embodiment and each configuration in the embodiment will be described below with additional notes.

[0326] The configurations shown in each embodiment can be combined as appropriate with configurations shown in other embodiments or examples to form one aspect of the present invention. Furthermore, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0327] In addition, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, and / or with the content (or even a part of the content) described in one or more other embodiments.

[0328] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0329] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0330] In addition, in the present specification and the like, in the block diagrams, components are classified by function and shown as independent blocks. However, in actual circuits, etc., it is difficult to separate components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately depending on the situation.

[0331] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0332] Furthermore, the positional relationships of components shown in the drawings are relative. Therefore, when describing components with reference to the drawings, terms such as "above" and "below" indicating the positional relationships may be used for convenience. The positional relationships of components are not limited to the content described in this specification, and can be rephrased appropriately depending on the situation.

[0333] In this specification and the like, when describing the connection relationship of a transistor, the term "one of the source or drain" (or first electrode or first terminal) is used, and the other of the source and drain is referred to as "the other of the source or drain" (or second electrode or second terminal). This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the names of the source and drain of a transistor can be appropriately changed to source (drain) terminal, source (drain) electrode, etc. depending on the situation.

[0334] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" and "wirings" are integrally formed.

[0335] Furthermore, in this specification and the like, voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0336] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration, device structure, etc. Also, a terminal, a wiring, etc. can be referred to as a node.

[0337] In this specification, "A and B are connected" means that A and B are electrically connected. Here, "A and B are electrically connected" means a connection in which an electrical signal can be transmitted between A and B when an object (such as a switch, transistor element, or diode, or a circuit including such an object and wiring) is present between A and B. Note that "A and B are electrically connected" also includes a case in which A and B are directly connected. Here, "A and B are directly connected" means a connection in which an electrical signal can be transmitted between A and B via wiring (or electrodes) or the like, without passing through the object. In other words, a direct connection means a connection that can be regarded as the same circuit diagram when represented by an equivalent circuit.

[0338] In this specification, a switch refers to a device that has the function of controlling whether a current flows by being in a conductive state (on state) or a non-conductive state (off state), or a device that has the function of selecting and switching a path for a current to flow.

[0339] In this specification, the channel length refers to, for example, in a top view of a transistor, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap, or a distance between a source and a drain in a region where a channel is formed.

[0340] In this specification, the channel width refers to, for example, the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed.

[0341] In this specification and the like, terms such as "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer." [Explanation of symbols]

[0342] SCL1: scribe line, SCL2: scribe line, T1: period, T2: period, T3: period, T4: period, T5: period, T6: period, T7: period, T8: period, T9: period, 10: layer, 20: layer, 20_k: layer, 20_t: layer, 20_1: layer, 30: layer, 40: layer, 100: information processing device, 100A: information processing device, 110: information processing device, 110M: information processing device, 150: host, 200A: information processing device, 211: insulator, 212: insulator, 213: insulator, 214: insulator, 215: insulator, 216: insulator, 221: conductor, 222: Conductor, 223: Conductor, 231: Semiconductor, 232: Semiconductor, 240: Insulator, 241: Insulator, 242: Insulator, 250: Conductor, 251: Conductor, 252: Conductor, 300: Transistor, 300A: Information processing device, 311: Substrate, 313: Semiconductor region, 314a: Low resistance region, 314b: Low resistance region, 315: Insulator, 316: Conductor, 320: Insulator, 322: Insulator, 324: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 350: Insulator, 410: Memory element, 411: Transistor, 412: Transistor, 413: Node, 421: terminal, 422: terminal, 423: terminal, 425: capacitance, 431: transistor, 432: transistor, 433: terminal, 434: terminal, 690: integrated circuit, 693: bus, 694: host controller, 790: automobile, 791: camera, 792: imaging direction, 831: master device, 832: interface, 841: IoT terminal equipment, 842: industrial robot, 881: home, 882: office, 883: cloud, 884: factory, 885: factory, 886: factory, 901: boundary area, 902: boundary area, 4700: electronic component, 4702: processor Print substrate, 4704: mounting substrate, 4710: information processing device, 4711: mold, 4712: land, 4713: electrode pad, 4714: wire, 4730: electronic component, 4731: interposer, 4732: package substrate, 4733: electrode, 4735: semiconductor device, 4800: semiconductor wafer, 4800a: chip, 4801: wafer, 4801a: wafer, 4802: circuit unit, 4803: spacing, 4803a: spacing, 5110: SD card, 5111: housing, 5112: connector, 5113: substrate, 5115: controller chip,5150: SSD, 5151: housing, 5152: connector, 5153: circuit board, 5155: memory chip, 5156: controller chip, 5200: portable game console, 5201: housing, 5202: display unit, 5203: button, 5300: desktop information terminal, 5301: main unit, 5302: display unit, 5303: keyboard, 5400: ICD main unit, 5401: battery, 5402: wire, 5403: wire, 54 04: Antenna, 5405: Subclavian vein, 5406: Superior vena cava, 5500: Information terminal, 5510: Housing, 5511: Display unit, 5600: Computer, 5610: Rack, 5620: Computer, 5621: PC card, 5622: Board, 5623: Connection terminal, 5624: Connection terminal, 5625: Connection terminal, 5626: Semiconductor device, 5627: Semiconductor device, 5628: Semiconductor device, 5629: Connection terminal, 5630: Motherboard, 5631: Slot, 5700: Automobile, 5800: Electric refrigerator-freezer, 5801: Housing, 5802: Refrigerator door, 5803: Freezer door, 5900: Information terminal, 5901: Housing, 5902: Display unit, 5903: Operation switch, 5904: Operation switch, 5905: Band, 6100: Expansion device, 6101: Housing, 6102: Cap, 6103: USB connector, 6104: Board, 6106: Controller chip ,6240: Digital camera, 6241: Housing, 6242: Display unit, 6243: Operation switch, 6244: Shutter button, 6246: Lens, 6300: Video camera, 6301: First housing, 6302: Second housing, 6303: Display unit, 6304: Operation switch, 6305: Lens, 6306: Connection unit, 7000: Computer system, 7500: Stationary game console, 7520: Main unit, 7522: Controller,

Claims

[Claim 1] A computing device; A storage device; a wiring layer; the storage device is stacked above the arithmetic device, the wiring layer is stacked above the storage device, The arithmetic unit is an information processing device that executes product-sum operations for performing inference processing based on a neural network.

Images