Semiconductor optical element and method for manufacturing semiconductor optical element

Abstract

To provide a semiconductor optical element capable of restraining unintentional etching and restraining optical loss, and a method for manufacturing the semiconductor optical element.SOLUTION: A semiconductor optical element includes a substrate having a silicon layer, and a semiconductor element that is formed of a III-V compound semiconductor and bonded to the silicon layer. The silicon layer has a first waveguide, a first recess portion, a terrace, and a first slab portion. The first recess portion is a portion that is recessed beyond the surfaces of the first waveguide, the terrace, and the first slab portion. The first recess portion and the terrace are arranged in this order on both sides of the first waveguide. The first waveguide is connected to one end portion of the first slab portion, and the first slab portion is connected to the terrace. The semiconductor element has a second slab portion, a protruding portion, and a mesa. The second slab portion is located on the first slab portion. The protruding portion protrudes from the second slab portion above the first waveguide. The mesa is located above the second slab portion and the protruding portion.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor optical device and a method for manufacturing the semiconductor optical device. [Background technology]

[0002] A hybrid semiconductor optical device can be formed by bonding a semiconductor device made of a compound semiconductor and having optical gain to a substrate such as an SOI (Silicon On Insulator) substrate (silicon photonics) on which a waveguide is formed (see, for example, Non-Patent Document 1). After bonding, the semiconductor device is etched, etc. Light is transferred between the silicon waveguide and the semiconductor device. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] D.Huang, et al. “High-power sub-kHz linewidth lasers fully integrated on silicon” Optica Vol.6, No.6 745-752 (June 2019) Summary of the Invention [Problem to be solved by the invention]

[0004] A groove (trench) is formed in the substrate. An etchant may enter the groove and etch the semiconductor element from the bonding interface. To prevent damage to the semiconductor element, it is necessary to prevent unintentional etching. To prevent light loss, it is necessary to increase the coupling efficiency between the waveguide and the semiconductor element. Therefore, it is an object of the present invention to provide a semiconductor optical element and a method for manufacturing a semiconductor optical element that can prevent unintentional etching and reduce light loss. [Means for solving the problem]

[0005] A semiconductor optical device according to the present disclosure comprises a substrate having a silicon layer, and a semiconductor element formed of a III-V compound semiconductor and bonded to the silicon layer, wherein the silicon layer has a first waveguide, a first recess, a terrace, and a first slab portion, the first recess being recessed below the surfaces of the first waveguide, the terrace, and the first slab portion, the first recess and the terrace being arranged in this order on both sides of the first waveguide, the first waveguide being connected to one end of the first slab portion, and the first slab portion being connected to the terrace, the semiconductor element having a second slab portion, a protrusion, and a mesa, the second slab portion being located on the first slab portion, the protrusion protruding from the second slab portion above the first waveguide, and the mesa being located on the second slab portion and the protrusion. [Effects of the Invention]

[0006] According to the present disclosure, it is possible to provide a semiconductor optical device and a method for manufacturing a semiconductor optical device that can suppress unintentional etching and suppress light loss. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a perspective view illustrating a semiconductor optical device according to an embodiment. [Figure 2A] FIG. 2A is an enlarged plan view of the transition structure and its vicinity. [Figure 2B] FIG. 2B is a plan view illustrating the substrate. [Figure 3A] FIG. 3A is a cross-sectional view illustrating an example of a semiconductor optical device. [Figure 3B] FIG. 3B is a cross-sectional view illustrating an example of a semiconductor optical device. [Figure 3C] FIG. 3C is a cross-sectional view illustrating an example of a semiconductor optical device. [Figure 4A] FIG. 4A is a cross-sectional view illustrating an example of a semiconductor optical device. [Figure 4B] FIG. 4B is a cross-sectional view illustrating an example of a semiconductor optical device. [Figure 4C]FIG. 4C is a cross-sectional view illustrating an example of a semiconductor optical device. [Figure 5A] FIG. 5A is a diagram illustrating the calculation results of the transmittance. [Figure 5B] FIG. 5B is a diagram illustrating the calculation results of the transmittance. [Figure 6] FIG. 6 is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 7A] FIG. 7A is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 7B] FIG. 7B is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 7C] FIG. 7C is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 8A] FIG. 8A is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 8B] FIG. 8B is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 8C] FIG. 8C is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 9] FIG. 9 is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 10A] FIG. 10A is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 10B] FIG. 10B is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 10C] FIG. 10C is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 11A] FIG. 11A is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 11B] FIG. 11B is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 11C] FIG. 11C is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 12] FIG. 12 is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 13A] FIG. 13A is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 13B]FIG. 13B is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 13C] FIG. 13C is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 14A] FIG. 14A is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 14B] FIG. 14B is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 14C] FIG. 14C is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 15] FIG. 15 is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 16A] FIG. 16A is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 16B] FIG. 16B is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 16C] FIG. 16C is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 17A] FIG. 17A is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 17B] FIG. 17B is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 17C] FIG. 17C is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 18] FIG. 18 is a plan view illustrating a semiconductor optical device according to a comparative example. [Figure 19A] FIG. 19A is a cross-sectional view illustrating an example of a semiconductor optical device. [Figure 19B] FIG. 19B is a cross-sectional view illustrating an example of a semiconductor optical device. [Figure 19C] FIG. 19C is a cross-sectional view illustrating an example of a semiconductor optical device. [Figure 20A] FIG. 20A is a plan view illustrating a semiconductor optical device according to a modified example. [Figure 20B] FIG. 20B is a plan view illustrating the substrate. DETAILED DESCRIPTION OF THE INVENTION

[0008] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described.

[0009] One aspect of the present disclosure includes: (1) a substrate having a silicon layer; and a semiconductor element formed of a III-V compound semiconductor and bonded to the silicon layer, the silicon layer having a first waveguide, a first recess, a terrace, and a first slab portion, the first recess being recessed below the surfaces of the first waveguide, the terrace, and the first slab portion, the first recess and the terrace being arranged in this order on both sides of the first waveguide, the first waveguide being connected to one end of the first slab portion, the first slab portion being connected to the terrace, the semiconductor element having a second slab portion, a protrusion, and a mesa, the second slab portion being located on the first slab portion, the protrusion protruding from the second slab portion above the first waveguide, and the mesa being located on the second slab portion and the protrusion. The first slab portion is connected to the terrace, and the first recess terminates near the end of the first slab portion. Since the first recessed portion terminates just before the semiconductor element, unintended etching of the semiconductor element can be suppressed. Since light is confined near the mesa of the semiconductor element, optical loss can be suppressed. (2) In the above (1), the silicon layer may have a second waveguide and a second recess, the second waveguide is connected to an end of the first slab portion opposite the first waveguide, the second recess and the terrace are arranged in this order on both sides of the second waveguide, the first slab portion is located between the first recess and the second recess, the second slab portion is located on the first slab portion, the second waveguide, the second recess, and the terraces on both sides of the second waveguide, and the mesa may extend from a position overlapping the first waveguide to a position overlapping the second waveguide. Since the second recess is closed by the first slab portion and the second slab portion, penetration of an etchant into the second recess is suppressed. (3) In the above (1) or (2), the semiconductor element may have a first semiconductor layer, an active layer, and a second semiconductor layer, the first semiconductor layer, the active layer, and the second semiconductor layer being stacked in this order from the side closest to the substrate, the protruding portion including the first semiconductor layer, the second slab portion including the first semiconductor layer and the active layer, the portion of the mesa located above the protruding portion including the active layer and the second semiconductor layer, and the portion of the mesa located above the second slab portion including the second semiconductor layer. Since light is confined near the mesa of the semiconductor element, optical loss can be suppressed. (4) In the above (3), the first semiconductor layer and the second semiconductor layer may contain indium phosphide, and the active layer may contain gallium indium arsenide phosphide. The semiconductor element is processed by wet etching. Penetration of the etchant into the second recess is suppressed. Unintended etching of the semiconductor element can be suppressed. (5) In the above (3) or (4), the first semiconductor layer may be an n-type semiconductor layer, and the second semiconductor layer may be a p-type semiconductor layer. A pin structure is formed, allowing current to be injected into the active layer. (6) In any of the above (1) to (5), the protrusion may be located more inward than the first waveguide, and the mesa may be located more inward than the protrusion. This can suppress etching of the semiconductor element from the bonding interface. The protrusion and the mesa are easy to manufacture. (7) In any of the above (1) to (6), the first waveguide may have a first tapered portion, the protrusion may have a second tapered portion, and the mesa may have a third tapered portion, and the widths of the first tapered portion, the second tapered portion, and the third tapered portion may be larger the closer they are to the first slab portion and smaller the farther they are from the first slab portion. Since the coupling efficiency between the substrate and the semiconductor element is increased, optical loss can be suppressed. (8) In the above (7), the second tapered portion may be joined to the first tapered portion, and the third tapered portion may be located on the second tapered portion. This increases the coupling efficiency between the substrate and the semiconductor element, thereby reducing optical loss. (9) In any of the above (1) to (8), an insulating film may be provided to cover the silicon layer and the semiconductor element. The insulating film functions as a cladding layer, and optical loss can be reduced. (10) A method for manufacturing a semiconductor device, comprising: bonding a semiconductor element formed of a III-V compound semiconductor to a silicon layer of a substrate; and wet etching the bonded semiconductor element, wherein the silicon layer has a first waveguide, a first recess, a terrace, and a first slab portion; the first recess is a portion recessed below the surfaces of the first waveguide, the terrace, and the first slab portion; the first recess and the terrace are arranged in this order on both sides of the first waveguide; the first waveguide is connected to one end of the first slab portion; The slab portion is connected to the terrace, and the step of bonding the semiconductor element is a step of bonding the semiconductor element to the first waveguide, the first slab portion, and the terraces on both sides of the first waveguide, and the step of performing wet etching forms a second slab portion, a protrusion, and a mesa in the semiconductor element, the second slab portion being located on the first slab portion, the protrusion protruding from the second slab portion above the first waveguide, and the mesa being located on the second slab portion and the protrusion.This is a method for manufacturing a semiconductor optical element.Unintentional etching of the semiconductor element can be suppressed.Light is confined near the mesa of the semiconductor element, thereby suppressing optical loss. (11) In the above (10), the silicon layer may have a second waveguide and a second recess, the second waveguide is connected to an end of the first slab portion opposite to the first waveguide, the second recess and the terrace are arranged in this order on both sides of the second waveguide, the first slab portion is located between the first recess and the second recess, the bonding step may be a step of bonding the semiconductor element to the first waveguide, the first slab portion, the second waveguide, and the terrace on both sides of the first waveguide and the second waveguide, and the mesa may extend from a position overlapping the first waveguide to a position overlapping the second waveguide. Since the second recess is closed by the first slab portion and the second slab portion, penetration of an etchant into the second recess is suppressed.

[0010] [Details of the embodiments of the present disclosure] Specific examples of semiconductor optical devices and methods for manufacturing semiconductor optical devices according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0011] <Embodiment> (semiconductor optical element) FIG. 1 is a plan view illustrating a semiconductor optical device 100 according to an embodiment. The semiconductor optical device 100 is a hybrid-type tunable laser device and includes a substrate 10 and a semiconductor device 30. The semiconductor device 30 has optical gain and is bonded to one surface of the substrate 10. The Z-axis direction is the normal direction to the top surface of the substrate 10. The X-axis direction is a direction parallel to the waveguide. One direction along the X-axis is defined as the +X direction. The direction opposite to the +X direction is defined as the -X direction. The Y-axis direction is perpendicular to the X-axis and Z-axis directions.

[0012] The semiconductor optical device 100 has a transition structure 101, a transition structure 102, two ring resonators 103, and two loop mirrors 104. In the X-axis direction, the loop mirror 104, the ring resonator 103, the transition structure 102, the semiconductor device 30, the transition structure 101, the ring resonator 103, and the loop mirror 104 are arranged in this order. This configuration forms a laser resonator.

[0013] The ring resonator 103 and the loop mirror 104 are provided on the substrate 10. The transition structure 101 and the transition structure 102 are portions that cause light to transition between the substrate 10 and the semiconductor element 30, and are formed by the substrate 10 and the semiconductor element 30.

[0014] Fig. 2A is an enlarged plan view of the transition structure 101 and its vicinity. Fig. 2B is a plan view illustrating the substrate 10, with the semiconductor element 30 removed from Fig. 2A. Figs. 3A to 4C are cross-sectional views illustrating the semiconductor optical element 100, showing cross sections along lines A1, A2, A3, A4, A5, and A6 in Fig. 2A, respectively. In Figs. 3A to 4C, the light distribution is illustrated by dashed lines.

[0015] As shown in FIGS. 3A to 4C, substrate 10 is an SOI (Silicon on Insulator) substrate and includes substrate 12, box layer 14, and silicon (Si) layer 16, which are stacked in this order in the Z-axis direction. Substrate 12 is made of, for example, Si. Box layer 14 is made of, for example, silicon oxide (SiO2). Box layer 14 has a thickness of, for example, 3 μm. Silicon layer 16 has a thickness of, for example, 220 nm. The upper surface of substrate 10 and the surface of semiconductor element 30 are covered with insulating film 11. Insulating film 11 is made of, for example, SiO2 and has a thickness of 1 μm. Silicon layer 16 has a refractive index of 3.45. The refractive index of box layer 14 and insulating film 11 is 1.45, which is lower than that of silicon layer 16. Functional parts such as a waveguide are provided in silicon layer 16 of substrate 10.

[0016] As shown in Figures 2A and 2B, the substrate 10 has a waveguide 20 (first waveguide), a waveguide 22 (second waveguide), a recess 24 (first recess), a recess 26 (second recess), a terrace 27, and a slab portion 28 (first slab portion).

[0017] Waveguide 20, slab portion 28, and waveguide 22 are arranged in this order from the +X side to the -X side. Waveguide 20 is connected to one end (the end on the +X side) of slab portion 28 in the X-axis direction. Waveguide 22 is connected to the other end (the end on the -X side) of slab portion 28. Waveguide 20 and waveguide 22 are parallel to the X-axis direction.

[0018] Waveguide 20 has tapered portion 21 (first tapered portion). Waveguide 22 has tapered portion 23. The widths of tapered portion 21 and tapered portion 23 are larger the closer they are to slab portion 28 and smaller the farther they are from slab portion 28. Width W1 of the tip of waveguide 20 shown in FIG. 2B is, for example, 420 nm. The dimensions of waveguide 22 may be the same as or different from those of waveguide 20. The dimensions of recess 26 may be the same as or different from those of recess 24.

[0019] In the Y-axis direction, a recess 24 and a terrace 27 are provided in this order on both sides of the waveguide 20. That is, the recess 24 is arranged next to the waveguide 20. The terrace 27 is arranged on the opposite side of the recess 24 from the waveguide 20. A recess 26 and a terrace 27 are provided in this order on both sides of the waveguide 22. The recess 24 extends along the waveguide 20 and has a tapered shape corresponding to the tapered portion 21 of the waveguide 20. The recess 26 extends along the waveguide 22 and has a tapered shape corresponding to the tapered portion 23 of the waveguide 22.

[0020] The slab portion 28 is plate-shaped and is located between the recessed portion 24 and the recessed portion 26, and is connected to the two terraces 27 on both sides of the waveguide. The recessed portion 24 and the recessed portion 26 are separated by the slab portion 28.

[0021] As shown in Figures 3A to 4A, the waveguide 20 and the terrace 27 are portions of the silicon layer 16 that protrude in the Z-axis direction (upward) beyond the recess 24. The surface of the waveguide 20 is located at the same height as the surface of the terrace 27. The recess 24 is a portion that is recessed below the surfaces of the waveguide 20 and the terrace 27. As shown in Figure 4C, the surface of the waveguide 22 is located at the same height as the surface of the terrace 27. The recess 26 is a portion that is recessed below the surfaces of the waveguide 22 and the terrace 27. The silicon layer 16 forms the bottom surfaces of the recess 24 and the recess 26. The thickness of the silicon layer 16 in the recess is, for example, 30 nm. The recess 24 and the recess 26 may extend partway through the silicon layer 16 in the Z-axis direction, or may extend through the silicon layer 16 to the box layer 14. An insulating film 11 is buried in the recess 24 and the recess 26.

[0022] 4B, the surface of the slab portion 28 is located at the same height as the surface of the terrace 27. The slab portion 28 is integrated with the terrace 27, extends parallel to the XY plane, and forms the surface of the silicon layer 16.

[0023] 1, semiconductor element 30 has slab portion 32 (second slab portion), two protrusions 33, mesa 35, electrode 48, and electrode 49. Protrusion 33, slab portion 32, and protrusion 33 are arranged in this order from the +X side to the -X side. Mesa 35 extends from one protrusion 33 to the other protrusion 33.

[0024] As shown in FIGS. 2A and 4B, the slab portion 32 is bonded to the slab portion 28 of the substrate 10. The slab portion 32 is plate-shaped and has a width greater than that of the protruding portion 33 and the mesa 35. The planar shape of the slab portion 32 is rectangular. In the X-axis direction, the slab portion 32 does not protrude beyond the slab portion 28. The slab portion 28 extends outward from the slab portion 32 from the position where it overlaps with the slab portion 32. As shown in FIGS. 2A to 4A, the protruding portion 33 extends parallel to the X-axis, protrudes from the slab portion 32 above the waveguide 20, and is located above the tapered portion 21 of the waveguide 20.

[0025] The protruding portion 33 has a tapered portion 34 (second tapered portion). In the example of FIG. 2A, the entire protruding portion 33 is the tapered portion 34. The width of the tapered portion 34 increases the closer it is to the slab portion 32 and decreases the farther it is from the slab portion 32. The protruding portion 33 has a width greater than that of the mesa 35. The widths of the protruding portion 33 from the tip of the protruding portion 33 toward the slab portion 32 are designated W2, W3, W4, and W5. The width W2 is, for example, 1.7 μm. The width W3 is, for example, 2.7 μm. The width W4 is, for example, 3.7 μm. The width W5 of the portion of the protruding portion 33 connected to the slab portion 32 is, for example, 5.7 μm.

[0026] As shown in Fig. 2A, mesa 35 extends parallel to the X-axis, from a position overlapping waveguide 20 to a position overlapping waveguide 22. As shown in Figs. 2A and 3C to 4C, mesa 35 is located on slab portion 32 and protruding portion 33. Mesa 35 has portion 36 and portion 37. Portion 36 protrudes out of slab portion 32 and is located on protruding portion 33 and waveguide 20. Portion 37 is located on slab portion 32 and waveguide 22.

[0027] 2A, portion 36 of mesa 35 has tapered portion 38 (third tapered portion). Tapered portion 38 is located on protrusion 33. The width of tapered portion 38 increases as it approaches slab portion 28 and decreases as it is farther from slab portion 28. Width W6 of the tip of mesa 35 is, for example, 400 nm.

[0028] Tapered portion 31 of semiconductor element 30 protrudes from slab portion 32 in the X-axis direction, is located on both sides of mesa 35 in the Y-axis direction, and is located between slab portion 32 and tapered portion 38 of mesa 35 in the X-axis direction. A width W7 of the portion of tapered portion 31 connected to slab portion 32 is, for example, 3 μm.

[0029] The protrusion 33 and the mesa 35 do not protrude outward from the waveguide 20 in plan view, but are located inside the waveguide 20. The waveguide 20 protrudes outward from below the protrusion 33 and the mesa 35 to the outside of the protrusion 33.

[0030] 3B to 4C, the semiconductor element 30 has a cladding layer 40 (first semiconductor layer), an active layer 42, a cladding layer 44, and a contact layer 46 (these two layers are second semiconductor layers). As shown in FIGS. 3B to 4A, the protruding portion 33 of the semiconductor element 30 is formed of the cladding layer 40.

[0031] Mesa 35 includes active layer 42, cladding layer 44, and contact layer 46. As shown in Figures 3C and 4A, portion 36 of mesa 35 includes active layer 42, cladding layer 44, and contact layer 46 and has a deep ridge structure. As shown in Figures 4B and 4C, portion 37 of mesa 35 does not include active layer 42, but includes cladding layer 44 and contact layer 46 and has a shallow ridge structure.

[0032] As shown in Figure 4A, the tapered section 31 is formed of an active layer 42. As shown in Figures 4B and 4C, the slab section 32 includes a cladding layer 40 and an active layer 42.

[0033] The insulating film 11 covers the substrate 10, the slab portion 32, the protruding portion 33, and the mesa 35. The insulating film 11 has an opening above the mesa 35. The electrode 48 is a p-type electrode that is provided in the opening, is in contact with the surface of the contact layer 46, and is electrically connected to the contact layer 46. The insulating film 11 also has an opening at a position spaced apart from the mesa 35. The electrode 49 shown in FIG. 1 is an n-type electrode that is connected to the cladding layer 40 through the opening.

[0034] The cladding layer 40 is made of, for example, n-type indium phosphide (n-InP). The active layer 42 has a quantum well structure (MQW: Multiple Quantum Well) and includes barrier layers and well layers. Multiple barrier layers and multiple well layers are alternately stacked. The barrier layers and well layers are made of, for example, i-type gallium indium arsenide phosphide (GaInAsP). The cladding layer 44 is made of, for example, p-type indium phosphide (p-InP). The contact layer 46 is made of, for example, p-type gallium indium arsenide (p-GaInAs). The semiconductor layers of the semiconductor element 30 may be made of III-V compound semiconductors other than those mentioned above.

[0035] The electrodes 48 and 49 are made of metal. The electrode 48 is made of, for example, a laminate of titanium (Ti), platinum (Pt), and gold (Au) stacked from the side closest to the mesa 35. The electrode 49 is made of, for example, an alloy of gold, germanium, and nickel (AuGeNi).

[0036] Transition structure 102 has the same configuration as transition structure 101. Waveguide 22, recess 26, and terrace 27 extend from transition structure 101 to transition structure 102. Recess 26 is located between waveguide 22 and terrace 27. Slab portion 32 of semiconductor device 30 extends from transition structure 101 to transition structure 102 and is located above recess 26, terrace 27, and waveguide 22. Recess 26 is enclosed by slab portion 28 and slab portion 32.

[0037] A voltage is applied to the semiconductor element 30 using electrodes 48 and 49, and carriers are injected into the active layer 42. The active layer 42 has optical gain and generates light through carrier injection. The wavelength of the light is, for example, 1.55 μm. The semiconductor element 30 and the substrate 10 are evanescently optically coupled. Light generated in the semiconductor element 30 propagates through the waveguide 22 and transfers to the waveguide 20 at the transition structures 101 and 102. The light resonates in the ring resonator 103 and is reflected by the loop mirror 104. The reflected light propagates toward the semiconductor element 30 and transfers from the waveguide 20 to the waveguide 22 at the transition structures 101 and 102. The light is repeatedly reflected, resulting in laser oscillation.

[0038] The diameter of one of the two ring resonators 103 is different from the diameter of the other. The oscillation wavelength is determined by the Vernier effect of the two ring resonators 103. The transmittance of one of the two loop mirrors 104 is higher than that of the other. Part of the laser light passes through the loop mirror 104 and is emitted to the outside of the semiconductor optical device 100.

[0039] In Figures 3A to 4C, the shape of light is schematically illustrated by a dashed ellipse. The mode of light is determined by the waveguide and mesa 35. In the cross section of Figure 3A, the light is concentratedly distributed in the waveguide 20. In the transition structure 101, the light transfers from the waveguide 20 to the semiconductor element 30. Because the protrusion 33 and mesa 35 of the semiconductor element 30 have tapered shapes, the light transfers gradually and the mode of the light is converted gently. The light is confined near the mesa 35 of the semiconductor element 30 and does not easily spread. This maintains the mode of the light. Light loss can be suppressed.

[0040] 5A and 5B are diagrams illustrating calculation results of transmittance. Fig. 5A shows the calculation results of transmittance in protrusion 33. The horizontal axis represents the length of tapered portion 34 of protrusion 33. The vertical axis represents light transmittance. When tapered portion 34 is 5 μm or more, the transmittance exceeds 0.9.

[0041] FIG. 5B shows the calculation results for the transmittance of the tapered portion 38 of the mesa 35. The horizontal axis represents the length of the tapered portion 38, and the vertical axis represents the light transmittance. The longer the tapered portion 38, the higher the transmittance, and at lengths of 15 μm or more, the transmittance exceeds 0.9. As described above, the tapered protrusion 33 and mesa 35 can suppress light loss.

[0042] (Manufacturing method) 6, 9, 12, and 15 are plan views illustrating a method for manufacturing the semiconductor optical device 100. FIGS. 7A to 8C are cross-sectional views illustrating a method for manufacturing the semiconductor optical device 100, showing cross sections along lines A1 to A6 in FIG. 6. FIGS. 10A to 11C are cross-sectional views illustrating a method for manufacturing the semiconductor optical device 100, showing cross sections along lines A1 to A6 in FIG. 9. FIGS. 13A to 14C are cross-sectional views illustrating a method for manufacturing the semiconductor optical device 100, showing cross sections along lines A1 to A6 in FIG. 12. FIGS. 16A to 17C are cross-sectional views illustrating a method for manufacturing the semiconductor optical device 100, showing cross sections along lines A1 to A6 in FIG. 15.

[0043] 6, the silicon layer 16 of the substrate 10 is subjected to, for example, dry etching. The portions exposed by the mask (not shown) are etched, forming the recesses 24 and 26. The portions covered by the mask (not shown) are not etched. The waveguides 20 and 22, the terrace 27, and the slab portion 28 are formed.

[0044] A contact layer 46, a cladding layer 44, an active layer 42, and a cladding layer 40 are epitaxially grown in this order on an InP substrate separate from the SOI substrate (substrate 10) by metal organic chemical vapor deposition (MOCVD) or the like. The InP substrate is diced to form a semiconductor element 30. Immediately after dicing, the semiconductor element 30 is a rectangular parallelepiped, and does not have a slab portion 32, a protrusion 33, or a mesa 35.

[0045] As shown in FIGS. 6 to 8C, a semiconductor element 30 is bonded to the upper surface of the substrate 10. One surface of the silicon layer 16 and one surface of the semiconductor element 30 are irradiated with plasma to activate these surfaces. The semiconductor element 30 is brought into contact with the surface of the silicon layer 16 and bonded to the silicon layer 16. The semiconductor element 30 covers the upper surface of the silicon layer 16, for example, and is located on the waveguides 20 and 22, the recesses 24 and 26, the terrace 27, and the slab portion 28. After bonding, wet etching is performed to remove the InP substrate. The semiconductor layers from the contact layer 46 to the cladding layer 40 remain.

[0046] As shown in FIGS. 9 to 11C, a portion of the semiconductor element 30 is covered with a mask 50. The semiconductor element 30 is subjected to, for example, dry etching and wet etching to form a mesa 35. A hydrochloric acid-based chemical solution, for example, is used as an etchant for the wet etching. The portion of the semiconductor element 30 covered with the mask 50 is not etched and becomes the mesa 35. The mesa 35 is formed of a cladding layer 44 and a contact layer 46. In the portion exposed by the mask 50, the contact layer 46 and the cladding layer 44 are etched, exposing the active layer 42. The cladding layer 40 and the active layer 42 cover the waveguides 20 and 22, the recesses 24 and 26, the terraces 27, and the slab portion 28 of the silicon layer 16. After etching, the mask 50 is removed.

[0047] As shown in FIGS. 12 to 14C, a mask 52 is provided on the semiconductor device 30. As shown in FIGS. 13C to 14C, the mask 52 covers the top and side surfaces of the mesa 35 and also covers a portion of the active layer 42. Another portion of the active layer 42 is exposed through the mask 52. For example, wet etching is performed to remove the portion of the active layer 42 exposed through the mask 52. As shown in FIGS. 13A to 13C, the cladding layer 40 is exposed in the wet-etched portion. The portion covered by the mask 52 is not etched, and the mesa 35, the active layer 42, and the cladding layer 40 remain.

[0048] As shown in Figures 13C and 14A, portion 36 of mesa 35 includes active layer 42 and has a deep ridge structure. As shown in Figure 14A, the portion of cladding layer 40 that protrudes beyond mesa 35 in the Y-axis direction becomes tapered portion 31. As shown in Figures 14B and 14C, portion 37 of mesa 35 includes cladding layer 44 and contact layer 46 and has a shallow ridge structure. Active layer 42 and cladding layer 40 form slab portion 32. After etching, mask 52 is removed.

[0049] As shown in FIGS. 15 to 17C, a mask 54 is provided on the semiconductor device 30. As shown in FIGS. 16C to 17C, the mask 54 covers the top and side surfaces of the mesa 35. As shown in FIGS. 17B and 17C, the mask 54 covers the slab portion 32. As shown in FIG. 16B, the mask 54 covers the portion of the cladding layer 40 above the waveguide 20. A portion of the cladding layer 40 is exposed from the mask 54. For example, wet etching is performed to remove the portion of the cladding layer 40 exposed from the mask 54, thereby forming the protrusion 33. The cladding layer 40 is removed by wet etching, exposing the silicon layer 16. After etching, the mask 54 is removed.

[0050] An insulating film 11 is formed by plasma CVD (PECVD, Plasma Enhanced Chemical Vapor Deposition) or the like, as shown in FIGS. 3A to 4C. An opening is formed in the insulating film 11 above the mesa 35. An electrode 48 and an electrode 49 are formed in the opening by vacuum deposition or the like. Through the above steps, the semiconductor optical device 100 is formed.

[0051] As described above, after bonding, the semiconductor element 30 is subjected to wet etching. In the wet etching process, the insulating film 11 is not formed, and the recesses 24 are exposed. In the wet etching process, the etchant enters the recesses 24. Because the slab portion 28 is provided between the recesses 24 and 26, the etchant is blocked by the slab portion 28, and the etchant is prevented from entering the recesses 26. Therefore, etching of the semiconductor element 30 is prevented from occurring on the bonding interface side.

[0052] (Comparative Example) Fig. 18 is a plan view illustrating a semiconductor optical device 110 according to a comparative example. Figs. 19A to 19C are cross-sectional views illustrating the semiconductor optical device 110, respectively showing cross sections taken along lines B1, B2, and B3 in Fig. 18. Descriptions of configurations that are the same as those in the embodiment will be omitted.

[0053] As shown in Figures 18 to 19C, the substrate 10 has a waveguide 20, a recess 24, and a terrace 27, but does not have a slab portion. The waveguide 20, the recess 24, and the terrace 27 extend from one end of the substrate 10 to the other end in the X-axis direction. The waveguide 20 has a tapered portion 21, a portion 29, and a portion 25. In the X-axis direction, the portion 29, the tapered portion 21, the portion 25, the tapered portion 21, and the portion 29 are arranged in this order. The portion 25 is wider than the portion 29. The tapered portion 21 is connected to the portion 29 and the portion 25.

[0054] The semiconductor device 30 has a slab portion 39 and a protruding portion 33. The protruding portion 33 protrudes from the slab portion 39 in the X-axis direction and is located above the portion 25 of the waveguide 20. The slab portion 39 is located above the waveguide 20, the recess 24, and the terrace 27.

[0055] The recesses 24 are located on both sides of the waveguide 20 and extend from outside the semiconductor element 30 to below the semiconductor element 30. In the process of wet etching the semiconductor element 30, a liquid such as an etchant penetrates the recesses 24 and flows below the semiconductor element 30. When the semiconductor element 30 is etched from the bottom surface (bonding interface), damage occurs to the semiconductor element 30. The bonding strength of the semiconductor element 30 to the substrate 10 decreases.

[0056] According to this embodiment, the silicon layer 16 of the substrate 10 has the waveguides 20 and 22, the recesses 24 and 26, and the slab portion 28. The slab portion 28 is located between the recesses 24 and 26 and separates them. The recess 24 terminates at the edge of the semiconductor element 30 and is not connected to the recess 26. The semiconductor element 30 is bonded to the silicon layer 16 and has a slab portion 32. The slab portion 32 is located above the slab portion 28, the waveguide 22, the recess 26, and the terrace 27. The recess 26 is sealed by the slab portion 28 and the slab portion 32. Liquids such as etchants are less likely to penetrate into the recess 26. Unintentional etching of the semiconductor element 30 can be suppressed.

[0057] The semiconductor element 30 is made of a III-V compound semiconductor. After bonding, wet etching is performed to form the slab portion 32, the protrusion portion 33, the mesa 35, and the like. The semiconductor element 30 includes an InP cladding layer, an InGaAsP active layer 42, and an InGaAs contact layer 46. For wet etching, an etchant suitable for these semiconductors is used. For example, a hydrochloric acid-based solution is used as the etchant. The slab portions 28 and 32 prevent the etchant from penetrating the recessed portion 26, thereby preventing unintended etching of the semiconductor element 30.

[0058] The substrate 10 and the semiconductor element 30 form a transition structure 101 and a transition structure 102. As shown in FIG. 2A, the semiconductor element 30 has a protrusion 33 and a mesa 35. The protrusion 33 is located on the waveguide 20. The mesa 35 is located on the protrusion 33 and the slab portion 32. In the transition structure, light is transferred between the substrate 10 and the semiconductor element 30. The light propagates through the waveguide and is confined near the mesa 35. This can suppress light loss.

[0059] The semiconductor device 30 has a cladding layer 40, an active layer 42, a cladding layer 44, and a contact layer 46. The slab portion 32 includes the cladding layer 40 and the active layer 42. The protruding portion 33 includes the cladding layer 40. A portion 36 of the mesa 35 is located on the protruding portion 33 and includes the active layer 42, the cladding layer 44, and the contact layer 46. This increases the coupling efficiency between the semiconductor device 30 and the substrate 10 and allows for a gradual transition of light. A portion 37 of the mesa 35 is located on the slab portion 32 and includes the cladding layer 44 and the contact layer 46. Light is confined near the mesa 35. This reduces light loss.

[0060] The cladding layer 40 is made of n-type InP. The cladding layer 44 is made of p-type InP. The contact layer 46 is made of p-type InGaAs. The active layer 42 is made of undoped GaInAsP. A pin junction is formed in the semiconductor element 30. Carriers can be injected into the active layer 42 to generate light. Light is concentrated near the mesa 35 of the semiconductor element 30, reducing loss.

[0061] As shown in FIG. 2A, the waveguide 20 protrudes outside the protrusion 33 and the mesa 35. The protrusion 33 and the mesa 35 do not protrude, but are located inside the waveguide 20. This can suppress etching of the semiconductor element 30 from the bonding interface. The mesa 35 is located inside the protrusion 33. The protrusion 33 and the mesa 35 can be easily manufactured by etching. After the mesa 35 is formed, the protrusion 33 can be formed below the mesa 35.

[0062] The waveguide 20 has a tapered portion 21. The protrusion 33 has a tapered portion 34. The mesa 35 has a tapered portion 38. The coupling efficiency between the semiconductor element 30 and the substrate 10 can be increased, and optical loss can be suppressed.

[0063] The tapered portion 34 of the protruding portion 33 is joined to the tapered portion 21 of the waveguide 20. The tapered portion 38 of the mesa 35 is located on the tapered portion 34 of the protruding portion 33. The multi-step tapered structure can improve the coupling efficiency between the semiconductor element 30 and the substrate 10.

[0064] The insulating film 11 covers the silicon layer 16 of the substrate 10 and the semiconductor element 30. The insulating film 11 functions as a cladding layer, and therefore can suppress light loss.

[0065] 1 is a wavelength tunable laser element, but the semiconductor optical element 100 may be an optical device other than the wavelength tunable laser element.

[0066] (Variation) FIG. 20A is a plan view illustrating a semiconductor optical device according to a modified example, and similar to FIG. 2A, one transition structure 101 is illustrated. FIG. 20B is a plan view illustrating a substrate 60. Description of the same configuration as in the embodiment will be omitted. As shown in FIGS. 20A and 20B, the substrate 60 has a waveguide 20, a recess 24, a terrace 27, and a slab portion 28. The waveguide 20 is connected to one end of the slab portion 28. The slab portion 28 extends from one transition structure 101 to another transition structure 102. In the X-axis direction, no waveguide or recess is provided between the transition structure 101 and the transition structure 102. The slab portion 32 of the semiconductor device 30 is bonded to the slab portion 28.

[0067] According to this modification, since the slab portion 28 is provided, the recess 24 terminates near the edge of the semiconductor element 30. This makes it difficult for liquids such as etchant to seep under the semiconductor element 30. This makes it possible to suppress unintended etching of the semiconductor element 30.

[0068] Although the embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present disclosure as described in the claims. [Explanation of symbols]

[0069] 10, 12, 60 boards 11. Insulating film 14 Box Layer 16 Silicon Layer 20, 22 Waveguide 21, 23, 31, 34, 38 Tapered section 24, 26 Recess 25, 29, 36, 37 parts 27 Terrace 28, 32, 39 Slab section 30 Semiconductor elements 33 Protrusion 35 Mesa 40, 44 Cladding layer 42 Active layer 46 Contact layer 48, 49 electrode 50, 52, 54 Masks 100, 110 Semiconductor optical element 101, 102 transition structure 103 Ring resonator 104 Loop Mirror

Claims

1. a substrate having a silicon layer; a semiconductor element formed of a III-V compound semiconductor and bonded to the silicon layer; the silicon layer has a first waveguide, a first recess, a terrace, and a first slab portion; the first recess is a portion recessed below the surfaces of the first waveguide, the terrace, and the first slab portion, the first recess and the terrace are arranged in this order on both sides of the first waveguide; the first waveguide is connected to one end of the first slab portion; the first slab portion is connected to the terrace; the semiconductor element has a second slab portion, a protrusion portion, and a mesa; the second slab portion is located on top of the first slab portion; the protruding portion protrudes from the second slab portion onto the first waveguide; The mesa is a semiconductor optical device located on the second slab portion and the protruding portion.

2. the silicon layer has a second waveguide and a second recess; the second waveguide is connected to an end of the first slab portion opposite to the first waveguide, the second recess and the terrace are arranged in this order on both sides of the second waveguide; the first slab portion is located between the first recess and the second recess, the second slab portion is located on the first slab portion, the second waveguide, the second recess, and the terraces on both sides of the second waveguide; 2. The semiconductor optical device according to claim 1, wherein the mesa extends from a position overlapping the first waveguide to a position overlapping the second waveguide.

3. the semiconductor element has a first semiconductor layer, an active layer, and a second semiconductor layer; the first semiconductor layer, the active layer, and the second semiconductor layer are stacked in this order from the side closest to the substrate; the protrusion includes the first semiconductor layer, the second slab portion includes the first semiconductor layer and the active layer, a portion of the mesa located above the protruding portion includes the active layer and the second semiconductor layer; 3. The semiconductor optical device according to claim 1, wherein the portion of the mesa located above the second slab portion includes the second semiconductor layer.

4. the first semiconductor layer and the second semiconductor layer contain indium phosphide; 4. The semiconductor optical device according to claim 3, wherein the active layer contains gallium indium arsenide phosphide.

5. the first semiconductor layer is an n-type semiconductor layer, 4. The semiconductor optical device according to claim 3, wherein the second semiconductor layer is a p-type semiconductor layer.

6. the protrusion is located inside the first waveguide, 3. The semiconductor optical device according to claim 1, wherein the mesa is positioned inside the protruding portion.

7. the first waveguide has a first tapered portion; the protrusion has a second tapered portion; the mesa has a third tapered portion; 3. The semiconductor optical device according to claim 1, wherein the width of the first tapered portion, the width of the second tapered portion, and the width of the third tapered portion are larger as they are closer to the first slab portion and smaller as they are farther from the first slab portion.

8. the second tapered portion is joined to the first tapered portion; 8. The semiconductor optical device according to claim 7, wherein the third tapered portion is located above the second tapered portion.

9. 3. The semiconductor optical device according to claim 1, further comprising an insulating film covering the silicon layer and the semiconductor device.

10. bonding a semiconductor element formed of a III-V compound semiconductor to the silicon layer of the substrate; and wet etching the bonded semiconductor element, the silicon layer has a first waveguide, a first recess, a terrace, and a first slab portion; the first recess is a portion recessed below the surfaces of the first waveguide, the terrace, and the first slab portion, the first recess and the terrace are arranged in this order on both sides of the first waveguide; the first waveguide is connected to one end of the first slab portion; the first slab portion is connected to the terrace; the step of bonding the semiconductor element is a step of bonding the semiconductor element to the first waveguide, the first slab portion, and the terraces on both sides of the first waveguide; In the step of performing the wet etching, a second slab portion, a protrusion portion, and a mesa are formed in the semiconductor element; the second slab portion is located on top of the first slab portion; the protruding portion protrudes from the second slab portion onto the first waveguide; The mesa is located on the second slab portion and the protruding portion.

11. the silicon layer has a second waveguide and a second recess; the second waveguide is connected to an end of the first slab portion opposite to the first waveguide, the second recess and the terrace are arranged in this order on both sides of the second waveguide; the first slab portion is located between the first recess and the second recess, the bonding step is a step of bonding the semiconductor element to the terraces on both sides of the first waveguide, the first slab portion, the second waveguide, and the first and second waveguides, 11. The method for manufacturing a semiconductor optical device according to claim 10, wherein the mesa extends from a position overlapping the first waveguide to a position overlapping the second waveguide.

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